blob: 5cd70f9e7311a5e85294796f612451e53e8c3b3c [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
David Howells760285e2012-10-02 18:01:07 +010028#include <drm/drmP.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020029#include "radeon.h"
David Howells760285e2012-10-02 18:01:07 +010030#include <drm/radeon_drm.h>
Marek Olšák6759a0a2012-08-09 16:34:17 +020031#include "radeon_asic.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020032
Dave Airlie6a9ee8a2010-02-01 15:38:10 +100033#include <linux/vga_switcheroo.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Dave Airlie10ebc0b2012-09-17 14:40:31 +100035#include <linux/pm_runtime.h>
Alex Deucher78488652014-03-11 15:02:30 -040036
37#if defined(CONFIG_VGA_SWITCHEROO)
Alex Deucher90c4cde2014-04-10 22:29:01 -040038bool radeon_has_atpx(void);
Alex Deucher78488652014-03-11 15:02:30 -040039#else
Alex Deucher90c4cde2014-04-10 22:29:01 -040040static inline bool radeon_has_atpx(void) { return false; }
Alex Deucher78488652014-03-11 15:02:30 -040041#endif
42
Alex Deucherf482a142012-07-17 14:02:34 -040043/**
44 * radeon_driver_unload_kms - Main unload function for KMS.
45 *
46 * @dev: drm dev pointer
47 *
48 * This is the main unload function for KMS (all asics).
49 * It calls radeon_modeset_fini() to tear down the
50 * displays, and radeon_device_fini() to tear down
51 * the rest of the device (CP, writeback, etc.).
52 * Returns 0 on success.
53 */
Jerome Glissecf0fe452009-12-09 18:21:55 +010054int radeon_driver_unload_kms(struct drm_device *dev)
55{
56 struct radeon_device *rdev = dev->dev_private;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020057
Jerome Glissecf0fe452009-12-09 18:21:55 +010058 if (rdev == NULL)
59 return 0;
Dave Airlie10ebc0b2012-09-17 14:40:31 +100060
Alex Deucher0cd9cb72013-04-12 19:15:52 -040061 if (rdev->rmmio == NULL)
62 goto done_free;
Dave Airlie10ebc0b2012-09-17 14:40:31 +100063
64 pm_runtime_get_sync(dev->dev);
65
Alex Deucherc4917072012-07-31 17:14:35 -040066 radeon_acpi_fini(rdev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +100067
Jerome Glissecf0fe452009-12-09 18:21:55 +010068 radeon_modeset_fini(rdev);
69 radeon_device_fini(rdev);
Alex Deucher0cd9cb72013-04-12 19:15:52 -040070
71done_free:
Jerome Glissecf0fe452009-12-09 18:21:55 +010072 kfree(rdev);
73 dev->dev_private = NULL;
74 return 0;
75}
76
Alex Deucherf482a142012-07-17 14:02:34 -040077/**
78 * radeon_driver_load_kms - Main load function for KMS.
79 *
80 * @dev: drm dev pointer
81 * @flags: device flags
82 *
83 * This is the main load function for KMS (all asics).
84 * It calls radeon_device_init() to set up the non-display
85 * parts of the chip (asic init, CP, writeback, etc.), and
86 * radeon_modeset_init() to set up the display parts
87 * (crtcs, encoders, hotplug detect, etc.).
88 * Returns 0 on success, error on failure.
89 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +020090int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
91{
92 struct radeon_device *rdev;
Alberto Miloned7a29522010-07-06 11:40:24 -040093 int r, acpi_status;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020094
95 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
96 if (rdev == NULL) {
97 return -ENOMEM;
98 }
99 dev->dev_private = (void *)rdev;
100
101 /* update BUS flag */
Dave Airlie8410ea32010-12-15 03:16:38 +1000102 if (drm_pci_device_is_agp(dev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200103 flags |= RADEON_IS_AGP;
Jon Mason58b65422011-06-27 16:07:50 +0000104 } else if (pci_is_pcie(dev->pdev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200105 flags |= RADEON_IS_PCIE;
106 } else {
107 flags |= RADEON_IS_PCI;
108 }
109
Alex Deucher73acacc2014-04-15 12:44:35 -0400110 if ((radeon_runtime_pm != 0) &&
111 radeon_has_atpx() &&
112 ((flags & RADEON_IS_IGP) == 0))
Alex Deucher90c4cde2014-04-10 22:29:01 -0400113 flags |= RADEON_IS_PX;
114
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200115 /* radeon_device_init should report only fatal error
116 * like memory allocation failure or iomapping failure,
117 * or memory manager initialization failure, it must
118 * properly initialize the GPU MC controller and permit
119 * VRAM allocation
120 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200121 r = radeon_device_init(rdev, dev, dev->pdev, flags);
122 if (r) {
Jerome Glissecf0fe452009-12-09 18:21:55 +0100123 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
124 goto out;
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200125 }
Alberto Miloned7a29522010-07-06 11:40:24 -0400126
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200127 /* Again modeset_init should fail only on fatal error
128 * otherwise it should provide enough functionalities
129 * for shadowfb to run
130 */
131 r = radeon_modeset_init(rdev);
Jerome Glissecf0fe452009-12-09 18:21:55 +0100132 if (r)
133 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
Luca Tettamantifda4b252012-07-30 21:20:35 +0200134
135 /* Call ACPI methods: require modeset init
136 * but failure is not fatal
137 */
138 if (!r) {
139 acpi_status = radeon_acpi_init(rdev);
140 if (acpi_status)
141 dev_dbg(&dev->pdev->dev,
142 "Error during ACPI methods call\n");
143 }
144
Alex Deucher90c4cde2014-04-10 22:29:01 -0400145 if (radeon_is_px(dev)) {
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000146 pm_runtime_use_autosuspend(dev->dev);
147 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
148 pm_runtime_set_active(dev->dev);
149 pm_runtime_allow(dev->dev);
150 pm_runtime_mark_last_busy(dev->dev);
151 pm_runtime_put_autosuspend(dev->dev);
152 }
153
Jerome Glissecf0fe452009-12-09 18:21:55 +0100154out:
155 if (r)
156 radeon_driver_unload_kms(dev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000157
158
Jerome Glissecf0fe452009-12-09 18:21:55 +0100159 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200160}
161
Alex Deucherf482a142012-07-17 14:02:34 -0400162/**
163 * radeon_set_filp_rights - Set filp right.
164 *
165 * @dev: drm dev pointer
166 * @owner: drm file
167 * @applier: drm file
168 * @value: value
169 *
170 * Sets the filp rights for the device (all asics).
171 */
Marek Olšák9eba4a92011-01-05 05:46:48 +0100172static void radeon_set_filp_rights(struct drm_device *dev,
173 struct drm_file **owner,
174 struct drm_file *applier,
175 uint32_t *value)
176{
177 mutex_lock(&dev->struct_mutex);
178 if (*value == 1) {
179 /* wants rights */
180 if (!*owner)
181 *owner = applier;
182 } else if (*value == 0) {
183 /* revokes rights */
184 if (*owner == applier)
185 *owner = NULL;
186 }
187 *value = *owner == applier ? 1 : 0;
188 mutex_unlock(&dev->struct_mutex);
189}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200190
191/*
Marek Olšák9eba4a92011-01-05 05:46:48 +0100192 * Userspace get information ioctl
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200193 */
Alex Deucherf482a142012-07-17 14:02:34 -0400194/**
195 * radeon_info_ioctl - answer a device specific request.
196 *
197 * @rdev: radeon device pointer
198 * @data: request object
199 * @filp: drm filp
200 *
201 * This function is used to pass device specific parameters to the userspace
202 * drivers. Examples include: pci device id, pipeline parms, tiling params,
203 * etc. (all asics).
204 * Returns 0 on success, -EINVAL on failure.
205 */
Rashika Kheria55203452014-01-06 20:53:07 +0530206static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200207{
208 struct radeon_device *rdev = dev->dev_private;
Marek Olšák6759a0a2012-08-09 16:34:17 +0200209 struct drm_radeon_info *info = data;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200210 struct radeon_mode_info *minfo = &rdev->mode_info;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400211 uint32_t *value, value_tmp, *value_ptr, value_size;
212 uint64_t value64;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200213 struct drm_crtc *crtc;
214 int i, found;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200215
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200216 value_ptr = (uint32_t *)((unsigned long)info->value);
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400217 value = &value_tmp;
218 value_size = sizeof(uint32_t);
Dr. David Alan Gilbertd8ab3552010-08-02 09:43:52 +1000219
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200220 switch (info->request) {
221 case RADEON_INFO_DEVICE_ID:
Ville Syrjäläffbab09b2013-10-04 14:53:40 +0300222 *value = dev->pdev->device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200223 break;
224 case RADEON_INFO_NUM_GB_PIPES:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400225 *value = rdev->num_gb_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200226 break;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400227 case RADEON_INFO_NUM_Z_PIPES:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400228 *value = rdev->num_z_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400229 break;
Jerome Glisse733289c2009-09-16 15:24:21 +0200230 case RADEON_INFO_ACCEL_WORKING:
Alex Deucher148a03b2010-06-03 19:00:03 -0400231 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
232 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400233 *value = false;
Alex Deucher148a03b2010-06-03 19:00:03 -0400234 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400235 *value = rdev->accel_working;
Jerome Glisse733289c2009-09-16 15:24:21 +0200236 break;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200237 case RADEON_INFO_CRTC_FROM_ID:
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100238 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400239 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
240 return -EFAULT;
241 }
Jerome Glissebc35afd2010-05-12 18:01:13 +0200242 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
243 crtc = (struct drm_crtc *)minfo->crtcs[i];
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400244 if (crtc && crtc->base.id == *value) {
Alex Deucher0baf2d82010-07-21 14:05:35 -0400245 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400246 *value = radeon_crtc->crtc_id;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200247 found = 1;
248 break;
249 }
250 }
251 if (!found) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400252 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
Jerome Glissebc35afd2010-05-12 18:01:13 +0200253 return -EINVAL;
254 }
255 break;
Alex Deucher148a03b2010-06-03 19:00:03 -0400256 case RADEON_INFO_ACCEL_WORKING2:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400257 *value = rdev->accel_working;
Alex Deucher148a03b2010-06-03 19:00:03 -0400258 break;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400259 case RADEON_INFO_TILING_CONFIG:
Alex Deucher64f759c2012-07-06 17:40:32 -0400260 if (rdev->family >= CHIP_BONAIRE)
261 *value = rdev->config.cik.tile_config;
262 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400263 *value = rdev->config.si.tile_config;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400264 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400265 *value = rdev->config.cayman.tile_config;
Alex Deucherfecf1d02011-03-02 20:07:29 -0500266 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400267 *value = rdev->config.evergreen.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400268 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400269 *value = rdev->config.rv770.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400270 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400271 *value = rdev->config.r600.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400272 else {
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000273 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400274 return -EINVAL;
275 }
Alex Deucherb824b362010-08-12 08:25:47 -0400276 break;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000277 case RADEON_INFO_WANT_HYPERZ:
Marek Olšák43861f72010-08-07 03:36:34 +0200278 /* The "value" here is both an input and output parameter.
279 * If the input value is 1, filp requests hyper-z access.
280 * If the input value is 0, filp revokes its hyper-z access.
281 *
282 * When returning, the value is 1 if filp owns hyper-z access,
283 * 0 otherwise. */
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100284 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400285 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
286 return -EFAULT;
287 }
288 if (*value >= 2) {
289 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
Marek Olšák43861f72010-08-07 03:36:34 +0200290 return -EINVAL;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000291 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400292 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100293 break;
294 case RADEON_INFO_WANT_CMASK:
295 /* The same logic as Hyper-Z. */
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100296 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400297 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
298 return -EFAULT;
299 }
300 if (*value >= 2) {
301 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100302 return -EINVAL;
Marek Olšák43861f72010-08-07 03:36:34 +0200303 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400304 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400305 break;
Alex Deucher58bbf012011-01-24 17:14:26 -0500306 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
307 /* return clock value in KHz */
Alex Deucher454d2e22013-02-14 10:04:02 -0500308 if (rdev->asic->get_xclk)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400309 *value = radeon_get_xclk(rdev) * 10;
Alex Deucher454d2e22013-02-14 10:04:02 -0500310 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400311 *value = rdev->clock.spll.reference_freq * 10;
Alex Deucher58bbf012011-01-24 17:14:26 -0500312 break;
Dave Airlie486af182011-03-01 14:32:27 +1000313 case RADEON_INFO_NUM_BACKENDS:
Alex Deucher64f759c2012-07-06 17:40:32 -0400314 if (rdev->family >= CHIP_BONAIRE)
315 *value = rdev->config.cik.max_backends_per_se *
316 rdev->config.cik.max_shader_engines;
317 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400318 *value = rdev->config.si.max_backends_per_se *
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400319 rdev->config.si.max_shader_engines;
320 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400321 *value = rdev->config.cayman.max_backends_per_se *
Alex Deucherfecf1d02011-03-02 20:07:29 -0500322 rdev->config.cayman.max_shader_engines;
323 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400324 *value = rdev->config.evergreen.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000325 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400326 *value = rdev->config.rv770.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000327 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400328 *value = rdev->config.r600.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000329 else {
330 return -EINVAL;
331 }
332 break;
Alex Deucher65659452011-04-26 13:27:43 -0400333 case RADEON_INFO_NUM_TILE_PIPES:
Alex Deucher64f759c2012-07-06 17:40:32 -0400334 if (rdev->family >= CHIP_BONAIRE)
335 *value = rdev->config.cik.max_tile_pipes;
336 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400337 *value = rdev->config.si.max_tile_pipes;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400338 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400339 *value = rdev->config.cayman.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400340 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400341 *value = rdev->config.evergreen.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400342 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400343 *value = rdev->config.rv770.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400344 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400345 *value = rdev->config.r600.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400346 else {
347 return -EINVAL;
348 }
349 break;
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400350 case RADEON_INFO_FUSION_GART_WORKING:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400351 *value = 1;
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400352 break;
Alex Deuchere55b9422011-07-15 19:53:52 +0000353 case RADEON_INFO_BACKEND_MAP:
Alex Deucher64f759c2012-07-06 17:40:32 -0400354 if (rdev->family >= CHIP_BONAIRE)
Michel Dänzer1ddce272013-11-18 18:25:59 +0900355 *value = rdev->config.cik.backend_map;
Alex Deucher64f759c2012-07-06 17:40:32 -0400356 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400357 *value = rdev->config.si.backend_map;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400358 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400359 *value = rdev->config.cayman.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000360 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400361 *value = rdev->config.evergreen.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000362 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400363 *value = rdev->config.rv770.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000364 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400365 *value = rdev->config.r600.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000366 else {
367 return -EINVAL;
368 }
369 break;
Jerome Glisse721604a2012-01-05 22:11:05 -0500370 case RADEON_INFO_VA_START:
371 /* this is where we report if vm is supported or not */
372 if (rdev->family < CHIP_CAYMAN)
373 return -EINVAL;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400374 *value = RADEON_VA_RESERVED_SIZE;
Jerome Glisse721604a2012-01-05 22:11:05 -0500375 break;
376 case RADEON_INFO_IB_VM_MAX_SIZE:
377 /* this is where we report if vm is supported or not */
378 if (rdev->family < CHIP_CAYMAN)
379 return -EINVAL;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400380 *value = RADEON_IB_VM_MAX_SIZE;
Jerome Glisse721604a2012-01-05 22:11:05 -0500381 break;
Tom Stellard609c1e12012-03-20 17:17:55 -0400382 case RADEON_INFO_MAX_PIPES:
Alex Deucher64f759c2012-07-06 17:40:32 -0400383 if (rdev->family >= CHIP_BONAIRE)
384 *value = rdev->config.cik.max_cu_per_sh;
385 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400386 *value = rdev->config.si.max_cu_per_sh;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400387 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400388 *value = rdev->config.cayman.max_pipes_per_simd;
Tom Stellard609c1e12012-03-20 17:17:55 -0400389 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400390 *value = rdev->config.evergreen.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400391 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400392 *value = rdev->config.rv770.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400393 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400394 *value = rdev->config.r600.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400395 else {
396 return -EINVAL;
397 }
398 break;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400399 case RADEON_INFO_TIMESTAMP:
400 if (rdev->family < CHIP_R600) {
401 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
402 return -EINVAL;
403 }
404 value = (uint32_t*)&value64;
405 value_size = sizeof(uint64_t);
406 value64 = radeon_get_gpu_clock_counter(rdev);
407 break;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500408 case RADEON_INFO_MAX_SE:
Alex Deucher64f759c2012-07-06 17:40:32 -0400409 if (rdev->family >= CHIP_BONAIRE)
410 *value = rdev->config.cik.max_shader_engines;
411 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400412 *value = rdev->config.si.max_shader_engines;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500413 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400414 *value = rdev->config.cayman.max_shader_engines;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500415 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400416 *value = rdev->config.evergreen.num_ses;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500417 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400418 *value = 1;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500419 break;
420 case RADEON_INFO_MAX_SH_PER_SE:
Alex Deucher64f759c2012-07-06 17:40:32 -0400421 if (rdev->family >= CHIP_BONAIRE)
422 *value = rdev->config.cik.max_sh_per_se;
423 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400424 *value = rdev->config.si.max_sh_per_se;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500425 else
426 return -EINVAL;
427 break;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400428 case RADEON_INFO_FASTFB_WORKING:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400429 *value = rdev->fastfb_working;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400430 break;
Christian König902aaef2013-04-09 10:35:42 -0400431 case RADEON_INFO_RING_WORKING:
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100432 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400433 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
434 return -EFAULT;
435 }
436 switch (*value) {
Christian König902aaef2013-04-09 10:35:42 -0400437 case RADEON_CS_RING_GFX:
438 case RADEON_CS_RING_COMPUTE:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400439 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400440 break;
441 case RADEON_CS_RING_DMA:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400442 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
443 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400444 break;
445 case RADEON_CS_RING_UVD:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400446 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400447 break;
Christian Königf7ba8b02014-01-27 10:16:06 -0700448 case RADEON_CS_RING_VCE:
449 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
450 break;
Christian König902aaef2013-04-09 10:35:42 -0400451 default:
452 return -EINVAL;
453 }
454 break;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400455 case RADEON_INFO_SI_TILE_MODE_ARRAY:
Alex Deucher64f759c2012-07-06 17:40:32 -0400456 if (rdev->family >= CHIP_BONAIRE) {
Alex Deucher39aee492013-04-10 13:41:25 -0400457 value = rdev->config.cik.tile_mode_array;
458 value_size = sizeof(uint32_t)*32;
459 } else if (rdev->family >= CHIP_TAHITI) {
460 value = rdev->config.si.tile_mode_array;
461 value_size = sizeof(uint32_t)*32;
462 } else {
463 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
Alex Deucher64f759c2012-07-06 17:40:32 -0400464 return -EINVAL;
465 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400466 break;
Michel Dänzer32f79a82013-11-18 18:26:00 +0900467 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
468 if (rdev->family >= CHIP_BONAIRE) {
469 value = rdev->config.cik.macrotile_mode_array;
470 value_size = sizeof(uint32_t)*16;
471 } else {
472 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
473 return -EINVAL;
474 }
475 break;
Tom Stellarde5b9e752013-08-16 17:47:39 -0400476 case RADEON_INFO_SI_CP_DMA_COMPUTE:
477 *value = 1;
478 break;
Marek Olšák439a1cf2013-12-22 02:18:01 +0100479 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
480 if (rdev->family >= CHIP_BONAIRE) {
481 *value = rdev->config.cik.backend_enable_mask;
482 } else if (rdev->family >= CHIP_TAHITI) {
483 *value = rdev->config.si.backend_enable_mask;
484 } else {
485 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
486 }
487 break;
Alex Deucherf5f1f892014-01-20 18:20:29 -0500488 case RADEON_INFO_MAX_SCLK:
489 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
490 rdev->pm.dpm_enabled)
491 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
492 else
493 *value = rdev->pm.default_sclk * 10;
494 break;
Christian König98ccc292014-01-23 09:50:49 -0700495 case RADEON_INFO_VCE_FW_VERSION:
496 *value = rdev->vce.fw_version;
497 break;
498 case RADEON_INFO_VCE_FB_VERSION:
499 *value = rdev->vce.fb_version;
500 break;
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100501 case RADEON_INFO_NUM_BYTES_MOVED:
502 value = (uint32_t*)&value64;
503 value_size = sizeof(uint64_t);
504 value64 = atomic64_read(&rdev->num_bytes_moved);
505 break;
506 case RADEON_INFO_VRAM_USAGE:
507 value = (uint32_t*)&value64;
508 value_size = sizeof(uint64_t);
509 value64 = atomic64_read(&rdev->vram_usage);
510 break;
511 case RADEON_INFO_GTT_USAGE:
512 value = (uint32_t*)&value64;
513 value_size = sizeof(uint64_t);
514 value64 = atomic64_read(&rdev->gtt_usage);
515 break;
Alex Deucher65fcf662014-06-02 16:13:21 -0400516 case RADEON_INFO_ACTIVE_CU_COUNT:
517 if (rdev->family >= CHIP_BONAIRE)
518 *value = rdev->config.cik.active_cus;
519 else if (rdev->family >= CHIP_TAHITI)
520 *value = rdev->config.si.active_cus;
521 else if (rdev->family >= CHIP_CAYMAN)
522 *value = rdev->config.cayman.active_simds;
523 else if (rdev->family >= CHIP_CEDAR)
524 *value = rdev->config.evergreen.active_simds;
525 else if (rdev->family >= CHIP_RV770)
526 *value = rdev->config.rv770.active_simds;
527 else if (rdev->family >= CHIP_R600)
528 *value = rdev->config.r600.active_simds;
529 else
530 *value = 1;
531 break;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200532 default:
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000533 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200534 return -EINVAL;
535 }
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100536 if (copy_to_user(value_ptr, (char*)value, value_size)) {
Marek Olšák6759a0a2012-08-09 16:34:17 +0200537 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200538 return -EFAULT;
539 }
540 return 0;
541}
542
543
544/*
545 * Outdated mess for old drm with Xorg being in charge (void function now).
546 */
Alex Deucherf482a142012-07-17 14:02:34 -0400547/**
Alex Deucherf482a142012-07-17 14:02:34 -0400548 * radeon_driver_firstopen_kms - drm callback for last close
549 *
550 * @dev: drm dev pointer
551 *
552 * Switch vga switcheroo state after last close (all asics).
553 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200554void radeon_driver_lastclose_kms(struct drm_device *dev)
555{
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000556 vga_switcheroo_process_delayed_switch();
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200557}
558
Alex Deucherf482a142012-07-17 14:02:34 -0400559/**
560 * radeon_driver_open_kms - drm callback for open
561 *
562 * @dev: drm dev pointer
563 * @file_priv: drm file
564 *
565 * On device open, init vm on cayman+ (all asics).
566 * Returns 0 on success, error on failure.
567 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200568int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
569{
Jerome Glisse721604a2012-01-05 22:11:05 -0500570 struct radeon_device *rdev = dev->dev_private;
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000571 int r;
Jerome Glisse721604a2012-01-05 22:11:05 -0500572
573 file_priv->driver_priv = NULL;
574
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000575 r = pm_runtime_get_sync(dev->dev);
576 if (r < 0)
577 return r;
578
Jerome Glisse721604a2012-01-05 22:11:05 -0500579 /* new gpu have virtual address space support */
580 if (rdev->family >= CHIP_CAYMAN) {
581 struct radeon_fpriv *fpriv;
Christian Königd72d43c2012-10-09 13:31:18 +0200582 struct radeon_bo_va *bo_va;
Jerome Glisse721604a2012-01-05 22:11:05 -0500583 int r;
584
585 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
586 if (unlikely(!fpriv)) {
587 return -ENOMEM;
588 }
589
Christian König6d2f2942014-02-20 13:42:17 +0100590 r = radeon_vm_init(rdev, &fpriv->vm);
Quentin Casasnovas74073c92014-03-18 17:16:52 +0100591 if (r) {
592 kfree(fpriv);
Christian König6d2f2942014-02-20 13:42:17 +0100593 return r;
Quentin Casasnovas74073c92014-03-18 17:16:52 +0100594 }
Christian Königd72d43c2012-10-09 13:31:18 +0200595
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400596 if (rdev->accel_working) {
597 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
598 if (r) {
599 radeon_vm_fini(rdev, &fpriv->vm);
600 kfree(fpriv);
601 return r;
602 }
603
604 /* map the ib pool buffer read only into
605 * virtual address space */
606 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
607 rdev->ring_tmp_bo.bo);
608 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
609 RADEON_VM_PAGE_READABLE |
610 RADEON_VM_PAGE_SNOOPED);
611
612 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
613 if (r) {
614 radeon_vm_fini(rdev, &fpriv->vm);
615 kfree(fpriv);
616 return r;
617 }
Quentin Casasnovas74073c92014-03-18 17:16:52 +0100618 }
Jerome Glisse721604a2012-01-05 22:11:05 -0500619 file_priv->driver_priv = fpriv;
620 }
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000621
622 pm_runtime_mark_last_busy(dev->dev);
623 pm_runtime_put_autosuspend(dev->dev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200624 return 0;
625}
626
Alex Deucherf482a142012-07-17 14:02:34 -0400627/**
628 * radeon_driver_postclose_kms - drm callback for post close
629 *
630 * @dev: drm dev pointer
631 * @file_priv: drm file
632 *
633 * On device post close, tear down vm on cayman+ (all asics).
634 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200635void radeon_driver_postclose_kms(struct drm_device *dev,
636 struct drm_file *file_priv)
637{
Jerome Glisse721604a2012-01-05 22:11:05 -0500638 struct radeon_device *rdev = dev->dev_private;
639
640 /* new gpu have virtual address space support */
641 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
642 struct radeon_fpriv *fpriv = file_priv->driver_priv;
Christian Königd72d43c2012-10-09 13:31:18 +0200643 struct radeon_bo_va *bo_va;
644 int r;
645
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400646 if (rdev->accel_working) {
647 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
648 if (!r) {
649 bo_va = radeon_vm_bo_find(&fpriv->vm,
650 rdev->ring_tmp_bo.bo);
651 if (bo_va)
652 radeon_vm_bo_rmv(rdev, bo_va);
653 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
654 }
Christian Königd72d43c2012-10-09 13:31:18 +0200655 }
Jerome Glisse721604a2012-01-05 22:11:05 -0500656
657 radeon_vm_fini(rdev, &fpriv->vm);
658 kfree(fpriv);
659 file_priv->driver_priv = NULL;
660 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200661}
662
Alex Deucherf482a142012-07-17 14:02:34 -0400663/**
664 * radeon_driver_preclose_kms - drm callback for pre close
665 *
666 * @dev: drm dev pointer
667 * @file_priv: drm file
668 *
669 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
670 * (all asics).
671 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200672void radeon_driver_preclose_kms(struct drm_device *dev,
673 struct drm_file *file_priv)
674{
Dave Airlieab9e1f52010-07-13 11:11:11 +1000675 struct radeon_device *rdev = dev->dev_private;
676 if (rdev->hyperz_filp == file_priv)
677 rdev->hyperz_filp = NULL;
Marek Olšákdca0d612011-01-27 22:46:15 +0100678 if (rdev->cmask_filp == file_priv)
679 rdev->cmask_filp = NULL;
Christian Königf2ba57b2013-04-08 12:41:29 +0200680 radeon_uvd_free_handles(rdev, file_priv);
Christian Königd93f7932013-05-23 12:10:04 +0200681 radeon_vce_free_handles(rdev, file_priv);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200682}
683
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200684/*
685 * VBlank related functions.
686 */
Alex Deucherf482a142012-07-17 14:02:34 -0400687/**
688 * radeon_get_vblank_counter_kms - get frame count
689 *
690 * @dev: drm dev pointer
691 * @crtc: crtc to get the frame count from
692 *
693 * Gets the frame count on the requested crtc (all asics).
694 * Returns frame count on success, -EINVAL on failure.
695 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200696u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
697{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200698 struct radeon_device *rdev = dev->dev_private;
699
Dave Airlie9c950a42010-04-23 13:21:58 +1000700 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200701 DRM_ERROR("Invalid crtc %d\n", crtc);
702 return -EINVAL;
703 }
704
705 return radeon_get_vblank_counter(rdev, crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200706}
707
Alex Deucherf482a142012-07-17 14:02:34 -0400708/**
709 * radeon_enable_vblank_kms - enable vblank interrupt
710 *
711 * @dev: drm dev pointer
712 * @crtc: crtc to enable vblank interrupt for
713 *
714 * Enable the interrupt on the requested crtc (all asics).
715 * Returns 0 on success, -EINVAL on failure.
716 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200717int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
718{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200719 struct radeon_device *rdev = dev->dev_private;
Christian Koenigfb982572012-05-17 01:33:30 +0200720 unsigned long irqflags;
721 int r;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200722
Dave Airlie9c950a42010-04-23 13:21:58 +1000723 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200724 DRM_ERROR("Invalid crtc %d\n", crtc);
725 return -EINVAL;
726 }
727
Christian Koenigfb982572012-05-17 01:33:30 +0200728 spin_lock_irqsave(&rdev->irq.lock, irqflags);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200729 rdev->irq.crtc_vblank_int[crtc] = true;
Christian Koenigfb982572012-05-17 01:33:30 +0200730 r = radeon_irq_set(rdev);
731 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
732 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200733}
734
Alex Deucherf482a142012-07-17 14:02:34 -0400735/**
736 * radeon_disable_vblank_kms - disable vblank interrupt
737 *
738 * @dev: drm dev pointer
739 * @crtc: crtc to disable vblank interrupt for
740 *
741 * Disable the interrupt on the requested crtc (all asics).
742 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200743void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
744{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200745 struct radeon_device *rdev = dev->dev_private;
Christian Koenigfb982572012-05-17 01:33:30 +0200746 unsigned long irqflags;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200747
Dave Airlie9c950a42010-04-23 13:21:58 +1000748 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200749 DRM_ERROR("Invalid crtc %d\n", crtc);
750 return;
751 }
752
Christian Koenigfb982572012-05-17 01:33:30 +0200753 spin_lock_irqsave(&rdev->irq.lock, irqflags);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200754 rdev->irq.crtc_vblank_int[crtc] = false;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200755 radeon_irq_set(rdev);
Christian Koenigfb982572012-05-17 01:33:30 +0200756 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200757}
758
Alex Deucherf482a142012-07-17 14:02:34 -0400759/**
760 * radeon_get_vblank_timestamp_kms - get vblank timestamp
761 *
762 * @dev: drm dev pointer
763 * @crtc: crtc to get the timestamp for
764 * @max_error: max error
765 * @vblank_time: time value
766 * @flags: flags passed to the driver
767 *
768 * Gets the timestamp on the requested crtc based on the
769 * scanout position. (all asics).
770 * Returns postive status flags on success, negative error on failure.
771 */
Mario Kleinerf5a80202010-10-23 04:42:17 +0200772int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
773 int *max_error,
774 struct timeval *vblank_time,
775 unsigned flags)
776{
777 struct drm_crtc *drmcrtc;
778 struct radeon_device *rdev = dev->dev_private;
779
780 if (crtc < 0 || crtc >= dev->num_crtcs) {
781 DRM_ERROR("Invalid crtc %d\n", crtc);
782 return -EINVAL;
783 }
784
785 /* Get associated drm_crtc: */
786 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
787
788 /* Helper routine in DRM core does all the work: */
789 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
790 vblank_time, flags,
Ville Syrjälä7da903e2013-10-26 17:57:31 +0300791 drmcrtc, &drmcrtc->hwmode);
Mario Kleinerf5a80202010-10-23 04:42:17 +0200792}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200793
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200794#define KMS_INVALID_IOCTL(name) \
Rashika Kheriaf6e2e402014-01-06 21:06:44 +0530795static int name(struct drm_device *dev, void *data, struct drm_file \
796 *file_priv) \
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200797{ \
798 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
799 return -EINVAL; \
800}
801
802/*
803 * All these ioctls are invalid in kms world.
804 */
805KMS_INVALID_IOCTL(radeon_cp_init_kms)
806KMS_INVALID_IOCTL(radeon_cp_start_kms)
807KMS_INVALID_IOCTL(radeon_cp_stop_kms)
808KMS_INVALID_IOCTL(radeon_cp_reset_kms)
809KMS_INVALID_IOCTL(radeon_cp_idle_kms)
810KMS_INVALID_IOCTL(radeon_cp_resume_kms)
811KMS_INVALID_IOCTL(radeon_engine_reset_kms)
812KMS_INVALID_IOCTL(radeon_fullscreen_kms)
813KMS_INVALID_IOCTL(radeon_cp_swap_kms)
814KMS_INVALID_IOCTL(radeon_cp_clear_kms)
815KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
816KMS_INVALID_IOCTL(radeon_cp_indices_kms)
817KMS_INVALID_IOCTL(radeon_cp_texture_kms)
818KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
819KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
820KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
821KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
822KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
823KMS_INVALID_IOCTL(radeon_cp_flip_kms)
824KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
825KMS_INVALID_IOCTL(radeon_mem_free_kms)
826KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
827KMS_INVALID_IOCTL(radeon_irq_emit_kms)
828KMS_INVALID_IOCTL(radeon_irq_wait_kms)
829KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
830KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
831KMS_INVALID_IOCTL(radeon_surface_free_kms)
832
833
Rob Clarkbaa70942013-08-02 13:27:49 -0400834const struct drm_ioctl_desc radeon_ioctls_kms[] = {
Dave Airlie1b2f1482010-08-14 20:20:34 +1000835 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
836 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
837 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
838 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
839 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
840 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
841 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
842 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
843 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
844 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
845 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
846 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
847 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
848 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
849 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
850 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
851 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
852 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
853 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
854 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
855 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
856 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
857 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
858 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
859 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
860 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
861 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200862 /* KMS */
Christian Königf33bcab2013-08-25 18:29:03 +0200863 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
864 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
865 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
866 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
Dave Airlie1b2f1482010-08-14 20:20:34 +1000867 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
868 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
Christian Königf33bcab2013-08-25 18:29:03 +0200869 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
870 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
871 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
872 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
873 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
874 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
875 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
Marek Olšákbda72d52014-03-02 00:56:17 +0100876 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200877};
878int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);