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Eric Miao49cbe782009-01-20 14:15:18 +08001/*
2 * linux/arch/arm/mach-mmp/pxa168.c
3 *
4 * Code specific to PXA168
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
Eric Miao49cbe782009-01-20 14:15:18 +080010#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/list.h>
Eric Miaoe2bb6652009-01-20 14:38:24 +080014#include <linux/io.h>
Eric Miao49cbe782009-01-20 14:15:18 +080015#include <linux/clk.h>
Haojian Zhuang157d2642011-10-17 20:37:52 +080016#include <linux/platform_device.h>
Eric Miao49cbe782009-01-20 14:15:18 +080017
18#include <asm/mach/time.h>
19#include <mach/addr-map.h>
20#include <mach/cputype.h>
21#include <mach/regs-apbc.h>
Haojian Zhuanga0f266c2009-10-13 15:24:55 +080022#include <mach/regs-apmu.h>
Eric Miao49cbe782009-01-20 14:15:18 +080023#include <mach/irqs.h>
24#include <mach/dma.h>
25#include <mach/devices.h>
Eric Miaoa7a89d92009-01-20 17:20:56 +080026#include <mach/mfp.h>
Tanmay Upadhyay3abd7f62011-07-20 10:00:58 +053027#include <linux/platform_device.h>
28#include <linux/dma-mapping.h>
29#include <mach/pxa168.h>
Eric Miao49cbe782009-01-20 14:15:18 +080030
31#include "common.h"
32#include "clock.h"
33
Eric Miaoa7a89d92009-01-20 17:20:56 +080034#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
35
36static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata =
37{
38 MFP_ADDR_X(GPIO0, GPIO36, 0x04c),
39 MFP_ADDR_X(GPIO37, GPIO55, 0x000),
40 MFP_ADDR_X(GPIO56, GPIO123, 0x0e0),
41 MFP_ADDR_X(GPIO124, GPIO127, 0x0f4),
42
43 MFP_ADDR_END,
44};
45
Eric Miao49cbe782009-01-20 14:15:18 +080046void __init pxa168_init_irq(void)
47{
48 icu_init_irq();
Eric Miao49cbe782009-01-20 14:15:18 +080049}
50
51/* APB peripheral clocks */
52static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
53static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
Tanmay Upadhyay26407f82011-05-02 11:29:58 +053054static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
Eric Miao1a779202009-04-13 15:34:54 +080055static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
56static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
Eric Miaoa27ba762009-04-13 18:29:52 +080057static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
58static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
59static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
60static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
Haojian Zhuang7e499222010-03-19 11:53:17 -040061static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
62static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
63static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
64static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
65static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
Haojian Zhuang389eda12011-10-17 21:26:55 +080066static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
Mark F. Brown6d109462010-09-03 18:28:07 -040067static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
Eric Miao49cbe782009-01-20 14:15:18 +080068
Lei Wen66624982011-06-21 05:37:47 -070069static APMU_CLK(nand, NAND, 0x19b, 156000000);
Mark F. Brown58cf68b2010-08-25 23:51:54 -040070static APMU_CLK(lcd, LCD, 0x7f, 312000000);
Tanmay Upadhyay80def0d2011-05-02 11:29:59 +053071static APMU_CLK(eth, ETH, 0x09, 0);
Tanmay Upadhyay3abd7f62011-07-20 10:00:58 +053072static APMU_CLK(usb, USB, 0x12, 0);
Haojian Zhuanga0f266c2009-10-13 15:24:55 +080073
Eric Miao49cbe782009-01-20 14:15:18 +080074/* device and clock bindings */
75static struct clk_lookup pxa168_clkregs[] = {
76 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
77 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
Tanmay Upadhyay26407f82011-05-02 11:29:58 +053078 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
Eric Miao1a779202009-04-13 15:34:54 +080079 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
80 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
Eric Miaoa27ba762009-04-13 18:29:52 +080081 INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
82 INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
83 INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
84 INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
Haojian Zhuang7e499222010-03-19 11:53:17 -040085 INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
86 INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
87 INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
88 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
89 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
Haojian Zhuanga0f266c2009-10-13 15:24:55 +080090 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
Mark F. Brown58cf68b2010-08-25 23:51:54 -040091 INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
Haojian Zhuang389eda12011-10-17 21:26:55 +080092 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
Mark F. Brown6d109462010-09-03 18:28:07 -040093 INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
Tanmay Upadhyay80def0d2011-05-02 11:29:59 +053094 INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
Tanmay Upadhyay3abd7f62011-07-20 10:00:58 +053095 INIT_CLKREG(&clk_usb, "pxa168-ehci", "PXA168-USBCLK"),
Eric Miao49cbe782009-01-20 14:15:18 +080096};
97
98static int __init pxa168_init(void)
99{
100 if (cpu_is_pxa168()) {
Eric Miaoa7a89d92009-01-20 17:20:56 +0800101 mfp_init_base(MFPR_VIRT_BASE);
102 mfp_init_addr(pxa168_mfp_addr_map);
Eric Miao49cbe782009-01-20 14:15:18 +0800103 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
Russell King0a0300d2010-01-12 12:28:00 +0000104 clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
Eric Miao49cbe782009-01-20 14:15:18 +0800105 }
106
107 return 0;
108}
109postcore_initcall(pxa168_init);
110
111/* system timer - clock enabled, 3.25MHz */
112#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
113
114static void __init pxa168_timer_init(void)
115{
116 /* this is early, we have to initialize the CCU registers by
117 * ourselves instead of using clk_* API. Clock rate is defined
118 * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
119 */
120 __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS);
121
122 /* 3.25MHz, bus/functional clock enabled, release reset */
123 __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS);
124
125 timer_init(IRQ_PXA168_TIMER1);
126}
127
128struct sys_timer pxa168_timer = {
129 .init = pxa168_timer_init,
130};
131
Mark F. Brownab5739a2010-09-03 18:28:10 -0400132void pxa168_clear_keypad_wakeup(void)
133{
134 uint32_t val;
135 uint32_t mask = APMU_PXA168_KP_WAKE_CLR;
136
137 /* wake event clear is needed in order to clear keypad interrupt */
138 val = __raw_readl(APMU_WAKE_CLR);
139 __raw_writel(val | mask, APMU_WAKE_CLR);
140}
141
Eric Miao49cbe782009-01-20 14:15:18 +0800142/* on-chip devices */
143PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
144PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
Tanmay Upadhyay26407f82011-05-02 11:29:58 +0530145PXA168_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4026000, 0x30, 23, 24);
Eric Miao1a779202009-04-13 15:34:54 +0800146PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
147PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
Eric Miaoa27ba762009-04-13 18:29:52 +0800148PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10);
149PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10);
150PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10);
151PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10);
Haojian Zhuanga0f266c2009-10-13 15:24:55 +0800152PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
Haojian Zhuang7e499222010-03-19 11:53:17 -0400153PXA168_DEVICE(ssp1, "pxa168-ssp", 0, SSP1, 0xd401b000, 0x40, 52, 53);
154PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55);
155PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57);
156PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
157PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
Mark F. Brown58cf68b2010-08-25 23:51:54 -0400158PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
Mark F. Brown6d109462010-09-03 18:28:07 -0400159PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
Tanmay Upadhyay80def0d2011-05-02 11:29:59 +0530160PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff);
Tanmay Upadhyay3abd7f62011-07-20 10:00:58 +0530161
Haojian Zhuang157d2642011-10-17 20:37:52 +0800162struct resource pxa168_resource_gpio[] = {
163 {
164 .start = 0xd4019000,
165 .end = 0xd4019fff,
166 .flags = IORESOURCE_MEM,
167 }, {
168 .start = IRQ_PXA168_GPIOX,
169 .end = IRQ_PXA168_GPIOX,
170 .flags = IORESOURCE_IRQ,
171 },
172};
173
174struct platform_device pxa168_device_gpio = {
175 .name = "pxa-gpio",
176 .id = -1,
177 .num_resources = ARRAY_SIZE(pxa168_resource_gpio),
178 .resource = pxa168_resource_gpio,
179};
180
Tanmay Upadhyay3abd7f62011-07-20 10:00:58 +0530181struct resource pxa168_usb_host_resources[] = {
182 /* USB Host conroller register base */
183 [0] = {
184 .start = 0xd4209000,
185 .end = 0xd4209000 + 0x200,
186 .flags = IORESOURCE_MEM,
187 .name = "pxa168-usb-host",
188 },
189 /* USB PHY register base */
190 [1] = {
191 .start = 0xd4206000,
192 .end = 0xd4206000 + 0xff,
193 .flags = IORESOURCE_MEM,
194 .name = "pxa168-usb-phy",
195 },
196 [2] = {
197 .start = IRQ_PXA168_USB2,
198 .end = IRQ_PXA168_USB2,
199 .flags = IORESOURCE_IRQ,
200 },
201};
202
203static u64 pxa168_usb_host_dmamask = DMA_BIT_MASK(32);
204struct platform_device pxa168_device_usb_host = {
205 .name = "pxa168-ehci",
206 .id = -1,
207 .dev = {
208 .dma_mask = &pxa168_usb_host_dmamask,
209 .coherent_dma_mask = DMA_BIT_MASK(32),
210 },
211
212 .num_resources = ARRAY_SIZE(pxa168_usb_host_resources),
213 .resource = pxa168_usb_host_resources,
214};
215
216int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata)
217{
218 pxa168_device_usb_host.dev.platform_data = pdata;
219 return platform_device_register(&pxa168_device_usb_host);
220}
Russell King9854a382011-11-05 15:40:09 +0000221
222void pxa168_restart(char mode, const char *cmd)
223{
224 soft_restart(0xffff0000);
225}