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Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000011
Thierry Reding4aa3df72014-11-24 16:27:13 +010012#include <drm/drm_atomic_helper.h>
Thierry Reding3b0e5852014-12-16 18:30:16 +010013#include <drm/drm_panel.h>
14
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000015#include "drm.h"
16#include "dc.h"
17
18struct tegra_rgb {
19 struct tegra_output output;
Thierry Reding7602fa12013-10-30 09:55:33 +010020 struct tegra_dc *dc;
Dmitry Osipenkob1891532014-02-11 21:12:27 +040021 bool enabled;
Thierry Reding7602fa12013-10-30 09:55:33 +010022
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000023 struct clk *clk_parent;
24 struct clk *clk;
25};
26
27static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
28{
29 return container_of(output, struct tegra_rgb, output);
30}
31
32struct reg_entry {
33 unsigned long offset;
34 unsigned long value;
35};
36
37static const struct reg_entry rgb_enable[] = {
38 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
39 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
40 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
41 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
42 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
43 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
44 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
45 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
46 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
47 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
48 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
49 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
50 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
51 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
52 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
53 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
54 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
55 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
56 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
57};
58
59static const struct reg_entry rgb_disable[] = {
60 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
61 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
62 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
63 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
64 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
65 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
66 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
67 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
68 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
69 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
70 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
71 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
72 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
73 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
74 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
75 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
76 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
77 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
78 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
79};
80
81static void tegra_dc_write_regs(struct tegra_dc *dc,
82 const struct reg_entry *table,
83 unsigned int num)
84{
85 unsigned int i;
86
87 for (i = 0; i < num; i++)
88 tegra_dc_writel(dc, table[i].value, table[i].offset);
89}
90
Thierry Reding3b0e5852014-12-16 18:30:16 +010091static void tegra_rgb_connector_dpms(struct drm_connector *connector,
92 int mode)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000093{
Thierry Reding3b0e5852014-12-16 18:30:16 +010094}
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000095
Thierry Reding3b0e5852014-12-16 18:30:16 +010096static const struct drm_connector_funcs tegra_rgb_connector_funcs = {
97 .dpms = tegra_rgb_connector_dpms,
Thierry Reding9d441892014-11-24 17:02:53 +010098 .reset = drm_atomic_helper_connector_reset,
Thierry Reding3b0e5852014-12-16 18:30:16 +010099 .detect = tegra_output_connector_detect,
100 .fill_modes = drm_helper_probe_single_connector_modes,
101 .destroy = tegra_output_connector_destroy,
Thierry Reding9d441892014-11-24 17:02:53 +0100102 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
Thierry Reding4aa3df72014-11-24 16:27:13 +0100103 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
Thierry Reding3b0e5852014-12-16 18:30:16 +0100104};
105
106static enum drm_mode_status
107tegra_rgb_connector_mode_valid(struct drm_connector *connector,
108 struct drm_display_mode *mode)
109{
110 /*
111 * FIXME: For now, always assume that the mode is okay. There are
112 * unresolved issues with clk_round_rate(), which doesn't always
113 * reliably report whether a frequency can be set or not.
114 */
115 return MODE_OK;
116}
117
118static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = {
119 .get_modes = tegra_output_connector_get_modes,
120 .mode_valid = tegra_rgb_connector_mode_valid,
121 .best_encoder = tegra_output_connector_best_encoder,
122};
123
124static const struct drm_encoder_funcs tegra_rgb_encoder_funcs = {
125 .destroy = tegra_output_encoder_destroy,
126};
127
128static void tegra_rgb_encoder_dpms(struct drm_encoder *encoder, int mode)
129{
130}
131
Thierry Reding3b0e5852014-12-16 18:30:16 +0100132static void tegra_rgb_encoder_prepare(struct drm_encoder *encoder)
133{
134}
135
136static void tegra_rgb_encoder_commit(struct drm_encoder *encoder)
137{
138}
139
140static void tegra_rgb_encoder_mode_set(struct drm_encoder *encoder,
141 struct drm_display_mode *mode,
142 struct drm_display_mode *adjusted)
143{
144 struct tegra_output *output = encoder_to_output(encoder);
145 struct tegra_rgb *rgb = to_rgb(output);
146 u32 value;
147
148 if (output->panel)
149 drm_panel_prepare(output->panel);
Dmitry Osipenkob1891532014-02-11 21:12:27 +0400150
Thierry Reding7602fa12013-10-30 09:55:33 +0100151 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000152
Thierry Reding72d30282013-12-12 11:06:55 +0100153 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
154 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
155
156 /* XXX: parameterize? */
157 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
158 value &= ~LVS_OUTPUT_POLARITY_LOW;
159 value &= ~LHS_OUTPUT_POLARITY_LOW;
160 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
161
162 /* XXX: parameterize? */
163 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
164 DISP_ORDER_RED_BLUE;
165 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
166
167 /* XXX: parameterize? */
168 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
169 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
170
Thierry Reding62b9e062014-11-21 17:33:33 +0100171 tegra_dc_commit(rgb->dc);
Thierry Reding72d30282013-12-12 11:06:55 +0100172
Thierry Reding3b0e5852014-12-16 18:30:16 +0100173 if (output->panel)
174 drm_panel_enable(output->panel);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000175}
176
Thierry Reding3b0e5852014-12-16 18:30:16 +0100177static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000178{
Thierry Reding3b0e5852014-12-16 18:30:16 +0100179 struct tegra_output *output = encoder_to_output(encoder);
Thierry Reding7602fa12013-10-30 09:55:33 +0100180 struct tegra_rgb *rgb = to_rgb(output);
Thierry Reding72d30282013-12-12 11:06:55 +0100181
Thierry Reding3b0e5852014-12-16 18:30:16 +0100182 if (output->panel)
183 drm_panel_disable(output->panel);
Thierry Reding72d30282013-12-12 11:06:55 +0100184
Thierry Reding7602fa12013-10-30 09:55:33 +0100185 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
Thierry Reding666cb872014-12-08 16:32:47 +0100186 tegra_dc_commit(rgb->dc);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000187
Thierry Reding3b0e5852014-12-16 18:30:16 +0100188 if (output->panel)
189 drm_panel_unprepare(output->panel);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000190}
191
Thierry Reding3cebae62014-12-17 17:04:36 +0100192static int
193tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
194 struct drm_crtc_state *crtc_state,
195 struct drm_connector_state *conn_state)
196{
197 struct tegra_output *output = encoder_to_output(encoder);
198 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
199 unsigned long pclk = crtc_state->mode.clock * 1000;
200 struct tegra_rgb *rgb = to_rgb(output);
201 unsigned int div;
202 int err;
203
204 /*
205 * We may not want to change the frequency of the parent clock, since
206 * it may be a parent for other peripherals. This is due to the fact
207 * that on Tegra20 there's only a single clock dedicated to display
208 * (pll_d_out0), whereas later generations have a second one that can
209 * be used to independently drive a second output (pll_d2_out0).
210 *
211 * As a way to support multiple outputs on Tegra20 as well, pll_p is
212 * typically used as the parent clock for the display controllers.
213 * But this comes at a cost: pll_p is the parent of several other
214 * peripherals, so its frequency shouldn't change out of the blue.
215 *
216 * The best we can do at this point is to use the shift clock divider
217 * and hope that the desired frequency can be matched (or at least
218 * matched sufficiently close that the panel will still work).
219 */
220 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
221 pclk = 0;
222
223 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
224 pclk, div);
225 if (err < 0) {
226 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
227 return err;
228 }
229
230 return err;
231}
232
Thierry Reding3b0e5852014-12-16 18:30:16 +0100233static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
234 .dpms = tegra_rgb_encoder_dpms,
Thierry Reding3b0e5852014-12-16 18:30:16 +0100235 .prepare = tegra_rgb_encoder_prepare,
236 .commit = tegra_rgb_encoder_commit,
237 .mode_set = tegra_rgb_encoder_mode_set,
238 .disable = tegra_rgb_encoder_disable,
Thierry Reding3cebae62014-12-17 17:04:36 +0100239 .atomic_check = tegra_rgb_encoder_atomic_check,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000240};
241
242int tegra_dc_rgb_probe(struct tegra_dc *dc)
243{
244 struct device_node *np;
245 struct tegra_rgb *rgb;
246 int err;
247
248 np = of_get_child_by_name(dc->dev->of_node, "rgb");
249 if (!np || !of_device_is_available(np))
250 return -ENODEV;
251
252 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
253 if (!rgb)
254 return -ENOMEM;
255
Thierry Reding03da0e72013-08-30 15:27:16 +0200256 rgb->output.dev = dc->dev;
257 rgb->output.of_node = np;
Thierry Reding7602fa12013-10-30 09:55:33 +0100258 rgb->dc = dc;
Thierry Reding03da0e72013-08-30 15:27:16 +0200259
Thierry Reding59d29c02013-10-14 14:26:42 +0200260 err = tegra_output_probe(&rgb->output);
Thierry Reding03da0e72013-08-30 15:27:16 +0200261 if (err < 0)
262 return err;
263
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000264 rgb->clk = devm_clk_get(dc->dev, NULL);
265 if (IS_ERR(rgb->clk)) {
266 dev_err(dc->dev, "failed to get clock\n");
267 return PTR_ERR(rgb->clk);
268 }
269
270 rgb->clk_parent = devm_clk_get(dc->dev, "parent");
271 if (IS_ERR(rgb->clk_parent)) {
272 dev_err(dc->dev, "failed to get parent clock\n");
273 return PTR_ERR(rgb->clk_parent);
274 }
275
276 err = clk_set_parent(rgb->clk, rgb->clk_parent);
277 if (err < 0) {
278 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
279 return err;
280 }
281
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000282 dc->rgb = &rgb->output;
283
284 return 0;
285}
286
Thierry Reding59d29c02013-10-14 14:26:42 +0200287int tegra_dc_rgb_remove(struct tegra_dc *dc)
288{
Thierry Reding59d29c02013-10-14 14:26:42 +0200289 if (!dc->rgb)
290 return 0;
291
Thierry Reding328ec692014-12-19 15:55:08 +0100292 tegra_output_remove(dc->rgb);
Thierry Reding3b0e5852014-12-16 18:30:16 +0100293 dc->rgb = NULL;
294
Thierry Reding59d29c02013-10-14 14:26:42 +0200295 return 0;
296}
297
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000298int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
299{
Thierry Reding3b0e5852014-12-16 18:30:16 +0100300 struct tegra_output *output = dc->rgb;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000301 int err;
302
303 if (!dc->rgb)
304 return -ENODEV;
305
Thierry Reding3b0e5852014-12-16 18:30:16 +0100306 drm_connector_init(drm, &output->connector, &tegra_rgb_connector_funcs,
307 DRM_MODE_CONNECTOR_LVDS);
308 drm_connector_helper_add(&output->connector,
309 &tegra_rgb_connector_helper_funcs);
310 output->connector.dpms = DRM_MODE_DPMS_OFF;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000311
Thierry Reding3b0e5852014-12-16 18:30:16 +0100312 drm_encoder_init(drm, &output->encoder, &tegra_rgb_encoder_funcs,
313 DRM_MODE_ENCODER_LVDS);
314 drm_encoder_helper_add(&output->encoder,
315 &tegra_rgb_encoder_helper_funcs);
316
317 drm_mode_connector_attach_encoder(&output->connector,
318 &output->encoder);
319 drm_connector_register(&output->connector);
320
Thierry Redingea130b22014-12-19 15:51:35 +0100321 err = tegra_output_init(drm, output);
322 if (err < 0) {
323 dev_err(output->dev, "failed to initialize output: %d\n", err);
324 return err;
325 }
326
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000327 /*
Thierry Reding3b0e5852014-12-16 18:30:16 +0100328 * Other outputs can be attached to either display controller. The RGB
329 * outputs are an exception and work only with their parent display
330 * controller.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000331 */
Thierry Reding3b0e5852014-12-16 18:30:16 +0100332 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000333
334 return 0;
335}
336
337int tegra_dc_rgb_exit(struct tegra_dc *dc)
338{
Thierry Reding328ec692014-12-19 15:55:08 +0100339 if (dc->rgb)
340 tegra_output_exit(dc->rgb);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000341
Thierry Reding328ec692014-12-19 15:55:08 +0100342 return 0;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000343}