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Marc Zyngier021f6532014-06-30 16:01:31 +01001/*
2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
19#define __LINUX_IRQCHIP_ARM_GIC_V3_H
20
21/*
22 * Distributor registers. We assume we're running non-secure, with ARE
23 * being set. Secure-only and non-ARE registers are not described.
24 */
25#define GICD_CTLR 0x0000
26#define GICD_TYPER 0x0004
27#define GICD_IIDR 0x0008
28#define GICD_STATUSR 0x0010
29#define GICD_SETSPI_NSR 0x0040
30#define GICD_CLRSPI_NSR 0x0048
31#define GICD_SETSPI_SR 0x0050
32#define GICD_CLRSPI_SR 0x0058
33#define GICD_SEIR 0x0068
Andre Przywaraa0675c22014-06-07 00:54:51 +020034#define GICD_IGROUPR 0x0080
Marc Zyngier021f6532014-06-30 16:01:31 +010035#define GICD_ISENABLER 0x0100
36#define GICD_ICENABLER 0x0180
37#define GICD_ISPENDR 0x0200
38#define GICD_ICPENDR 0x0280
39#define GICD_ISACTIVER 0x0300
40#define GICD_ICACTIVER 0x0380
41#define GICD_IPRIORITYR 0x0400
42#define GICD_ICFGR 0x0C00
Andre Przywaraa0675c22014-06-07 00:54:51 +020043#define GICD_IGRPMODR 0x0D00
44#define GICD_NSACR 0x0E00
Marc Zyngier021f6532014-06-30 16:01:31 +010045#define GICD_IROUTER 0x6000
Andre Przywaraa0675c22014-06-07 00:54:51 +020046#define GICD_IDREGS 0xFFD0
Marc Zyngier021f6532014-06-30 16:01:31 +010047#define GICD_PIDR2 0xFFE8
48
Andre Przywaraa0675c22014-06-07 00:54:51 +020049/*
50 * Those registers are actually from GICv2, but the spec demands that they
51 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
52 */
53#define GICD_ITARGETSR 0x0800
54#define GICD_SGIR 0x0F00
55#define GICD_CPENDSGIR 0x0F10
56#define GICD_SPENDSGIR 0x0F20
57
Marc Zyngier021f6532014-06-30 16:01:31 +010058#define GICD_CTLR_RWP (1U << 31)
Andre Przywaraa0675c22014-06-07 00:54:51 +020059#define GICD_CTLR_DS (1U << 6)
Marc Zyngier021f6532014-06-30 16:01:31 +010060#define GICD_CTLR_ARE_NS (1U << 4)
61#define GICD_CTLR_ENABLE_G1A (1U << 1)
62#define GICD_CTLR_ENABLE_G1 (1U << 0)
63
Andre Przywaraa0675c22014-06-07 00:54:51 +020064/*
65 * In systems with a single security state (what we emulate in KVM)
66 * the meaning of the interrupt group enable bits is slightly different
67 */
68#define GICD_CTLR_ENABLE_SS_G1 (1U << 1)
69#define GICD_CTLR_ENABLE_SS_G0 (1U << 0)
70
71#define GICD_TYPER_LPIS (1U << 17)
72#define GICD_TYPER_MBIS (1U << 16)
73
Marc Zyngierf5c14342014-11-24 14:35:10 +000074#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
75#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
76#define GICD_TYPER_LPIS (1U << 17)
77
Marc Zyngier021f6532014-06-30 16:01:31 +010078#define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
79#define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
80
81#define GIC_PIDR2_ARCH_MASK 0xf0
82#define GIC_PIDR2_ARCH_GICv3 0x30
83#define GIC_PIDR2_ARCH_GICv4 0x40
84
Andre Przywaraa0675c22014-06-07 00:54:51 +020085#define GIC_V3_DIST_SIZE 0x10000
86
Marc Zyngier021f6532014-06-30 16:01:31 +010087/*
88 * Re-Distributor registers, offsets from RD_base
89 */
90#define GICR_CTLR GICD_CTLR
91#define GICR_IIDR 0x0004
92#define GICR_TYPER 0x0008
93#define GICR_STATUSR GICD_STATUSR
94#define GICR_WAKER 0x0014
95#define GICR_SETLPIR 0x0040
96#define GICR_CLRLPIR 0x0048
97#define GICR_SEIR GICD_SEIR
98#define GICR_PROPBASER 0x0070
99#define GICR_PENDBASER 0x0078
100#define GICR_INVLPIR 0x00A0
101#define GICR_INVALLR 0x00B0
102#define GICR_SYNCR 0x00C0
103#define GICR_MOVLPIR 0x0100
104#define GICR_MOVALLR 0x0110
Andre Przywaraa0675c22014-06-07 00:54:51 +0200105#define GICR_IDREGS GICD_IDREGS
Marc Zyngier021f6532014-06-30 16:01:31 +0100106#define GICR_PIDR2 GICD_PIDR2
107
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000108#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
109
110#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
111
Marc Zyngier021f6532014-06-30 16:01:31 +0100112#define GICR_WAKER_ProcessorSleep (1U << 1)
113#define GICR_WAKER_ChildrenAsleep (1U << 2)
114
Andre Przywara645b9e42016-07-15 12:43:28 +0100115#define GIC_BASER_CACHE_nCnB 0ULL
116#define GIC_BASER_CACHE_SameAsInner 0ULL
117#define GIC_BASER_CACHE_nC 1ULL
118#define GIC_BASER_CACHE_RaWt 2ULL
119#define GIC_BASER_CACHE_RaWb 3ULL
120#define GIC_BASER_CACHE_WaWt 4ULL
121#define GIC_BASER_CACHE_WaWb 5ULL
122#define GIC_BASER_CACHE_RaWaWt 6ULL
123#define GIC_BASER_CACHE_RaWaWb 7ULL
124#define GIC_BASER_CACHE_MASK 7ULL
125#define GIC_BASER_NonShareable 0ULL
126#define GIC_BASER_InnerShareable 1ULL
127#define GIC_BASER_OuterShareable 2ULL
128#define GIC_BASER_SHAREABILITY_MASK 3ULL
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000129
Andre Przywara645b9e42016-07-15 12:43:28 +0100130#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
131 (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
132
133#define GIC_BASER_SHAREABILITY(reg, type) \
134 (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
135
136#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
137#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
138#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
139#define GICR_PROPBASER_SHAREABILITY_MASK \
140 GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
141#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
142 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
143#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
144 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
145#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
146
147#define GICR_PROPBASER_InnerShareable \
148 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
Marc Zyngier8c828a52016-07-18 15:28:52 +0100149
150#define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
151#define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
152#define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
153#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
154#define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
155#define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
156#define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
157#define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
158
Andre Przywara645b9e42016-07-15 12:43:28 +0100159#define GICR_PROPBASER_IDBITS_MASK (0x1f)
160
161#define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
162#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
163#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
164#define GICR_PENDBASER_SHAREABILITY_MASK \
165 GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
166#define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
167 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
168#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
169 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
170#define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
171
172#define GICR_PENDBASER_InnerShareable \
173 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
Marc Zyngier8c828a52016-07-18 15:28:52 +0100174
175#define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
176#define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
177#define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
178#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
179#define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
180#define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
181#define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
182#define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
183
Andre Przywara645b9e42016-07-15 12:43:28 +0100184#define GICR_PENDBASER_PTZ BIT_ULL(62)
Marc Zyngier4ad3e362015-03-27 14:15:04 +0000185
Marc Zyngier021f6532014-06-30 16:01:31 +0100186/*
187 * Re-Distributor registers, offsets from SGI_base
188 */
Andre Przywaraa0675c22014-06-07 00:54:51 +0200189#define GICR_IGROUPR0 GICD_IGROUPR
Marc Zyngier021f6532014-06-30 16:01:31 +0100190#define GICR_ISENABLER0 GICD_ISENABLER
191#define GICR_ICENABLER0 GICD_ICENABLER
192#define GICR_ISPENDR0 GICD_ISPENDR
193#define GICR_ICPENDR0 GICD_ICPENDR
194#define GICR_ISACTIVER0 GICD_ISACTIVER
195#define GICR_ICACTIVER0 GICD_ICACTIVER
196#define GICR_IPRIORITYR0 GICD_IPRIORITYR
197#define GICR_ICFGR0 GICD_ICFGR
Andre Przywaraa0675c22014-06-07 00:54:51 +0200198#define GICR_IGRPMODR0 GICD_IGRPMODR
199#define GICR_NSACR GICD_NSACR
Marc Zyngier021f6532014-06-30 16:01:31 +0100200
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000201#define GICR_TYPER_PLPIS (1U << 0)
Marc Zyngier021f6532014-06-30 16:01:31 +0100202#define GICR_TYPER_VLPIS (1U << 1)
203#define GICR_TYPER_LAST (1U << 4)
204
Andre Przywaraa0675c22014-06-07 00:54:51 +0200205#define GIC_V3_REDIST_SIZE 0x20000
206
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000207#define LPI_PROP_GROUP1 (1 << 1)
208#define LPI_PROP_ENABLED (1 << 0)
209
210/*
211 * ITS registers, offsets from ITS_base
212 */
213#define GITS_CTLR 0x0000
214#define GITS_IIDR 0x0004
215#define GITS_TYPER 0x0008
216#define GITS_CBASER 0x0080
217#define GITS_CWRITER 0x0088
218#define GITS_CREADR 0x0090
219#define GITS_BASER 0x0100
Andre Przywara645b9e42016-07-15 12:43:28 +0100220#define GITS_IDREGS_BASE 0xffd0
221#define GITS_PIDR0 0xffe0
222#define GITS_PIDR1 0xffe4
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000223#define GITS_PIDR2 GICR_PIDR2
Andre Przywara645b9e42016-07-15 12:43:28 +0100224#define GITS_PIDR4 0xffd0
225#define GITS_CIDR0 0xfff0
226#define GITS_CIDR1 0xfff4
227#define GITS_CIDR2 0xfff8
228#define GITS_CIDR3 0xfffc
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000229
230#define GITS_TRANSLATER 0x10040
231
Yun Wu7cb99112015-03-06 16:37:49 +0000232#define GITS_CTLR_ENABLE (1U << 0)
233#define GITS_CTLR_QUIESCENT (1U << 31)
234
Andre Przywara645b9e42016-07-15 12:43:28 +0100235#define GITS_TYPER_PLPIS (1UL << 0)
236#define GITS_TYPER_IDBITS_SHIFT 8
Marc Zyngierf54b97e2015-03-06 16:37:41 +0000237#define GITS_TYPER_DEVBITS_SHIFT 13
238#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000239#define GITS_TYPER_PTA (1UL << 19)
Andre Przywara645b9e42016-07-15 12:43:28 +0100240#define GITS_TYPER_HWCOLLCNT_SHIFT 24
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000241
Andre Przywara645b9e42016-07-15 12:43:28 +0100242#define GITS_CBASER_VALID (1UL << 63)
243#define GITS_CBASER_SHAREABILITY_SHIFT (10)
244#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
245#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
246#define GITS_CBASER_SHAREABILITY_MASK \
247 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
248#define GITS_CBASER_INNER_CACHEABILITY_MASK \
249 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
250#define GITS_CBASER_OUTER_CACHEABILITY_MASK \
251 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
252#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
253
254#define GITS_CBASER_InnerShareable \
255 GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
Marc Zyngier8c828a52016-07-18 15:28:52 +0100256
257#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
258#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
259#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
260#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
261#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
262#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
263#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
264#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000265
266#define GITS_BASER_NR_REGS 8
267
Andre Przywara645b9e42016-07-15 12:43:28 +0100268#define GITS_BASER_VALID (1UL << 63)
269#define GITS_BASER_INDIRECT (1ULL << 62)
Marc Zyngier8c828a52016-07-18 15:28:52 +0100270
Andre Przywara645b9e42016-07-15 12:43:28 +0100271#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
272#define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
273#define GITS_BASER_INNER_CACHEABILITY_MASK \
274 GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
Marc Zyngier8c828a52016-07-18 15:28:52 +0100275#define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK
Andre Przywara645b9e42016-07-15 12:43:28 +0100276#define GITS_BASER_OUTER_CACHEABILITY_MASK \
277 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
278#define GITS_BASER_SHAREABILITY_MASK \
279 GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)
280
Marc Zyngier8c828a52016-07-18 15:28:52 +0100281#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
282#define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
283#define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
284#define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
285#define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
286#define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
287#define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
288#define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)
289
Andre Przywara645b9e42016-07-15 12:43:28 +0100290#define GITS_BASER_TYPE_SHIFT (56)
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000291#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
Andre Przywara645b9e42016-07-15 12:43:28 +0100292#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000293#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1)
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000294#define GITS_BASER_SHAREABILITY_SHIFT (10)
Andre Przywara645b9e42016-07-15 12:43:28 +0100295#define GITS_BASER_InnerShareable \
296 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000297#define GITS_BASER_PAGE_SIZE_SHIFT (8)
298#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT)
299#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT)
300#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT)
301#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT)
Robert Richter30f21362015-09-21 22:58:34 +0200302#define GITS_BASER_PAGES_MAX 256
Shanker Donthineni93473592016-06-06 18:17:30 -0500303#define GITS_BASER_PAGES_SHIFT (0)
Andre Przywara645b9e42016-07-15 12:43:28 +0100304#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000305
306#define GITS_BASER_TYPE_NONE 0
307#define GITS_BASER_TYPE_DEVICE 1
308#define GITS_BASER_TYPE_VCPU 2
309#define GITS_BASER_TYPE_CPU 3
310#define GITS_BASER_TYPE_COLLECTION 4
311#define GITS_BASER_TYPE_RESERVED5 5
312#define GITS_BASER_TYPE_RESERVED6 6
313#define GITS_BASER_TYPE_RESERVED7 7
314
Shanker Donthineni3faf24e2016-06-06 18:17:32 -0500315#define GITS_LVL1_ENTRY_SIZE (8UL)
316
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000317/*
318 * ITS commands
319 */
320#define GITS_CMD_MAPD 0x08
321#define GITS_CMD_MAPC 0x09
Andre Przywara645b9e42016-07-15 12:43:28 +0100322#define GITS_CMD_MAPTI 0x0a
323/* older GIC documentation used MAPVI for this command */
324#define GITS_CMD_MAPVI GITS_CMD_MAPTI
325#define GITS_CMD_MAPI 0x0b
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000326#define GITS_CMD_MOVI 0x01
327#define GITS_CMD_DISCARD 0x0f
328#define GITS_CMD_INV 0x0c
329#define GITS_CMD_MOVALL 0x0e
330#define GITS_CMD_INVALL 0x0d
331#define GITS_CMD_INT 0x03
332#define GITS_CMD_CLEAR 0x04
333#define GITS_CMD_SYNC 0x05
334
Marc Zyngier021f6532014-06-30 16:01:31 +0100335/*
Andre Przywara645b9e42016-07-15 12:43:28 +0100336 * ITS error numbers
337 */
338#define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107
339#define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109
Andre Przywarafd837b02016-08-08 17:29:28 +0100340#define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307
Andre Przywara645b9e42016-07-15 12:43:28 +0100341#define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
342#define E_ITS_MAPD_DEVICE_OOR 0x010801
343#define E_ITS_MAPC_PROCNUM_OOR 0x010902
344#define E_ITS_MAPC_COLLECTION_OOR 0x010903
345#define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
346#define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
347#define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
348#define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
349#define E_ITS_MOVALL_PROCNUM_OOR 0x010e01
350#define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07
351
352/*
Marc Zyngier021f6532014-06-30 16:01:31 +0100353 * CPU interface registers
354 */
355#define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1)
356#define ICC_CTLR_EL1_EOImode_drop (1U << 1)
357#define ICC_SRE_EL1_SRE (1U << 0)
358
359/*
360 * Hypervisor interface registers (SRE only)
361 */
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100362#define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
Marc Zyngier021f6532014-06-30 16:01:31 +0100363
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100364#define ICH_LR_EOI (1ULL << 41)
365#define ICH_LR_GROUP (1ULL << 60)
366#define ICH_LR_HW (1ULL << 61)
367#define ICH_LR_STATE (3ULL << 62)
368#define ICH_LR_PENDING_BIT (1ULL << 62)
369#define ICH_LR_ACTIVE_BIT (1ULL << 63)
Marc Zyngierfb182cf2015-06-08 15:37:26 +0100370#define ICH_LR_PHYS_ID_SHIFT 32
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100371#define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
Marc Zyngier59529f62015-11-30 13:09:53 +0000372#define ICH_LR_PRIORITY_SHIFT 48
Marc Zyngier021f6532014-06-30 16:01:31 +0100373
Andre Przywara44bfc422016-05-04 14:35:48 +0100374/* These are for GICv2 emulation only */
375#define GICH_LR_VIRTUALID (0x3ffUL << 0)
376#define GICH_LR_PHYSID_CPUID_SHIFT (10)
377#define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
Marc Zyngier021f6532014-06-30 16:01:31 +0100378
379#define ICH_MISR_EOI (1 << 0)
380#define ICH_MISR_U (1 << 1)
381
382#define ICH_HCR_EN (1 << 0)
383#define ICH_HCR_UIE (1 << 1)
384
385#define ICH_VMCR_CTLR_SHIFT 0
386#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT)
387#define ICH_VMCR_BPR1_SHIFT 18
388#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
389#define ICH_VMCR_BPR0_SHIFT 21
390#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
391#define ICH_VMCR_PMR_SHIFT 24
392#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
393
Marc Zyngier021f6532014-06-30 16:01:31 +0100394#define ICC_IAR1_EL1_SPURIOUS 0x3ff
395
Marc Zyngier021f6532014-06-30 16:01:31 +0100396#define ICC_SRE_EL2_SRE (1 << 0)
397#define ICC_SRE_EL2_ENABLE (1 << 3)
398
Andre Przywara7e580272014-11-12 13:46:06 +0000399#define ICC_SGI1R_TARGET_LIST_SHIFT 0
400#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
401#define ICC_SGI1R_AFFINITY_1_SHIFT 16
402#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
403#define ICC_SGI1R_SGI_ID_SHIFT 24
Marc Zyngierdd5f1b02016-06-02 09:00:28 +0100404#define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
Andre Przywara7e580272014-11-12 13:46:06 +0000405#define ICC_SGI1R_AFFINITY_2_SHIFT 32
Andrew Jonesfab0cdc2016-05-12 10:46:34 +0200406#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
Andre Przywara7e580272014-11-12 13:46:06 +0000407#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
408#define ICC_SGI1R_AFFINITY_3_SHIFT 48
Andrew Jonesfab0cdc2016-05-12 10:46:34 +0200409#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
Andre Przywara7e580272014-11-12 13:46:06 +0000410
Jean-Philippe Brucker7936e912015-10-01 13:47:14 +0100411#include <asm/arch_gicv3.h>
Marc Zyngier021f6532014-06-30 16:01:31 +0100412
413#ifndef __ASSEMBLY__
414
Marc Zyngierb48ac832014-11-24 14:35:16 +0000415/*
416 * We need a value to serve as a irq-type for LPIs. Choose one that will
417 * hopefully pique the interest of the reviewer.
418 */
419#define GIC_IRQ_TYPE_LPI 0xa110c8ed
420
Marc Zyngierf5c14342014-11-24 14:35:10 +0000421struct rdists {
422 struct {
423 void __iomem *rd_base;
424 struct page *pend_page;
425 phys_addr_t phys_base;
426 } __percpu *rdist;
427 struct page *prop_page;
428 int id_bits;
429 u64 flags;
430};
431
Marc Zyngierda33f312014-11-24 14:35:18 +0000432struct irq_domain;
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +0200433struct fwnode_handle;
Marc Zyngierda33f312014-11-24 14:35:18 +0000434int its_cpu_init(void);
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +0200435int its_init(struct fwnode_handle *handle, struct rdists *rdists,
Marc Zyngierda33f312014-11-24 14:35:18 +0000436 struct irq_domain *domain);
437
Jean-Philippe Brucker7936e912015-10-01 13:47:14 +0100438static inline bool gic_enable_sre(void)
439{
440 u32 val;
441
442 val = gic_read_sre();
443 if (val & ICC_SRE_EL1_SRE)
444 return true;
445
446 val |= ICC_SRE_EL1_SRE;
447 gic_write_sre(val);
448 val = gic_read_sre();
449
450 return !!(val & ICC_SRE_EL1_SRE);
451}
452
Marc Zyngier021f6532014-06-30 16:01:31 +0100453#endif
454
455#endif