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gerrit-public.fairphone.software / kernel / msm-4.9 / 68d41f23ce8d049d05bdd96889d3a2504e7f21f0 / . / arch / arm / boot / dts / am33xx.dtsi
blob: 831810583823b78f735a11b354c715461f376401 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 };
39
40 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]41 #address-cells = <1>;
42 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 cpu@0 {
44 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]45 device_type = "cpu";
46 reg = <0>;
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]66 };
67 };
68
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]74 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +0100[diff] [blame]75 * The soc node represents the soc top level view. It is used for IPs
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]86 am33xx_pinmux: pinmux@44e10800 {
87 compatible = "pinctrl-single";
88 reg = <0x44e10800 0x0238>;
89 #address-cells = <1>;
90 #size-cells = <0>;
91 pinctrl-single,register-width = <32>;
92 pinctrl-single,function-mask = <0x7f>;
93 };
94
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]95 /*
96 * XXX: Use a flat representation of the AM33XX interconnect.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]97 * The real AM33XX interconnect network is quite complex. Since
98 * it will not bring real advantage to represent that in DT
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]99 * for the moment, just use a fake OCP bus entry to represent
100 * the whole bus hierarchy.
101 */
102 ocp {
103 compatible = "simple-bus";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 ranges;
107 ti,hwmods = "l3_main";
108
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]109 prcm: prcm@44e00000 {
110 compatible = "ti,am3-prcm";
111 reg = <0x44e00000 0x4000>;
112
113 prcm_clocks: clocks {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 };
117
118 prcm_clockdomains: clockdomains {
119 };
120 };
121
122 scrm: scrm@44e10000 {
123 compatible = "ti,am3-scrm";
124 reg = <0x44e10000 0x2000>;
125
126 scrm_clocks: clocks {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 };
130
131 scrm_clockdomains: clockdomains {
132 };
133 };
134
Markus Pargmannc9aaf872014-09-29 08:53:18 +0200[diff] [blame]135 cm: syscon@44e10000 {
136 compatible = "ti,am33xx-controlmodule", "syscon";
137 reg = <0x44e10000 0x800>;
138 };
139
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]140 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]141 compatible = "ti,am33xx-intc";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]142 interrupt-controller;
143 #interrupt-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]144 reg = <0x48200000 0x1000>;
145 };
146
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]147 edma: edma@49000000 {
148 compatible = "ti,edma3";
149 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
150 reg = <0x49000000 0x10000>,
Thomas Gleixnercf7eb972014-04-13 20:44:46 +0200[diff] [blame]151 <0x44e10f90 0x40>;
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]152 interrupts = <12 13 14>;
153 #dma-cells = <1>;
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]154 };
155
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]156 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]157 compatible = "ti,omap4-gpio";
158 ti,hwmods = "gpio1";
159 gpio-controller;
160 #gpio-cells = <2>;
161 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]162 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]163 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]164 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]165 };
166
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]167 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]168 compatible = "ti,omap4-gpio";
169 ti,hwmods = "gpio2";
170 gpio-controller;
171 #gpio-cells = <2>;
172 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]173 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]174 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]175 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]176 };
177
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]178 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]179 compatible = "ti,omap4-gpio";
180 ti,hwmods = "gpio3";
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]184 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]185 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]186 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]187 };
188
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]189 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]190 compatible = "ti,omap4-gpio";
191 ti,hwmods = "gpio4";
192 gpio-controller;
193 #gpio-cells = <2>;
194 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]195 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]196 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]197 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]198 };
199
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]200 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]201 compatible = "ti,omap3-uart";
202 ti,hwmods = "uart1";
203 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]204 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]205 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]206 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]207 };
208
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]209 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]210 compatible = "ti,omap3-uart";
211 ti,hwmods = "uart2";
212 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]213 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]214 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]215 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]216 };
217
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]218 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]219 compatible = "ti,omap3-uart";
220 ti,hwmods = "uart3";
221 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]222 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]223 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]224 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]225 };
226
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]227 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]228 compatible = "ti,omap3-uart";
229 ti,hwmods = "uart4";
230 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]231 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]232 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]233 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]234 };
235
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]236 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]237 compatible = "ti,omap3-uart";
238 ti,hwmods = "uart5";
239 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]240 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]241 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]242 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]243 };
244
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]245 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]246 compatible = "ti,omap3-uart";
247 ti,hwmods = "uart6";
248 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]249 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]250 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]251 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]252 };
253
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]254 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]255 compatible = "ti,omap4-i2c";
256 #address-cells = <1>;
257 #size-cells = <0>;
258 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]259 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]260 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]261 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]262 };
263
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]264 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]265 compatible = "ti,omap4-i2c";
266 #address-cells = <1>;
267 #size-cells = <0>;
268 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]269 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]270 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]271 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]272 };
273
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]274 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]275 compatible = "ti,omap4-i2c";
276 #address-cells = <1>;
277 #size-cells = <0>;
278 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]279 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]280 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]281 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]282 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]283
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]284 mmc1: mmc@48060000 {
285 compatible = "ti,omap4-hsmmc";
286 ti,hwmods = "mmc1";
287 ti,dual-volt;
288 ti,needs-special-reset;
289 ti,needs-special-hs-handling;
290 dmas = <&edma 24
291 &edma 25>;
292 dma-names = "tx", "rx";
293 interrupts = <64>;
294 interrupt-parent = <&intc>;
295 reg = <0x48060000 0x1000>;
296 status = "disabled";
297 };
298
299 mmc2: mmc@481d8000 {
300 compatible = "ti,omap4-hsmmc";
301 ti,hwmods = "mmc2";
302 ti,needs-special-reset;
303 dmas = <&edma 2
304 &edma 3>;
305 dma-names = "tx", "rx";
306 interrupts = <28>;
307 interrupt-parent = <&intc>;
308 reg = <0x481d8000 0x1000>;
309 status = "disabled";
310 };
311
312 mmc3: mmc@47810000 {
313 compatible = "ti,omap4-hsmmc";
314 ti,hwmods = "mmc3";
315 ti,needs-special-reset;
316 interrupts = <29>;
317 interrupt-parent = <&intc>;
318 reg = <0x47810000 0x1000>;
319 status = "disabled";
320 };
321
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]322 hwspinlock: spinlock@480ca000 {
323 compatible = "ti,omap4-hwspinlock";
324 reg = <0x480ca000 0x1000>;
325 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]326 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]327 };
328
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]329 wdt2: wdt@44e35000 {
330 compatible = "ti,omap3-wdt";
331 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]332 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]333 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]334 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]335
336 dcan0: d_can@481cc000 {
337 compatible = "bosch,d_can";
338 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]339 reg = <0x481cc000 0x2000
340 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]341 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]342 status = "disabled";
343 };
344
345 dcan1: d_can@481d0000 {
346 compatible = "bosch,d_can";
347 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]348 reg = <0x481d0000 0x2000
349 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]350 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]351 status = "disabled";
352 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]353
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]354 mailbox: mailbox@480C8000 {
355 compatible = "ti,omap4-mailbox";
356 reg = <0x480C8000 0x200>;
357 interrupts = <77>;
358 ti,hwmods = "mailbox";
359 ti,mbox-num-users = <4>;
360 ti,mbox-num-fifos = <8>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]361 mbox_wkupm3: wkup_m3 {
362 ti,mbox-tx = <0 0 0>;
363 ti,mbox-rx = <0 0 3>;
364 };
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]365 };
366
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]367 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]368 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]369 reg = <0x44e31000 0x400>;
370 interrupts = <67>;
371 ti,hwmods = "timer1";
372 ti,timer-alwon;
373 };
374
375 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]376 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]377 reg = <0x48040000 0x400>;
378 interrupts = <68>;
379 ti,hwmods = "timer2";
380 };
381
382 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]383 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]384 reg = <0x48042000 0x400>;
385 interrupts = <69>;
386 ti,hwmods = "timer3";
387 };
388
389 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]390 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]391 reg = <0x48044000 0x400>;
392 interrupts = <92>;
393 ti,hwmods = "timer4";
394 ti,timer-pwm;
395 };
396
397 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]398 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]399 reg = <0x48046000 0x400>;
400 interrupts = <93>;
401 ti,hwmods = "timer5";
402 ti,timer-pwm;
403 };
404
405 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]406 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]407 reg = <0x48048000 0x400>;
408 interrupts = <94>;
409 ti,hwmods = "timer6";
410 ti,timer-pwm;
411 };
412
413 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]414 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]415 reg = <0x4804a000 0x400>;
416 interrupts = <95>;
417 ti,hwmods = "timer7";
418 ti,timer-pwm;
419 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]420
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]421 rtc: rtc@44e3e000 {
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]422 compatible = "ti,da830-rtc";
423 reg = <0x44e3e000 0x1000>;
424 interrupts = <75
425 76>;
426 ti,hwmods = "rtc";
427 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]428
429 spi0: spi@48030000 {
430 compatible = "ti,omap4-mcspi";
431 #address-cells = <1>;
432 #size-cells = <0>;
433 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]434 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]435 ti,spi-num-cs = <2>;
436 ti,hwmods = "spi0";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]437 dmas = <&edma 16
438 &edma 17
439 &edma 18
440 &edma 19>;
441 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]442 status = "disabled";
443 };
444
445 spi1: spi@481a0000 {
446 compatible = "ti,omap4-mcspi";
447 #address-cells = <1>;
448 #size-cells = <0>;
449 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]450 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]451 ti,spi-num-cs = <2>;
452 ti,hwmods = "spi1";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]453 dmas = <&edma 42
454 &edma 43
455 &edma 44
456 &edma 45>;
457 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]458 status = "disabled";
459 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]460
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]461 usb: usb@47400000 {
462 compatible = "ti,am33xx-usb";
463 reg = <0x47400000 0x1000>;
464 ranges;
465 #address-cells = <1>;
466 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]467 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]468 status = "disabled";
469
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]470 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]471 compatible = "ti,am335x-usb-ctrl-module";
472 reg = <0x44e10620 0x10
473 0x44e10648 0x4>;
474 reg-names = "phy_ctrl", "wakeup";
475 status = "disabled";
476 };
477
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]478 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]479 compatible = "ti,am335x-usb-phy";
480 reg = <0x47401300 0x100>;
481 reg-names = "phy";
482 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]483 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]484 };
485
486 usb0: usb@47401000 {
487 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]488 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]489 reg = <0x47401400 0x400
490 0x47401000 0x200>;
491 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]492
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]493 interrupts = <18>;
494 interrupt-names = "mc";
495 dr_mode = "otg";
496 mentor,multipoint = <1>;
497 mentor,num-eps = <16>;
498 mentor,ram-bits = <12>;
499 mentor,power = <500>;
500 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]501
502 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
503 &cppi41dma 2 0 &cppi41dma 3 0
504 &cppi41dma 4 0 &cppi41dma 5 0
505 &cppi41dma 6 0 &cppi41dma 7 0
506 &cppi41dma 8 0 &cppi41dma 9 0
507 &cppi41dma 10 0 &cppi41dma 11 0
508 &cppi41dma 12 0 &cppi41dma 13 0
509 &cppi41dma 14 0 &cppi41dma 0 1
510 &cppi41dma 1 1 &cppi41dma 2 1
511 &cppi41dma 3 1 &cppi41dma 4 1
512 &cppi41dma 5 1 &cppi41dma 6 1
513 &cppi41dma 7 1 &cppi41dma 8 1
514 &cppi41dma 9 1 &cppi41dma 10 1
515 &cppi41dma 11 1 &cppi41dma 12 1
516 &cppi41dma 13 1 &cppi41dma 14 1>;
517 dma-names =
518 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
519 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
520 "rx14", "rx15",
521 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
522 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
523 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]524 };
525
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]526 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]527 compatible = "ti,am335x-usb-phy";
528 reg = <0x47401b00 0x100>;
529 reg-names = "phy";
530 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]531 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]532 };
533
534 usb1: usb@47401800 {
535 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]536 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]537 reg = <0x47401c00 0x400
538 0x47401800 0x200>;
539 reg-names = "mc", "control";
540 interrupts = <19>;
541 interrupt-names = "mc";
542 dr_mode = "otg";
543 mentor,multipoint = <1>;
544 mentor,num-eps = <16>;
545 mentor,ram-bits = <12>;
546 mentor,power = <500>;
547 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]548
549 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
550 &cppi41dma 17 0 &cppi41dma 18 0
551 &cppi41dma 19 0 &cppi41dma 20 0
552 &cppi41dma 21 0 &cppi41dma 22 0
553 &cppi41dma 23 0 &cppi41dma 24 0
554 &cppi41dma 25 0 &cppi41dma 26 0
555 &cppi41dma 27 0 &cppi41dma 28 0
556 &cppi41dma 29 0 &cppi41dma 15 1
557 &cppi41dma 16 1 &cppi41dma 17 1
558 &cppi41dma 18 1 &cppi41dma 19 1
559 &cppi41dma 20 1 &cppi41dma 21 1
560 &cppi41dma 22 1 &cppi41dma 23 1
561 &cppi41dma 24 1 &cppi41dma 25 1
562 &cppi41dma 26 1 &cppi41dma 27 1
563 &cppi41dma 28 1 &cppi41dma 29 1>;
564 dma-names =
565 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
566 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
567 "rx14", "rx15",
568 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
569 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
570 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]571 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]572
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]573 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]574 compatible = "ti,am3359-cppi41";
575 reg = <0x47400000 0x1000
576 0x47402000 0x1000
577 0x47403000 0x1000
578 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]579 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]580 interrupts = <17>;
581 interrupt-names = "glue";
582 #dma-cells = <2>;
583 #dma-channels = <30>;
584 #dma-requests = <256>;
585 status = "disabled";
586 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]587 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]588
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]589 epwmss0: epwmss@48300000 {
590 compatible = "ti,am33xx-pwmss";
591 reg = <0x48300000 0x10>;
592 ti,hwmods = "epwmss0";
593 #address-cells = <1>;
594 #size-cells = <1>;
595 status = "disabled";
596 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
597 0x48300180 0x48300180 0x80 /* EQEP */
598 0x48300200 0x48300200 0x80>; /* EHRPWM */
599
600 ecap0: ecap@48300100 {
601 compatible = "ti,am33xx-ecap";
602 #pwm-cells = <3>;
603 reg = <0x48300100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]604 interrupts = <31>;
605 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]606 ti,hwmods = "ecap0";
607 status = "disabled";
608 };
609
610 ehrpwm0: ehrpwm@48300200 {
611 compatible = "ti,am33xx-ehrpwm";
612 #pwm-cells = <3>;
613 reg = <0x48300200 0x80>;
614 ti,hwmods = "ehrpwm0";
615 status = "disabled";
616 };
617 };
618
619 epwmss1: epwmss@48302000 {
620 compatible = "ti,am33xx-pwmss";
621 reg = <0x48302000 0x10>;
622 ti,hwmods = "epwmss1";
623 #address-cells = <1>;
624 #size-cells = <1>;
625 status = "disabled";
626 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
627 0x48302180 0x48302180 0x80 /* EQEP */
628 0x48302200 0x48302200 0x80>; /* EHRPWM */
629
630 ecap1: ecap@48302100 {
631 compatible = "ti,am33xx-ecap";
632 #pwm-cells = <3>;
633 reg = <0x48302100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]634 interrupts = <47>;
635 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]636 ti,hwmods = "ecap1";
637 status = "disabled";
638 };
639
640 ehrpwm1: ehrpwm@48302200 {
641 compatible = "ti,am33xx-ehrpwm";
642 #pwm-cells = <3>;
643 reg = <0x48302200 0x80>;
644 ti,hwmods = "ehrpwm1";
645 status = "disabled";
646 };
647 };
648
649 epwmss2: epwmss@48304000 {
650 compatible = "ti,am33xx-pwmss";
651 reg = <0x48304000 0x10>;
652 ti,hwmods = "epwmss2";
653 #address-cells = <1>;
654 #size-cells = <1>;
655 status = "disabled";
656 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
657 0x48304180 0x48304180 0x80 /* EQEP */
658 0x48304200 0x48304200 0x80>; /* EHRPWM */
659
660 ecap2: ecap@48304100 {
661 compatible = "ti,am33xx-ecap";
662 #pwm-cells = <3>;
663 reg = <0x48304100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]664 interrupts = <61>;
665 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]666 ti,hwmods = "ecap2";
667 status = "disabled";
668 };
669
670 ehrpwm2: ehrpwm@48304200 {
671 compatible = "ti,am33xx-ehrpwm";
672 #pwm-cells = <3>;
673 reg = <0x48304200 0x80>;
674 ti,hwmods = "ehrpwm2";
675 status = "disabled";
676 };
677 };
678
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]679 mac: ethernet@4a100000 {
680 compatible = "ti,cpsw";
681 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame]682 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
683 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]684 cpdma_channels = <8>;
685 ale_entries = <1024>;
686 bd_ram_size = <0x2000>;
687 no_bd_ram = <0>;
688 rx_descs = <64>;
689 mac_control = <0x20>;
690 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]691 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]692 cpts_clock_mult = <0x80000000>;
693 cpts_clock_shift = <29>;
694 reg = <0x4a100000 0x800
695 0x4a101200 0x100>;
696 #address-cells = <1>;
697 #size-cells = <1>;
698 interrupt-parent = <&intc>;
699 /*
700 * c0_rx_thresh_pend
701 * c0_rx_pend
702 * c0_tx_pend
703 * c0_misc_pend
704 */
705 interrupts = <40 41 42 43>;
706 ranges;
Markus Pargmannfa5f4ad2014-09-29 08:53:19 +0200[diff] [blame]707 syscon = <&cm>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]708 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]709
710 davinci_mdio: mdio@4a101000 {
711 compatible = "ti,davinci_mdio";
712 #address-cells = <1>;
713 #size-cells = <0>;
714 ti,hwmods = "davinci_mdio";
715 bus_freq = <1000000>;
716 reg = <0x4a101000 0x100>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]717 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]718 };
719
720 cpsw_emac0: slave@4a100200 {
721 /* Filled in by U-Boot */
722 mac-address = [ 00 00 00 00 00 00 ];
723 };
724
725 cpsw_emac1: slave@4a100300 {
726 /* Filled in by U-Boot */
727 mac-address = [ 00 00 00 00 00 00 ];
728 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]729
730 phy_sel: cpsw-phy-sel@44e10650 {
731 compatible = "ti,am3352-cpsw-phy-sel";
732 reg= <0x44e10650 0x4>;
733 reg-names = "gmii-sel";
734 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]735 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]736
737 ocmcram: ocmcram@40300000 {
Rajendra Nayak8b9a2812014-09-10 11:04:03 -0500[diff] [blame]738 compatible = "mmio-sram";
739 reg = <0x40300000 0x10000>; /* 64k */
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]740 };
741
742 wkup_m3: wkup_m3@44d00000 {
743 compatible = "ti,am3353-wkup-m3";
744 reg = <0x44d00000 0x4000 /* M3 UMEM */
745 0x44d80000 0x2000>; /* M3 DMEM */
746 ti,hwmods = "wkup_m3";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]747 ti,no-reset-on-init;
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]748 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]749
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]750 elm: elm@48080000 {
751 compatible = "ti,am3352-elm";
752 reg = <0x48080000 0x2000>;
753 interrupts = <4>;
754 ti,hwmods = "elm";
755 status = "disabled";
756 };
757
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]758 lcdc: lcdc@4830e000 {
759 compatible = "ti,am33xx-tilcdc";
760 reg = <0x4830e000 0x1000>;
761 interrupt-parent = <&intc>;
762 interrupts = <36>;
763 ti,hwmods = "lcdc";
764 status = "disabled";
765 };
766
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]767 tscadc: tscadc@44e0d000 {
768 compatible = "ti,am3359-tscadc";
769 reg = <0x44e0d000 0x1000>;
770 interrupt-parent = <&intc>;
771 interrupts = <16>;
772 ti,hwmods = "adc_tsc";
773 status = "disabled";
774
775 tsc {
776 compatible = "ti,am3359-tsc";
777 };
778 am335x_adc: adc {
779 #io-channel-cells = <1>;
780 compatible = "ti,am3359-adc";
781 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]782 };
783
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]784 gpmc: gpmc@50000000 {
785 compatible = "ti,am3352-gpmc";
786 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]787 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]788 reg = <0x50000000 0x2000>;
789 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]790 gpmc,num-cs = <7>;
791 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]792 #address-cells = <2>;
793 #size-cells = <1>;
794 status = "disabled";
795 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]796
797 sham: sham@53100000 {
798 compatible = "ti,omap4-sham";
799 ti,hwmods = "sham";
800 reg = <0x53100000 0x200>;
801 interrupts = <109>;
802 dmas = <&edma 36>;
803 dma-names = "rx";
804 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]805
806 aes: aes@53500000 {
807 compatible = "ti,omap4-aes";
808 ti,hwmods = "aes";
809 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]810 interrupts = <103>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]811 dmas = <&edma 6>,
812 <&edma 5>;
813 dma-names = "tx", "rx";
814 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]815
816 mcasp0: mcasp@48038000 {
817 compatible = "ti,am33xx-mcasp-audio";
818 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]819 reg = <0x48038000 0x2000>,
820 <0x46000000 0x400000>;
821 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]822 interrupts = <80>, <81>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]823 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]824 status = "disabled";
825 dmas = <&edma 8>,
826 <&edma 9>;
827 dma-names = "tx", "rx";
828 };
829
830 mcasp1: mcasp@4803C000 {
831 compatible = "ti,am33xx-mcasp-audio";
832 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]833 reg = <0x4803C000 0x2000>,
834 <0x46400000 0x400000>;
835 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]836 interrupts = <82>, <83>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]837 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]838 status = "disabled";
839 dmas = <&edma 10>,
840 <&edma 11>;
841 dma-names = "tx", "rx";
842 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]843
844 rng: rng@48310000 {
845 compatible = "ti,omap4-rng";
846 ti,hwmods = "rng";
847 reg = <0x48310000 0x2000>;
848 interrupts = <111>;
849 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]850 };
851};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]852
853/include/ "am33xx-clocks.dtsi"