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Cory Maccarrone35c90492009-12-13 01:02:11 -07001/*
2 * OMAP7xx SPI 100k controller driver
3 * Author: Fabrice Crohas <fcrohas@gmail.com>
4 * from original omap1_mcspi driver
5 *
6 * Copyright (C) 2005, 2006 Nokia Corporation
7 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
8 * Juha Yrj�l� <juha.yrjola@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/module.h>
29#include <linux/device.h>
30#include <linux/delay.h>
31#include <linux/platform_device.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/io.h>
35#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090036#include <linux/slab.h>
Cory Maccarrone35c90492009-12-13 01:02:11 -070037
38#include <linux/spi/spi.h>
39
Cory Maccarrone35c90492009-12-13 01:02:11 -070040#define OMAP1_SPI100K_MAX_FREQ 48000000
41
42#define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12)
43
44#define SPI_SETUP1 0x00
45#define SPI_SETUP2 0x02
46#define SPI_CTRL 0x04
47#define SPI_STATUS 0x06
48#define SPI_TX_LSB 0x08
49#define SPI_TX_MSB 0x0a
50#define SPI_RX_LSB 0x0c
51#define SPI_RX_MSB 0x0e
52
53#define SPI_SETUP1_INT_READ_ENABLE (1UL << 5)
54#define SPI_SETUP1_INT_WRITE_ENABLE (1UL << 4)
55#define SPI_SETUP1_CLOCK_DIVISOR(x) ((x) << 1)
56#define SPI_SETUP1_CLOCK_ENABLE (1UL << 0)
57
58#define SPI_SETUP2_ACTIVE_EDGE_FALLING (0UL << 0)
59#define SPI_SETUP2_ACTIVE_EDGE_RISING (1UL << 0)
60#define SPI_SETUP2_NEGATIVE_LEVEL (0UL << 5)
61#define SPI_SETUP2_POSITIVE_LEVEL (1UL << 5)
62#define SPI_SETUP2_LEVEL_TRIGGER (0UL << 10)
63#define SPI_SETUP2_EDGE_TRIGGER (1UL << 10)
64
65#define SPI_CTRL_SEN(x) ((x) << 7)
66#define SPI_CTRL_WORD_SIZE(x) (((x) - 1) << 2)
67#define SPI_CTRL_WR (1UL << 1)
68#define SPI_CTRL_RD (1UL << 0)
69
70#define SPI_STATUS_WE (1UL << 1)
71#define SPI_STATUS_RD (1UL << 0)
72
73#define WRITE 0
74#define READ 1
75
76
77/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
78 * cache operations; better heuristics consider wordsize and bitrate.
79 */
80#define DMA_MIN_BYTES 8
81
82#define SPI_RUNNING 0
83#define SPI_SHUTDOWN 1
84
85struct omap1_spi100k {
86 struct work_struct work;
87
88 /* lock protects queue and registers */
89 spinlock_t lock;
90 struct list_head msg_queue;
91 struct spi_master *master;
92 struct clk *ick;
93 struct clk *fck;
94
95 /* Virtual base address of the controller */
96 void __iomem *base;
97
98 /* State of the SPI */
99 unsigned int state;
100};
101
102struct omap1_spi100k_cs {
103 void __iomem *base;
104 int word_len;
105};
106
107static struct workqueue_struct *omap1_spi100k_wq;
108
109#define MOD_REG_BIT(val, mask, set) do { \
110 if (set) \
111 val |= mask; \
112 else \
113 val &= ~mask; \
114} while (0)
115
116static void spi100k_enable_clock(struct spi_master *master)
117{
118 unsigned int val;
119 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
120
121 /* enable SPI */
122 val = readw(spi100k->base + SPI_SETUP1);
123 val |= SPI_SETUP1_CLOCK_ENABLE;
124 writew(val, spi100k->base + SPI_SETUP1);
125}
126
127static void spi100k_disable_clock(struct spi_master *master)
128{
129 unsigned int val;
130 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
131
132 /* disable SPI */
133 val = readw(spi100k->base + SPI_SETUP1);
134 val &= ~SPI_SETUP1_CLOCK_ENABLE;
135 writew(val, spi100k->base + SPI_SETUP1);
136}
137
138static void spi100k_write_data(struct spi_master *master, int len, int data)
139{
140 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
141
Cory Maccarrone5c2818c2010-05-30 00:12:23 +0000142 /* write 16-bit word, shifting 8-bit data if necessary */
143 if (len <= 8) {
144 data <<= 8;
145 len = 16;
146 }
147
Cory Maccarrone35c90492009-12-13 01:02:11 -0700148 spi100k_enable_clock(master);
149 writew( data , spi100k->base + SPI_TX_MSB);
150
151 writew(SPI_CTRL_SEN(0) |
152 SPI_CTRL_WORD_SIZE(len) |
153 SPI_CTRL_WR,
154 spi100k->base + SPI_CTRL);
155
156 /* Wait for bit ack send change */
157 while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE);
158 udelay(1000);
159
160 spi100k_disable_clock(master);
161}
162
163static int spi100k_read_data(struct spi_master *master, int len)
164{
165 int dataH,dataL;
166 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
167
Cory Maccarrone5c2818c2010-05-30 00:12:23 +0000168 /* Always do at least 16 bits */
169 if (len <= 8)
170 len = 16;
171
Cory Maccarrone35c90492009-12-13 01:02:11 -0700172 spi100k_enable_clock(master);
173 writew(SPI_CTRL_SEN(0) |
174 SPI_CTRL_WORD_SIZE(len) |
175 SPI_CTRL_RD,
176 spi100k->base + SPI_CTRL);
177
178 while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD);
179 udelay(1000);
180
181 dataL = readw(spi100k->base + SPI_RX_LSB);
182 dataH = readw(spi100k->base + SPI_RX_MSB);
183 spi100k_disable_clock(master);
184
185 return dataL;
186}
187
188static void spi100k_open(struct spi_master *master)
189{
190 /* get control of SPI */
191 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
192
193 writew(SPI_SETUP1_INT_READ_ENABLE |
194 SPI_SETUP1_INT_WRITE_ENABLE |
195 SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
196
197 /* configure clock and interrupts */
198 writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
199 SPI_SETUP2_NEGATIVE_LEVEL |
200 SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
201}
202
203static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
204{
205 if (enable)
206 writew(0x05fc, spi100k->base + SPI_CTRL);
207 else
208 writew(0x05fd, spi100k->base + SPI_CTRL);
209}
210
211static unsigned
212omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
213{
214 struct omap1_spi100k *spi100k;
215 struct omap1_spi100k_cs *cs = spi->controller_state;
216 unsigned int count, c;
217 int word_len;
218
219 spi100k = spi_master_get_devdata(spi->master);
220 count = xfer->len;
221 c = count;
222 word_len = cs->word_len;
223
Cory Maccarrone35c90492009-12-13 01:02:11 -0700224 if (word_len <= 8) {
225 u8 *rx;
226 const u8 *tx;
227
228 rx = xfer->rx_buf;
229 tx = xfer->tx_buf;
230 do {
231 c-=1;
232 if (xfer->tx_buf != NULL)
Cory Maccarrone5c2818c2010-05-30 00:12:23 +0000233 spi100k_write_data(spi->master, word_len, *tx++);
Cory Maccarrone35c90492009-12-13 01:02:11 -0700234 if (xfer->rx_buf != NULL)
Cory Maccarrone5c2818c2010-05-30 00:12:23 +0000235 *rx++ = spi100k_read_data(spi->master, word_len);
Cory Maccarrone35c90492009-12-13 01:02:11 -0700236 } while(c);
237 } else if (word_len <= 16) {
238 u16 *rx;
239 const u16 *tx;
240
241 rx = xfer->rx_buf;
242 tx = xfer->tx_buf;
243 do {
244 c-=2;
245 if (xfer->tx_buf != NULL)
246 spi100k_write_data(spi->master,word_len, *tx++);
247 if (xfer->rx_buf != NULL)
248 *rx++ = spi100k_read_data(spi->master,word_len);
249 } while(c);
250 } else if (word_len <= 32) {
251 u32 *rx;
252 const u32 *tx;
253
254 rx = xfer->rx_buf;
255 tx = xfer->tx_buf;
256 do {
257 c-=4;
258 if (xfer->tx_buf != NULL)
259 spi100k_write_data(spi->master,word_len, *tx);
260 if (xfer->rx_buf != NULL)
261 *rx = spi100k_read_data(spi->master,word_len);
262 } while(c);
263 }
264 return count - c;
265}
266
267/* called only when no transfer is active to this device */
268static int omap1_spi100k_setup_transfer(struct spi_device *spi,
269 struct spi_transfer *t)
270{
271 struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
272 struct omap1_spi100k_cs *cs = spi->controller_state;
273 u8 word_len = spi->bits_per_word;
274
275 if (t != NULL && t->bits_per_word)
276 word_len = t->bits_per_word;
277 if (!word_len)
278 word_len = 8;
279
280 if (spi->bits_per_word > 32)
281 return -EINVAL;
282 cs->word_len = word_len;
283
284 /* SPI init before transfer */
285 writew(0x3e , spi100k->base + SPI_SETUP1);
286 writew(0x00 , spi100k->base + SPI_STATUS);
287 writew(0x3e , spi100k->base + SPI_CTRL);
288
289 return 0;
290}
291
292/* the spi->mode bits understood by this driver: */
293#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
294
295static int omap1_spi100k_setup(struct spi_device *spi)
296{
297 int ret;
298 struct omap1_spi100k *spi100k;
299 struct omap1_spi100k_cs *cs = spi->controller_state;
300
Cory Maccarrone35c90492009-12-13 01:02:11 -0700301 spi100k = spi_master_get_devdata(spi->master);
302
303 if (!cs) {
304 cs = kzalloc(sizeof *cs, GFP_KERNEL);
305 if (!cs)
306 return -ENOMEM;
307 cs->base = spi100k->base + spi->chip_select * 0x14;
308 spi->controller_state = cs;
309 }
310
311 spi100k_open(spi->master);
312
313 clk_enable(spi100k->ick);
314 clk_enable(spi100k->fck);
315
316 ret = omap1_spi100k_setup_transfer(spi, NULL);
317
318 clk_disable(spi100k->ick);
319 clk_disable(spi100k->fck);
320
321 return ret;
322}
323
324static void omap1_spi100k_work(struct work_struct *work)
325{
326 struct omap1_spi100k *spi100k;
327 int status = 0;
328
329 spi100k = container_of(work, struct omap1_spi100k, work);
330 spin_lock_irq(&spi100k->lock);
331
332 clk_enable(spi100k->ick);
333 clk_enable(spi100k->fck);
334
335 /* We only enable one channel at a time -- the one whose message is
336 * at the head of the queue -- although this controller would gladly
337 * arbitrate among multiple channels. This corresponds to "single
338 * channel" master mode. As a side effect, we need to manage the
339 * chipselect with the FORCE bit ... CS != channel enable.
340 */
341 while (!list_empty(&spi100k->msg_queue)) {
342 struct spi_message *m;
343 struct spi_device *spi;
344 struct spi_transfer *t = NULL;
345 int cs_active = 0;
346 struct omap1_spi100k_cs *cs;
347 int par_override = 0;
348
349 m = container_of(spi100k->msg_queue.next, struct spi_message,
350 queue);
351
352 list_del_init(&m->queue);
353 spin_unlock_irq(&spi100k->lock);
354
355 spi = m->spi;
356 cs = spi->controller_state;
357
358 list_for_each_entry(t, &m->transfers, transfer_list) {
359 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
360 status = -EINVAL;
361 break;
362 }
363 if (par_override || t->speed_hz || t->bits_per_word) {
364 par_override = 1;
365 status = omap1_spi100k_setup_transfer(spi, t);
366 if (status < 0)
367 break;
368 if (!t->speed_hz && !t->bits_per_word)
369 par_override = 0;
370 }
371
372 if (!cs_active) {
373 omap1_spi100k_force_cs(spi100k, 1);
374 cs_active = 1;
375 }
376
377 if (t->len) {
378 unsigned count;
379
Cory Maccarrone35c90492009-12-13 01:02:11 -0700380 count = omap1_spi100k_txrx_pio(spi, t);
381 m->actual_length += count;
382
383 if (count != t->len) {
384 status = -EIO;
385 break;
386 }
387 }
388
389 if (t->delay_usecs)
390 udelay(t->delay_usecs);
391
392 /* ignore the "leave it on after last xfer" hint */
393
394 if (t->cs_change) {
395 omap1_spi100k_force_cs(spi100k, 0);
396 cs_active = 0;
397 }
398 }
399
400 /* Restore defaults if they were overriden */
401 if (par_override) {
402 par_override = 0;
403 status = omap1_spi100k_setup_transfer(spi, NULL);
404 }
405
406 if (cs_active)
407 omap1_spi100k_force_cs(spi100k, 0);
408
409 m->status = status;
410 m->complete(m->context);
411
412 spin_lock_irq(&spi100k->lock);
413 }
414
415 clk_disable(spi100k->ick);
416 clk_disable(spi100k->fck);
417 spin_unlock_irq(&spi100k->lock);
418
419 if (status < 0)
420 printk(KERN_WARNING "spi transfer failed with %d\n", status);
421}
422
423static int omap1_spi100k_transfer(struct spi_device *spi, struct spi_message *m)
424{
425 struct omap1_spi100k *spi100k;
426 unsigned long flags;
Cory Maccarrone35c90492009-12-13 01:02:11 -0700427
428 m->actual_length = 0;
429 m->status = -EINPROGRESS;
430
431 spi100k = spi_master_get_devdata(spi->master);
432
433 /* Don't accept new work if we're shutting down */
434 if (spi100k->state == SPI_SHUTDOWN)
435 return -ESHUTDOWN;
436
Cory Maccarrone35c90492009-12-13 01:02:11 -0700437 spin_lock_irqsave(&spi100k->lock, flags);
438 list_add_tail(&m->queue, &spi100k->msg_queue);
439 queue_work(omap1_spi100k_wq, &spi100k->work);
440 spin_unlock_irqrestore(&spi100k->lock, flags);
441
442 return 0;
443}
444
Grant Likelyfd4a3192012-12-07 16:57:14 +0000445static int omap1_spi100k_probe(struct platform_device *pdev)
Cory Maccarrone35c90492009-12-13 01:02:11 -0700446{
447 struct spi_master *master;
448 struct omap1_spi100k *spi100k;
449 int status = 0;
450
451 if (!pdev->id)
452 return -EINVAL;
453
454 master = spi_alloc_master(&pdev->dev, sizeof *spi100k);
455 if (master == NULL) {
456 dev_dbg(&pdev->dev, "master allocation failed\n");
457 return -ENOMEM;
458 }
459
460 if (pdev->id != -1)
461 master->bus_num = pdev->id;
462
463 master->setup = omap1_spi100k_setup;
464 master->transfer = omap1_spi100k_transfer;
465 master->cleanup = NULL;
466 master->num_chipselect = 2;
467 master->mode_bits = MODEBITS;
Stephen Warren24778be2013-05-21 20:36:35 -0600468 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
Mark Brown69ea6722013-07-10 15:06:46 +0100469 master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
470 master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
Cory Maccarrone35c90492009-12-13 01:02:11 -0700471
Jingoo Han24b5a822013-05-23 19:20:40 +0900472 platform_set_drvdata(pdev, master);
Cory Maccarrone35c90492009-12-13 01:02:11 -0700473
474 spi100k = spi_master_get_devdata(master);
475 spi100k->master = master;
476
477 /*
478 * The memory region base address is taken as the platform_data.
479 * You should allocate this with ioremap() before initializing
480 * the SPI.
481 */
482 spi100k->base = (void __iomem *) pdev->dev.platform_data;
483
484 INIT_WORK(&spi100k->work, omap1_spi100k_work);
485
486 spin_lock_init(&spi100k->lock);
487 INIT_LIST_HEAD(&spi100k->msg_queue);
488 spi100k->ick = clk_get(&pdev->dev, "ick");
489 if (IS_ERR(spi100k->ick)) {
490 dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
491 status = PTR_ERR(spi100k->ick);
492 goto err1;
493 }
494
495 spi100k->fck = clk_get(&pdev->dev, "fck");
496 if (IS_ERR(spi100k->fck)) {
497 dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
498 status = PTR_ERR(spi100k->fck);
499 goto err2;
500 }
501
Cory Maccarrone35c90492009-12-13 01:02:11 -0700502 status = spi_register_master(master);
503 if (status < 0)
504 goto err3;
505
506 spi100k->state = SPI_RUNNING;
507
508 return status;
509
510err3:
511 clk_put(spi100k->fck);
512err2:
513 clk_put(spi100k->ick);
514err1:
515 spi_master_put(master);
516 return status;
517}
518
Grant Likely2deff8d2013-02-05 13:27:35 +0000519static int omap1_spi100k_remove(struct platform_device *pdev)
Cory Maccarrone35c90492009-12-13 01:02:11 -0700520{
521 struct spi_master *master;
522 struct omap1_spi100k *spi100k;
523 struct resource *r;
524 unsigned limit = 500;
525 unsigned long flags;
526 int status = 0;
527
Jingoo Han24b5a822013-05-23 19:20:40 +0900528 master = platform_get_drvdata(pdev);
Cory Maccarrone35c90492009-12-13 01:02:11 -0700529 spi100k = spi_master_get_devdata(master);
530
531 spin_lock_irqsave(&spi100k->lock, flags);
532
533 spi100k->state = SPI_SHUTDOWN;
534 while (!list_empty(&spi100k->msg_queue) && limit--) {
535 spin_unlock_irqrestore(&spi100k->lock, flags);
536 msleep(10);
537 spin_lock_irqsave(&spi100k->lock, flags);
538 }
539
540 if (!list_empty(&spi100k->msg_queue))
541 status = -EBUSY;
542
543 spin_unlock_irqrestore(&spi100k->lock, flags);
544
545 if (status != 0)
546 return status;
547
548 clk_put(spi100k->fck);
549 clk_put(spi100k->ick);
550
551 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
552
553 spi_unregister_master(master);
554
555 return 0;
556}
557
558static struct platform_driver omap1_spi100k_driver = {
559 .driver = {
560 .name = "omap1_spi100k",
561 .owner = THIS_MODULE,
562 },
Grant Likely2deff8d2013-02-05 13:27:35 +0000563 .remove = omap1_spi100k_remove,
Cory Maccarrone35c90492009-12-13 01:02:11 -0700564};
565
566
567static int __init omap1_spi100k_init(void)
568{
569 omap1_spi100k_wq = create_singlethread_workqueue(
570 omap1_spi100k_driver.driver.name);
571
572 if (omap1_spi100k_wq == NULL)
573 return -1;
574
575 return platform_driver_probe(&omap1_spi100k_driver, omap1_spi100k_probe);
576}
577
578static void __exit omap1_spi100k_exit(void)
579{
580 platform_driver_unregister(&omap1_spi100k_driver);
581
582 destroy_workqueue(omap1_spi100k_wq);
583}
584
585module_init(omap1_spi100k_init);
586module_exit(omap1_spi100k_exit);
587
588MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
589MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
590MODULE_LICENSE("GPL");
591