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Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Suthikulpanit, Suraveeb6197b92015-06-10 11:08:53 -05003 select ACPI_CCA_REQUIRED if ACPI
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00004 select ACPI_GENERIC_GSI if ACPI
Al Stone6933de02015-03-24 14:02:51 +00005 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01006 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Kees Cook2b68f6c2015-04-14 15:48:00 -07007 select ARCH_HAS_ELF_RANDOMIZE
Riku Voipio957e3fa2014-12-12 16:57:44 -08008 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07009 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010010 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +010011 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +020012 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010013 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000014 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000015 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000016 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000017 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000018 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010019 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000020 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010021 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000022 select ARM_GIC_V3_ITS if PCI_MSI
Will Deaconadace892013-05-08 17:29:24 +010023 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000024 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070025 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000026 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000027 select DCACHE_WORD_ACCESS
Catalin Marinasef375662015-07-07 17:15:39 +010028 select EDAC_SUPPORT
Laura Abbottd4932f92014-10-09 15:26:44 -070029 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010030 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010031 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000032 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070033 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010034 select GENERIC_IRQ_PROBE
35 select GENERIC_IRQ_SHOW
Sudeep Holla6544e672015-04-22 18:16:33 +010036 select GENERIC_IRQ_SHOW_LEVEL
Arnd Bergmanncb61f672014-11-19 14:09:07 +010037 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070038 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000040 select GENERIC_STRNCPY_FROM_USER
41 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010042 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010043 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010044 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010045 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010046 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010047 select HAVE_ARCH_BITREVERSE
Jiang Liu9732caf2014-01-07 22:17:13 +080048 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000049 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000050 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010051 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070052 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010053 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010054 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010055 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070056 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070057 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010058 select HAVE_DMA_API_DEBUG
59 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000060 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010061 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000062 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010063 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090064 select HAVE_FUNCTION_TRACER
65 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010066 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010067 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010068 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000069 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010070 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010071 select HAVE_PERF_REGS
72 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070073 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010074 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010075 select IRQ_DOMAIN
Anders Roxelle8557d12015-04-27 22:53:09 +020076 select IRQ_FORCED_THREADING
Catalin Marinasfea2aca2012-10-16 11:26:57 +010077 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010078 select NO_BOOTMEM
79 select OF
80 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010081 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010082 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000083 select POWER_RESET
84 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010085 select RTC_LIB
86 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070087 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070088 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010089 help
90 ARM 64-bit (AArch64) Linux support.
91
92config 64BIT
93 def_bool y
94
95config ARCH_PHYS_ADDR_T_64BIT
96 def_bool y
97
98config MMU
99 def_bool y
100
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -0700101config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100102 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100103
104config STACKTRACE_SUPPORT
105 def_bool y
106
107config LOCKDEP_SUPPORT
108 def_bool y
109
110config TRACE_IRQFLAGS_SUPPORT
111 def_bool y
112
Will Deaconc209f792014-03-14 17:47:05 +0000113config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100114 def_bool y
115
116config GENERIC_HWEIGHT
117 def_bool y
118
119config GENERIC_CSUM
120 def_bool y
121
122config GENERIC_CALIBRATE_DELAY
123 def_bool y
124
Catalin Marinas19e76402014-02-27 12:09:22 +0000125config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100126 def_bool y
127
Steve Capper29e56942014-10-09 15:29:25 -0700128config HAVE_GENERIC_RCU_GUP
129 def_bool y
130
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100131config ARCH_DMA_ADDR_T_64BIT
132 def_bool y
133
134config NEED_DMA_MAP_STATE
135 def_bool y
136
137config NEED_SG_DMA_LENGTH
138 def_bool y
139
140config SWIOTLB
141 def_bool y
142
143config IOMMU_HELPER
144 def_bool SWIOTLB
145
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100146config KERNEL_MODE_NEON
147 def_bool y
148
Rob Herring92cc15f2014-04-18 17:19:59 -0500149config FIX_EARLYCON_MEM
150 def_bool y
151
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700152config PGTABLE_LEVELS
153 int
154 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
155 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
156 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
157 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
158
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100159source "init/Kconfig"
160
161source "kernel/Kconfig.freezer"
162
Olof Johansson6a377492015-07-20 12:09:16 -0700163source "arch/arm64/Kconfig.platforms"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100164
165menu "Bus support"
166
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100167config PCI
168 bool "PCI support"
169 help
170 This feature enables support for PCI bus system. If you say Y
171 here, the kernel will include drivers and infrastructure code
172 to support PCI bus devices.
173
174config PCI_DOMAINS
175 def_bool PCI
176
177config PCI_DOMAINS_GENERIC
178 def_bool PCI
179
180config PCI_SYSCALL
181 def_bool PCI
182
183source "drivers/pci/Kconfig"
184source "drivers/pci/pcie/Kconfig"
185source "drivers/pci/hotplug/Kconfig"
186
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100187endmenu
188
189menu "Kernel Features"
190
Andre Przywarac0a01b82014-11-14 15:54:12 +0000191menu "ARM errata workarounds via the alternatives framework"
192
193config ARM64_ERRATUM_826319
194 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
195 default y
196 help
197 This option adds an alternative code sequence to work around ARM
198 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
199 AXI master interface and an L2 cache.
200
201 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
202 and is unable to accept a certain write via this interface, it will
203 not progress on read data presented on the read data channel and the
204 system can deadlock.
205
206 The workaround promotes data cache clean instructions to
207 data cache clean-and-invalidate.
208 Please note that this does not necessarily enable the workaround,
209 as it depends on the alternative framework, which will only patch
210 the kernel if an affected CPU is detected.
211
212 If unsure, say Y.
213
214config ARM64_ERRATUM_827319
215 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
216 default y
217 help
218 This option adds an alternative code sequence to work around ARM
219 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
220 master interface and an L2 cache.
221
222 Under certain conditions this erratum can cause a clean line eviction
223 to occur at the same time as another transaction to the same address
224 on the AMBA 5 CHI interface, which can cause data corruption if the
225 interconnect reorders the two transactions.
226
227 The workaround promotes data cache clean instructions to
228 data cache clean-and-invalidate.
229 Please note that this does not necessarily enable the workaround,
230 as it depends on the alternative framework, which will only patch
231 the kernel if an affected CPU is detected.
232
233 If unsure, say Y.
234
235config ARM64_ERRATUM_824069
236 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
237 default y
238 help
239 This option adds an alternative code sequence to work around ARM
240 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
241 to a coherent interconnect.
242
243 If a Cortex-A53 processor is executing a store or prefetch for
244 write instruction at the same time as a processor in another
245 cluster is executing a cache maintenance operation to the same
246 address, then this erratum might cause a clean cache line to be
247 incorrectly marked as dirty.
248
249 The workaround promotes data cache clean instructions to
250 data cache clean-and-invalidate.
251 Please note that this option does not necessarily enable the
252 workaround, as it depends on the alternative framework, which will
253 only patch the kernel if an affected CPU is detected.
254
255 If unsure, say Y.
256
257config ARM64_ERRATUM_819472
258 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
259 default y
260 help
261 This option adds an alternative code sequence to work around ARM
262 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
263 present when it is connected to a coherent interconnect.
264
265 If the processor is executing a load and store exclusive sequence at
266 the same time as a processor in another cluster is executing a cache
267 maintenance operation to the same address, then this erratum might
268 cause data corruption.
269
270 The workaround promotes data cache clean instructions to
271 data cache clean-and-invalidate.
272 Please note that this does not necessarily enable the workaround,
273 as it depends on the alternative framework, which will only patch
274 the kernel if an affected CPU is detected.
275
276 If unsure, say Y.
277
278config ARM64_ERRATUM_832075
279 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
280 default y
281 help
282 This option adds an alternative code sequence to work around ARM
283 erratum 832075 on Cortex-A57 parts up to r1p2.
284
285 Affected Cortex-A57 parts might deadlock when exclusive load/store
286 instructions to Write-Back memory are mixed with Device loads.
287
288 The workaround is to promote device loads to use Load-Acquire
289 semantics.
290 Please note that this does not necessarily enable the workaround,
291 as it depends on the alternative framework, which will only patch
292 the kernel if an affected CPU is detected.
293
294 If unsure, say Y.
295
Will Deacon905e8c52015-03-23 19:07:02 +0000296config ARM64_ERRATUM_845719
297 bool "Cortex-A53: 845719: a load might read incorrect data"
298 depends on COMPAT
299 default y
300 help
301 This option adds an alternative code sequence to work around ARM
302 erratum 845719 on Cortex-A53 parts up to r0p4.
303
304 When running a compat (AArch32) userspace on an affected Cortex-A53
305 part, a load at EL0 from a virtual address that matches the bottom 32
306 bits of the virtual address used by a recent load at (AArch64) EL1
307 might return incorrect data.
308
309 The workaround is to write the contextidr_el1 register on exception
310 return to a 32-bit task.
311 Please note that this does not necessarily enable the workaround,
312 as it depends on the alternative framework, which will only patch
313 the kernel if an affected CPU is detected.
314
315 If unsure, say Y.
316
Andre Przywarac0a01b82014-11-14 15:54:12 +0000317endmenu
318
319
Jungseok Leee41ceed2014-05-12 10:40:38 +0100320choice
321 prompt "Page size"
322 default ARM64_4K_PAGES
323 help
324 Page size (translation granule) configuration.
325
326config ARM64_4K_PAGES
327 bool "4KB"
328 help
329 This feature enables 4KB pages support.
330
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100331config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100332 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100333 help
334 This feature enables 64KB pages support (4KB by default)
335 allowing only two levels of page tables and faster TLB
336 look-up. AArch32 emulation is not available when this feature
337 is enabled.
338
Jungseok Leee41ceed2014-05-12 10:40:38 +0100339endchoice
340
341choice
342 prompt "Virtual address space size"
343 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
344 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
345 help
346 Allows choosing one of multiple possible virtual address
347 space sizes. The level of translation table is determined by
348 a combination of page size and virtual address space size.
349
350config ARM64_VA_BITS_39
351 bool "39-bit"
352 depends on ARM64_4K_PAGES
353
354config ARM64_VA_BITS_42
355 bool "42-bit"
356 depends on ARM64_64K_PAGES
357
Jungseok Leec79b9542014-05-12 18:40:51 +0900358config ARM64_VA_BITS_48
359 bool "48-bit"
Jungseok Leec79b9542014-05-12 18:40:51 +0900360
Jungseok Leee41ceed2014-05-12 10:40:38 +0100361endchoice
362
363config ARM64_VA_BITS
364 int
365 default 39 if ARM64_VA_BITS_39
366 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900367 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100368
Will Deacona8720132013-10-11 14:52:19 +0100369config CPU_BIG_ENDIAN
370 bool "Build big-endian kernel"
371 help
372 Say Y if you plan on running a kernel in big-endian mode.
373
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100374config SMP
375 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100376 help
377 This enables support for systems with more than one CPU. If
378 you say N here, the kernel will run on single and
379 multiprocessor machines, but will use only one CPU of a
380 multiprocessor machine. If you say Y here, the kernel will run
381 on many, but not all, single processor machines. On a single
382 processor machine, the kernel will run faster if you say N
383 here.
384
385 If you don't know what to do here, say N.
386
Mark Brownf6e763b2014-03-04 07:51:17 +0000387config SCHED_MC
388 bool "Multi-core scheduler support"
389 depends on SMP
390 help
391 Multi-core scheduler support improves the CPU scheduler's decision
392 making when dealing with multi-core CPU chips at a cost of slightly
393 increased overhead in some places. If unsure say N here.
394
395config SCHED_SMT
396 bool "SMT scheduler support"
397 depends on SMP
398 help
399 Improves the CPU scheduler's decision making when dealing with
400 MultiThreading at a cost of slightly increased overhead in some
401 places. If unsure say N here.
402
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100403config NR_CPUS
Ganapatrao Kulkarni62aa9652015-03-18 11:01:18 +0000404 int "Maximum number of CPUs (2-4096)"
405 range 2 4096
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100406 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100407 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100408 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100409
Mark Rutland9327e2c2013-10-24 20:30:18 +0100410config HOTPLUG_CPU
411 bool "Support for hot-pluggable CPUs"
412 depends on SMP
413 help
414 Say Y here to experiment with turning CPUs off and on. CPUs
415 can be controlled through /sys/devices/system/cpu.
416
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100417source kernel/Kconfig.preempt
418
Mark Rutland137650aa2015-03-13 16:14:34 +0000419config UP_LATE_INIT
420 def_bool y
421 depends on !SMP
422
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100423config HZ
424 int
425 default 100
426
427config ARCH_HAS_HOLES_MEMORYMODEL
428 def_bool y if SPARSEMEM
429
430config ARCH_SPARSEMEM_ENABLE
431 def_bool y
432 select SPARSEMEM_VMEMMAP_ENABLE
433
434config ARCH_SPARSEMEM_DEFAULT
435 def_bool ARCH_SPARSEMEM_ENABLE
436
437config ARCH_SELECT_MEMORY_MODEL
438 def_bool ARCH_SPARSEMEM_ENABLE
439
440config HAVE_ARCH_PFN_VALID
441 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
442
443config HW_PERF_EVENTS
444 bool "Enable hardware performance counter support for perf events"
445 depends on PERF_EVENTS
446 default y
447 help
448 Enable hardware performance counter support for perf events. If
449 disabled, perf events will use software events only.
450
Steve Capper084bd292013-04-10 13:48:00 +0100451config SYS_SUPPORTS_HUGETLBFS
452 def_bool y
453
454config ARCH_WANT_GENERAL_HUGETLB
455 def_bool y
456
457config ARCH_WANT_HUGE_PMD_SHARE
458 def_bool y if !ARM64_64K_PAGES
459
Steve Capperaf074842013-04-19 16:23:57 +0100460config HAVE_ARCH_TRANSPARENT_HUGEPAGE
461 def_bool y
462
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100463config ARCH_HAS_CACHE_LINE_SIZE
464 def_bool y
465
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100466source "mm/Kconfig"
467
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000468config SECCOMP
469 bool "Enable seccomp to safely compute untrusted bytecode"
470 ---help---
471 This kernel feature is useful for number crunching applications
472 that may need to compute untrusted bytecode during their
473 execution. By using pipes or other transports made available to
474 the process as file descriptors supporting the read/write
475 syscalls, it's possible to isolate those applications in
476 their own address space using seccomp. Once seccomp is
477 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
478 and the task is only allowed to execute a few safe syscalls
479 defined by each seccomp mode.
480
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000481config XEN_DOM0
482 def_bool y
483 depends on XEN
484
485config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700486 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000487 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000488 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000489 help
490 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
491
Steve Capperd03bb142013-04-25 15:19:21 +0100492config FORCE_MAX_ZONEORDER
493 int
494 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
495 default "11"
496
Will Deacon1b907f42014-11-20 16:51:10 +0000497menuconfig ARMV8_DEPRECATED
498 bool "Emulate deprecated/obsolete ARMv8 instructions"
499 depends on COMPAT
500 help
501 Legacy software support may require certain instructions
502 that have been deprecated or obsoleted in the architecture.
503
504 Enable this config to enable selective emulation of these
505 features.
506
507 If unsure, say Y
508
509if ARMV8_DEPRECATED
510
511config SWP_EMULATION
512 bool "Emulate SWP/SWPB instructions"
513 help
514 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
515 they are always undefined. Say Y here to enable software
516 emulation of these instructions for userspace using LDXR/STXR.
517
518 In some older versions of glibc [<=2.8] SWP is used during futex
519 trylock() operations with the assumption that the code will not
520 be preempted. This invalid assumption may be more likely to fail
521 with SWP emulation enabled, leading to deadlock of the user
522 application.
523
524 NOTE: when accessing uncached shared regions, LDXR/STXR rely
525 on an external transaction monitoring block called a global
526 monitor to maintain update atomicity. If your system does not
527 implement a global monitor, this option can cause programs that
528 perform SWP operations to uncached memory to deadlock.
529
530 If unsure, say Y
531
532config CP15_BARRIER_EMULATION
533 bool "Emulate CP15 Barrier instructions"
534 help
535 The CP15 barrier instructions - CP15ISB, CP15DSB, and
536 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
537 strongly recommended to use the ISB, DSB, and DMB
538 instructions instead.
539
540 Say Y here to enable software emulation of these
541 instructions for AArch32 userspace code. When this option is
542 enabled, CP15 barrier usage is traced which can help
543 identify software that needs updating.
544
545 If unsure, say Y
546
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000547config SETEND_EMULATION
548 bool "Emulate SETEND instruction"
549 help
550 The SETEND instruction alters the data-endianness of the
551 AArch32 EL0, and is deprecated in ARMv8.
552
553 Say Y here to enable software emulation of the instruction
554 for AArch32 userspace code.
555
556 Note: All the cpus on the system must have mixed endian support at EL0
557 for this feature to be enabled. If a new CPU - which doesn't support mixed
558 endian - is hotplugged in after this feature has been enabled, there could
559 be unexpected results in the applications.
560
561 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000562endif
563
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100564endmenu
565
566menu "Boot options"
567
568config CMDLINE
569 string "Default kernel command string"
570 default ""
571 help
572 Provide a set of default command-line options at build time by
573 entering them here. As a minimum, you should specify the the
574 root device (e.g. root=/dev/nfs).
575
576config CMDLINE_FORCE
577 bool "Always use the default kernel command string"
578 help
579 Always use the default kernel command string, even if the boot
580 loader passes other arguments to the kernel.
581 This is useful if you cannot or don't want to change the
582 command-line options your boot loader passes to the kernel.
583
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200584config EFI_STUB
585 bool
586
Mark Salterf84d0272014-04-15 21:59:30 -0400587config EFI
588 bool "UEFI runtime support"
589 depends on OF && !CPU_BIG_ENDIAN
590 select LIBFDT
591 select UCS2_STRING
592 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200593 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200594 select EFI_STUB
595 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400596 default y
597 help
598 This option provides support for runtime services provided
599 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400600 clock, and platform reset). A UEFI stub is also provided to
601 allow the kernel to be booted as an EFI application. This
602 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400603
Yi Lid1ae8c02014-10-04 23:46:43 +0800604config DMI
605 bool "Enable support for SMBIOS (DMI) tables"
606 depends on EFI
607 default y
608 help
609 This enables SMBIOS/DMI feature for systems.
610
611 This option is only useful on systems that have UEFI firmware.
612 However, even with this option, the resultant kernel should
613 continue to boot on existing non-UEFI platforms.
614
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100615endmenu
616
617menu "Userspace binary formats"
618
619source "fs/Kconfig.binfmt"
620
621config COMPAT
622 bool "Kernel support for 32-bit EL0"
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000623 depends on !ARM64_64K_PAGES || EXPERT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100624 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700625 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500626 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500627 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100628 help
629 This option enables support for a 32-bit EL0 running under a 64-bit
630 kernel at EL1. AArch32-specific components such as system calls,
631 the user helper functions, VFP support and the ptrace interface are
632 handled appropriately by the kernel.
633
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000634 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
635 will only be able to execute AArch32 binaries that were compiled with
636 64k aligned segments.
637
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100638 If you want to execute 32-bit userspace applications, say Y.
639
640config SYSVIPC_COMPAT
641 def_bool y
642 depends on COMPAT && SYSVIPC
643
644endmenu
645
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000646menu "Power management options"
647
648source "kernel/power/Kconfig"
649
650config ARCH_SUSPEND_POSSIBLE
651 def_bool y
652
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000653endmenu
654
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100655menu "CPU Power Management"
656
657source "drivers/cpuidle/Kconfig"
658
Rob Herring52e7e812014-02-24 11:27:57 +0900659source "drivers/cpufreq/Kconfig"
660
661endmenu
662
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100663source "net/Kconfig"
664
665source "drivers/Kconfig"
666
Mark Salterf84d0272014-04-15 21:59:30 -0400667source "drivers/firmware/Kconfig"
668
Graeme Gregoryb6a02172015-03-24 14:02:53 +0000669source "drivers/acpi/Kconfig"
670
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100671source "fs/Kconfig"
672
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100673source "arch/arm64/kvm/Kconfig"
674
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100675source "arch/arm64/Kconfig.debug"
676
677source "security/Kconfig"
678
679source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800680if CRYPTO
681source "arch/arm64/crypto/Kconfig"
682endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100683
684source "lib/Kconfig"