Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/cpuidle34xx.c |
| 3 | * |
| 4 | * OMAP3 CPU IDLE Routines |
| 5 | * |
| 6 | * Copyright (C) 2008 Texas Instruments, Inc. |
| 7 | * Rajendra Nayak <rnayak@ti.com> |
| 8 | * |
| 9 | * Copyright (C) 2007 Texas Instruments, Inc. |
| 10 | * Karthik Dasu <karthik-dp@ti.com> |
| 11 | * |
| 12 | * Copyright (C) 2006 Nokia Corporation |
| 13 | * Tony Lindgren <tony@atomide.com> |
| 14 | * |
| 15 | * Copyright (C) 2005 Texas Instruments, Inc. |
| 16 | * Richard Woodruff <r-woodruff2@ti.com> |
| 17 | * |
| 18 | * Based on pm.c for omap2 |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License version 2 as |
| 22 | * published by the Free Software Foundation. |
| 23 | */ |
| 24 | |
Tero Kristo | cf22854 | 2009-03-20 15:21:02 +0200 | [diff] [blame] | 25 | #include <linux/sched.h> |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 26 | #include <linux/cpuidle.h> |
| 27 | |
| 28 | #include <plat/prcm.h> |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 29 | #include <plat/irqs.h> |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 30 | #include <plat/powerdomain.h> |
| 31 | #include <plat/clockdomain.h> |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 32 | #include <plat/control.h> |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 33 | #include <plat/serial.h> |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 34 | |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 35 | #include "pm.h" |
| 36 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 37 | #ifdef CONFIG_CPU_IDLE |
| 38 | |
Sanjeev Premi | 8e431ed | 2009-03-13 21:34:25 +0530 | [diff] [blame] | 39 | #define OMAP3_MAX_STATES 7 |
| 40 | #define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */ |
| 41 | #define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */ |
| 42 | #define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */ |
| 43 | #define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */ |
| 44 | #define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */ |
| 45 | #define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */ |
| 46 | #define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */ |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 47 | |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame^] | 48 | #define OMAP3_STATE_MAX OMAP3_STATE_C7 |
| 49 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 50 | struct omap3_processor_cx { |
| 51 | u8 valid; |
| 52 | u8 type; |
| 53 | u32 sleep_latency; |
| 54 | u32 wakeup_latency; |
| 55 | u32 mpu_state; |
| 56 | u32 core_state; |
| 57 | u32 threshold; |
| 58 | u32 flags; |
| 59 | }; |
| 60 | |
| 61 | struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; |
| 62 | struct omap3_processor_cx current_cx_state; |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 63 | struct powerdomain *mpu_pd, *core_pd; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 64 | |
| 65 | static int omap3_idle_bm_check(void) |
| 66 | { |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 67 | if (!omap3_can_sleep()) |
| 68 | return 1; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 69 | return 0; |
| 70 | } |
| 71 | |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 72 | static int _cpuidle_allow_idle(struct powerdomain *pwrdm, |
| 73 | struct clockdomain *clkdm) |
| 74 | { |
| 75 | omap2_clkdm_allow_idle(clkdm); |
| 76 | return 0; |
| 77 | } |
| 78 | |
| 79 | static int _cpuidle_deny_idle(struct powerdomain *pwrdm, |
| 80 | struct clockdomain *clkdm) |
| 81 | { |
| 82 | omap2_clkdm_deny_idle(clkdm); |
| 83 | return 0; |
| 84 | } |
| 85 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 86 | /** |
| 87 | * omap3_enter_idle - Programs OMAP3 to enter the specified state |
| 88 | * @dev: cpuidle device |
| 89 | * @state: The target state to be programmed |
| 90 | * |
| 91 | * Called from the CPUidle framework to program the device to the |
| 92 | * specified target state selected by the governor. |
| 93 | */ |
| 94 | static int omap3_enter_idle(struct cpuidle_device *dev, |
| 95 | struct cpuidle_state *state) |
| 96 | { |
| 97 | struct omap3_processor_cx *cx = cpuidle_get_statedata(state); |
| 98 | struct timespec ts_preidle, ts_postidle, ts_idle; |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 99 | u32 mpu_state = cx->mpu_state, core_state = cx->core_state; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 100 | |
| 101 | current_cx_state = *cx; |
| 102 | |
| 103 | /* Used to keep track of the total time in idle */ |
| 104 | getnstimeofday(&ts_preidle); |
| 105 | |
| 106 | local_irq_disable(); |
| 107 | local_fiq_disable(); |
| 108 | |
Jouni Hogander | 7139178 | 2008-10-28 10:59:05 +0200 | [diff] [blame] | 109 | pwrdm_set_next_pwrst(mpu_pd, mpu_state); |
| 110 | pwrdm_set_next_pwrst(core_pd, core_state); |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 111 | |
Tero Kristo | cf22854 | 2009-03-20 15:21:02 +0200 | [diff] [blame] | 112 | if (omap_irq_pending() || need_resched()) |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 113 | goto return_sleep_time; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 114 | |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 115 | if (cx->type == OMAP3_STATE_C1) { |
| 116 | pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle); |
| 117 | pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle); |
| 118 | } |
| 119 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 120 | /* Execute ARM wfi */ |
| 121 | omap_sram_idle(); |
| 122 | |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 123 | if (cx->type == OMAP3_STATE_C1) { |
| 124 | pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle); |
| 125 | pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle); |
| 126 | } |
| 127 | |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 128 | return_sleep_time: |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 129 | getnstimeofday(&ts_postidle); |
| 130 | ts_idle = timespec_sub(ts_postidle, ts_preidle); |
| 131 | |
| 132 | local_irq_enable(); |
| 133 | local_fiq_enable(); |
| 134 | |
Tero Kristo | afbcf61 | 2009-10-26 15:10:40 +0200 | [diff] [blame] | 135 | return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | /** |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame^] | 139 | * next_valid_state - Find next valid c-state |
| 140 | * @dev: cpuidle device |
| 141 | * @state: Currently selected c-state |
| 142 | * |
| 143 | * If the current state is valid, it is returned back to the caller. |
| 144 | * Else, this function searches for a lower c-state which is still |
| 145 | * valid (as defined in omap3_power_states[]). |
| 146 | */ |
| 147 | static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev, |
| 148 | struct cpuidle_state *curr) |
| 149 | { |
| 150 | struct cpuidle_state *next = NULL; |
| 151 | struct omap3_processor_cx *cx; |
| 152 | |
| 153 | cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr); |
| 154 | |
| 155 | /* Check if current state is valid */ |
| 156 | if (cx->valid) { |
| 157 | return curr; |
| 158 | } else { |
| 159 | u8 idx = OMAP3_STATE_MAX; |
| 160 | |
| 161 | /* |
| 162 | * Reach the current state starting at highest C-state |
| 163 | */ |
| 164 | for (; idx >= OMAP3_STATE_C1; idx--) { |
| 165 | if (&dev->states[idx] == curr) { |
| 166 | next = &dev->states[idx]; |
| 167 | break; |
| 168 | } |
| 169 | } |
| 170 | |
| 171 | /* |
| 172 | * Should never hit this condition. |
| 173 | */ |
| 174 | WARN_ON(next == NULL); |
| 175 | |
| 176 | /* |
| 177 | * Drop to next valid state. |
| 178 | * Start search from the next (lower) state. |
| 179 | */ |
| 180 | idx--; |
| 181 | for (; idx >= OMAP3_STATE_C1; idx--) { |
| 182 | struct omap3_processor_cx *cx; |
| 183 | |
| 184 | cx = cpuidle_get_statedata(&dev->states[idx]); |
| 185 | if (cx->valid) { |
| 186 | next = &dev->states[idx]; |
| 187 | break; |
| 188 | } |
| 189 | } |
| 190 | /* |
| 191 | * C1 and C2 are always valid. |
| 192 | * So, no need to check for 'next==NULL' outside this loop. |
| 193 | */ |
| 194 | } |
| 195 | |
| 196 | return next; |
| 197 | } |
| 198 | |
| 199 | /** |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 200 | * omap3_enter_idle_bm - Checks for any bus activity |
| 201 | * @dev: cpuidle device |
| 202 | * @state: The target state to be programmed |
| 203 | * |
| 204 | * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This |
| 205 | * function checks for any pending activity and then programs the |
| 206 | * device to the specified or a safer state. |
| 207 | */ |
| 208 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, |
| 209 | struct cpuidle_state *state) |
| 210 | { |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame^] | 211 | struct cpuidle_state *new_state = next_valid_state(dev, state); |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 212 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 213 | if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 214 | BUG_ON(!dev->safe_state); |
| 215 | new_state = dev->safe_state; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 216 | } |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 217 | |
| 218 | dev->last_state = new_state; |
| 219 | return omap3_enter_idle(dev, new_state); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 220 | } |
| 221 | |
| 222 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); |
| 223 | |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame^] | 224 | /** |
| 225 | * omap3_cpuidle_update_states - Update the cpuidle states. |
| 226 | * |
| 227 | * Currently, this function toggles the validity of idle states based upon |
| 228 | * the flag 'enable_off_mode'. When the flag is set all states are valid. |
| 229 | * Else, states leading to OFF state set to be invalid. |
| 230 | */ |
| 231 | void omap3_cpuidle_update_states(void) |
| 232 | { |
| 233 | int i; |
| 234 | |
| 235 | for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { |
| 236 | struct omap3_processor_cx *cx = &omap3_power_states[i]; |
| 237 | |
| 238 | if (enable_off_mode) { |
| 239 | cx->valid = 1; |
| 240 | } else { |
| 241 | if ((cx->mpu_state == PWRDM_POWER_OFF) || |
| 242 | (cx->core_state == PWRDM_POWER_OFF)) |
| 243 | cx->valid = 0; |
| 244 | } |
| 245 | } |
| 246 | } |
| 247 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 248 | /* omap3_init_power_states - Initialises the OMAP3 specific C states. |
| 249 | * |
| 250 | * Below is the desciption of each C state. |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 251 | * C1 . MPU WFI + Core active |
| 252 | * C2 . MPU WFI + Core inactive |
| 253 | * C3 . MPU CSWR + Core inactive |
| 254 | * C4 . MPU OFF + Core inactive |
| 255 | * C5 . MPU CSWR + Core CSWR |
| 256 | * C6 . MPU OFF + Core CSWR |
| 257 | * C7 . MPU OFF + Core OFF |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 258 | */ |
| 259 | void omap_init_power_states(void) |
| 260 | { |
| 261 | /* C1 . MPU WFI + Core active */ |
| 262 | omap3_power_states[OMAP3_STATE_C1].valid = 1; |
| 263 | omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1; |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 264 | omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2; |
| 265 | omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2; |
| 266 | omap3_power_states[OMAP3_STATE_C1].threshold = 5; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 267 | omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON; |
| 268 | omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON; |
| 269 | omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID; |
| 270 | |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 271 | /* C2 . MPU WFI + Core inactive */ |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 272 | omap3_power_states[OMAP3_STATE_C2].valid = 1; |
| 273 | omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2; |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 274 | omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10; |
| 275 | omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10; |
| 276 | omap3_power_states[OMAP3_STATE_C2].threshold = 30; |
| 277 | omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 278 | omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 279 | omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 280 | |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 281 | /* C3 . MPU CSWR + Core inactive */ |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 282 | omap3_power_states[OMAP3_STATE_C3].valid = 1; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 283 | omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3; |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 284 | omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50; |
| 285 | omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50; |
| 286 | omap3_power_states[OMAP3_STATE_C3].threshold = 300; |
| 287 | omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 288 | omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 289 | omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | |
| 290 | CPUIDLE_FLAG_CHECK_BM; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 291 | |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 292 | /* C4 . MPU OFF + Core inactive */ |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 293 | omap3_power_states[OMAP3_STATE_C4].valid = 1; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 294 | omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4; |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 295 | omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500; |
| 296 | omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800; |
| 297 | omap3_power_states[OMAP3_STATE_C4].threshold = 4000; |
| 298 | omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF; |
| 299 | omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 300 | omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | |
| 301 | CPUIDLE_FLAG_CHECK_BM; |
| 302 | |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 303 | /* C5 . MPU CSWR + Core CSWR*/ |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 304 | omap3_power_states[OMAP3_STATE_C5].valid = 1; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 305 | omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5; |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 306 | omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500; |
| 307 | omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500; |
| 308 | omap3_power_states[OMAP3_STATE_C5].threshold = 12000; |
| 309 | omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 310 | omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET; |
| 311 | omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID | |
| 312 | CPUIDLE_FLAG_CHECK_BM; |
| 313 | |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 314 | /* C6 . MPU OFF + Core CSWR */ |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 315 | omap3_power_states[OMAP3_STATE_C6].valid = 1; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 316 | omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 317 | omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000; |
| 318 | omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500; |
| 319 | omap3_power_states[OMAP3_STATE_C6].threshold = 15000; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 320 | omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF; |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 321 | omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 322 | omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID | |
| 323 | CPUIDLE_FLAG_CHECK_BM; |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 324 | |
| 325 | /* C7 . MPU OFF + Core OFF */ |
| 326 | omap3_power_states[OMAP3_STATE_C7].valid = 1; |
| 327 | omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7; |
| 328 | omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000; |
| 329 | omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000; |
| 330 | omap3_power_states[OMAP3_STATE_C7].threshold = 300000; |
| 331 | omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF; |
| 332 | omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; |
| 333 | omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | |
| 334 | CPUIDLE_FLAG_CHECK_BM; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | struct cpuidle_driver omap3_idle_driver = { |
| 338 | .name = "omap3_idle", |
| 339 | .owner = THIS_MODULE, |
| 340 | }; |
| 341 | |
| 342 | /** |
| 343 | * omap3_idle_init - Init routine for OMAP3 idle |
| 344 | * |
| 345 | * Registers the OMAP3 specific cpuidle driver with the cpuidle |
| 346 | * framework with the valid set of states. |
| 347 | */ |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame] | 348 | int __init omap3_idle_init(void) |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 349 | { |
| 350 | int i, count = 0; |
| 351 | struct omap3_processor_cx *cx; |
| 352 | struct cpuidle_state *state; |
| 353 | struct cpuidle_device *dev; |
| 354 | |
| 355 | mpu_pd = pwrdm_lookup("mpu_pwrdm"); |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 356 | core_pd = pwrdm_lookup("core_pwrdm"); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 357 | |
| 358 | omap_init_power_states(); |
| 359 | cpuidle_register_driver(&omap3_idle_driver); |
| 360 | |
| 361 | dev = &per_cpu(omap3_idle_dev, smp_processor_id()); |
| 362 | |
Sanjeev Premi | 8e431ed | 2009-03-13 21:34:25 +0530 | [diff] [blame] | 363 | for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 364 | cx = &omap3_power_states[i]; |
| 365 | state = &dev->states[count]; |
| 366 | |
| 367 | if (!cx->valid) |
| 368 | continue; |
| 369 | cpuidle_set_statedata(state, cx); |
| 370 | state->exit_latency = cx->sleep_latency + cx->wakeup_latency; |
| 371 | state->target_residency = cx->threshold; |
| 372 | state->flags = cx->flags; |
| 373 | state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? |
| 374 | omap3_enter_idle_bm : omap3_enter_idle; |
| 375 | if (cx->type == OMAP3_STATE_C1) |
| 376 | dev->safe_state = state; |
| 377 | sprintf(state->name, "C%d", count+1); |
| 378 | count++; |
| 379 | } |
| 380 | |
| 381 | if (!count) |
| 382 | return -EINVAL; |
| 383 | dev->state_count = count; |
| 384 | |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame^] | 385 | omap3_cpuidle_update_states(); |
| 386 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 387 | if (cpuidle_register_device(dev)) { |
| 388 | printk(KERN_ERR "%s: CPUidle register device failed\n", |
| 389 | __func__); |
| 390 | return -EIO; |
| 391 | } |
| 392 | |
| 393 | return 0; |
| 394 | } |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame] | 395 | #else |
| 396 | int __init omap3_idle_init(void) |
| 397 | { |
| 398 | return 0; |
| 399 | } |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 400 | #endif /* CONFIG_CPU_IDLE */ |