Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | &soc { |
| 14 | |
| 15 | replicator_qdss: replicator@6046000 { |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 16 | compatible = "arm,primecell"; |
| 17 | arm,primecell-periphid = <0x0003b909>; |
| 18 | |
| 19 | reg = <0x6046000 0x1000>; |
| 20 | reg-names = "replicator-base"; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 21 | |
| 22 | coresight-name = "coresight-replicator"; |
| 23 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 24 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 25 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 26 | clock-names = "apb_pclk", "core_a_clk"; |
| 27 | |
| 28 | ports { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 29 | #address-cells = <1>; |
| 30 | #size-cells = <0>; |
| 31 | |
| 32 | port@0 { |
| 33 | reg = <0>; |
| 34 | replicator_out_tmc_etr: endpoint { |
| 35 | remote-endpoint= |
| 36 | <&tmc_etr_in_replicator>; |
| 37 | }; |
| 38 | }; |
| 39 | |
| 40 | port@1 { |
| 41 | reg = <0>; |
| 42 | replicator_in_tmc_etf: endpoint { |
| 43 | slave-mode; |
| 44 | remote-endpoint= |
| 45 | <&tmc_etf_out_replicator>; |
| 46 | }; |
| 47 | }; |
| 48 | }; |
| 49 | }; |
| 50 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 51 | replicator_swao: replicator@6b0a000 { |
| 52 | compatible = "arm,primecell"; |
| 53 | arm,primecell-periphid = <0x0003b909>; |
| 54 | |
| 55 | reg = <0x6b0a000 0x1000>; |
| 56 | reg-names = "replicator-base"; |
| 57 | |
| 58 | coresight-name = "coresight-replicator-swao"; |
| 59 | |
| 60 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 61 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 62 | clock-names = "apb_pclk", "core_a_clk"; |
| 63 | |
| 64 | ports { |
| 65 | #address-cells = <1>; |
| 66 | #size-cells = <0>; |
| 67 | |
| 68 | port@0 { |
| 69 | reg = <0>; |
| 70 | replicator_swao_in_tmc_etf_swao: endpoint { |
| 71 | slave-mode; |
| 72 | remote-endpoint = |
| 73 | <&tmc_etf_swao_out_replicator>; |
| 74 | }; |
| 75 | }; |
| 76 | |
| 77 | /* Always have EUD before funnel leading to ETR. If both |
| 78 | * sink are active we need to give preference to EUD |
| 79 | * over ETR |
| 80 | */ |
| 81 | port@1 { |
| 82 | reg = <1>; |
| 83 | replicator_swao_out_eud: endpoint { |
| 84 | remote-endpoint = |
| 85 | <&eud_in_replicator_swao>; |
| 86 | }; |
| 87 | }; |
| 88 | |
| 89 | port@2 { |
| 90 | reg = <0>; |
| 91 | replicator_swao_out_funnel_in2: endpoint { |
| 92 | remote-endpoint = |
| 93 | <&funnel_in2_in_replicator_swao>; |
| 94 | }; |
| 95 | }; |
| 96 | |
| 97 | }; |
| 98 | }; |
| 99 | |
| 100 | tmc_etf_swao: tmc@6b09000 { |
| 101 | compatible = "arm,primecell"; |
| 102 | arm,primecell-periphid = <0x0003b961>; |
| 103 | |
| 104 | reg = <0x6b09000 0x1000>; |
| 105 | reg-names = "tmc-base"; |
| 106 | |
| 107 | coresight-name = "coresight-tmc-etf-swao"; |
| 108 | |
| 109 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 110 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 111 | clock-names = "apb_pclk", "core_a_clk"; |
| 112 | |
| 113 | ports { |
| 114 | #address-cells = <1>; |
| 115 | #size-cells = <0>; |
| 116 | |
| 117 | port@0 { |
| 118 | reg = <0>; |
| 119 | tmc_etf_swao_out_replicator: endpoint { |
| 120 | remote-endpoint= |
| 121 | <&replicator_swao_in_tmc_etf_swao>; |
| 122 | }; |
| 123 | }; |
| 124 | |
| 125 | port@1 { |
| 126 | reg = <0>; |
| 127 | tmc_etf_swao_in_funnel_swao: endpoint { |
| 128 | slave-mode; |
| 129 | remote-endpoint= |
| 130 | <&funnel_swao_out_tmc_etf_swao>; |
| 131 | }; |
| 132 | }; |
| 133 | }; |
| 134 | |
| 135 | }; |
| 136 | |
| 137 | funnel_swao:funnel@0x6b08000 { |
| 138 | compatible = "arm,primecell"; |
| 139 | arm,primecell-periphid = <0x0003b908>; |
| 140 | |
| 141 | reg = <0x6b08000 0x1000>; |
| 142 | reg-names = "funnel-base"; |
| 143 | |
| 144 | coresight-name = "coresight-funnel-swao"; |
| 145 | |
| 146 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 147 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 148 | clock-names = "apb_pclk", "core_a_clk"; |
| 149 | |
| 150 | ports { |
| 151 | #address-cells = <1>; |
| 152 | #size-cells = <0>; |
| 153 | |
| 154 | port@0 { |
| 155 | reg = <0>; |
| 156 | funnel_swao_out_tmc_etf_swao: endpoint { |
| 157 | remote-endpoint = |
| 158 | <&tmc_etf_swao_in_funnel_swao>; |
| 159 | }; |
| 160 | }; |
| 161 | |
| 162 | port@1 { |
| 163 | reg = <7>; |
| 164 | funnel_swao_in_tpda_swao: endpoint { |
| 165 | slave-mode; |
| 166 | remote-endpoint= |
| 167 | <&tpda_swao_out_funnel_swao>; |
| 168 | }; |
| 169 | }; |
| 170 | }; |
| 171 | }; |
| 172 | |
| 173 | tpda_swao: tpda@6b01000 { |
| 174 | compatible = "qcom,coresight-tpda"; |
| 175 | reg = <0x6b01000 0x1000>; |
| 176 | reg-names = "tpda-base"; |
| 177 | |
| 178 | coresight-name = "coresight-tpda-swao"; |
| 179 | |
| 180 | qcom,tpda-atid = <71>; |
| 181 | qcom,dsb-elem-size = <1 32>; |
| 182 | qcom,cmb-elem-size = <0 64>; |
| 183 | |
| 184 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 185 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 186 | clock-names = "core_clk", "core_a_clk"; |
| 187 | |
| 188 | ports { |
| 189 | #address-cells = <1>; |
| 190 | #size-cells = <0>; |
| 191 | |
| 192 | port@0 { |
| 193 | reg = <0>; |
| 194 | tpda_swao_out_funnel_swao: endpoint { |
| 195 | remote-endpoint = |
| 196 | <&funnel_swao_in_tpda_swao>; |
| 197 | }; |
| 198 | |
| 199 | }; |
| 200 | |
| 201 | port@1 { |
| 202 | reg = <0>; |
| 203 | tpda_swao_in_tpdm_swao0: endpoint { |
| 204 | slave-mode; |
| 205 | remote-endpoint = |
| 206 | <&tpdm_swao0_out_tpda_swao>; |
| 207 | }; |
| 208 | }; |
| 209 | |
| 210 | port@2 { |
| 211 | reg = <1>; |
| 212 | tpda_swao_in_tpdm_swao1: endpoint { |
| 213 | slave-mode; |
| 214 | remote-endpoint = |
| 215 | <&tpdm_swao1_out_tpda_swao>; |
| 216 | }; |
| 217 | |
| 218 | }; |
| 219 | }; |
| 220 | }; |
| 221 | |
| 222 | tpdm_swao0: tpdm@6b02000 { |
| 223 | compatible = "qcom,coresight-tpdm"; |
| 224 | |
| 225 | reg = <0x6b02000 0x1000>; |
| 226 | reg-names = "tpdm-base"; |
| 227 | |
| 228 | coresight-name = "coresight-tpdm-swao-0"; |
| 229 | |
| 230 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 231 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 232 | clock-names = "core_clk", "core_a_clk"; |
| 233 | |
| 234 | port { |
| 235 | tpdm_swao0_out_tpda_swao: endpoint { |
| 236 | remote-endpoint = <&tpda_swao_in_tpdm_swao0>; |
| 237 | }; |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | tpdm_swao1: tpdm@6b03000 { |
| 242 | compatible = "qcom,coresight-tpdm"; |
| 243 | reg = <0x6b03000 0x1000>; |
| 244 | reg-names = "tpdm-base"; |
| 245 | |
| 246 | coresight-name="coresight-tpdm-swao-1"; |
| 247 | |
| 248 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 249 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 250 | clock-names = "core_clk", "core_a_clk"; |
| 251 | |
| 252 | port { |
| 253 | tpdm_swao1_out_tpda_swao: endpoint { |
| 254 | remote-endpoint = <&tpda_swao_in_tpdm_swao1>; |
| 255 | }; |
| 256 | }; |
| 257 | }; |
| 258 | |
| 259 | tmc_etr: tmc@6048000 { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 260 | compatible = "arm,primecell"; |
| 261 | arm,primecell-periphid = <0x0003b961>; |
| 262 | |
| 263 | reg = <0x6048000 0x1000>, |
| 264 | <0x6064000 0x15000>; |
| 265 | reg-names = "tmc-base", "bam-base"; |
| 266 | |
| 267 | arm,buffer-size = <0x400000>; |
Satyajit Desai | 6b9ee37 | 2017-04-25 11:11:36 -0700 | [diff] [blame^] | 268 | arm,sg-enable; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 269 | |
| 270 | coresight-name = "coresight-tmc-etr"; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 271 | coresight-ctis = <&cti0 &cti8>; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 272 | |
| 273 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 274 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 275 | clock-names = "apb_pclk", "core_a_clk"; |
| 276 | |
| 277 | port { |
| 278 | tmc_etr_in_replicator: endpoint { |
| 279 | slave-mode; |
| 280 | remote-endpoint = <&replicator_out_tmc_etr>; |
| 281 | }; |
| 282 | }; |
| 283 | }; |
| 284 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 285 | tmc_etf: tmc@6047000 { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 286 | compatible = "arm,primecell"; |
| 287 | arm,primecell-periphid = <0x0003b961>; |
| 288 | |
| 289 | reg = <0x6047000 0x1000>; |
| 290 | reg-names = "tmc-base"; |
| 291 | |
| 292 | coresight-name = "coresight-tmc-etf"; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 293 | coresight-ctis = <&cti0 &cti8>; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 294 | arm,default-sink; |
| 295 | |
| 296 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 297 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 298 | clock-names = "apb_pclk", "core_a_clk"; |
| 299 | |
| 300 | ports { |
| 301 | #address-cells = <1>; |
| 302 | #size-cells = <0>; |
| 303 | |
| 304 | port@0 { |
| 305 | reg = <0>; |
| 306 | tmc_etf_out_replicator: endpoint { |
| 307 | remote-endpoint = |
| 308 | <&replicator_in_tmc_etf>; |
| 309 | }; |
| 310 | }; |
| 311 | |
| 312 | port@1 { |
| 313 | reg = <1>; |
| 314 | tmc_etf_in_funnel_merg: endpoint { |
| 315 | slave-mode; |
| 316 | remote-endpoint = |
| 317 | <&funnel_merg_out_tmc_etf>; |
| 318 | }; |
| 319 | }; |
| 320 | }; |
| 321 | |
| 322 | }; |
| 323 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 324 | funnel_merg: funnel@6045000 { |
| 325 | compatible = "arm,primecell"; |
| 326 | arm,primecell-periphid = <0x0003b908>; |
| 327 | |
| 328 | reg = <0x6045000 0x1000>; |
| 329 | reg-names = "funnel-base"; |
| 330 | |
| 331 | coresight-name = "coresight-funnel-merg"; |
| 332 | |
| 333 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 334 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 335 | clock-names = "apb_pclk", "core_a_clk"; |
| 336 | |
| 337 | ports { |
| 338 | #address-cells = <1>; |
| 339 | #size-cells = <0>; |
| 340 | |
| 341 | port@0 { |
| 342 | reg = <0>; |
| 343 | funnel_merg_out_tmc_etf: endpoint { |
| 344 | remote-endpoint = |
| 345 | <&tmc_etf_in_funnel_merg>; |
| 346 | }; |
| 347 | }; |
| 348 | |
| 349 | port@1 { |
| 350 | reg = <0>; |
| 351 | funnel_merg_in_funnel_in0: endpoint { |
| 352 | slave-mode; |
| 353 | remote-endpoint = |
| 354 | <&funnel_in0_out_funnel_merg>; |
| 355 | }; |
| 356 | }; |
| 357 | |
| 358 | port@2 { |
| 359 | reg = <2>; |
| 360 | funnel_merg_in_funnel_in2: endpoint { |
| 361 | slave-mode; |
| 362 | remote-endpoint = |
| 363 | <&funnel_in2_out_funnel_merg>; |
| 364 | }; |
| 365 | }; |
| 366 | }; |
| 367 | }; |
| 368 | |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 369 | stm: stm@6002000 { |
| 370 | compatible = "arm,primecell"; |
| 371 | arm,primecell-periphid = <0x0003b962>; |
| 372 | |
| 373 | reg = <0x6002000 0x1000>, |
| 374 | <0x16280000 0x180000>; |
| 375 | reg-names = "stm-base", "stm-stimulus-base"; |
| 376 | |
| 377 | coresight-name = "coresight-stm"; |
| 378 | |
| 379 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 380 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 381 | clock-names = "apb_pclk", "core_a_clk"; |
| 382 | |
| 383 | port { |
| 384 | stm_out_funnel_in0: endpoint { |
| 385 | remote-endpoint = <&funnel_in0_in_stm>; |
| 386 | }; |
| 387 | }; |
| 388 | |
| 389 | }; |
| 390 | |
| 391 | funnel_in0: funnel@0x6041000 { |
| 392 | compatible = "arm,primecell"; |
| 393 | arm,primecell-periphid = <0x0003b908>; |
| 394 | |
| 395 | reg = <0x6041000 0x1000>; |
| 396 | reg-names = "funnel-base"; |
| 397 | |
| 398 | coresight-name = "coresight-funnel-in0"; |
| 399 | |
| 400 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 401 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 402 | clock-names = "apb_pclk", "core_a_clk"; |
| 403 | |
| 404 | ports { |
| 405 | #address-cells = <1>; |
| 406 | #size-cells = <0>; |
| 407 | |
| 408 | port@0 { |
| 409 | reg = <0>; |
| 410 | funnel_in0_out_funnel_merg: endpoint { |
| 411 | remote-endpoint = |
| 412 | <&funnel_merg_in_funnel_in0>; |
| 413 | }; |
| 414 | }; |
| 415 | |
| 416 | port@1 { |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 417 | reg = <3>; |
| 418 | funnel_in0_in_funnel_spss: endpoint { |
| 419 | slave-mode; |
| 420 | remote-endpoint = |
| 421 | <&funnel_spss_out_funnel_in0>; |
| 422 | }; |
| 423 | }; |
| 424 | |
| 425 | port@2 { |
| 426 | reg = <6>; |
| 427 | funnel_in0_in_funnel_qatb: endpoint { |
| 428 | slave-mode; |
| 429 | remote-endpoint = |
| 430 | <&funnel_qatb_out_funnel_in0>; |
| 431 | }; |
| 432 | }; |
| 433 | |
| 434 | port@3 { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 435 | reg = <7>; |
| 436 | funnel_in0_in_stm: endpoint { |
| 437 | slave-mode; |
| 438 | remote-endpoint = <&stm_out_funnel_in0>; |
| 439 | }; |
| 440 | }; |
| 441 | }; |
| 442 | }; |
| 443 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 444 | funnel_in2: funnel@0x6043000 { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 445 | compatible = "arm,primecell"; |
| 446 | arm,primecell-periphid = <0x0003b908>; |
| 447 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 448 | reg = <0x6043000 0x1000>; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 449 | reg-names = "funnel-base"; |
| 450 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 451 | coresight-name = "coresight-funnel-in2"; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 452 | |
| 453 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 454 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 455 | clock-names = "apb_pclk", "core_a_clk"; |
| 456 | |
| 457 | ports { |
| 458 | #address-cells = <1>; |
| 459 | #size-cells = <0>; |
| 460 | |
| 461 | port@0 { |
| 462 | reg = <0>; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 463 | funnel_in2_out_funnel_merg: endpoint { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 464 | remote-endpoint = |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 465 | <&funnel_merg_in_funnel_in2>; |
| 466 | }; |
| 467 | }; |
| 468 | |
| 469 | port@1 { |
| 470 | reg = <1>; |
| 471 | funnel_in2_in_replicator_swao: endpoint { |
| 472 | slave-mode; |
| 473 | remote-endpoint = |
| 474 | <&replicator_swao_out_funnel_in2>; |
| 475 | }; |
| 476 | |
| 477 | }; |
| 478 | |
| 479 | port@2 { |
Satyajit Desai | 03889a1 | 2017-04-03 16:52:06 -0700 | [diff] [blame] | 480 | reg = <2>; |
| 481 | funnel_in2_in_funnel_modem: endpoint { |
| 482 | slave-mode; |
| 483 | remote-endpoint = |
| 484 | <&funnel_modem_out_funnel_in2>; |
| 485 | }; |
| 486 | |
| 487 | }; |
| 488 | |
| 489 | port@3 { |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 490 | reg = <5>; |
| 491 | funnel_in2_in_funnel_apss_merg: endpoint { |
| 492 | slave-mode; |
| 493 | remote-endpoint = |
| 494 | <&funnel_apss_merg_out_funnel_in2>; |
| 495 | }; |
| 496 | }; |
| 497 | |
| 498 | }; |
| 499 | }; |
| 500 | |
| 501 | tpda: tpda@6004000 { |
| 502 | compatible = "qcom,coresight-tpda"; |
| 503 | reg = <0x6004000 0x1000>; |
| 504 | reg-names = "tpda-base"; |
| 505 | |
| 506 | coresight-name = "coresight-tpda"; |
| 507 | |
| 508 | qcom,tpda-atid = <65>; |
Satyajit Desai | 03889a1 | 2017-04-03 16:52:06 -0700 | [diff] [blame] | 509 | qcom,bc-elem-size = <10 32>, |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 510 | <13 32>; |
Satyajit Desai | 03889a1 | 2017-04-03 16:52:06 -0700 | [diff] [blame] | 511 | qcom,tc-elem-size = <13 32>; |
| 512 | qcom,dsb-elem-size = <0 32>, |
| 513 | <2 32>, |
| 514 | <3 32>, |
Satyajit Desai | 6509f34 | 2017-04-18 13:03:57 -0700 | [diff] [blame] | 515 | <5 32>, |
Satyajit Desai | 03889a1 | 2017-04-03 16:52:06 -0700 | [diff] [blame] | 516 | <10 32>, |
| 517 | <11 32>, |
| 518 | <13 32>; |
| 519 | qcom,cmb-elem-size = <3 64>, |
| 520 | <7 64>, |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 521 | <13 64>; |
| 522 | |
| 523 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 524 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 525 | clock-names = "core_clk", "core_a_clk"; |
| 526 | |
| 527 | ports { |
| 528 | #address-cells = <1>; |
| 529 | #size-cells = <0>; |
| 530 | port@0 { |
| 531 | reg = <0>; |
| 532 | tpda_out_funnel_qatb: endpoint { |
| 533 | remote-endpoint = |
| 534 | <&funnel_qatb_in_tpda>; |
| 535 | }; |
| 536 | |
| 537 | }; |
| 538 | |
| 539 | port@1 { |
Satyajit Desai | 03889a1 | 2017-04-03 16:52:06 -0700 | [diff] [blame] | 540 | reg = <0>; |
| 541 | tpda_in_tpdm_center: endpoint { |
| 542 | slave-mode; |
| 543 | remote-endpoint = |
| 544 | <&tpdm_center_out_tpda>; |
| 545 | }; |
| 546 | }; |
| 547 | |
| 548 | port@2 { |
| 549 | reg = <2>; |
| 550 | tpda_in_funnel_dl_mm: endpoint { |
| 551 | slave-mode; |
| 552 | remote-endpoint = |
| 553 | <&funnel_dl_mm_out_tpda>; |
| 554 | }; |
| 555 | }; |
| 556 | |
| 557 | port@3 { |
| 558 | reg = <3>; |
| 559 | tpda_in_funnel_ddr_0: endpoint { |
| 560 | slave-mode; |
| 561 | remote-endpoint = |
| 562 | <&funnel_ddr_0_out_tpda>; |
| 563 | }; |
| 564 | }; |
| 565 | |
| 566 | port@4 { |
Satyajit Desai | 6509f34 | 2017-04-18 13:03:57 -0700 | [diff] [blame] | 567 | reg = <5>; |
| 568 | tpda_in_funnel_lpass: endpoint { |
| 569 | slave-mode; |
| 570 | remote-endpoint = |
| 571 | <&funnel_lpass_out_tpda>; |
| 572 | }; |
| 573 | }; |
| 574 | |
| 575 | port@5 { |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 576 | reg = <7>; |
| 577 | tpda_in_tpdm_vsense: endpoint { |
| 578 | slave-mode; |
| 579 | remote-endpoint = |
| 580 | <&tpdm_vsense_out_tpda>; |
| 581 | }; |
| 582 | }; |
| 583 | |
Satyajit Desai | 6509f34 | 2017-04-18 13:03:57 -0700 | [diff] [blame] | 584 | port@6 { |
Satyajit Desai | 03889a1 | 2017-04-03 16:52:06 -0700 | [diff] [blame] | 585 | reg = <10>; |
| 586 | tpda_in_tpdm_qm: endpoint { |
| 587 | slave-mode; |
| 588 | remote-endpoint = |
| 589 | <&tpdm_qm_out_tpda>; |
| 590 | }; |
| 591 | }; |
| 592 | |
Satyajit Desai | 6509f34 | 2017-04-18 13:03:57 -0700 | [diff] [blame] | 593 | port@7 { |
Satyajit Desai | 03889a1 | 2017-04-03 16:52:06 -0700 | [diff] [blame] | 594 | reg = <11>; |
| 595 | tpda_in_tpdm_north: endpoint { |
| 596 | slave-mode; |
| 597 | remote-endpoint = |
| 598 | <&tpdm_north_out_tpda>; |
| 599 | }; |
| 600 | }; |
| 601 | |
Satyajit Desai | 6509f34 | 2017-04-18 13:03:57 -0700 | [diff] [blame] | 602 | port@8 { |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 603 | reg = <13>; |
| 604 | tpda_in_tpdm_pimem: endpoint { |
| 605 | slave-mode; |
| 606 | remote-endpoint = |
| 607 | <&tpdm_pimem_out_tpda>; |
| 608 | }; |
| 609 | }; |
| 610 | }; |
| 611 | }; |
| 612 | |
Satyajit Desai | 03889a1 | 2017-04-03 16:52:06 -0700 | [diff] [blame] | 613 | funnel_modem: funnel@6832000 { |
| 614 | compatible = "arm,primecell"; |
| 615 | arm,primecell-periphid = <0x0003b908>; |
| 616 | |
| 617 | reg = <0x6832000 0x1000>; |
| 618 | reg-names = "funnel-base"; |
| 619 | |
| 620 | coresight-name = "coresight-funnel-modem"; |
| 621 | |
| 622 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 623 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 624 | clock-names = "apb_pclk", "core_a_clk"; |
| 625 | |
| 626 | ports { |
| 627 | #address-cells = <1>; |
| 628 | #size-cells = <0>; |
| 629 | |
| 630 | port@0 { |
| 631 | reg = <0>; |
| 632 | funnel_modem_out_funnel_in2: endpoint { |
| 633 | remote-endpoint = |
| 634 | <&funnel_in2_in_funnel_modem>; |
| 635 | }; |
| 636 | }; |
| 637 | |
| 638 | port@1 { |
| 639 | reg = <0>; |
| 640 | funnel_modem_in_tpda_modem: endpoint { |
| 641 | slave-mode; |
| 642 | remote-endpoint = |
| 643 | <&tpda_modem_out_funnel_modem>; |
| 644 | }; |
| 645 | }; |
| 646 | }; |
| 647 | }; |
| 648 | |
| 649 | tpda_modem: tpda@6831000 { |
| 650 | compatible = "qcom,coresight-tpda"; |
| 651 | reg = <0x6831000 0x1000>; |
| 652 | reg-names = "tpda-base"; |
| 653 | |
| 654 | coresight-name = "coresight-tpda-modem"; |
| 655 | |
| 656 | qcom,tpda-atid = <67>; |
| 657 | qcom,dsb-elem-size = <0 32>; |
| 658 | qcom,cmb-elem-size = <0 64>; |
| 659 | |
| 660 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 661 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 662 | clock-names = "core_clk", "core_a_clk"; |
| 663 | |
| 664 | ports { |
| 665 | #address-cells = <1>; |
| 666 | #size-cells = <0>; |
| 667 | port@0 { |
| 668 | reg = <0>; |
| 669 | tpda_modem_out_funnel_modem: endpoint { |
| 670 | remote-endpoint = |
| 671 | <&funnel_modem_in_tpda_modem>; |
| 672 | }; |
| 673 | }; |
| 674 | |
| 675 | port@1 { |
| 676 | reg = <0>; |
| 677 | tpda_modem_in_tpdm_modem: endpoint { |
| 678 | slave-mode; |
| 679 | remote-endpoint = |
| 680 | <&tpdm_modem_out_tpda_modem>; |
| 681 | }; |
| 682 | }; |
| 683 | }; |
| 684 | }; |
| 685 | |
| 686 | tpdm_modem: tpdm@6830000 { |
| 687 | compatible = "qcom,coresight-tpdm"; |
| 688 | reg = <0x6830000 0x1000>; |
| 689 | reg-names = "tpdm-base"; |
| 690 | |
| 691 | coresight-name = "coresight-tpdm-modem"; |
| 692 | |
| 693 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 694 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 695 | clock-names = "core_clk", "core_a_clk"; |
| 696 | |
| 697 | port { |
| 698 | tpdm_modem_out_tpda_modem: endpoint { |
| 699 | remote-endpoint = <&tpda_modem_in_tpdm_modem>; |
| 700 | }; |
| 701 | }; |
| 702 | }; |
| 703 | |
Satyajit Desai | 6509f34 | 2017-04-18 13:03:57 -0700 | [diff] [blame] | 704 | funnel_lpass: funnel@6845000 { |
| 705 | compatible = "arm,primecell"; |
| 706 | arm,primecell-periphid = <0x0003b908>; |
| 707 | |
| 708 | reg = <0x6845000 0x1000>; |
| 709 | reg-names = "funnel-base"; |
| 710 | |
| 711 | coresight-name = "coresight-funnel-lpass"; |
| 712 | |
| 713 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 714 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 715 | clock-names = "apb_pclk", "core_a_clk"; |
| 716 | |
| 717 | ports { |
| 718 | #address-cells = <1>; |
| 719 | #size-cells = <0>; |
| 720 | |
| 721 | port@0 { |
| 722 | reg = <0>; |
| 723 | funnel_lpass_out_tpda: endpoint { |
| 724 | remote-endpoint = |
| 725 | <&tpda_in_funnel_lpass>; |
| 726 | }; |
| 727 | }; |
| 728 | |
| 729 | port@1 { |
| 730 | reg = <0>; |
| 731 | funnel_lpass_in_tpdm_lpass: endpoint { |
| 732 | slave-mode; |
| 733 | remote-endpoint = |
| 734 | <&tpdm_lpass_out_funnel_lpass>; |
| 735 | }; |
| 736 | }; |
| 737 | }; |
| 738 | }; |
| 739 | |
| 740 | tpdm_lpass: tpdm@6844000 { |
| 741 | compatible = "qcom,coresight-tpdm"; |
| 742 | reg = <0x6844000 0x1000>; |
| 743 | reg-names = "tpdm-base"; |
| 744 | |
| 745 | coresight-name = "coresight-tpdm-lpass"; |
| 746 | |
| 747 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 748 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 749 | clock-names = "core_clk", "core_a_clk"; |
| 750 | |
| 751 | port { |
| 752 | tpdm_lpass_out_funnel_lpass: endpoint { |
| 753 | remote-endpoint = <&funnel_lpass_in_tpdm_lpass>; |
| 754 | }; |
| 755 | }; |
| 756 | }; |
| 757 | |
Satyajit Desai | 03889a1 | 2017-04-03 16:52:06 -0700 | [diff] [blame] | 758 | tpdm_center: tpdm@6c28000 { |
| 759 | compatible = "qcom,coresight-tpdm"; |
| 760 | reg = <0x6c28000 0x1000>; |
| 761 | reg-names = "tpdm-base"; |
| 762 | |
| 763 | coresight-name = "coresight-tpdm-center"; |
| 764 | |
| 765 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 766 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 767 | clock-names = "core_clk", "core_a_clk"; |
| 768 | |
| 769 | port { |
| 770 | tpdm_center_out_tpda: endpoint { |
| 771 | remote-endpoint = <&tpda_in_tpdm_center>; |
| 772 | }; |
| 773 | }; |
| 774 | }; |
| 775 | |
| 776 | tpdm_north: tpdm@6a24000 { |
| 777 | compatible = "qcom,coresight-tpdm"; |
| 778 | reg = <0x6a24000 0x1000>; |
| 779 | reg-names = "tpdm-base"; |
| 780 | |
| 781 | coresight-name = "coresight-tpdm-north"; |
| 782 | |
| 783 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 784 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 785 | clock-names = "core_clk", "core_a_clk"; |
| 786 | |
| 787 | port { |
| 788 | tpdm_north_out_tpda: endpoint { |
| 789 | remote-endpoint = <&tpda_in_tpdm_north>; |
| 790 | }; |
| 791 | }; |
| 792 | }; |
| 793 | |
| 794 | tpdm_qm: tpdm@69d0000 { |
| 795 | compatible = "qcom,coresight-tpdm"; |
| 796 | reg = <0x69d0000 0x1000>; |
| 797 | reg-names = "tpdm-base"; |
| 798 | |
| 799 | coresight-name = "coresight-tpdm-qm"; |
| 800 | |
| 801 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 802 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 803 | clock-names = "core_clk", "core_a_clk"; |
| 804 | |
| 805 | port { |
| 806 | tpdm_qm_out_tpda: endpoint { |
| 807 | remote-endpoint = <&tpda_in_tpdm_qm>; |
| 808 | }; |
| 809 | }; |
| 810 | }; |
| 811 | |
| 812 | tpda_apss: tpda@7862000 { |
| 813 | compatible = "qcom,coresight-tpda"; |
| 814 | reg = <0x7862000 0x1000>; |
| 815 | reg-names = "tpda-base"; |
| 816 | |
| 817 | coresight-name = "coresight-tpda-apss"; |
| 818 | |
| 819 | qcom,tpda-atid = <66>; |
| 820 | qcom,dsb-elem-size = <0 32>; |
| 821 | |
| 822 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 823 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 824 | clock-names = "core_clk", "core_a_clk"; |
| 825 | |
| 826 | ports { |
| 827 | #address-cells = <1>; |
| 828 | #size-cells = <0>; |
| 829 | port@0 { |
| 830 | reg = <0>; |
| 831 | tpda_apss_out_funnel_apss_merg: endpoint { |
| 832 | remote-endpoint = |
| 833 | <&funnel_apss_merg_in_tpda_apss>; |
| 834 | }; |
| 835 | }; |
| 836 | |
| 837 | port@1 { |
| 838 | reg = <0>; |
| 839 | tpda_apss_in_tpdm_apss: endpoint { |
| 840 | slave-mode; |
| 841 | remote-endpoint = |
| 842 | <&tpdm_apss_out_tpda_apss>; |
| 843 | }; |
| 844 | }; |
| 845 | }; |
| 846 | }; |
| 847 | |
| 848 | tpdm_apss: tpdm@7860000 { |
| 849 | compatible = "qcom,coresight-tpdm"; |
| 850 | reg = <0x7860000 0x1000>; |
| 851 | reg-names = "tpdm-base"; |
| 852 | |
| 853 | coresight-name = "coresight-tpdm-apss"; |
| 854 | |
| 855 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 856 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 857 | clock-names = "core_clk", "core_a_clk"; |
| 858 | |
| 859 | port { |
| 860 | tpdm_apss_out_tpda_apss: endpoint { |
| 861 | remote-endpoint = <&tpda_apss_in_tpdm_apss>; |
| 862 | }; |
| 863 | }; |
| 864 | }; |
| 865 | |
| 866 | tpda_llm_silver: tpda@78c0000 { |
| 867 | compatible = "qcom,coresight-tpda"; |
| 868 | reg = <0x78c0000 0x1000>; |
| 869 | reg-names = "tpda-base"; |
| 870 | |
| 871 | coresight-name = "coresight-tpda-llm-silver"; |
| 872 | |
| 873 | qcom,tpda-atid = <72>; |
| 874 | qcom,cmb-elem-size = <0 64>; |
| 875 | |
| 876 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 877 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 878 | clock-names = "core_clk", "core_a_clk"; |
| 879 | |
| 880 | ports { |
| 881 | #address-cells = <1>; |
| 882 | #size-cells = <0>; |
| 883 | port@0 { |
| 884 | reg = <0>; |
| 885 | tpda_llm_silver_out_funnel_apss_merg: endpoint { |
| 886 | remote-endpoint = |
| 887 | <&funnel_apss_merg_in_tpda_llm_silver>; |
| 888 | }; |
| 889 | }; |
| 890 | |
| 891 | port@1 { |
| 892 | reg = <0>; |
| 893 | tpda_llm_silver_in_tpdm_llm_silver: endpoint { |
| 894 | slave-mode; |
| 895 | remote-endpoint = |
| 896 | <&tpdm_llm_silver_out_tpda_llm_silver>; |
| 897 | }; |
| 898 | }; |
| 899 | }; |
| 900 | }; |
| 901 | |
| 902 | tpdm_llm_silver: tpdm@78a0000 { |
| 903 | compatible = "qcom,coresight-tpdm"; |
| 904 | reg = <0x78a0000 0x1000>; |
| 905 | reg-names = "tpdm-base"; |
| 906 | |
| 907 | coresight-name = "coresight-tpdm-llm-silver"; |
| 908 | |
| 909 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 910 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 911 | clock-names = "core_clk", "core_a_clk"; |
| 912 | |
| 913 | port { |
| 914 | tpdm_llm_silver_out_tpda_llm_silver: endpoint { |
| 915 | remote-endpoint = |
| 916 | <&tpda_llm_silver_in_tpdm_llm_silver>; |
| 917 | }; |
| 918 | }; |
| 919 | }; |
| 920 | |
| 921 | tpda_llm_gold: tpda@78d0000 { |
| 922 | compatible = "qcom,coresight-tpda"; |
| 923 | reg = <0x78d0000 0x1000>; |
| 924 | reg-names = "tpda-base"; |
| 925 | |
| 926 | coresight-name = "coresight-tpda-llm-gold"; |
| 927 | |
| 928 | qcom,tpda-atid = <73>; |
| 929 | qcom,cmb-elem-size = <0 64>; |
| 930 | |
| 931 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 932 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 933 | clock-names = "core_clk", "core_a_clk"; |
| 934 | |
| 935 | ports { |
| 936 | #address-cells = <1>; |
| 937 | #size-cells = <0>; |
| 938 | port@0 { |
| 939 | reg = <0>; |
| 940 | tpda_llm_gold_out_funnel_apss_merg: endpoint { |
| 941 | remote-endpoint = |
| 942 | <&funnel_apss_merg_in_tpda_llm_gold>; |
| 943 | }; |
| 944 | }; |
| 945 | |
| 946 | port@1 { |
| 947 | reg = <0>; |
| 948 | tpda_llm_gold_in_tpdm_llm_gold: endpoint { |
| 949 | slave-mode; |
| 950 | remote-endpoint = |
| 951 | <&tpdm_llm_gold_out_tpda_llm_gold>; |
| 952 | }; |
| 953 | }; |
| 954 | }; |
| 955 | }; |
| 956 | |
| 957 | tpdm_llm_gold: tpdm@78b0000 { |
| 958 | compatible = "qcom,coresight-tpdm"; |
| 959 | reg = <0x78b0000 0x1000>; |
| 960 | reg-names = "tpdm-base"; |
| 961 | |
| 962 | coresight-name = "coresight-tpdm-llm-gold"; |
| 963 | |
| 964 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 965 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 966 | clock-names = "core_clk", "core_a_clk"; |
| 967 | |
| 968 | port { |
| 969 | tpdm_llm_gold_out_tpda_llm_gold: endpoint { |
| 970 | remote-endpoint = |
| 971 | <&tpda_llm_gold_in_tpdm_llm_gold>; |
| 972 | }; |
| 973 | }; |
| 974 | }; |
| 975 | |
| 976 | funnel_dl_mm: funnel@6c0b000 { |
| 977 | compatible = "arm,primecell"; |
| 978 | arm,primecell-periphid = <0x0003b908>; |
| 979 | |
| 980 | reg = <0x6c0b000 0x1000>; |
| 981 | reg-names = "funnel-base"; |
| 982 | |
| 983 | coresight-name = "coresight-funnel-dl-mm"; |
| 984 | |
| 985 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 986 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 987 | clock-names = "apb_pclk", "core_a_clk"; |
| 988 | |
| 989 | ports { |
| 990 | #address-cells = <1>; |
| 991 | #size-cells = <0>; |
| 992 | |
| 993 | port@0 { |
| 994 | reg = <0>; |
| 995 | funnel_dl_mm_out_tpda: endpoint { |
| 996 | remote-endpoint = |
| 997 | <&tpda_in_funnel_dl_mm>; |
| 998 | }; |
| 999 | }; |
| 1000 | |
| 1001 | port@1 { |
| 1002 | reg = <1>; |
| 1003 | funnel_dl_mm_in_tpdm_mm: endpoint { |
| 1004 | slave-mode; |
| 1005 | remote-endpoint = |
| 1006 | <&tpdm_mm_out_funnel_dl_mm>; |
| 1007 | }; |
| 1008 | }; |
| 1009 | }; |
| 1010 | }; |
| 1011 | |
| 1012 | tpdm_mm: tpdm@6c08000 { |
| 1013 | compatible = "qcom,coresight-tpdm"; |
| 1014 | reg = <0x6c08000 0x1000>; |
| 1015 | reg-names = "tpdm-base"; |
| 1016 | |
| 1017 | coresight-name = "coresight-tpdm-mm"; |
| 1018 | |
| 1019 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1020 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1021 | clock-names = "core_clk", "core_a_clk"; |
| 1022 | |
| 1023 | port { |
| 1024 | tpdm_mm_out_funnel_dl_mm: endpoint { |
| 1025 | remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; |
| 1026 | }; |
| 1027 | }; |
| 1028 | }; |
| 1029 | |
| 1030 | funnel_ddr_0: funnel@69e2000 { |
| 1031 | compatible = "arm,primecell"; |
| 1032 | arm,primecell-periphid = <0x0003b908>; |
| 1033 | |
| 1034 | reg = <0x69e2000 0x1000>; |
| 1035 | reg-names = "funnel-base"; |
| 1036 | |
| 1037 | coresight-name = "coresight-funnel-ddr-0"; |
| 1038 | |
| 1039 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1040 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1041 | clock-names = "apb_pclk", "core_a_clk"; |
| 1042 | |
| 1043 | ports { |
| 1044 | #address-cells = <1>; |
| 1045 | #size-cells = <0>; |
| 1046 | |
| 1047 | port@0 { |
| 1048 | reg = <0>; |
| 1049 | funnel_ddr_0_out_tpda: endpoint { |
| 1050 | remote-endpoint = |
| 1051 | <&tpda_in_funnel_ddr_0>; |
| 1052 | }; |
| 1053 | }; |
| 1054 | |
| 1055 | port@1 { |
| 1056 | reg = <0>; |
| 1057 | funnel_ddr_0_in_tpdm_ddr: endpoint { |
| 1058 | slave-mode; |
| 1059 | remote-endpoint = |
| 1060 | <&tpdm_ddr_out_funnel_ddr_0>; |
| 1061 | }; |
| 1062 | }; |
| 1063 | }; |
| 1064 | }; |
| 1065 | |
| 1066 | tpdm_ddr: tpdm@69e0000 { |
| 1067 | compatible = "qcom,coresight-tpdm"; |
| 1068 | reg = <0x69e0000 0x1000>; |
| 1069 | reg-names = "tpdm-base"; |
| 1070 | |
| 1071 | coresight-name = "coresight-tpdm-ddr"; |
| 1072 | |
| 1073 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1074 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1075 | clock-names = "core_clk", "core_a_clk"; |
| 1076 | |
| 1077 | port { |
| 1078 | tpdm_ddr_out_funnel_ddr_0: endpoint { |
| 1079 | remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>; |
| 1080 | }; |
| 1081 | }; |
| 1082 | }; |
| 1083 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1084 | tpdm_pimem: tpdm@6850000 { |
| 1085 | compatible = "qcom,coresight-tpdm"; |
| 1086 | reg = <0x6850000 0x1000>; |
| 1087 | reg-names = "tpdm-base"; |
| 1088 | |
| 1089 | coresight-name = "coresight-tpdm-pimem"; |
| 1090 | |
| 1091 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1092 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1093 | clock-names = "core_clk", "core_a_clk"; |
| 1094 | |
| 1095 | port { |
| 1096 | tpdm_pimem_out_tpda: endpoint { |
| 1097 | remote-endpoint = <&tpda_in_tpdm_pimem>; |
| 1098 | }; |
| 1099 | }; |
| 1100 | }; |
| 1101 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1102 | tpdm_vsense: tpdm@6840000 { |
| 1103 | compatible = "qcom,coresight-tpdm"; |
| 1104 | reg = <0x6840000 0x1000>; |
| 1105 | reg-names = "tpdm-base"; |
| 1106 | |
| 1107 | coresight-name = "coresight-tpdm-vsense"; |
| 1108 | |
| 1109 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1110 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1111 | clock-names = "core_clk", "core_a_clk"; |
| 1112 | |
| 1113 | port{ |
| 1114 | tpdm_vsense_out_tpda: endpoint { |
| 1115 | remote-endpoint = <&tpda_in_tpdm_vsense>; |
| 1116 | }; |
| 1117 | }; |
| 1118 | }; |
| 1119 | |
| 1120 | tpda_olc: tpda@7832000 { |
| 1121 | compatible = "qcom,coresight-tpda"; |
| 1122 | reg = <0x7832000 0x1000>; |
| 1123 | reg-names = "tpda-base"; |
| 1124 | |
| 1125 | coresight-name = "coresight-tpda-olc"; |
| 1126 | |
| 1127 | qcom,tpda-atid = <69>; |
| 1128 | qcom,cmb-elem-size = <0 64>; |
| 1129 | |
| 1130 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1131 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1132 | clock-names = "core_clk", "core_a_clk"; |
| 1133 | |
| 1134 | ports { |
| 1135 | #address-cells = <1>; |
| 1136 | #size-cells = <0>; |
| 1137 | port@0 { |
| 1138 | reg = <0>; |
| 1139 | tpda_olc_out_funnel_apss_merg: endpoint { |
| 1140 | remote-endpoint = |
| 1141 | <&funnel_apss_merg_in_tpda_olc>; |
| 1142 | }; |
| 1143 | }; |
| 1144 | port@1 { |
| 1145 | reg = <0>; |
| 1146 | tpda_olc_in_tpdm_olc: endpoint { |
| 1147 | slave-mode; |
| 1148 | remote-endpoint = |
| 1149 | <&tpdm_olc_out_tpda_olc>; |
| 1150 | }; |
| 1151 | }; |
| 1152 | }; |
| 1153 | }; |
| 1154 | |
| 1155 | tpdm_olc: tpdm@7830000 { |
| 1156 | compatible = "qcom,coresight-tpdm"; |
| 1157 | reg = <0x7830000 0x1000>; |
| 1158 | reg-names = "tpdm-base"; |
| 1159 | |
| 1160 | coresight-name = "coresight-tpdm-olc"; |
| 1161 | |
| 1162 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1163 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1164 | clock-names = "core_clk", "core_a_clk"; |
| 1165 | |
| 1166 | port{ |
| 1167 | tpdm_olc_out_tpda_olc: endpoint { |
| 1168 | remote-endpoint = <&tpda_olc_in_tpdm_olc>; |
| 1169 | }; |
| 1170 | }; |
| 1171 | }; |
| 1172 | |
| 1173 | tpda_spss: tpda@6882000 { |
| 1174 | compatible = "qcom,coresight-tpda"; |
| 1175 | reg = <0x6882000 0x1000>; |
| 1176 | reg-names = "tpda-base"; |
| 1177 | |
| 1178 | coresight-name = "coresight-tpda-spss"; |
| 1179 | |
| 1180 | qcom,tpda-atid = <70>; |
| 1181 | qcom,dsb-elem-size = <0 32>; |
| 1182 | |
| 1183 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1184 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1185 | clock-names = "core_clk", "core_a_clk"; |
| 1186 | |
| 1187 | ports { |
| 1188 | #address-cells = <1>; |
| 1189 | #size-cells = <0>; |
| 1190 | port@0 { |
| 1191 | reg = <0>; |
| 1192 | tpda_spss_out_funnel_spss: endpoint { |
| 1193 | remote-endpoint = |
| 1194 | <&funnel_spss_in_tpda_spss>; |
| 1195 | }; |
| 1196 | }; |
| 1197 | port@1 { |
| 1198 | reg = <0>; |
| 1199 | tpda_spss_in_tpdm_spss: endpoint { |
| 1200 | slave-mode; |
| 1201 | remote-endpoint = |
| 1202 | <&tpdm_spss_out_tpda_spss>; |
| 1203 | }; |
| 1204 | }; |
| 1205 | }; |
| 1206 | }; |
| 1207 | |
| 1208 | tpdm_spss: tpdm@6880000 { |
| 1209 | compatible = "qcom,coresight-tpdm"; |
| 1210 | reg = <0x6880000 0x1000>; |
| 1211 | reg-names = "tpdm-base"; |
| 1212 | |
| 1213 | coresight-name = "coresight-tpdm-spss"; |
| 1214 | |
| 1215 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1216 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1217 | clock-names = "core_clk", "core_a_clk"; |
| 1218 | |
| 1219 | qcom,msr-fix-req; |
| 1220 | |
| 1221 | port{ |
| 1222 | tpdm_spss_out_tpda_spss: endpoint { |
| 1223 | remote-endpoint = <&tpda_spss_in_tpdm_spss>; |
| 1224 | }; |
| 1225 | }; |
| 1226 | }; |
| 1227 | |
| 1228 | funnel_spss: funnel@6883000 { |
| 1229 | compatible = "arm,primecell"; |
| 1230 | arm,primecell-periphid = <0x0003b908>; |
| 1231 | |
| 1232 | reg = <0x6883000 0x1000>; |
| 1233 | reg-names = "funnel-base"; |
| 1234 | |
| 1235 | coresight-name = "coresight-funnel-spss"; |
| 1236 | |
| 1237 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1238 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1239 | clock-names = "apb_pclk", "core_a_clk"; |
| 1240 | |
| 1241 | ports { |
| 1242 | #address-cells = <1>; |
| 1243 | #size-cells = <0>; |
| 1244 | |
| 1245 | port@0 { |
| 1246 | reg = <0>; |
| 1247 | funnel_spss_out_funnel_in0: endpoint { |
| 1248 | remote-endpoint = |
| 1249 | <&funnel_in0_in_funnel_spss>; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 1250 | }; |
| 1251 | }; |
| 1252 | |
| 1253 | port@1 { |
| 1254 | reg = <0>; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1255 | funnel_spss_in_tpda_spss: endpoint { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 1256 | slave-mode; |
| 1257 | remote-endpoint = |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1258 | <&tpda_spss_out_funnel_spss>; |
| 1259 | }; |
| 1260 | }; |
| 1261 | }; |
| 1262 | }; |
| 1263 | |
| 1264 | funnel_qatb: funnel@6005000 { |
| 1265 | compatible = "arm,primecell"; |
| 1266 | arm,primecell-periphid = <0x0003b908>; |
| 1267 | |
| 1268 | reg = <0x6005000 0x1000>; |
| 1269 | reg-names = "funnel-base"; |
| 1270 | |
| 1271 | coresight-name = "coresight-funnel-qatb"; |
| 1272 | |
| 1273 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1274 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1275 | clock-names = "apb_pclk", "core_a_clk"; |
| 1276 | |
| 1277 | ports { |
| 1278 | #address-cells = <1>; |
| 1279 | #size-cells = <0>; |
| 1280 | |
| 1281 | port@0 { |
| 1282 | reg = <0>; |
| 1283 | funnel_qatb_out_funnel_in0: endpoint { |
| 1284 | remote-endpoint = |
| 1285 | <&funnel_in0_in_funnel_qatb>; |
| 1286 | }; |
| 1287 | }; |
| 1288 | |
| 1289 | port@1 { |
| 1290 | reg = <0>; |
| 1291 | funnel_qatb_in_tpda: endpoint { |
| 1292 | slave-mode; |
| 1293 | remote-endpoint = |
| 1294 | <&tpda_out_funnel_qatb>; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 1295 | }; |
| 1296 | }; |
| 1297 | }; |
| 1298 | }; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1299 | |
| 1300 | cti0: cti@6010000 { |
| 1301 | compatible = "arm,coresight-cti"; |
| 1302 | reg = <0x6010000 0x1000>; |
| 1303 | reg-names = "cti-base"; |
| 1304 | |
| 1305 | coresight-name = "coresight-cti0"; |
| 1306 | |
| 1307 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1308 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1309 | clock-names = "core_clk", "core_a_clk"; |
| 1310 | }; |
| 1311 | |
| 1312 | cti1: cti@6011000 { |
| 1313 | compatible = "arm,coresight-cti"; |
| 1314 | reg = <0x6011000 0x1000>; |
| 1315 | reg-names = "cti-base"; |
| 1316 | |
| 1317 | coresight-name = "coresight-cti1"; |
| 1318 | |
| 1319 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1320 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1321 | clock-names = "core_clk", "core_a_clk"; |
| 1322 | }; |
| 1323 | |
| 1324 | cti2: cti@6012000 { |
| 1325 | compatible = "arm,coresight-cti"; |
| 1326 | reg = <0x6012000 0x1000>; |
| 1327 | reg-names = "cti-base"; |
| 1328 | |
| 1329 | coresight-name = "coresight-cti2"; |
| 1330 | |
| 1331 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1332 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1333 | clock-names = "core_clk", "core_a_clk"; |
| 1334 | }; |
| 1335 | |
| 1336 | cti3: cti@6013000 { |
| 1337 | compatible = "arm,coresight-cti"; |
| 1338 | reg = <0x6013000 0x1000>; |
| 1339 | reg-names = "cti-base"; |
| 1340 | |
| 1341 | coresight-name = "coresight-cti3"; |
| 1342 | |
| 1343 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1344 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1345 | clock-names = "core_clk", "core_a_clk"; |
| 1346 | }; |
| 1347 | |
| 1348 | cti4: cti@6014000 { |
| 1349 | compatible = "arm,coresight-cti"; |
| 1350 | reg = <0x6014000 0x1000>; |
| 1351 | reg-names = "cti-base"; |
| 1352 | |
| 1353 | coresight-name = "coresight-cti4"; |
| 1354 | |
| 1355 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1356 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1357 | clock-names = "core_clk", "core_a_clk"; |
| 1358 | }; |
| 1359 | |
| 1360 | cti5: cti@6015000 { |
| 1361 | compatible = "arm,coresight-cti"; |
| 1362 | reg = <0x6015000 0x1000>; |
| 1363 | reg-names = "cti-base"; |
| 1364 | |
| 1365 | coresight-name = "coresight-cti5"; |
| 1366 | |
| 1367 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1368 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1369 | clock-names = "core_clk", "core_a_clk"; |
| 1370 | }; |
| 1371 | |
| 1372 | cti6: cti@6016000 { |
| 1373 | compatible = "arm,coresight-cti"; |
| 1374 | reg = <0x6016000 0x1000>; |
| 1375 | reg-names = "cti-base"; |
| 1376 | |
| 1377 | coresight-name = "coresight-cti6"; |
| 1378 | |
| 1379 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1380 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1381 | clock-names = "core_clk", "core_a_clk"; |
| 1382 | }; |
| 1383 | |
| 1384 | cti7: cti@6017000 { |
| 1385 | compatible = "arm,coresight-cti"; |
| 1386 | reg = <0x6017000 0x1000>; |
| 1387 | reg-names = "cti-base"; |
| 1388 | |
| 1389 | coresight-name = "coresight-cti7"; |
| 1390 | |
| 1391 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1392 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1393 | clock-names = "core_clk", "core_a_clk"; |
| 1394 | }; |
| 1395 | |
| 1396 | cti8: cti@6018000 { |
| 1397 | compatible = "arm,coresight-cti"; |
| 1398 | reg = <0x6018000 0x1000>; |
| 1399 | reg-names = "cti-base"; |
| 1400 | |
| 1401 | coresight-name = "coresight-cti8"; |
| 1402 | |
| 1403 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1404 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1405 | clock-names = "core_clk", "core_a_clk"; |
| 1406 | }; |
| 1407 | |
| 1408 | cti9: cti@6019000 { |
| 1409 | compatible = "arm,coresight-cti"; |
| 1410 | reg = <0x6019000 0x1000>; |
| 1411 | reg-names = "cti-base"; |
| 1412 | |
| 1413 | coresight-name = "coresight-cti9"; |
| 1414 | |
| 1415 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1416 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1417 | clock-names = "core_clk", "core_a_clk"; |
| 1418 | }; |
| 1419 | |
| 1420 | cti10: cti@601a000 { |
| 1421 | compatible = "arm,coresight-cti"; |
| 1422 | reg = <0x601a000 0x1000>; |
| 1423 | reg-names = "cti-base"; |
| 1424 | |
| 1425 | coresight-name = "coresight-cti10"; |
| 1426 | |
| 1427 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1428 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1429 | clock-names = "core_clk", "core_a_clk"; |
| 1430 | }; |
| 1431 | |
| 1432 | cti11: cti@601b000 { |
| 1433 | compatible = "arm,coresight-cti"; |
| 1434 | reg = <0x601b000 0x1000>; |
| 1435 | reg-names = "cti-base"; |
| 1436 | |
| 1437 | coresight-name = "coresight-cti11"; |
| 1438 | |
| 1439 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1440 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1441 | clock-names = "core_clk", "core_a_clk"; |
| 1442 | }; |
| 1443 | |
| 1444 | cti12: cti@601c000 { |
| 1445 | compatible = "arm,coresight-cti"; |
| 1446 | reg = <0x601c000 0x1000>; |
| 1447 | reg-names = "cti-base"; |
| 1448 | |
| 1449 | coresight-name = "coresight-cti12"; |
| 1450 | |
| 1451 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1452 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1453 | clock-names = "core_clk", "core_a_clk"; |
| 1454 | }; |
| 1455 | |
| 1456 | cti13: cti@601d000 { |
| 1457 | compatible = "arm,coresight-cti"; |
| 1458 | reg = <0x601d000 0x1000>; |
| 1459 | reg-names = "cti-base"; |
| 1460 | |
| 1461 | coresight-name = "coresight-cti13"; |
| 1462 | |
| 1463 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1464 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1465 | clock-names = "core_clk", "core_a_clk"; |
| 1466 | }; |
| 1467 | |
| 1468 | cti14: cti@601e000 { |
| 1469 | compatible = "arm,coresight-cti"; |
| 1470 | reg = <0x601e000 0x1000>; |
| 1471 | reg-names = "cti-base"; |
| 1472 | |
| 1473 | coresight-name = "coresight-cti14"; |
| 1474 | |
| 1475 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1476 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1477 | clock-names = "core_clk", "core_a_clk"; |
| 1478 | }; |
| 1479 | |
| 1480 | cti15: cti@601f000 { |
| 1481 | compatible = "arm,coresight-cti"; |
| 1482 | reg = <0x601f000 0x1000>; |
| 1483 | reg-names = "cti-base"; |
| 1484 | |
| 1485 | coresight-name = "coresight-cti15"; |
| 1486 | |
| 1487 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1488 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1489 | clock-names = "core_clk", "core_a_clk"; |
| 1490 | }; |
| 1491 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1492 | cti_cpu0: cti@7020000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1493 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1494 | reg = <0x7020000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1495 | reg-names = "cti-base"; |
| 1496 | |
| 1497 | coresight-name = "coresight-cti-cpu0"; |
| 1498 | cpu = <&CPU0>; |
| 1499 | |
| 1500 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1501 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1502 | clock-names = "core_clk", "core_a_clk"; |
| 1503 | }; |
| 1504 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1505 | cti_cpu1: cti@7120000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1506 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1507 | reg = <0x7120000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1508 | reg-names = "cti-base"; |
| 1509 | |
| 1510 | coresight-name = "coresight-cti-cpu1"; |
| 1511 | cpu = <&CPU1>; |
| 1512 | |
| 1513 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1514 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1515 | clock-names = "core_clk", "core_a_clk"; |
| 1516 | }; |
| 1517 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1518 | cti_cpu2: cti@7220000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1519 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1520 | reg = <0x7220000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1521 | reg-names = "cti-base"; |
| 1522 | |
| 1523 | coresight-name = "coresight-cti-cpu2"; |
| 1524 | cpu = <&CPU2>; |
| 1525 | |
| 1526 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1527 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1528 | clock-names = "core_clk", "core_a_clk"; |
| 1529 | }; |
| 1530 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1531 | cti_cpu3: cti@7320000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1532 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1533 | reg = <0x7320000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1534 | reg-names = "cti-base"; |
| 1535 | |
| 1536 | coresight-name = "coresight-cti-cpu3"; |
| 1537 | cpu = <&CPU3>; |
| 1538 | |
| 1539 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1540 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1541 | clock-names = "core_clk", "core_a_clk"; |
| 1542 | }; |
| 1543 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1544 | cti_cpu4: cti@7420000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1545 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1546 | reg = <0x7420000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1547 | reg-names = "cti-base"; |
| 1548 | |
| 1549 | coresight-name = "coresight-cti-cpu4"; |
| 1550 | cpu = <&CPU4>; |
| 1551 | |
| 1552 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1553 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1554 | clock-names = "core_clk", "core_a_clk"; |
| 1555 | }; |
| 1556 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1557 | cti_cpu5: cti@7520000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1558 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1559 | reg = <0x7520000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1560 | reg-names = "cti-base"; |
| 1561 | |
| 1562 | coresight-name = "coresight-cti-cpu5"; |
| 1563 | cpu = <&CPU5>; |
| 1564 | |
| 1565 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1566 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1567 | clock-names = "core_clk", "core_a_clk"; |
| 1568 | }; |
| 1569 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1570 | cti_cpu6: cti@7620000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1571 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1572 | reg = <0x7620000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1573 | reg-names = "cti-base"; |
| 1574 | |
| 1575 | coresight-name = "coresight-cti-cpu6"; |
| 1576 | cpu = <&CPU6>; |
| 1577 | |
| 1578 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1579 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1580 | clock-names = "core_clk", "core_a_clk"; |
| 1581 | }; |
| 1582 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1583 | cti_cpu7: cti@7720000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1584 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1585 | reg = <0x7720000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1586 | reg-names = "cti-base"; |
| 1587 | |
| 1588 | coresight-name = "coresight-cti-cpu7"; |
| 1589 | cpu = <&CPU7>; |
| 1590 | |
| 1591 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1592 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1593 | clock-names = "core_clk", "core_a_clk"; |
| 1594 | }; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1595 | |
| 1596 | dummy_eud: dummy_sink { |
| 1597 | compatible = "qcom,coresight-dummy"; |
| 1598 | |
| 1599 | coresight-name = "coresight-eud"; |
| 1600 | |
| 1601 | qcom,dummy-sink; |
| 1602 | port { |
| 1603 | eud_in_replicator_swao: endpoint { |
| 1604 | slave-mode; |
| 1605 | remote-endpoint = |
| 1606 | <&replicator_swao_out_eud>; |
| 1607 | }; |
| 1608 | }; |
| 1609 | }; |
| 1610 | |
| 1611 | funnel_apss_merg: funnel@7810000 { |
| 1612 | compatible = "arm,primecell"; |
| 1613 | arm,primecell-periphid = <0x0003b908>; |
| 1614 | |
| 1615 | reg = <0x7810000 0x1000>; |
| 1616 | reg-names = "funnel-base"; |
| 1617 | |
| 1618 | coresight-name = "coresight-funnel-apss-merg"; |
| 1619 | |
| 1620 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1621 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1622 | clock-names = "apb_pclk", "core_a_clk"; |
| 1623 | |
| 1624 | ports { |
| 1625 | #address-cells = <1>; |
| 1626 | #size-cells = <0>; |
| 1627 | |
| 1628 | port@0 { |
| 1629 | reg = <0>; |
| 1630 | funnel_apss_merg_out_funnel_in2: endpoint { |
| 1631 | remote-endpoint = |
| 1632 | <&funnel_in2_in_funnel_apss_merg>; |
| 1633 | }; |
| 1634 | }; |
| 1635 | |
| 1636 | port@1 { |
| 1637 | reg = <0>; |
| 1638 | funnel_apss_merg_in_funnel_apss: endpoint { |
| 1639 | slave-mode; |
| 1640 | remote-endpoint = |
| 1641 | <&funnel_apss_out_funnel_apss_merg>; |
| 1642 | }; |
| 1643 | }; |
| 1644 | |
| 1645 | port@2 { |
Satyajit Desai | 03889a1 | 2017-04-03 16:52:06 -0700 | [diff] [blame] | 1646 | reg = <2>; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1647 | funnel_apss_merg_in_tpda_olc: endpoint { |
| 1648 | slave-mode; |
| 1649 | remote-endpoint = |
| 1650 | <&tpda_olc_out_funnel_apss_merg>; |
| 1651 | }; |
| 1652 | }; |
Satyajit Desai | 03889a1 | 2017-04-03 16:52:06 -0700 | [diff] [blame] | 1653 | |
| 1654 | port@3 { |
| 1655 | reg = <4>; |
| 1656 | funnel_apss_merg_in_tpda_apss: endpoint { |
| 1657 | slave-mode; |
| 1658 | remote-endpoint = |
| 1659 | <&tpda_apss_out_funnel_apss_merg>; |
| 1660 | }; |
| 1661 | }; |
| 1662 | |
| 1663 | port@4 { |
| 1664 | reg = <5>; |
| 1665 | funnel_apss_merg_in_tpda_llm_silver: endpoint { |
| 1666 | slave-mode; |
| 1667 | remote-endpoint = |
| 1668 | <&tpda_llm_silver_out_funnel_apss_merg>; |
| 1669 | }; |
| 1670 | }; |
| 1671 | |
| 1672 | port@5 { |
| 1673 | reg = <6>; |
| 1674 | funnel_apss_merg_in_tpda_llm_gold: endpoint { |
| 1675 | slave-mode; |
| 1676 | remote-endpoint = |
| 1677 | <&tpda_llm_gold_out_funnel_apss_merg>; |
| 1678 | }; |
| 1679 | }; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1680 | }; |
| 1681 | }; |
| 1682 | |
Satyajit Desai | da8d7bf | 2017-04-10 11:34:58 -0700 | [diff] [blame] | 1683 | etm0: etm@7040000 { |
| 1684 | compatible = "arm,primecell"; |
| 1685 | arm,primecell-periphid = <0x000bb95d>; |
| 1686 | |
| 1687 | reg = <0x7040000 0x1000>; |
| 1688 | cpu = <&CPU0>; |
| 1689 | |
| 1690 | coresight-name = "coresight-etm0"; |
| 1691 | |
| 1692 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1693 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1694 | clock-names = "apb_pclk", "core_a_clk"; |
| 1695 | |
| 1696 | port { |
| 1697 | etm0_out_funnel_apss: endpoint { |
| 1698 | remote-endpoint = <&funnel_apss_in_etm0>; |
| 1699 | }; |
| 1700 | }; |
| 1701 | }; |
| 1702 | |
| 1703 | etm1: etm@7140000 { |
| 1704 | compatible = "arm,primecell"; |
| 1705 | arm,primecell-periphid = <0x000bb95d>; |
| 1706 | |
| 1707 | reg = <0x7140000 0x1000>; |
| 1708 | cpu = <&CPU1>; |
| 1709 | |
| 1710 | coresight-name = "coresight-etm1"; |
| 1711 | |
| 1712 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1713 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1714 | clock-names = "apb_pclk", "core_a_clk"; |
| 1715 | |
| 1716 | port { |
| 1717 | etm1_out_funnel_apss: endpoint { |
| 1718 | remote-endpoint = <&funnel_apss_in_etm1>; |
| 1719 | }; |
| 1720 | }; |
| 1721 | }; |
| 1722 | |
| 1723 | etm2: etm@7240000 { |
| 1724 | compatible = "arm,primecell"; |
| 1725 | arm,primecell-periphid = <0x000bb95d>; |
| 1726 | |
| 1727 | reg = <0x7240000 0x1000>; |
| 1728 | cpu = <&CPU2>; |
| 1729 | |
| 1730 | coresight-name = "coresight-etm2"; |
| 1731 | |
| 1732 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1733 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1734 | clock-names = "apb_pclk", "core_a_clk"; |
| 1735 | |
| 1736 | port { |
| 1737 | etm2_out_funnel_apss: endpoint { |
| 1738 | remote-endpoint = <&funnel_apss_in_etm2>; |
| 1739 | }; |
| 1740 | }; |
| 1741 | }; |
| 1742 | |
| 1743 | etm3: etm@7340000 { |
| 1744 | compatible = "arm,primecell"; |
| 1745 | arm,primecell-periphid = <0x000bb95d>; |
| 1746 | |
| 1747 | reg = <0x7340000 0x1000>; |
| 1748 | cpu = <&CPU3>; |
| 1749 | |
| 1750 | coresight-name = "coresight-etm3"; |
| 1751 | |
| 1752 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1753 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1754 | clock-names = "apb_pclk", "core_a_clk"; |
| 1755 | |
| 1756 | port { |
| 1757 | etm3_out_funnel_apss: endpoint { |
| 1758 | remote-endpoint = <&funnel_apss_in_etm3>; |
| 1759 | }; |
| 1760 | }; |
| 1761 | }; |
| 1762 | |
| 1763 | etm4: etm@7440000 { |
| 1764 | compatible = "arm,primecell"; |
| 1765 | arm,primecell-periphid = <0x000bb95d>; |
| 1766 | |
| 1767 | reg = <0x7440000 0x1000>; |
| 1768 | cpu = <&CPU4>; |
| 1769 | |
| 1770 | coresight-name = "coresight-etm4"; |
| 1771 | |
| 1772 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1773 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1774 | clock-names = "apb_pclk", "core_a_clk"; |
| 1775 | |
| 1776 | port { |
| 1777 | etm4_out_funnel_apss: endpoint { |
| 1778 | remote-endpoint = <&funnel_apss_in_etm4>; |
| 1779 | }; |
| 1780 | }; |
| 1781 | }; |
| 1782 | |
| 1783 | etm5: etm@7540000 { |
| 1784 | compatible = "arm,primecell"; |
| 1785 | arm,primecell-periphid = <0x000bb95d>; |
| 1786 | |
| 1787 | reg = <0x7540000 0x1000>; |
| 1788 | cpu = <&CPU5>; |
| 1789 | |
| 1790 | coresight-name = "coresight-etm5"; |
| 1791 | |
| 1792 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1793 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1794 | clock-names = "apb_pclk", "core_a_clk"; |
| 1795 | |
| 1796 | port { |
| 1797 | etm5_out_funnel_apss: endpoint { |
| 1798 | remote-endpoint = <&funnel_apss_in_etm5>; |
| 1799 | }; |
| 1800 | }; |
| 1801 | }; |
| 1802 | |
| 1803 | etm6: etm@7640000 { |
| 1804 | compatible = "arm,primecell"; |
| 1805 | arm,primecell-periphid = <0x000bb95d>; |
| 1806 | |
| 1807 | reg = <0x7640000 0x1000>; |
| 1808 | cpu = <&CPU6>; |
| 1809 | |
| 1810 | coresight-name = "coresight-etm6"; |
| 1811 | |
| 1812 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1813 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1814 | clock-names = "apb_pclk", "core_a_clk"; |
| 1815 | |
| 1816 | port { |
| 1817 | etm6_out_funnel_apss: endpoint { |
| 1818 | remote-endpoint = <&funnel_apss_in_etm6>; |
| 1819 | }; |
| 1820 | }; |
| 1821 | }; |
| 1822 | |
| 1823 | etm7: etm@7740000 { |
| 1824 | compatible = "arm,primecell"; |
| 1825 | arm,primecell-periphid = <0x000bb95d>; |
| 1826 | |
| 1827 | reg = <0x7740000 0x1000>; |
| 1828 | cpu = <&CPU7>; |
| 1829 | |
| 1830 | coresight-name = "coresight-etm7"; |
| 1831 | |
| 1832 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1833 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1834 | clock-names = "apb_pclk", "core_a_clk"; |
| 1835 | |
| 1836 | port { |
| 1837 | etm7_out_funnel_apss: endpoint { |
| 1838 | remote-endpoint = <&funnel_apss_in_etm7>; |
| 1839 | }; |
| 1840 | }; |
| 1841 | }; |
| 1842 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1843 | funnel_apss: funnel@7800000 { |
| 1844 | compatible = "arm,primecell"; |
| 1845 | arm,primecell-periphid = <0x0003b908>; |
| 1846 | |
| 1847 | reg = <0x7800000 0x1000>; |
| 1848 | reg-names = "funnel-base"; |
| 1849 | |
| 1850 | coresight-name = "coresight-funnel-apss"; |
| 1851 | |
| 1852 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1853 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1854 | clock-names = "apb_pclk", "core_a_clk"; |
| 1855 | |
| 1856 | ports { |
| 1857 | #address-cells = <1>; |
| 1858 | #size-cells = <0>; |
| 1859 | |
| 1860 | port@0 { |
| 1861 | reg = <0>; |
| 1862 | funnel_apss_out_funnel_apss_merg: endpoint { |
| 1863 | remote-endpoint = |
| 1864 | <&funnel_apss_merg_in_funnel_apss>; |
| 1865 | }; |
| 1866 | }; |
Satyajit Desai | da8d7bf | 2017-04-10 11:34:58 -0700 | [diff] [blame] | 1867 | port@1 { |
| 1868 | reg = <0>; |
| 1869 | funnel_apss_in_etm0: endpoint { |
| 1870 | slave-mode; |
| 1871 | remote-endpoint = |
| 1872 | <&etm0_out_funnel_apss>; |
| 1873 | }; |
| 1874 | }; |
| 1875 | |
| 1876 | port@2 { |
| 1877 | reg = <1>; |
| 1878 | funnel_apss_in_etm1: endpoint { |
| 1879 | slave-mode; |
| 1880 | remote-endpoint = |
| 1881 | <&etm1_out_funnel_apss>; |
| 1882 | }; |
| 1883 | }; |
| 1884 | |
| 1885 | port@3 { |
| 1886 | reg = <2>; |
| 1887 | funnel_apss_in_etm2: endpoint { |
| 1888 | slave-mode; |
| 1889 | remote-endpoint = |
| 1890 | <&etm2_out_funnel_apss>; |
| 1891 | }; |
| 1892 | }; |
| 1893 | |
| 1894 | port@4 { |
| 1895 | reg = <3>; |
| 1896 | funnel_apss_in_etm3: endpoint { |
| 1897 | slave-mode; |
| 1898 | remote-endpoint = |
| 1899 | <&etm3_out_funnel_apss>; |
| 1900 | }; |
| 1901 | }; |
| 1902 | |
| 1903 | port@5 { |
| 1904 | reg = <4>; |
| 1905 | funnel_apss_in_etm4: endpoint { |
| 1906 | slave-mode; |
| 1907 | remote-endpoint = |
| 1908 | <&etm4_out_funnel_apss>; |
| 1909 | }; |
| 1910 | }; |
| 1911 | |
| 1912 | port@6 { |
| 1913 | reg = <5>; |
| 1914 | funnel_apss_in_etm5: endpoint { |
| 1915 | slave-mode; |
| 1916 | remote-endpoint = |
| 1917 | <&etm5_out_funnel_apss>; |
| 1918 | }; |
| 1919 | }; |
| 1920 | |
| 1921 | port@7 { |
| 1922 | reg = <6>; |
| 1923 | funnel_apss_in_etm6: endpoint { |
| 1924 | slave-mode; |
| 1925 | remote-endpoint = |
| 1926 | <&etm6_out_funnel_apss>; |
| 1927 | }; |
| 1928 | }; |
| 1929 | |
| 1930 | port@8 { |
| 1931 | reg = <7>; |
| 1932 | funnel_apss_in_etm7: endpoint { |
| 1933 | slave-mode; |
| 1934 | remote-endpoint = |
| 1935 | <&etm7_out_funnel_apss>; |
| 1936 | }; |
| 1937 | }; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame] | 1938 | }; |
| 1939 | }; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 1940 | }; |