blob: b371066dd5bc914d24a79fe604d1eec9bfdd0e1e [file] [log] [blame]
Mark Browna2342ae2009-07-29 21:21:49 +01001/*
2 * wm_hubs.c -- WM8993/4 common code
3 *
Mark Brown656baae2012-05-23 12:39:07 +01004 * Copyright 2009-12 Wolfson Microelectronics plc
Mark Browna2342ae2009-07-29 21:21:49 +01005 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
Mark Brown79ef0ab2011-08-01 13:02:17 +090020#include <linux/mfd/wm8994/registers.h>
Mark Browna2342ae2009-07-29 21:21:49 +010021#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
Mark Browna2342ae2009-07-29 21:21:49 +010025#include <sound/initval.h>
26#include <sound/tlv.h>
27
28#include "wm8993.h"
29#include "wm_hubs.h"
30
31const DECLARE_TLV_DB_SCALE(wm_hubs_spkmix_tlv, -300, 300, 0);
32EXPORT_SYMBOL_GPL(wm_hubs_spkmix_tlv);
33
34static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1650, 150, 0);
35static const DECLARE_TLV_DB_SCALE(inmix_sw_tlv, 0, 3000, 0);
36static const DECLARE_TLV_DB_SCALE(inmix_tlv, -1500, 300, 1);
37static const DECLARE_TLV_DB_SCALE(earpiece_tlv, -600, 600, 0);
38static const DECLARE_TLV_DB_SCALE(outmix_tlv, -2100, 300, 0);
39static const DECLARE_TLV_DB_SCALE(spkmixout_tlv, -1800, 600, 1);
40static const DECLARE_TLV_DB_SCALE(outpga_tlv, -5700, 100, 0);
41static const unsigned int spkboost_tlv[] = {
Clemens Ladisch028aa632011-11-20 15:15:31 +010042 TLV_DB_RANGE_HEAD(2),
Mark Browna2342ae2009-07-29 21:21:49 +010043 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
44 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
45};
46static const DECLARE_TLV_DB_SCALE(line_tlv, -600, 600, 0);
47
48static const char *speaker_ref_text[] = {
49 "SPKVDD/2",
50 "VMID",
51};
52
53static const struct soc_enum speaker_ref =
54 SOC_ENUM_SINGLE(WM8993_SPEAKER_MIXER, 8, 2, speaker_ref_text);
55
56static const char *speaker_mode_text[] = {
57 "Class D",
58 "Class AB",
59};
60
61static const struct soc_enum speaker_mode =
62 SOC_ENUM_SINGLE(WM8993_SPKMIXR_ATTENUATION, 8, 2, speaker_mode_text);
63
Mark Brown4dcc93d2010-03-29 17:18:41 +010064static void wait_for_dc_servo(struct snd_soc_codec *codec, unsigned int op)
Mark Browna2342ae2009-07-29 21:21:49 +010065{
Mark Brownd96ca3c2011-07-12 15:25:03 +090066 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
Mark Browna2342ae2009-07-29 21:21:49 +010067 unsigned int reg;
68 int count = 0;
Mark Brown1479c3f2011-07-15 17:33:26 +090069 int timeout;
Mark Brown4dcc93d2010-03-29 17:18:41 +010070 unsigned int val;
71
72 val = op | WM8993_DCS_ENA_CHAN_0 | WM8993_DCS_ENA_CHAN_1;
73
74 /* Trigger the command */
75 snd_soc_write(codec, WM8993_DC_SERVO_0, val);
Mark Browna2342ae2009-07-29 21:21:49 +010076
77 dev_dbg(codec->dev, "Waiting for DC servo...\n");
Mark Brown3ed70742010-01-20 17:39:45 +000078
Mark Brown1479c3f2011-07-15 17:33:26 +090079 if (hubs->dcs_done_irq)
80 timeout = 4;
81 else
82 timeout = 400;
83
84 do {
85 count++;
86
87 if (hubs->dcs_done_irq)
88 wait_for_completion_timeout(&hubs->dcs_done,
89 msecs_to_jiffies(250));
90 else
91 msleep(1);
Mark Brownd96ca3c2011-07-12 15:25:03 +090092
Mark Brown4dcc93d2010-03-29 17:18:41 +010093 reg = snd_soc_read(codec, WM8993_DC_SERVO_0);
Mark Brown1479c3f2011-07-15 17:33:26 +090094 dev_dbg(codec->dev, "DC servo: %x\n", reg);
95 } while (reg & op && count < timeout);
Mark Browna2342ae2009-07-29 21:21:49 +010096
Mark Brown4dcc93d2010-03-29 17:18:41 +010097 if (reg & op)
Mark Brown5a9f91c2011-02-17 12:05:46 -080098 dev_err(codec->dev, "Timed out waiting for DC Servo %x\n",
99 op);
Mark Browna2342ae2009-07-29 21:21:49 +0100100}
101
Mark Brownd96ca3c2011-07-12 15:25:03 +0900102irqreturn_t wm_hubs_dcs_done(int irq, void *data)
103{
104 struct wm_hubs_data *hubs = data;
105
106 complete(&hubs->dcs_done);
107
108 return IRQ_HANDLED;
109}
110EXPORT_SYMBOL_GPL(wm_hubs_dcs_done);
111
Mark Brownaf31a222012-04-26 20:06:56 +0100112static bool wm_hubs_dac_hp_direct(struct snd_soc_codec *codec)
113{
114 int reg;
115
116 /* If we're going via the mixer we'll need to do additional checks */
117 reg = snd_soc_read(codec, WM8993_OUTPUT_MIXER1);
118 if (!(reg & WM8993_DACL_TO_HPOUT1L)) {
119 if (reg & ~WM8993_DACL_TO_MIXOUTL) {
120 dev_vdbg(codec->dev, "Analogue paths connected: %x\n",
121 reg & ~WM8993_DACL_TO_HPOUT1L);
122 return false;
123 } else {
124 dev_vdbg(codec->dev, "HPL connected to mixer\n");
Mark Brownaf31a222012-04-26 20:06:56 +0100125 }
126 } else {
127 dev_vdbg(codec->dev, "HPL connected to DAC\n");
128 }
129
130 reg = snd_soc_read(codec, WM8993_OUTPUT_MIXER2);
131 if (!(reg & WM8993_DACR_TO_HPOUT1R)) {
132 if (reg & ~WM8993_DACR_TO_MIXOUTR) {
133 dev_vdbg(codec->dev, "Analogue paths connected: %x\n",
134 reg & ~WM8993_DACR_TO_HPOUT1R);
135 return false;
136 } else {
137 dev_vdbg(codec->dev, "HPR connected to mixer\n");
Mark Brownaf31a222012-04-26 20:06:56 +0100138 }
139 } else {
140 dev_vdbg(codec->dev, "HPR connected to DAC\n");
141 }
142
143 return true;
144}
145
Mark Brown94aa7332012-05-01 18:45:09 +0100146struct wm_hubs_dcs_cache {
147 struct list_head list;
148 unsigned int left;
149 unsigned int right;
150 u16 dcs_cfg;
151};
152
153static bool wm_hubs_dcs_cache_get(struct snd_soc_codec *codec,
154 struct wm_hubs_dcs_cache **entry)
155{
156 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
157 struct wm_hubs_dcs_cache *cache;
158 unsigned int left, right;
159
160 left = snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME);
161 left &= WM8993_HPOUT1L_VOL_MASK;
162
163 right = snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME);
164 right &= WM8993_HPOUT1R_VOL_MASK;
165
166 list_for_each_entry(cache, &hubs->dcs_cache, list) {
167 if (cache->left != left || cache->right != right)
168 continue;
169
170 *entry = cache;
171 return true;
172 }
173
174 return false;
175}
176
177static void wm_hubs_dcs_cache_set(struct snd_soc_codec *codec, u16 dcs_cfg)
178{
179 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
180 struct wm_hubs_dcs_cache *cache;
181
182 if (hubs->no_cache_dac_hp_direct)
183 return;
184
185 cache = devm_kzalloc(codec->dev, sizeof(*cache), GFP_KERNEL);
186 if (!cache) {
187 dev_err(codec->dev, "Failed to allocate DCS cache entry\n");
188 return;
189 }
190
191 cache->left = snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME);
192 cache->left &= WM8993_HPOUT1L_VOL_MASK;
193
194 cache->right = snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME);
195 cache->right &= WM8993_HPOUT1R_VOL_MASK;
196
197 cache->dcs_cfg = dcs_cfg;
198
199 list_add_tail(&cache->list, &hubs->dcs_cache);
200}
201
Tim Gardner1f5353e2013-03-10 10:58:21 -0600202static int wm_hubs_read_dc_servo(struct snd_soc_codec *codec,
Mark Brownfae4efa2012-07-23 19:49:06 +0100203 u16 *reg_l, u16 *reg_r)
204{
205 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
206 u16 dcs_reg, reg;
Tim Gardner1f5353e2013-03-10 10:58:21 -0600207 int ret = 0;
Mark Brownfae4efa2012-07-23 19:49:06 +0100208
209 switch (hubs->dcs_readback_mode) {
210 case 2:
211 dcs_reg = WM8994_DC_SERVO_4E;
212 break;
213 case 1:
214 dcs_reg = WM8994_DC_SERVO_READBACK;
215 break;
216 default:
217 dcs_reg = WM8993_DC_SERVO_3;
218 break;
219 }
220
221 /* Different chips in the family support different readback
222 * methods.
223 */
224 switch (hubs->dcs_readback_mode) {
225 case 0:
226 *reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1)
227 & WM8993_DCS_INTEG_CHAN_0_MASK;
228 *reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2)
229 & WM8993_DCS_INTEG_CHAN_1_MASK;
230 break;
231 case 2:
232 case 1:
233 reg = snd_soc_read(codec, dcs_reg);
234 *reg_r = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK)
235 >> WM8993_DCS_DAC_WR_VAL_1_SHIFT;
236 *reg_l = reg & WM8993_DCS_DAC_WR_VAL_0_MASK;
237 break;
238 default:
239 WARN(1, "Unknown DCS readback method\n");
Tim Gardner1f5353e2013-03-10 10:58:21 -0600240 ret = -1;
Mark Brownfae4efa2012-07-23 19:49:06 +0100241 }
Tim Gardner1f5353e2013-03-10 10:58:21 -0600242 return ret;
Mark Brownfae4efa2012-07-23 19:49:06 +0100243}
244
Mark Browna2342ae2009-07-29 21:21:49 +0100245/*
Mark Brown3ed70742010-01-20 17:39:45 +0000246 * Startup calibration of the DC servo
247 */
Mark Browna7892c32012-07-23 19:50:45 +0100248static void enable_dc_servo(struct snd_soc_codec *codec)
Mark Brown3ed70742010-01-20 17:39:45 +0000249{
Mark Brownb2c812e2010-04-14 15:35:19 +0900250 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
Mark Brown94aa7332012-05-01 18:45:09 +0100251 struct wm_hubs_dcs_cache *cache;
Mark Brown20a4e7f2011-01-21 12:47:33 +0000252 s8 offset;
Mark Brownfae4efa2012-07-23 19:49:06 +0100253 u16 reg_l, reg_r, dcs_cfg, dcs_reg;
Mark Brown79ef0ab2011-08-01 13:02:17 +0900254
255 switch (hubs->dcs_readback_mode) {
256 case 2:
257 dcs_reg = WM8994_DC_SERVO_4E;
258 break;
259 default:
260 dcs_reg = WM8993_DC_SERVO_3;
261 break;
262 }
Mark Brown3ed70742010-01-20 17:39:45 +0000263
Mark Brownfec6dd82010-10-27 13:48:36 -0700264 /* If we're using a digital only path and have a previously
265 * callibrated DC servo offset stored then use that. */
Mark Brown94aa7332012-05-01 18:45:09 +0100266 if (wm_hubs_dac_hp_direct(codec) &&
267 wm_hubs_dcs_cache_get(codec, &cache)) {
268 dev_dbg(codec->dev, "Using cached DCS offset %x for %d,%d\n",
269 cache->dcs_cfg, cache->left, cache->right);
270 snd_soc_write(codec, dcs_reg, cache->dcs_cfg);
Mark Brownfec6dd82010-10-27 13:48:36 -0700271 wait_for_dc_servo(codec,
272 WM8993_DCS_TRIG_DAC_WR_0 |
273 WM8993_DCS_TRIG_DAC_WR_1);
274 return;
275 }
276
Mark Brownf9acf9f2011-06-07 23:23:52 +0100277 if (hubs->series_startup) {
Mark Brown11cef5f2010-11-26 17:23:44 +0000278 /* Set for 32 series updates */
279 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
280 WM8993_DCS_SERIES_NO_01_MASK,
281 32 << WM8993_DCS_SERIES_NO_01_SHIFT);
282 wait_for_dc_servo(codec,
283 WM8993_DCS_TRIG_SERIES_0 |
284 WM8993_DCS_TRIG_SERIES_1);
285 } else {
286 wait_for_dc_servo(codec,
287 WM8993_DCS_TRIG_STARTUP_0 |
288 WM8993_DCS_TRIG_STARTUP_1);
289 }
Mark Brown3ed70742010-01-20 17:39:45 +0000290
Tim Gardner1f5353e2013-03-10 10:58:21 -0600291 if (wm_hubs_read_dc_servo(codec, &reg_l, &reg_r) < 0)
292 return;
Mark Brownfec6dd82010-10-27 13:48:36 -0700293
294 dev_dbg(codec->dev, "DCS input: %x %x\n", reg_l, reg_r);
295
Mark Brown3ed70742010-01-20 17:39:45 +0000296 /* Apply correction to DC servo result */
Mark Brown4537c4e2011-08-01 13:10:16 +0900297 if (hubs->dcs_codes_l || hubs->dcs_codes_r) {
298 dev_dbg(codec->dev,
299 "Applying %d/%d code DC servo correction\n",
300 hubs->dcs_codes_l, hubs->dcs_codes_r);
Mark Brown3ed70742010-01-20 17:39:45 +0000301
Mark Brownd5b040c2011-06-07 23:28:45 +0100302 /* HPOUT1R */
Mark Brown363947d2012-08-20 19:54:24 +0100303 offset = (s8)reg_r;
Mark Brown20bac1f2012-08-20 20:01:51 +0100304 dev_dbg(codec->dev, "DCS right %d->%d\n", offset,
305 offset + hubs->dcs_codes_r);
Mark Brown4537c4e2011-08-01 13:10:16 +0900306 offset += hubs->dcs_codes_r;
Mark Brown20a4e7f2011-01-21 12:47:33 +0000307 dcs_cfg = (u8)offset << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
Mark Brown3ed70742010-01-20 17:39:45 +0000308
Mark Brownd5b040c2011-06-07 23:28:45 +0100309 /* HPOUT1L */
Mark Brown363947d2012-08-20 19:54:24 +0100310 offset = (s8)reg_l;
Mark Brown20bac1f2012-08-20 20:01:51 +0100311 dev_dbg(codec->dev, "DCS left %d->%d\n", offset,
312 offset + hubs->dcs_codes_l);
Mark Brown4537c4e2011-08-01 13:10:16 +0900313 offset += hubs->dcs_codes_l;
Mark Brown20a4e7f2011-01-21 12:47:33 +0000314 dcs_cfg |= (u8)offset;
Mark Brown3ed70742010-01-20 17:39:45 +0000315
Mark Brown3254d282010-05-10 14:56:03 +0100316 dev_dbg(codec->dev, "DCS result: %x\n", dcs_cfg);
317
Mark Brown3ed70742010-01-20 17:39:45 +0000318 /* Do it */
Mark Brown79ef0ab2011-08-01 13:02:17 +0900319 snd_soc_write(codec, dcs_reg, dcs_cfg);
Mark Brown4dcc93d2010-03-29 17:18:41 +0100320 wait_for_dc_servo(codec,
321 WM8993_DCS_TRIG_DAC_WR_0 |
322 WM8993_DCS_TRIG_DAC_WR_1);
Mark Brownfec6dd82010-10-27 13:48:36 -0700323 } else {
Mark Brownd5b040c2011-06-07 23:28:45 +0100324 dcs_cfg = reg_r << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
325 dcs_cfg |= reg_l;
Mark Brown3ed70742010-01-20 17:39:45 +0000326 }
Mark Brownfec6dd82010-10-27 13:48:36 -0700327
328 /* Save the callibrated offset if we're in class W mode and
329 * therefore don't have any analogue signal mixed in. */
Mark Brown94aa7332012-05-01 18:45:09 +0100330 if (wm_hubs_dac_hp_direct(codec))
331 wm_hubs_dcs_cache_set(codec, dcs_cfg);
Mark Brown3ed70742010-01-20 17:39:45 +0000332}
333
334/*
Mark Browna2342ae2009-07-29 21:21:49 +0100335 * Update the DC servo calibration on gain changes
336 */
337static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
Mark Brown3ed70742010-01-20 17:39:45 +0000338 struct snd_ctl_elem_value *ucontrol)
Mark Browna2342ae2009-07-29 21:21:49 +0100339{
340 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Mark Brownb2c812e2010-04-14 15:35:19 +0900341 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
Mark Browna2342ae2009-07-29 21:21:49 +0100342 int ret;
343
Peter Ujfalusic4671a92011-10-06 09:59:12 +0300344 ret = snd_soc_put_volsw(kcontrol, ucontrol);
Mark Browna2342ae2009-07-29 21:21:49 +0100345
Mark Brownae9d8602010-03-29 16:34:42 +0100346 /* If we're applying an offset correction then updating the
347 * callibration would be likely to introduce further offsets. */
Mark Brown4537c4e2011-08-01 13:10:16 +0900348 if (hubs->dcs_codes_l || hubs->dcs_codes_r || hubs->no_series_update)
Mark Brownae9d8602010-03-29 16:34:42 +0100349 return ret;
350
Mark Browna2342ae2009-07-29 21:21:49 +0100351 /* Only need to do this if the outputs are active */
352 if (snd_soc_read(codec, WM8993_POWER_MANAGEMENT_1)
353 & (WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA))
354 snd_soc_update_bits(codec,
355 WM8993_DC_SERVO_0,
356 WM8993_DCS_TRIG_SINGLE_0 |
357 WM8993_DCS_TRIG_SINGLE_1,
358 WM8993_DCS_TRIG_SINGLE_0 |
359 WM8993_DCS_TRIG_SINGLE_1);
360
361 return ret;
362}
363
364static const struct snd_kcontrol_new analogue_snd_controls[] = {
365SOC_SINGLE_TLV("IN1L Volume", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
366 inpga_tlv),
367SOC_SINGLE("IN1L Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
Mark Brownea02c632011-05-27 21:56:16 +0800368SOC_SINGLE("IN1L ZC Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100369
370SOC_SINGLE_TLV("IN1R Volume", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
371 inpga_tlv),
372SOC_SINGLE("IN1R Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
Mark Brownea02c632011-05-27 21:56:16 +0800373SOC_SINGLE("IN1R ZC Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100374
375
376SOC_SINGLE_TLV("IN2L Volume", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
377 inpga_tlv),
378SOC_SINGLE("IN2L Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
Mark Brownea02c632011-05-27 21:56:16 +0800379SOC_SINGLE("IN2L ZC Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100380
381SOC_SINGLE_TLV("IN2R Volume", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
382 inpga_tlv),
383SOC_SINGLE("IN2R Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
Mark Brownea02c632011-05-27 21:56:16 +0800384SOC_SINGLE("IN2R ZC Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100385
386SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8993_INPUT_MIXER3, 7, 1, 0,
387 inmix_sw_tlv),
388SOC_SINGLE_TLV("MIXINL IN1L Volume", WM8993_INPUT_MIXER3, 4, 1, 0,
389 inmix_sw_tlv),
390SOC_SINGLE_TLV("MIXINL Output Record Volume", WM8993_INPUT_MIXER3, 0, 7, 0,
391 inmix_tlv),
392SOC_SINGLE_TLV("MIXINL IN1LP Volume", WM8993_INPUT_MIXER5, 6, 7, 0, inmix_tlv),
393SOC_SINGLE_TLV("MIXINL Direct Voice Volume", WM8993_INPUT_MIXER5, 0, 6, 0,
394 inmix_tlv),
395
396SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8993_INPUT_MIXER4, 7, 1, 0,
397 inmix_sw_tlv),
398SOC_SINGLE_TLV("MIXINR IN1R Volume", WM8993_INPUT_MIXER4, 4, 1, 0,
399 inmix_sw_tlv),
400SOC_SINGLE_TLV("MIXINR Output Record Volume", WM8993_INPUT_MIXER4, 0, 7, 0,
401 inmix_tlv),
402SOC_SINGLE_TLV("MIXINR IN1RP Volume", WM8993_INPUT_MIXER6, 6, 7, 0, inmix_tlv),
403SOC_SINGLE_TLV("MIXINR Direct Voice Volume", WM8993_INPUT_MIXER6, 0, 6, 0,
404 inmix_tlv),
405
406SOC_SINGLE_TLV("Left Output Mixer IN2RN Volume", WM8993_OUTPUT_MIXER5, 6, 7, 1,
407 outmix_tlv),
408SOC_SINGLE_TLV("Left Output Mixer IN2LN Volume", WM8993_OUTPUT_MIXER3, 6, 7, 1,
409 outmix_tlv),
410SOC_SINGLE_TLV("Left Output Mixer IN2LP Volume", WM8993_OUTPUT_MIXER3, 9, 7, 1,
411 outmix_tlv),
412SOC_SINGLE_TLV("Left Output Mixer IN1L Volume", WM8993_OUTPUT_MIXER3, 0, 7, 1,
413 outmix_tlv),
414SOC_SINGLE_TLV("Left Output Mixer IN1R Volume", WM8993_OUTPUT_MIXER3, 3, 7, 1,
415 outmix_tlv),
416SOC_SINGLE_TLV("Left Output Mixer Right Input Volume",
417 WM8993_OUTPUT_MIXER5, 3, 7, 1, outmix_tlv),
418SOC_SINGLE_TLV("Left Output Mixer Left Input Volume",
419 WM8993_OUTPUT_MIXER5, 0, 7, 1, outmix_tlv),
420SOC_SINGLE_TLV("Left Output Mixer DAC Volume", WM8993_OUTPUT_MIXER5, 9, 7, 1,
421 outmix_tlv),
422
423SOC_SINGLE_TLV("Right Output Mixer IN2LN Volume",
424 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
425SOC_SINGLE_TLV("Right Output Mixer IN2RN Volume",
426 WM8993_OUTPUT_MIXER4, 6, 7, 1, outmix_tlv),
427SOC_SINGLE_TLV("Right Output Mixer IN1L Volume",
428 WM8993_OUTPUT_MIXER4, 3, 7, 1, outmix_tlv),
429SOC_SINGLE_TLV("Right Output Mixer IN1R Volume",
430 WM8993_OUTPUT_MIXER4, 0, 7, 1, outmix_tlv),
431SOC_SINGLE_TLV("Right Output Mixer IN2RP Volume",
432 WM8993_OUTPUT_MIXER4, 9, 7, 1, outmix_tlv),
433SOC_SINGLE_TLV("Right Output Mixer Left Input Volume",
434 WM8993_OUTPUT_MIXER6, 3, 7, 1, outmix_tlv),
435SOC_SINGLE_TLV("Right Output Mixer Right Input Volume",
436 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
437SOC_SINGLE_TLV("Right Output Mixer DAC Volume",
438 WM8993_OUTPUT_MIXER6, 9, 7, 1, outmix_tlv),
439
440SOC_DOUBLE_R_TLV("Output Volume", WM8993_LEFT_OPGA_VOLUME,
441 WM8993_RIGHT_OPGA_VOLUME, 0, 63, 0, outpga_tlv),
442SOC_DOUBLE_R("Output Switch", WM8993_LEFT_OPGA_VOLUME,
443 WM8993_RIGHT_OPGA_VOLUME, 6, 1, 0),
444SOC_DOUBLE_R("Output ZC Switch", WM8993_LEFT_OPGA_VOLUME,
445 WM8993_RIGHT_OPGA_VOLUME, 7, 1, 0),
446
447SOC_SINGLE("Earpiece Switch", WM8993_HPOUT2_VOLUME, 5, 1, 1),
448SOC_SINGLE_TLV("Earpiece Volume", WM8993_HPOUT2_VOLUME, 4, 1, 1, earpiece_tlv),
449
450SOC_SINGLE_TLV("SPKL Input Volume", WM8993_SPKMIXL_ATTENUATION,
451 5, 1, 1, wm_hubs_spkmix_tlv),
452SOC_SINGLE_TLV("SPKL IN1LP Volume", WM8993_SPKMIXL_ATTENUATION,
453 4, 1, 1, wm_hubs_spkmix_tlv),
454SOC_SINGLE_TLV("SPKL Output Volume", WM8993_SPKMIXL_ATTENUATION,
455 3, 1, 1, wm_hubs_spkmix_tlv),
456
457SOC_SINGLE_TLV("SPKR Input Volume", WM8993_SPKMIXR_ATTENUATION,
458 5, 1, 1, wm_hubs_spkmix_tlv),
459SOC_SINGLE_TLV("SPKR IN1RP Volume", WM8993_SPKMIXR_ATTENUATION,
460 4, 1, 1, wm_hubs_spkmix_tlv),
461SOC_SINGLE_TLV("SPKR Output Volume", WM8993_SPKMIXR_ATTENUATION,
462 3, 1, 1, wm_hubs_spkmix_tlv),
463
464SOC_DOUBLE_R_TLV("Speaker Mixer Volume",
465 WM8993_SPKMIXL_ATTENUATION, WM8993_SPKMIXR_ATTENUATION,
466 0, 3, 1, spkmixout_tlv),
467SOC_DOUBLE_R_TLV("Speaker Volume",
468 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
469 0, 63, 0, outpga_tlv),
470SOC_DOUBLE_R("Speaker Switch",
471 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
472 6, 1, 0),
473SOC_DOUBLE_R("Speaker ZC Switch",
474 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
475 7, 1, 0),
Uk Kimed8cc472010-12-05 17:26:07 +0900476SOC_DOUBLE_TLV("Speaker Boost Volume", WM8993_SPKOUT_BOOST, 3, 0, 7, 0,
Mark Browna2342ae2009-07-29 21:21:49 +0100477 spkboost_tlv),
478SOC_ENUM("Speaker Reference", speaker_ref),
479SOC_ENUM("Speaker Mode", speaker_mode),
480
Peter Ujfalusi0f9887d2011-10-05 10:29:19 +0300481SOC_DOUBLE_R_EXT_TLV("Headphone Volume",
482 WM8993_LEFT_OUTPUT_VOLUME, WM8993_RIGHT_OUTPUT_VOLUME,
Peter Ujfalusic4671a92011-10-06 09:59:12 +0300483 0, 63, 0, snd_soc_get_volsw, wm8993_put_dc_servo,
Peter Ujfalusi0f9887d2011-10-05 10:29:19 +0300484 outpga_tlv),
485
Mark Browna2342ae2009-07-29 21:21:49 +0100486SOC_DOUBLE_R("Headphone Switch", WM8993_LEFT_OUTPUT_VOLUME,
487 WM8993_RIGHT_OUTPUT_VOLUME, 6, 1, 0),
488SOC_DOUBLE_R("Headphone ZC Switch", WM8993_LEFT_OUTPUT_VOLUME,
489 WM8993_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
490
491SOC_SINGLE("LINEOUT1N Switch", WM8993_LINE_OUTPUTS_VOLUME, 6, 1, 1),
492SOC_SINGLE("LINEOUT1P Switch", WM8993_LINE_OUTPUTS_VOLUME, 5, 1, 1),
493SOC_SINGLE_TLV("LINEOUT1 Volume", WM8993_LINE_OUTPUTS_VOLUME, 4, 1, 1,
494 line_tlv),
495
496SOC_SINGLE("LINEOUT2N Switch", WM8993_LINE_OUTPUTS_VOLUME, 2, 1, 1),
497SOC_SINGLE("LINEOUT2P Switch", WM8993_LINE_OUTPUTS_VOLUME, 1, 1, 1),
498SOC_SINGLE_TLV("LINEOUT2 Volume", WM8993_LINE_OUTPUTS_VOLUME, 0, 1, 1,
499 line_tlv),
500};
501
Mark Brown3ed70742010-01-20 17:39:45 +0000502static int hp_supply_event(struct snd_soc_dapm_widget *w,
503 struct snd_kcontrol *kcontrol, int event)
504{
505 struct snd_soc_codec *codec = w->codec;
Mark Brownb2c812e2010-04-14 15:35:19 +0900506 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
Mark Brown3ed70742010-01-20 17:39:45 +0000507
508 switch (event) {
509 case SND_SOC_DAPM_PRE_PMU:
510 switch (hubs->hp_startup_mode) {
511 case 0:
512 break;
513 case 1:
514 /* Enable the headphone amp */
515 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
516 WM8993_HPOUT1L_ENA |
517 WM8993_HPOUT1R_ENA,
518 WM8993_HPOUT1L_ENA |
519 WM8993_HPOUT1R_ENA);
520
521 /* Enable the second stage */
522 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
523 WM8993_HPOUT1L_DLY |
524 WM8993_HPOUT1R_DLY,
525 WM8993_HPOUT1L_DLY |
526 WM8993_HPOUT1R_DLY);
527 break;
528 default:
529 dev_err(codec->dev, "Unknown HP startup mode %d\n",
530 hubs->hp_startup_mode);
531 break;
532 }
Takashi Iwai268ff142013-10-30 08:35:02 +0100533 break;
Mark Brown3ed70742010-01-20 17:39:45 +0000534
535 case SND_SOC_DAPM_PRE_PMD:
536 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
537 WM8993_CP_ENA, 0);
538 break;
539 }
540
541 return 0;
542}
543
Mark Browna2342ae2009-07-29 21:21:49 +0100544static int hp_event(struct snd_soc_dapm_widget *w,
545 struct snd_kcontrol *kcontrol, int event)
546{
547 struct snd_soc_codec *codec = w->codec;
548 unsigned int reg = snd_soc_read(codec, WM8993_ANALOGUE_HP_0);
549
550 switch (event) {
551 case SND_SOC_DAPM_POST_PMU:
552 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
553 WM8993_CP_ENA, WM8993_CP_ENA);
554
555 msleep(5);
556
557 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
558 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
559 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA);
560
561 reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
562 snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
563
Mark Brown3ed70742010-01-20 17:39:45 +0000564 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
Mark Brownf9925d42011-07-28 12:44:44 +0100565 WM8993_DCS_TIMER_PERIOD_01_MASK, 0);
Mark Brown3ed70742010-01-20 17:39:45 +0000566
Mark Browna7892c32012-07-23 19:50:45 +0100567 enable_dc_servo(codec);
Mark Browna2342ae2009-07-29 21:21:49 +0100568
569 reg |= WM8993_HPOUT1R_OUTP | WM8993_HPOUT1R_RMV_SHORT |
570 WM8993_HPOUT1L_OUTP | WM8993_HPOUT1L_RMV_SHORT;
571 snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
572 break;
573
574 case SND_SOC_DAPM_PRE_PMD:
Mark Brown3ed70742010-01-20 17:39:45 +0000575 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
Mark Brown6adb26b2010-05-10 16:13:11 +0100576 WM8993_HPOUT1L_OUTP |
577 WM8993_HPOUT1R_OUTP |
Mark Brown3ed70742010-01-20 17:39:45 +0000578 WM8993_HPOUT1L_RMV_SHORT |
579 WM8993_HPOUT1R_RMV_SHORT, 0);
Mark Browna2342ae2009-07-29 21:21:49 +0100580
Mark Brown3ed70742010-01-20 17:39:45 +0000581 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
Mark Brown6adb26b2010-05-10 16:13:11 +0100582 WM8993_HPOUT1L_DLY |
583 WM8993_HPOUT1R_DLY, 0);
Mark Browna2342ae2009-07-29 21:21:49 +0100584
Mark Brown395e4b72010-05-10 21:06:14 +0100585 snd_soc_write(codec, WM8993_DC_SERVO_0, 0);
586
Mark Browna2342ae2009-07-29 21:21:49 +0100587 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
588 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
589 0);
Mark Browna2342ae2009-07-29 21:21:49 +0100590 break;
591 }
592
593 return 0;
594}
595
596static int earpiece_event(struct snd_soc_dapm_widget *w,
597 struct snd_kcontrol *control, int event)
598{
599 struct snd_soc_codec *codec = w->codec;
600 u16 reg = snd_soc_read(codec, WM8993_ANTIPOP1) & ~WM8993_HPOUT2_IN_ENA;
601
602 switch (event) {
603 case SND_SOC_DAPM_PRE_PMU:
604 reg |= WM8993_HPOUT2_IN_ENA;
605 snd_soc_write(codec, WM8993_ANTIPOP1, reg);
606 udelay(50);
607 break;
608
609 case SND_SOC_DAPM_POST_PMD:
610 snd_soc_write(codec, WM8993_ANTIPOP1, reg);
611 break;
612
613 default:
Takashi Iwai9a743402013-11-06 11:07:18 +0100614 WARN(1, "Invalid event %d\n", event);
Mark Browna2342ae2009-07-29 21:21:49 +0100615 break;
616 }
617
618 return 0;
619}
620
Mark Brown5f2f38902012-02-08 18:51:42 +0000621static int lineout_event(struct snd_soc_dapm_widget *w,
622 struct snd_kcontrol *control, int event)
623{
624 struct snd_soc_codec *codec = w->codec;
625 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
626 bool *flag;
627
628 switch (w->shift) {
629 case WM8993_LINEOUT1N_ENA_SHIFT:
630 flag = &hubs->lineout1n_ena;
631 break;
632 case WM8993_LINEOUT1P_ENA_SHIFT:
633 flag = &hubs->lineout1p_ena;
634 break;
635 case WM8993_LINEOUT2N_ENA_SHIFT:
636 flag = &hubs->lineout2n_ena;
637 break;
638 case WM8993_LINEOUT2P_ENA_SHIFT:
639 flag = &hubs->lineout2p_ena;
640 break;
641 default:
642 WARN(1, "Unknown line output");
643 return -EINVAL;
644 }
645
646 *flag = SND_SOC_DAPM_EVENT_ON(event);
647
648 return 0;
649}
650
Mark Brown02e79472012-08-21 17:54:52 +0100651static int micbias_event(struct snd_soc_dapm_widget *w,
652 struct snd_kcontrol *kcontrol, int event)
653{
654 struct snd_soc_codec *codec = w->codec;
655 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
656
657 switch (w->shift) {
658 case WM8993_MICB1_ENA_SHIFT:
659 if (hubs->micb1_delay)
660 msleep(hubs->micb1_delay);
661 break;
662 case WM8993_MICB2_ENA_SHIFT:
663 if (hubs->micb2_delay)
664 msleep(hubs->micb2_delay);
665 break;
666 default:
667 return -EINVAL;
668 }
669
670 return 0;
671}
672
Mark Brownc3403042012-04-26 21:29:29 +0100673void wm_hubs_update_class_w(struct snd_soc_codec *codec)
674{
675 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
676 int enable = WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ;
677
678 if (!wm_hubs_dac_hp_direct(codec))
679 enable = false;
680
681 if (hubs->check_class_w_digital && !hubs->check_class_w_digital(codec))
682 enable = false;
683
684 dev_vdbg(codec->dev, "Class W %s\n", enable ? "enabled" : "disabled");
685
686 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
687 WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ, enable);
Mark Browneb4d5fc2012-09-27 18:35:24 +0100688
689 snd_soc_write(codec, WM8993_LEFT_OUTPUT_VOLUME,
690 snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME));
691 snd_soc_write(codec, WM8993_RIGHT_OUTPUT_VOLUME,
692 snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME));
Mark Brownc3403042012-04-26 21:29:29 +0100693}
694EXPORT_SYMBOL_GPL(wm_hubs_update_class_w);
695
Mark Brown04de57c2012-04-26 22:08:50 +0100696#define WM_HUBS_SINGLE_W(xname, reg, shift, max, invert) \
Lars-Peter Clausen98809ae2013-06-19 19:34:01 +0200697 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
698 snd_soc_dapm_get_volsw, class_w_put_volsw)
Mark Brown04de57c2012-04-26 22:08:50 +0100699
700static int class_w_put_volsw(struct snd_kcontrol *kcontrol,
701 struct snd_ctl_elem_value *ucontrol)
702{
Lars-Peter Clauseneee5d7f2013-07-29 17:13:57 +0200703 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
Mark Brown04de57c2012-04-26 22:08:50 +0100704 int ret;
705
706 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
707
708 wm_hubs_update_class_w(codec);
709
710 return ret;
711}
712
Mark Brownc3403042012-04-26 21:29:29 +0100713#define WM_HUBS_ENUM_W(xname, xenum) \
714{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
715 .info = snd_soc_info_enum_double, \
716 .get = snd_soc_dapm_get_enum_double, \
Mark Brown04de57c2012-04-26 22:08:50 +0100717 .put = class_w_put_double, \
Mark Brownc3403042012-04-26 21:29:29 +0100718 .private_value = (unsigned long)&xenum }
719
Mark Brown04de57c2012-04-26 22:08:50 +0100720static int class_w_put_double(struct snd_kcontrol *kcontrol,
721 struct snd_ctl_elem_value *ucontrol)
Mark Brownc3403042012-04-26 21:29:29 +0100722{
Lars-Peter Clauseneee5d7f2013-07-29 17:13:57 +0200723 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
Mark Brownc3403042012-04-26 21:29:29 +0100724 int ret;
725
726 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
727
728 wm_hubs_update_class_w(codec);
729
730 return ret;
731}
732
733static const char *hp_mux_text[] = {
734 "Mixer",
735 "DAC",
736};
737
738static const struct soc_enum hpl_enum =
739 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
740
741const struct snd_kcontrol_new wm_hubs_hpl_mux =
742 WM_HUBS_ENUM_W("Left Headphone Mux", hpl_enum);
743EXPORT_SYMBOL_GPL(wm_hubs_hpl_mux);
744
745static const struct soc_enum hpr_enum =
746 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
747
748const struct snd_kcontrol_new wm_hubs_hpr_mux =
749 WM_HUBS_ENUM_W("Right Headphone Mux", hpr_enum);
750EXPORT_SYMBOL_GPL(wm_hubs_hpr_mux);
751
Mark Browna2342ae2009-07-29 21:21:49 +0100752static const struct snd_kcontrol_new in1l_pga[] = {
753SOC_DAPM_SINGLE("IN1LP Switch", WM8993_INPUT_MIXER2, 5, 1, 0),
754SOC_DAPM_SINGLE("IN1LN Switch", WM8993_INPUT_MIXER2, 4, 1, 0),
755};
756
757static const struct snd_kcontrol_new in1r_pga[] = {
758SOC_DAPM_SINGLE("IN1RP Switch", WM8993_INPUT_MIXER2, 1, 1, 0),
759SOC_DAPM_SINGLE("IN1RN Switch", WM8993_INPUT_MIXER2, 0, 1, 0),
760};
761
762static const struct snd_kcontrol_new in2l_pga[] = {
763SOC_DAPM_SINGLE("IN2LP Switch", WM8993_INPUT_MIXER2, 7, 1, 0),
764SOC_DAPM_SINGLE("IN2LN Switch", WM8993_INPUT_MIXER2, 6, 1, 0),
765};
766
767static const struct snd_kcontrol_new in2r_pga[] = {
768SOC_DAPM_SINGLE("IN2RP Switch", WM8993_INPUT_MIXER2, 3, 1, 0),
769SOC_DAPM_SINGLE("IN2RN Switch", WM8993_INPUT_MIXER2, 2, 1, 0),
770};
771
772static const struct snd_kcontrol_new mixinl[] = {
773SOC_DAPM_SINGLE("IN2L Switch", WM8993_INPUT_MIXER3, 8, 1, 0),
774SOC_DAPM_SINGLE("IN1L Switch", WM8993_INPUT_MIXER3, 5, 1, 0),
775};
776
777static const struct snd_kcontrol_new mixinr[] = {
778SOC_DAPM_SINGLE("IN2R Switch", WM8993_INPUT_MIXER4, 8, 1, 0),
779SOC_DAPM_SINGLE("IN1R Switch", WM8993_INPUT_MIXER4, 5, 1, 0),
780};
781
782static const struct snd_kcontrol_new left_output_mixer[] = {
Mark Brown04de57c2012-04-26 22:08:50 +0100783WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER1, 7, 1, 0),
784WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER1, 6, 1, 0),
785WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER1, 5, 1, 0),
786WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER1, 4, 1, 0),
787WM_HUBS_SINGLE_W("IN2LP Switch", WM8993_OUTPUT_MIXER1, 1, 1, 0),
788WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER1, 3, 1, 0),
789WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER1, 2, 1, 0),
790WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER1, 0, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100791};
792
793static const struct snd_kcontrol_new right_output_mixer[] = {
Mark Brown04de57c2012-04-26 22:08:50 +0100794WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER2, 7, 1, 0),
795WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER2, 6, 1, 0),
796WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER2, 5, 1, 0),
797WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER2, 4, 1, 0),
798WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER2, 3, 1, 0),
799WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER2, 2, 1, 0),
800WM_HUBS_SINGLE_W("IN2RP Switch", WM8993_OUTPUT_MIXER2, 1, 1, 0),
801WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER2, 0, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100802};
803
804static const struct snd_kcontrol_new earpiece_mixer[] = {
805SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_HPOUT2_MIXER, 5, 1, 0),
806SOC_DAPM_SINGLE("Left Output Switch", WM8993_HPOUT2_MIXER, 4, 1, 0),
807SOC_DAPM_SINGLE("Right Output Switch", WM8993_HPOUT2_MIXER, 3, 1, 0),
808};
809
810static const struct snd_kcontrol_new left_speaker_boost[] = {
811SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 5, 1, 0),
812SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 4, 1, 0),
813SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 3, 1, 0),
814};
815
816static const struct snd_kcontrol_new right_speaker_boost[] = {
817SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 2, 1, 0),
818SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 1, 1, 0),
819SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 0, 1, 0),
820};
821
822static const struct snd_kcontrol_new line1_mix[] = {
823SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER1, 2, 1, 0),
824SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER1, 1, 1, 0),
825SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
826};
827
828static const struct snd_kcontrol_new line1n_mix[] = {
829SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 6, 1, 0),
830SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER1, 5, 1, 0),
831};
832
833static const struct snd_kcontrol_new line1p_mix[] = {
834SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
835};
836
837static const struct snd_kcontrol_new line2_mix[] = {
Mark Brown43b6cec2012-02-01 23:46:58 +0000838SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER2, 2, 1, 0),
839SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER2, 1, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100840SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
841};
842
843static const struct snd_kcontrol_new line2n_mix[] = {
UK KIM114395c2012-01-28 01:52:22 +0900844SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER2, 5, 1, 0),
845SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 6, 1, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100846};
847
848static const struct snd_kcontrol_new line2p_mix[] = {
849SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
850};
851
852static const struct snd_soc_dapm_widget analogue_dapm_widgets[] = {
853SND_SOC_DAPM_INPUT("IN1LN"),
854SND_SOC_DAPM_INPUT("IN1LP"),
855SND_SOC_DAPM_INPUT("IN2LN"),
Joonyoung Shim34825942009-12-04 15:12:10 +0900856SND_SOC_DAPM_INPUT("IN2LP:VXRN"),
Mark Browna2342ae2009-07-29 21:21:49 +0100857SND_SOC_DAPM_INPUT("IN1RN"),
858SND_SOC_DAPM_INPUT("IN1RP"),
859SND_SOC_DAPM_INPUT("IN2RN"),
Joonyoung Shim34825942009-12-04 15:12:10 +0900860SND_SOC_DAPM_INPUT("IN2RP:VXRP"),
Mark Browna2342ae2009-07-29 21:21:49 +0100861
Mark Brown02e79472012-08-21 17:54:52 +0100862SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8993_POWER_MANAGEMENT_1, 5, 0,
863 micbias_event, SND_SOC_DAPM_POST_PMU),
864SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8993_POWER_MANAGEMENT_1, 4, 0,
865 micbias_event, SND_SOC_DAPM_POST_PMU),
Mark Browna2342ae2009-07-29 21:21:49 +0100866
867SND_SOC_DAPM_MIXER("IN1L PGA", WM8993_POWER_MANAGEMENT_2, 6, 0,
868 in1l_pga, ARRAY_SIZE(in1l_pga)),
869SND_SOC_DAPM_MIXER("IN1R PGA", WM8993_POWER_MANAGEMENT_2, 4, 0,
870 in1r_pga, ARRAY_SIZE(in1r_pga)),
871
872SND_SOC_DAPM_MIXER("IN2L PGA", WM8993_POWER_MANAGEMENT_2, 7, 0,
873 in2l_pga, ARRAY_SIZE(in2l_pga)),
874SND_SOC_DAPM_MIXER("IN2R PGA", WM8993_POWER_MANAGEMENT_2, 5, 0,
875 in2r_pga, ARRAY_SIZE(in2r_pga)),
876
Mark Browna2342ae2009-07-29 21:21:49 +0100877SND_SOC_DAPM_MIXER("MIXINL", WM8993_POWER_MANAGEMENT_2, 9, 0,
878 mixinl, ARRAY_SIZE(mixinl)),
879SND_SOC_DAPM_MIXER("MIXINR", WM8993_POWER_MANAGEMENT_2, 8, 0,
880 mixinr, ARRAY_SIZE(mixinr)),
881
Mark Browna2342ae2009-07-29 21:21:49 +0100882SND_SOC_DAPM_MIXER("Left Output Mixer", WM8993_POWER_MANAGEMENT_3, 5, 0,
883 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
884SND_SOC_DAPM_MIXER("Right Output Mixer", WM8993_POWER_MANAGEMENT_3, 4, 0,
885 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
886
887SND_SOC_DAPM_PGA("Left Output PGA", WM8993_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
888SND_SOC_DAPM_PGA("Right Output PGA", WM8993_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
889
Mark Brown3ed70742010-01-20 17:39:45 +0000890SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, hp_supply_event,
891 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
Mark Brown26422622012-02-21 09:36:49 +0000892SND_SOC_DAPM_OUT_DRV_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
893 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
Mark Browna2342ae2009-07-29 21:21:49 +0100894
895SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
896 earpiece_mixer, ARRAY_SIZE(earpiece_mixer)),
897SND_SOC_DAPM_PGA_E("Earpiece Driver", WM8993_POWER_MANAGEMENT_1, 11, 0,
898 NULL, 0, earpiece_event,
899 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
900
901SND_SOC_DAPM_MIXER("SPKL Boost", SND_SOC_NOPM, 0, 0,
902 left_speaker_boost, ARRAY_SIZE(left_speaker_boost)),
903SND_SOC_DAPM_MIXER("SPKR Boost", SND_SOC_NOPM, 0, 0,
904 right_speaker_boost, ARRAY_SIZE(right_speaker_boost)),
905
Mark Brown03431972011-11-04 17:11:54 +0000906SND_SOC_DAPM_SUPPLY("TSHUT", WM8993_POWER_MANAGEMENT_2, 14, 0, NULL, 0),
Mark Browndc9c7452012-02-07 14:24:57 +0000907SND_SOC_DAPM_OUT_DRV("SPKL Driver", WM8993_POWER_MANAGEMENT_1, 12, 0,
908 NULL, 0),
909SND_SOC_DAPM_OUT_DRV("SPKR Driver", WM8993_POWER_MANAGEMENT_1, 13, 0,
910 NULL, 0),
Mark Browna2342ae2009-07-29 21:21:49 +0100911
912SND_SOC_DAPM_MIXER("LINEOUT1 Mixer", SND_SOC_NOPM, 0, 0,
913 line1_mix, ARRAY_SIZE(line1_mix)),
914SND_SOC_DAPM_MIXER("LINEOUT2 Mixer", SND_SOC_NOPM, 0, 0,
915 line2_mix, ARRAY_SIZE(line2_mix)),
916
917SND_SOC_DAPM_MIXER("LINEOUT1N Mixer", SND_SOC_NOPM, 0, 0,
918 line1n_mix, ARRAY_SIZE(line1n_mix)),
919SND_SOC_DAPM_MIXER("LINEOUT1P Mixer", SND_SOC_NOPM, 0, 0,
920 line1p_mix, ARRAY_SIZE(line1p_mix)),
921SND_SOC_DAPM_MIXER("LINEOUT2N Mixer", SND_SOC_NOPM, 0, 0,
922 line2n_mix, ARRAY_SIZE(line2n_mix)),
923SND_SOC_DAPM_MIXER("LINEOUT2P Mixer", SND_SOC_NOPM, 0, 0,
924 line2p_mix, ARRAY_SIZE(line2p_mix)),
925
Mark Brown5f2f38902012-02-08 18:51:42 +0000926SND_SOC_DAPM_OUT_DRV_E("LINEOUT1N Driver", WM8993_POWER_MANAGEMENT_3, 13, 0,
927 NULL, 0, lineout_event,
928 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
929SND_SOC_DAPM_OUT_DRV_E("LINEOUT1P Driver", WM8993_POWER_MANAGEMENT_3, 12, 0,
930 NULL, 0, lineout_event,
931 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
932SND_SOC_DAPM_OUT_DRV_E("LINEOUT2N Driver", WM8993_POWER_MANAGEMENT_3, 11, 0,
933 NULL, 0, lineout_event,
934 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
935SND_SOC_DAPM_OUT_DRV_E("LINEOUT2P Driver", WM8993_POWER_MANAGEMENT_3, 10, 0,
936 NULL, 0, lineout_event,
937 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
Mark Browna2342ae2009-07-29 21:21:49 +0100938
939SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
940SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
941SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
942SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
943SND_SOC_DAPM_OUTPUT("HPOUT1L"),
944SND_SOC_DAPM_OUTPUT("HPOUT1R"),
945SND_SOC_DAPM_OUTPUT("HPOUT2P"),
946SND_SOC_DAPM_OUTPUT("HPOUT2N"),
947SND_SOC_DAPM_OUTPUT("LINEOUT1P"),
948SND_SOC_DAPM_OUTPUT("LINEOUT1N"),
949SND_SOC_DAPM_OUTPUT("LINEOUT2P"),
950SND_SOC_DAPM_OUTPUT("LINEOUT2N"),
951};
952
953static const struct snd_soc_dapm_route analogue_routes[] = {
Mark Brown4baafdd2011-02-18 15:05:53 -0800954 { "MICBIAS1", NULL, "CLK_SYS" },
955 { "MICBIAS2", NULL, "CLK_SYS" },
956
Mark Browna2342ae2009-07-29 21:21:49 +0100957 { "IN1L PGA", "IN1LP Switch", "IN1LP" },
958 { "IN1L PGA", "IN1LN Switch", "IN1LN" },
959
Mark Brown4e04ada2011-07-15 15:12:31 +0900960 { "IN1L PGA", NULL, "VMID" },
961 { "IN1R PGA", NULL, "VMID" },
962 { "IN2L PGA", NULL, "VMID" },
963 { "IN2R PGA", NULL, "VMID" },
964
Mark Browna2342ae2009-07-29 21:21:49 +0100965 { "IN1R PGA", "IN1RP Switch", "IN1RP" },
966 { "IN1R PGA", "IN1RN Switch", "IN1RN" },
967
Joonyoung Shim34825942009-12-04 15:12:10 +0900968 { "IN2L PGA", "IN2LP Switch", "IN2LP:VXRN" },
Mark Browna2342ae2009-07-29 21:21:49 +0100969 { "IN2L PGA", "IN2LN Switch", "IN2LN" },
970
Joonyoung Shim34825942009-12-04 15:12:10 +0900971 { "IN2R PGA", "IN2RP Switch", "IN2RP:VXRP" },
Mark Browna2342ae2009-07-29 21:21:49 +0100972 { "IN2R PGA", "IN2RN Switch", "IN2RN" },
973
Joonyoung Shim34825942009-12-04 15:12:10 +0900974 { "Direct Voice", NULL, "IN2LP:VXRN" },
975 { "Direct Voice", NULL, "IN2RP:VXRP" },
Mark Browna2342ae2009-07-29 21:21:49 +0100976
977 { "MIXINL", "IN1L Switch", "IN1L PGA" },
978 { "MIXINL", "IN2L Switch", "IN2L PGA" },
979 { "MIXINL", NULL, "Direct Voice" },
980 { "MIXINL", NULL, "IN1LP" },
981 { "MIXINL", NULL, "Left Output Mixer" },
Mark Brown4e04ada2011-07-15 15:12:31 +0900982 { "MIXINL", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +0100983
984 { "MIXINR", "IN1R Switch", "IN1R PGA" },
985 { "MIXINR", "IN2R Switch", "IN2R PGA" },
986 { "MIXINR", NULL, "Direct Voice" },
987 { "MIXINR", NULL, "IN1RP" },
988 { "MIXINR", NULL, "Right Output Mixer" },
Mark Brown4e04ada2011-07-15 15:12:31 +0900989 { "MIXINR", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +0100990
991 { "ADCL", NULL, "MIXINL" },
992 { "ADCR", NULL, "MIXINR" },
993
994 { "Left Output Mixer", "Left Input Switch", "MIXINL" },
995 { "Left Output Mixer", "Right Input Switch", "MIXINR" },
996 { "Left Output Mixer", "IN2RN Switch", "IN2RN" },
997 { "Left Output Mixer", "IN2LN Switch", "IN2LN" },
Joonyoung Shim34825942009-12-04 15:12:10 +0900998 { "Left Output Mixer", "IN2LP Switch", "IN2LP:VXRN" },
Mark Browna2342ae2009-07-29 21:21:49 +0100999 { "Left Output Mixer", "IN1L Switch", "IN1L PGA" },
1000 { "Left Output Mixer", "IN1R Switch", "IN1R PGA" },
1001
1002 { "Right Output Mixer", "Left Input Switch", "MIXINL" },
1003 { "Right Output Mixer", "Right Input Switch", "MIXINR" },
1004 { "Right Output Mixer", "IN2LN Switch", "IN2LN" },
1005 { "Right Output Mixer", "IN2RN Switch", "IN2RN" },
Joonyoung Shim34825942009-12-04 15:12:10 +09001006 { "Right Output Mixer", "IN2RP Switch", "IN2RP:VXRP" },
Mark Browna2342ae2009-07-29 21:21:49 +01001007 { "Right Output Mixer", "IN1L Switch", "IN1L PGA" },
1008 { "Right Output Mixer", "IN1R Switch", "IN1R PGA" },
1009
1010 { "Left Output PGA", NULL, "Left Output Mixer" },
1011 { "Left Output PGA", NULL, "TOCLK" },
1012
1013 { "Right Output PGA", NULL, "Right Output Mixer" },
1014 { "Right Output PGA", NULL, "TOCLK" },
1015
1016 { "Earpiece Mixer", "Direct Voice Switch", "Direct Voice" },
1017 { "Earpiece Mixer", "Left Output Switch", "Left Output PGA" },
1018 { "Earpiece Mixer", "Right Output Switch", "Right Output PGA" },
1019
Mark Brown4e04ada2011-07-15 15:12:31 +09001020 { "Earpiece Driver", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +01001021 { "Earpiece Driver", NULL, "Earpiece Mixer" },
1022 { "HPOUT2N", NULL, "Earpiece Driver" },
1023 { "HPOUT2P", NULL, "Earpiece Driver" },
1024
1025 { "SPKL", "Input Switch", "MIXINL" },
1026 { "SPKL", "IN1LP Switch", "IN1LP" },
Mark Brown39cca162011-04-08 16:32:16 +09001027 { "SPKL", "Output Switch", "Left Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +01001028 { "SPKL", NULL, "TOCLK" },
1029
1030 { "SPKR", "Input Switch", "MIXINR" },
1031 { "SPKR", "IN1RP Switch", "IN1RP" },
Mark Brown39cca162011-04-08 16:32:16 +09001032 { "SPKR", "Output Switch", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +01001033 { "SPKR", NULL, "TOCLK" },
1034
1035 { "SPKL Boost", "Direct Voice Switch", "Direct Voice" },
1036 { "SPKL Boost", "SPKL Switch", "SPKL" },
1037 { "SPKL Boost", "SPKR Switch", "SPKR" },
1038
1039 { "SPKR Boost", "Direct Voice Switch", "Direct Voice" },
1040 { "SPKR Boost", "SPKR Switch", "SPKR" },
1041 { "SPKR Boost", "SPKL Switch", "SPKL" },
1042
Mark Brown4e04ada2011-07-15 15:12:31 +09001043 { "SPKL Driver", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +01001044 { "SPKL Driver", NULL, "SPKL Boost" },
1045 { "SPKL Driver", NULL, "CLK_SYS" },
Mark Brown03431972011-11-04 17:11:54 +00001046 { "SPKL Driver", NULL, "TSHUT" },
Mark Browna2342ae2009-07-29 21:21:49 +01001047
Mark Brown4e04ada2011-07-15 15:12:31 +09001048 { "SPKR Driver", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +01001049 { "SPKR Driver", NULL, "SPKR Boost" },
1050 { "SPKR Driver", NULL, "CLK_SYS" },
Mark Brown03431972011-11-04 17:11:54 +00001051 { "SPKR Driver", NULL, "TSHUT" },
Mark Browna2342ae2009-07-29 21:21:49 +01001052
1053 { "SPKOUTLP", NULL, "SPKL Driver" },
1054 { "SPKOUTLN", NULL, "SPKL Driver" },
1055 { "SPKOUTRP", NULL, "SPKR Driver" },
1056 { "SPKOUTRN", NULL, "SPKR Driver" },
1057
Mark Brown39cca162011-04-08 16:32:16 +09001058 { "Left Headphone Mux", "Mixer", "Left Output PGA" },
1059 { "Right Headphone Mux", "Mixer", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +01001060
1061 { "Headphone PGA", NULL, "Left Headphone Mux" },
1062 { "Headphone PGA", NULL, "Right Headphone Mux" },
Mark Brown4e04ada2011-07-15 15:12:31 +09001063 { "Headphone PGA", NULL, "VMID" },
Mark Browna2342ae2009-07-29 21:21:49 +01001064 { "Headphone PGA", NULL, "CLK_SYS" },
Mark Brown3ed70742010-01-20 17:39:45 +00001065 { "Headphone PGA", NULL, "Headphone Supply" },
Mark Browna2342ae2009-07-29 21:21:49 +01001066
1067 { "HPOUT1L", NULL, "Headphone PGA" },
1068 { "HPOUT1R", NULL, "Headphone PGA" },
1069
Mark Brown4e04ada2011-07-15 15:12:31 +09001070 { "LINEOUT1N Driver", NULL, "VMID" },
1071 { "LINEOUT1P Driver", NULL, "VMID" },
1072 { "LINEOUT2N Driver", NULL, "VMID" },
1073 { "LINEOUT2P Driver", NULL, "VMID" },
1074
Mark Browna2342ae2009-07-29 21:21:49 +01001075 { "LINEOUT1N", NULL, "LINEOUT1N Driver" },
1076 { "LINEOUT1P", NULL, "LINEOUT1P Driver" },
1077 { "LINEOUT2N", NULL, "LINEOUT2N Driver" },
1078 { "LINEOUT2P", NULL, "LINEOUT2P Driver" },
1079};
1080
1081static const struct snd_soc_dapm_route lineout1_diff_routes[] = {
1082 { "LINEOUT1 Mixer", "IN1L Switch", "IN1L PGA" },
1083 { "LINEOUT1 Mixer", "IN1R Switch", "IN1R PGA" },
Mark Brownd0b48af2011-05-14 17:21:28 -07001084 { "LINEOUT1 Mixer", "Output Switch", "Left Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +01001085
1086 { "LINEOUT1N Driver", NULL, "LINEOUT1 Mixer" },
1087 { "LINEOUT1P Driver", NULL, "LINEOUT1 Mixer" },
1088};
1089
1090static const struct snd_soc_dapm_route lineout1_se_routes[] = {
Mark Brownd0b48af2011-05-14 17:21:28 -07001091 { "LINEOUT1N Mixer", "Left Output Switch", "Left Output PGA" },
1092 { "LINEOUT1N Mixer", "Right Output Switch", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +01001093
Mark Brownd0b48af2011-05-14 17:21:28 -07001094 { "LINEOUT1P Mixer", "Left Output Switch", "Left Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +01001095
1096 { "LINEOUT1N Driver", NULL, "LINEOUT1N Mixer" },
1097 { "LINEOUT1P Driver", NULL, "LINEOUT1P Mixer" },
1098};
1099
1100static const struct snd_soc_dapm_route lineout2_diff_routes[] = {
Mark Brownee767442012-01-31 11:55:32 +00001101 { "LINEOUT2 Mixer", "IN1L Switch", "IN1L PGA" },
1102 { "LINEOUT2 Mixer", "IN1R Switch", "IN1R PGA" },
Mark Brownd0b48af2011-05-14 17:21:28 -07001103 { "LINEOUT2 Mixer", "Output Switch", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +01001104
1105 { "LINEOUT2N Driver", NULL, "LINEOUT2 Mixer" },
1106 { "LINEOUT2P Driver", NULL, "LINEOUT2 Mixer" },
1107};
1108
1109static const struct snd_soc_dapm_route lineout2_se_routes[] = {
Mark Brownd0b48af2011-05-14 17:21:28 -07001110 { "LINEOUT2N Mixer", "Left Output Switch", "Left Output PGA" },
1111 { "LINEOUT2N Mixer", "Right Output Switch", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +01001112
Mark Brownd0b48af2011-05-14 17:21:28 -07001113 { "LINEOUT2P Mixer", "Right Output Switch", "Right Output PGA" },
Mark Browna2342ae2009-07-29 21:21:49 +01001114
1115 { "LINEOUT2N Driver", NULL, "LINEOUT2N Mixer" },
1116 { "LINEOUT2P Driver", NULL, "LINEOUT2P Mixer" },
1117};
1118
1119int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec)
1120{
Liam Girdwoodce6120c2010-11-05 15:53:46 +02001121 struct snd_soc_dapm_context *dapm = &codec->dapm;
1122
Mark Browna2342ae2009-07-29 21:21:49 +01001123 /* Latch volume update bits & default ZC on */
1124 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_1_2_VOLUME,
1125 WM8993_IN1_VU, WM8993_IN1_VU);
1126 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_1_2_VOLUME,
1127 WM8993_IN1_VU, WM8993_IN1_VU);
1128 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_3_4_VOLUME,
1129 WM8993_IN2_VU, WM8993_IN2_VU);
1130 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_3_4_VOLUME,
1131 WM8993_IN2_VU, WM8993_IN2_VU);
1132
Mark Brownfb5af532011-05-15 12:18:38 -07001133 snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_LEFT,
1134 WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
Mark Browna2342ae2009-07-29 21:21:49 +01001135 snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_RIGHT,
1136 WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
1137
1138 snd_soc_update_bits(codec, WM8993_LEFT_OUTPUT_VOLUME,
Mark Brownfb5af532011-05-15 12:18:38 -07001139 WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC,
1140 WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC);
Mark Browna2342ae2009-07-29 21:21:49 +01001141 snd_soc_update_bits(codec, WM8993_RIGHT_OUTPUT_VOLUME,
1142 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC,
1143 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC);
1144
1145 snd_soc_update_bits(codec, WM8993_LEFT_OPGA_VOLUME,
Mark Brownfb5af532011-05-15 12:18:38 -07001146 WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU,
1147 WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU);
Mark Browna2342ae2009-07-29 21:21:49 +01001148 snd_soc_update_bits(codec, WM8993_RIGHT_OPGA_VOLUME,
1149 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU,
1150 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU);
1151
Liam Girdwood022658b2012-02-03 17:43:09 +00001152 snd_soc_add_codec_controls(codec, analogue_snd_controls,
Mark Browna2342ae2009-07-29 21:21:49 +01001153 ARRAY_SIZE(analogue_snd_controls));
1154
Liam Girdwoodce6120c2010-11-05 15:53:46 +02001155 snd_soc_dapm_new_controls(dapm, analogue_dapm_widgets,
Mark Browna2342ae2009-07-29 21:21:49 +01001156 ARRAY_SIZE(analogue_dapm_widgets));
1157 return 0;
1158}
1159EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_controls);
1160
1161int wm_hubs_add_analogue_routes(struct snd_soc_codec *codec,
1162 int lineout1_diff, int lineout2_diff)
1163{
Mark Brownd96ca3c2011-07-12 15:25:03 +09001164 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
Liam Girdwoodce6120c2010-11-05 15:53:46 +02001165 struct snd_soc_dapm_context *dapm = &codec->dapm;
1166
Mark Brown8cb8e832012-07-25 18:10:03 +01001167 hubs->codec = codec;
1168
Mark Brown94aa7332012-05-01 18:45:09 +01001169 INIT_LIST_HEAD(&hubs->dcs_cache);
Mark Brownd96ca3c2011-07-12 15:25:03 +09001170 init_completion(&hubs->dcs_done);
1171
Liam Girdwoodce6120c2010-11-05 15:53:46 +02001172 snd_soc_dapm_add_routes(dapm, analogue_routes,
Mark Browna2342ae2009-07-29 21:21:49 +01001173 ARRAY_SIZE(analogue_routes));
1174
1175 if (lineout1_diff)
Liam Girdwoodce6120c2010-11-05 15:53:46 +02001176 snd_soc_dapm_add_routes(dapm,
Mark Browna2342ae2009-07-29 21:21:49 +01001177 lineout1_diff_routes,
1178 ARRAY_SIZE(lineout1_diff_routes));
1179 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +02001180 snd_soc_dapm_add_routes(dapm,
Mark Browna2342ae2009-07-29 21:21:49 +01001181 lineout1_se_routes,
1182 ARRAY_SIZE(lineout1_se_routes));
1183
1184 if (lineout2_diff)
Liam Girdwoodce6120c2010-11-05 15:53:46 +02001185 snd_soc_dapm_add_routes(dapm,
Mark Browna2342ae2009-07-29 21:21:49 +01001186 lineout2_diff_routes,
1187 ARRAY_SIZE(lineout2_diff_routes));
1188 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +02001189 snd_soc_dapm_add_routes(dapm,
Mark Browna2342ae2009-07-29 21:21:49 +01001190 lineout2_se_routes,
1191 ARRAY_SIZE(lineout2_se_routes));
1192
1193 return 0;
1194}
1195EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_routes);
1196
Mark Brownaa983d92009-09-30 14:16:11 +01001197int wm_hubs_handle_analogue_pdata(struct snd_soc_codec *codec,
1198 int lineout1_diff, int lineout2_diff,
1199 int lineout1fb, int lineout2fb,
Mark Brown02e79472012-08-21 17:54:52 +01001200 int jd_scthr, int jd_thr,
1201 int micbias1_delay, int micbias2_delay,
1202 int micbias1_lvl, int micbias2_lvl)
Mark Brownaa983d92009-09-30 14:16:11 +01001203{
Mark Brown5f2f38902012-02-08 18:51:42 +00001204 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
1205
1206 hubs->lineout1_se = !lineout1_diff;
1207 hubs->lineout2_se = !lineout2_diff;
Mark Brown02e79472012-08-21 17:54:52 +01001208 hubs->micb1_delay = micbias1_delay;
1209 hubs->micb2_delay = micbias2_delay;
Mark Brown5f2f38902012-02-08 18:51:42 +00001210
Mark Brownaa983d92009-09-30 14:16:11 +01001211 if (!lineout1_diff)
1212 snd_soc_update_bits(codec, WM8993_LINE_MIXER1,
1213 WM8993_LINEOUT1_MODE,
1214 WM8993_LINEOUT1_MODE);
1215 if (!lineout2_diff)
1216 snd_soc_update_bits(codec, WM8993_LINE_MIXER2,
1217 WM8993_LINEOUT2_MODE,
1218 WM8993_LINEOUT2_MODE);
1219
Mark Brown5472bbc2012-03-19 17:31:56 +00001220 if (!lineout1_diff && !lineout2_diff)
1221 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1222 WM8993_LINEOUT_VMID_BUF_ENA,
1223 WM8993_LINEOUT_VMID_BUF_ENA);
1224
Mark Brownaa983d92009-09-30 14:16:11 +01001225 if (lineout1fb)
1226 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
1227 WM8993_LINEOUT1_FB, WM8993_LINEOUT1_FB);
1228
1229 if (lineout2fb)
1230 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
1231 WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB);
1232
1233 snd_soc_update_bits(codec, WM8993_MICBIAS,
1234 WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK |
1235 WM8993_MICB1_LVL | WM8993_MICB2_LVL,
1236 jd_scthr << WM8993_JD_SCTHR_SHIFT |
1237 jd_thr << WM8993_JD_THR_SHIFT |
1238 micbias1_lvl |
1239 micbias2_lvl << WM8993_MICB2_LVL_SHIFT);
1240
1241 return 0;
1242}
1243EXPORT_SYMBOL_GPL(wm_hubs_handle_analogue_pdata);
1244
Mark Brown5f2f38902012-02-08 18:51:42 +00001245void wm_hubs_vmid_ena(struct snd_soc_codec *codec)
1246{
1247 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
1248 int val = 0;
1249
1250 if (hubs->lineout1_se)
1251 val |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA;
1252
1253 if (hubs->lineout2_se)
1254 val |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA;
1255
1256 /* Enable the line outputs while we power up */
1257 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_3, val, val);
1258}
1259EXPORT_SYMBOL_GPL(wm_hubs_vmid_ena);
1260
1261void wm_hubs_set_bias_level(struct snd_soc_codec *codec,
1262 enum snd_soc_bias_level level)
1263{
1264 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
Mark Brownde050ac2012-04-17 20:28:10 +01001265 int mask, val;
Mark Brown5f2f38902012-02-08 18:51:42 +00001266
1267 switch (level) {
Mark Brownd60d6c32012-02-10 18:09:42 +00001268 case SND_SOC_BIAS_STANDBY:
1269 /* Clamp the inputs to VMID while we ramp to charge caps */
1270 snd_soc_update_bits(codec, WM8993_INPUTS_CLAMP_REG,
1271 WM8993_INPUTS_CLAMP, WM8993_INPUTS_CLAMP);
1272 break;
1273
Mark Brown5f2f38902012-02-08 18:51:42 +00001274 case SND_SOC_BIAS_ON:
1275 /* Turn off any unneded single ended outputs */
1276 val = 0;
Mark Brownde050ac2012-04-17 20:28:10 +01001277 mask = 0;
1278
1279 if (hubs->lineout1_se)
1280 mask |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA;
1281
1282 if (hubs->lineout2_se)
1283 mask |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA;
Mark Brown5f2f38902012-02-08 18:51:42 +00001284
1285 if (hubs->lineout1_se && hubs->lineout1n_ena)
1286 val |= WM8993_LINEOUT1N_ENA;
1287
1288 if (hubs->lineout1_se && hubs->lineout1p_ena)
1289 val |= WM8993_LINEOUT1P_ENA;
1290
1291 if (hubs->lineout2_se && hubs->lineout2n_ena)
1292 val |= WM8993_LINEOUT2N_ENA;
1293
1294 if (hubs->lineout2_se && hubs->lineout2p_ena)
1295 val |= WM8993_LINEOUT2P_ENA;
1296
1297 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_3,
Mark Brownde050ac2012-04-17 20:28:10 +01001298 mask, val);
Mark Brown5f2f38902012-02-08 18:51:42 +00001299
Mark Brownd60d6c32012-02-10 18:09:42 +00001300 /* Remove the input clamps */
1301 snd_soc_update_bits(codec, WM8993_INPUTS_CLAMP_REG,
1302 WM8993_INPUTS_CLAMP, 0);
Mark Brown5f2f38902012-02-08 18:51:42 +00001303 break;
1304
1305 default:
1306 break;
1307 }
1308}
1309EXPORT_SYMBOL_GPL(wm_hubs_set_bias_level);
1310
Mark Browna2342ae2009-07-29 21:21:49 +01001311MODULE_DESCRIPTION("Shared support for Wolfson hubs products");
1312MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1313MODULE_LICENSE("GPL");