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Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001/*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
Nicolas Ferre1ccc4042013-04-03 13:59:19 +080018#include <linux/dmaengine.h>
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080019#include <linux/err.h>
20#include <linux/interrupt.h>
21#include <linux/spi/spi.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090022#include <linux/slab.h>
Jean-Christophe PLAGNIOL-VILLARDbcd23602012-10-30 05:12:23 +080023#include <linux/platform_data/atmel.h>
Nicolas Ferre1ccc4042013-04-03 13:59:19 +080024#include <linux/platform_data/dma-atmel.h>
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +010025#include <linux/of.h>
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080026
Wenyou Yangd4820b72013-03-19 15:42:15 +080027#include <linux/io.h>
28#include <linux/gpio.h>
David Brownellbb2d1c32007-02-20 13:58:19 -080029
Grant Likelyca632f52011-06-06 01:16:30 -060030/* SPI register offsets */
31#define SPI_CR 0x0000
32#define SPI_MR 0x0004
33#define SPI_RDR 0x0008
34#define SPI_TDR 0x000c
35#define SPI_SR 0x0010
36#define SPI_IER 0x0014
37#define SPI_IDR 0x0018
38#define SPI_IMR 0x001c
39#define SPI_CSR0 0x0030
40#define SPI_CSR1 0x0034
41#define SPI_CSR2 0x0038
42#define SPI_CSR3 0x003c
Wenyou Yangd4820b72013-03-19 15:42:15 +080043#define SPI_VERSION 0x00fc
Grant Likelyca632f52011-06-06 01:16:30 -060044#define SPI_RPR 0x0100
45#define SPI_RCR 0x0104
46#define SPI_TPR 0x0108
47#define SPI_TCR 0x010c
48#define SPI_RNPR 0x0110
49#define SPI_RNCR 0x0114
50#define SPI_TNPR 0x0118
51#define SPI_TNCR 0x011c
52#define SPI_PTCR 0x0120
53#define SPI_PTSR 0x0124
54
55/* Bitfields in CR */
56#define SPI_SPIEN_OFFSET 0
57#define SPI_SPIEN_SIZE 1
58#define SPI_SPIDIS_OFFSET 1
59#define SPI_SPIDIS_SIZE 1
60#define SPI_SWRST_OFFSET 7
61#define SPI_SWRST_SIZE 1
62#define SPI_LASTXFER_OFFSET 24
63#define SPI_LASTXFER_SIZE 1
64
65/* Bitfields in MR */
66#define SPI_MSTR_OFFSET 0
67#define SPI_MSTR_SIZE 1
68#define SPI_PS_OFFSET 1
69#define SPI_PS_SIZE 1
70#define SPI_PCSDEC_OFFSET 2
71#define SPI_PCSDEC_SIZE 1
72#define SPI_FDIV_OFFSET 3
73#define SPI_FDIV_SIZE 1
74#define SPI_MODFDIS_OFFSET 4
75#define SPI_MODFDIS_SIZE 1
Wenyou Yangd4820b72013-03-19 15:42:15 +080076#define SPI_WDRBT_OFFSET 5
77#define SPI_WDRBT_SIZE 1
Grant Likelyca632f52011-06-06 01:16:30 -060078#define SPI_LLB_OFFSET 7
79#define SPI_LLB_SIZE 1
80#define SPI_PCS_OFFSET 16
81#define SPI_PCS_SIZE 4
82#define SPI_DLYBCS_OFFSET 24
83#define SPI_DLYBCS_SIZE 8
84
85/* Bitfields in RDR */
86#define SPI_RD_OFFSET 0
87#define SPI_RD_SIZE 16
88
89/* Bitfields in TDR */
90#define SPI_TD_OFFSET 0
91#define SPI_TD_SIZE 16
92
93/* Bitfields in SR */
94#define SPI_RDRF_OFFSET 0
95#define SPI_RDRF_SIZE 1
96#define SPI_TDRE_OFFSET 1
97#define SPI_TDRE_SIZE 1
98#define SPI_MODF_OFFSET 2
99#define SPI_MODF_SIZE 1
100#define SPI_OVRES_OFFSET 3
101#define SPI_OVRES_SIZE 1
102#define SPI_ENDRX_OFFSET 4
103#define SPI_ENDRX_SIZE 1
104#define SPI_ENDTX_OFFSET 5
105#define SPI_ENDTX_SIZE 1
106#define SPI_RXBUFF_OFFSET 6
107#define SPI_RXBUFF_SIZE 1
108#define SPI_TXBUFE_OFFSET 7
109#define SPI_TXBUFE_SIZE 1
110#define SPI_NSSR_OFFSET 8
111#define SPI_NSSR_SIZE 1
112#define SPI_TXEMPTY_OFFSET 9
113#define SPI_TXEMPTY_SIZE 1
114#define SPI_SPIENS_OFFSET 16
115#define SPI_SPIENS_SIZE 1
116
117/* Bitfields in CSR0 */
118#define SPI_CPOL_OFFSET 0
119#define SPI_CPOL_SIZE 1
120#define SPI_NCPHA_OFFSET 1
121#define SPI_NCPHA_SIZE 1
122#define SPI_CSAAT_OFFSET 3
123#define SPI_CSAAT_SIZE 1
124#define SPI_BITS_OFFSET 4
125#define SPI_BITS_SIZE 4
126#define SPI_SCBR_OFFSET 8
127#define SPI_SCBR_SIZE 8
128#define SPI_DLYBS_OFFSET 16
129#define SPI_DLYBS_SIZE 8
130#define SPI_DLYBCT_OFFSET 24
131#define SPI_DLYBCT_SIZE 8
132
133/* Bitfields in RCR */
134#define SPI_RXCTR_OFFSET 0
135#define SPI_RXCTR_SIZE 16
136
137/* Bitfields in TCR */
138#define SPI_TXCTR_OFFSET 0
139#define SPI_TXCTR_SIZE 16
140
141/* Bitfields in RNCR */
142#define SPI_RXNCR_OFFSET 0
143#define SPI_RXNCR_SIZE 16
144
145/* Bitfields in TNCR */
146#define SPI_TXNCR_OFFSET 0
147#define SPI_TXNCR_SIZE 16
148
149/* Bitfields in PTCR */
150#define SPI_RXTEN_OFFSET 0
151#define SPI_RXTEN_SIZE 1
152#define SPI_RXTDIS_OFFSET 1
153#define SPI_RXTDIS_SIZE 1
154#define SPI_TXTEN_OFFSET 8
155#define SPI_TXTEN_SIZE 1
156#define SPI_TXTDIS_OFFSET 9
157#define SPI_TXTDIS_SIZE 1
158
159/* Constants for BITS */
160#define SPI_BITS_8_BPT 0
161#define SPI_BITS_9_BPT 1
162#define SPI_BITS_10_BPT 2
163#define SPI_BITS_11_BPT 3
164#define SPI_BITS_12_BPT 4
165#define SPI_BITS_13_BPT 5
166#define SPI_BITS_14_BPT 6
167#define SPI_BITS_15_BPT 7
168#define SPI_BITS_16_BPT 8
169
170/* Bit manipulation macros */
171#define SPI_BIT(name) \
172 (1 << SPI_##name##_OFFSET)
Sachin Kamata536d762013-09-10 17:06:27 +0530173#define SPI_BF(name, value) \
Grant Likelyca632f52011-06-06 01:16:30 -0600174 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
Sachin Kamata536d762013-09-10 17:06:27 +0530175#define SPI_BFEXT(name, value) \
Grant Likelyca632f52011-06-06 01:16:30 -0600176 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
Sachin Kamata536d762013-09-10 17:06:27 +0530177#define SPI_BFINS(name, value, old) \
178 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
179 | SPI_BF(name, value))
Grant Likelyca632f52011-06-06 01:16:30 -0600180
181/* Register access macros */
Sachin Kamata536d762013-09-10 17:06:27 +0530182#define spi_readl(port, reg) \
Grant Likelyca632f52011-06-06 01:16:30 -0600183 __raw_readl((port)->regs + SPI_##reg)
Sachin Kamata536d762013-09-10 17:06:27 +0530184#define spi_writel(port, reg, value) \
Grant Likelyca632f52011-06-06 01:16:30 -0600185 __raw_writel((value), (port)->regs + SPI_##reg)
186
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800187/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
188 * cache operations; better heuristics consider wordsize and bitrate.
189 */
190#define DMA_MIN_BYTES 16
191
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800192#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
193
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800194struct atmel_spi_dma {
195 struct dma_chan *chan_rx;
196 struct dma_chan *chan_tx;
197 struct scatterlist sgrx;
198 struct scatterlist sgtx;
199 struct dma_async_tx_descriptor *data_desc_rx;
200 struct dma_async_tx_descriptor *data_desc_tx;
201
202 struct at_dma_slave dma_slave;
203};
204
Wenyou Yangd4820b72013-03-19 15:42:15 +0800205struct atmel_spi_caps {
206 bool is_spi2;
207 bool has_wdrbt;
208 bool has_dma_support;
209};
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800210
211/*
212 * The core SPI transfer engine just talks to a register bank to set up
213 * DMA transfers; transfer queue progress is driven by IRQs. The clock
214 * framework provides the base clock, subdivided for each spi_device.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800215 */
216struct atmel_spi {
217 spinlock_t lock;
Nicolas Ferre8aad7922013-04-03 13:58:36 +0800218 unsigned long flags;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800219
Nicolas Ferredfab30e2013-04-03 13:57:42 +0800220 phys_addr_t phybase;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800221 void __iomem *regs;
222 int irq;
223 struct clk *clk;
224 struct platform_device *pdev;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800225
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800226 struct spi_transfer *current_transfer;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800227 unsigned long current_remaining_bytes;
Nicolas Ferre823cd042013-03-19 15:45:01 +0800228 int done_status;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800229
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800230 struct completion xfer_completion;
231
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800232 /* scratch buffer */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800233 void *buffer;
234 dma_addr_t buffer_dma;
Wenyou Yangd4820b72013-03-19 15:42:15 +0800235
236 struct atmel_spi_caps caps;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800237
238 bool use_dma;
239 bool use_pdc;
240 /* dmaengine data */
241 struct atmel_spi_dma dma;
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800242
243 bool keep_cs;
244 bool cs_active;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800245};
246
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800247/* Controller-specific per-slave state */
248struct atmel_spi_device {
249 unsigned int npcs_pin;
250 u32 csr;
251};
252
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800253#define BUFFER_SIZE PAGE_SIZE
254#define INVALID_DMA_ADDRESS 0xffffffff
255
256/*
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800257 * Version 2 of the SPI controller has
258 * - CR.LASTXFER
259 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
260 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
261 * - SPI_CSRx.CSAAT
262 * - SPI_CSRx.SBCR allows faster clocking
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800263 */
Wenyou Yangd4820b72013-03-19 15:42:15 +0800264static bool atmel_spi_is_v2(struct atmel_spi *as)
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800265{
Wenyou Yangd4820b72013-03-19 15:42:15 +0800266 return as->caps.is_spi2;
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800267}
268
269/*
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800270 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
271 * they assume that spi slave device state will not change on deselect, so
David Brownelldefbd3b2007-07-17 04:04:08 -0700272 * that automagic deselection is OK. ("NPCSx rises if no data is to be
273 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
274 * controllers have CSAAT and friends.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800275 *
David Brownelldefbd3b2007-07-17 04:04:08 -0700276 * Since the CSAAT functionality is a bit weird on newer controllers as
277 * well, we use GPIO to control nCSx pins on all controllers, updating
278 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
279 * support active-high chipselects despite the controller's belief that
280 * only active-low devices/systems exists.
281 *
282 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
283 * right when driven with GPIO. ("Mode Fault does not allow more than one
284 * Master on Chip Select 0.") No workaround exists for that ... so for
285 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
286 * and (c) will trigger that first erratum in some cases.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800287 */
288
David Brownelldefbd3b2007-07-17 04:04:08 -0700289static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800290{
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800291 struct atmel_spi_device *asd = spi->controller_state;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800292 unsigned active = spi->mode & SPI_CS_HIGH;
David Brownelldefbd3b2007-07-17 04:04:08 -0700293 u32 mr;
Atsushi Nemotof6febcc2008-02-23 15:23:39 -0800294
Wenyou Yangd4820b72013-03-19 15:42:15 +0800295 if (atmel_spi_is_v2(as)) {
Wenyou Yang97ed4652013-03-19 15:43:01 +0800296 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
297 /* For the low SPI version, there is a issue that PDC transfer
298 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800299 */
300 spi_writel(as, CSR0, asd->csr);
Wenyou Yangd4820b72013-03-19 15:42:15 +0800301 if (as->caps.has_wdrbt) {
Wenyou Yang97ed4652013-03-19 15:43:01 +0800302 spi_writel(as, MR,
303 SPI_BF(PCS, ~(0x01 << spi->chip_select))
304 | SPI_BIT(WDRBT)
305 | SPI_BIT(MODFDIS)
306 | SPI_BIT(MSTR));
Wenyou Yangd4820b72013-03-19 15:42:15 +0800307 } else {
Wenyou Yang97ed4652013-03-19 15:43:01 +0800308 spi_writel(as, MR,
309 SPI_BF(PCS, ~(0x01 << spi->chip_select))
310 | SPI_BIT(MODFDIS)
311 | SPI_BIT(MSTR));
Wenyou Yangd4820b72013-03-19 15:42:15 +0800312 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800313
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800314 mr = spi_readl(as, MR);
315 gpio_set_value(asd->npcs_pin, active);
316 } else {
317 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
318 int i;
319 u32 csr;
320
321 /* Make sure clock polarity is correct */
322 for (i = 0; i < spi->master->num_chipselect; i++) {
323 csr = spi_readl(as, CSR0 + 4 * i);
324 if ((csr ^ cpol) & SPI_BIT(CPOL))
325 spi_writel(as, CSR0 + 4 * i,
326 csr ^ SPI_BIT(CPOL));
327 }
328
329 mr = spi_readl(as, MR);
330 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
331 if (spi->chip_select != 0)
332 gpio_set_value(asd->npcs_pin, active);
333 spi_writel(as, MR, mr);
Atsushi Nemotof6febcc2008-02-23 15:23:39 -0800334 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800335
David Brownelldefbd3b2007-07-17 04:04:08 -0700336 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800337 asd->npcs_pin, active ? " (high)" : "",
David Brownelldefbd3b2007-07-17 04:04:08 -0700338 mr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800339}
340
David Brownelldefbd3b2007-07-17 04:04:08 -0700341static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800342{
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800343 struct atmel_spi_device *asd = spi->controller_state;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800344 unsigned active = spi->mode & SPI_CS_HIGH;
David Brownelldefbd3b2007-07-17 04:04:08 -0700345 u32 mr;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800346
David Brownelldefbd3b2007-07-17 04:04:08 -0700347 /* only deactivate *this* device; sometimes transfers to
348 * another device may be active when this routine is called.
349 */
350 mr = spi_readl(as, MR);
351 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
352 mr = SPI_BFINS(PCS, 0xf, mr);
353 spi_writel(as, MR, mr);
354 }
355
356 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800357 asd->npcs_pin, active ? " (low)" : "",
David Brownelldefbd3b2007-07-17 04:04:08 -0700358 mr);
359
Wenyou Yangd4820b72013-03-19 15:42:15 +0800360 if (atmel_spi_is_v2(as) || spi->chip_select != 0)
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800361 gpio_set_value(asd->npcs_pin, !active);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800362}
363
Mark Brown6c07ef22013-07-28 14:32:27 +0100364static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
Nicolas Ferre8aad7922013-04-03 13:58:36 +0800365{
366 spin_lock_irqsave(&as->lock, as->flags);
367}
368
Mark Brown6c07ef22013-07-28 14:32:27 +0100369static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
Nicolas Ferre8aad7922013-04-03 13:58:36 +0800370{
371 spin_unlock_irqrestore(&as->lock, as->flags);
372}
373
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800374static inline bool atmel_spi_use_dma(struct atmel_spi *as,
375 struct spi_transfer *xfer)
376{
377 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
378}
379
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800380static int atmel_spi_dma_slave_config(struct atmel_spi *as,
381 struct dma_slave_config *slave_config,
382 u8 bits_per_word)
383{
384 int err = 0;
385
386 if (bits_per_word > 8) {
387 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
388 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
389 } else {
390 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
391 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
392 }
393
394 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
395 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
396 slave_config->src_maxburst = 1;
397 slave_config->dst_maxburst = 1;
398 slave_config->device_fc = false;
399
400 slave_config->direction = DMA_MEM_TO_DEV;
401 if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
402 dev_err(&as->pdev->dev,
403 "failed to configure tx dma channel\n");
404 err = -EINVAL;
405 }
406
407 slave_config->direction = DMA_DEV_TO_MEM;
408 if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
409 dev_err(&as->pdev->dev,
410 "failed to configure rx dma channel\n");
411 err = -EINVAL;
412 }
413
414 return err;
415}
416
Richard Genoud2f767a92013-05-31 17:01:59 +0200417static bool filter(struct dma_chan *chan, void *pdata)
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800418{
Richard Genoud2f767a92013-05-31 17:01:59 +0200419 struct atmel_spi_dma *sl_pdata = pdata;
420 struct at_dma_slave *sl;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800421
Richard Genoud2f767a92013-05-31 17:01:59 +0200422 if (!sl_pdata)
423 return false;
424
425 sl = &sl_pdata->dma_slave;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800426 if (sl->dma_dev == chan->device->dev) {
427 chan->private = sl;
428 return true;
429 } else {
430 return false;
431 }
432}
433
434static int atmel_spi_configure_dma(struct atmel_spi *as)
435{
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800436 struct dma_slave_config slave_config;
Richard Genoud2f767a92013-05-31 17:01:59 +0200437 struct device *dev = &as->pdev->dev;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800438 int err;
439
Richard Genoud2f767a92013-05-31 17:01:59 +0200440 dma_cap_mask_t mask;
441 dma_cap_zero(mask);
442 dma_cap_set(DMA_SLAVE, mask);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800443
Richard Genoud2f767a92013-05-31 17:01:59 +0200444 as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter,
445 &as->dma,
446 dev, "tx");
447 if (!as->dma.chan_tx) {
448 dev_err(dev,
449 "DMA TX channel not available, SPI unable to use DMA\n");
450 err = -EBUSY;
451 goto error;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800452 }
Richard Genoud2f767a92013-05-31 17:01:59 +0200453
454 as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter,
455 &as->dma,
456 dev, "rx");
457
458 if (!as->dma.chan_rx) {
459 dev_err(dev,
460 "DMA RX channel not available, SPI unable to use DMA\n");
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800461 err = -EBUSY;
462 goto error;
463 }
464
465 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
466 if (err)
467 goto error;
468
469 dev_info(&as->pdev->dev,
470 "Using %s (tx) and %s (rx) for DMA transfers\n",
471 dma_chan_name(as->dma.chan_tx),
472 dma_chan_name(as->dma.chan_rx));
473 return 0;
474error:
475 if (as->dma.chan_rx)
476 dma_release_channel(as->dma.chan_rx);
477 if (as->dma.chan_tx)
478 dma_release_channel(as->dma.chan_tx);
479 return err;
480}
481
482static void atmel_spi_stop_dma(struct atmel_spi *as)
483{
484 if (as->dma.chan_rx)
485 as->dma.chan_rx->device->device_control(as->dma.chan_rx,
486 DMA_TERMINATE_ALL, 0);
487 if (as->dma.chan_tx)
488 as->dma.chan_tx->device->device_control(as->dma.chan_tx,
489 DMA_TERMINATE_ALL, 0);
490}
491
492static void atmel_spi_release_dma(struct atmel_spi *as)
493{
494 if (as->dma.chan_rx)
495 dma_release_channel(as->dma.chan_rx);
496 if (as->dma.chan_tx)
497 dma_release_channel(as->dma.chan_tx);
498}
499
500/* This function is called by the DMA driver from tasklet context */
501static void dma_callback(void *data)
502{
503 struct spi_master *master = data;
504 struct atmel_spi *as = spi_master_get_devdata(master);
505
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800506 complete(&as->xfer_completion);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800507}
508
509/*
510 * Next transfer using PIO.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800511 */
512static void atmel_spi_next_xfer_pio(struct spi_master *master,
513 struct spi_transfer *xfer)
514{
515 struct atmel_spi *as = spi_master_get_devdata(master);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800516 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800517
518 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
519
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800520 /* Make sure data is not remaining in RDR */
521 spi_readl(as, RDR);
522 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
523 spi_readl(as, RDR);
524 cpu_relax();
525 }
526
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800527 if (xfer->tx_buf) {
Richard Genoudf557c982013-05-02 19:25:11 +0800528 if (xfer->bits_per_word > 8)
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800529 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
Richard Genoudf557c982013-05-02 19:25:11 +0800530 else
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800531 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
532 } else {
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800533 spi_writel(as, TDR, 0);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800534 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800535
536 dev_dbg(master->dev.parent,
Richard Genoudf557c982013-05-02 19:25:11 +0800537 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
538 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
539 xfer->bits_per_word);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800540
541 /* Enable relevant interrupts */
542 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
543}
544
545/*
546 * Submit next transfer for DMA.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800547 */
548static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
549 struct spi_transfer *xfer,
550 u32 *plen)
551{
552 struct atmel_spi *as = spi_master_get_devdata(master);
553 struct dma_chan *rxchan = as->dma.chan_rx;
554 struct dma_chan *txchan = as->dma.chan_tx;
555 struct dma_async_tx_descriptor *rxdesc;
556 struct dma_async_tx_descriptor *txdesc;
557 struct dma_slave_config slave_config;
558 dma_cookie_t cookie;
559 u32 len = *plen;
560
561 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
562
563 /* Check that the channels are available */
564 if (!rxchan || !txchan)
565 return -ENODEV;
566
567 /* release lock for DMA operations */
568 atmel_spi_unlock(as);
569
570 /* prepare the RX dma transfer */
571 sg_init_table(&as->dma.sgrx, 1);
572 if (xfer->rx_buf) {
573 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
574 } else {
575 as->dma.sgrx.dma_address = as->buffer_dma;
576 if (len > BUFFER_SIZE)
577 len = BUFFER_SIZE;
578 }
579
580 /* prepare the TX dma transfer */
581 sg_init_table(&as->dma.sgtx, 1);
582 if (xfer->tx_buf) {
583 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
584 } else {
585 as->dma.sgtx.dma_address = as->buffer_dma;
586 if (len > BUFFER_SIZE)
587 len = BUFFER_SIZE;
588 memset(as->buffer, 0, len);
589 }
590
591 sg_dma_len(&as->dma.sgtx) = len;
592 sg_dma_len(&as->dma.sgrx) = len;
593
594 *plen = len;
595
596 if (atmel_spi_dma_slave_config(as, &slave_config, 8))
597 goto err_exit;
598
599 /* Send both scatterlists */
600 rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
601 &as->dma.sgrx,
602 1,
603 DMA_FROM_DEVICE,
604 DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
605 NULL);
606 if (!rxdesc)
607 goto err_dma;
608
609 txdesc = txchan->device->device_prep_slave_sg(txchan,
610 &as->dma.sgtx,
611 1,
612 DMA_TO_DEVICE,
613 DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
614 NULL);
615 if (!txdesc)
616 goto err_dma;
617
618 dev_dbg(master->dev.parent,
Emil Goode2de024b2013-07-30 19:35:35 +0200619 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
620 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
621 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800622
623 /* Enable relevant interrupts */
624 spi_writel(as, IER, SPI_BIT(OVRES));
625
626 /* Put the callback on the RX transfer only, that should finish last */
627 rxdesc->callback = dma_callback;
628 rxdesc->callback_param = master;
629
630 /* Submit and fire RX and TX with TX last so we're ready to read! */
631 cookie = rxdesc->tx_submit(rxdesc);
632 if (dma_submit_error(cookie))
633 goto err_dma;
634 cookie = txdesc->tx_submit(txdesc);
635 if (dma_submit_error(cookie))
636 goto err_dma;
637 rxchan->device->device_issue_pending(rxchan);
638 txchan->device->device_issue_pending(txchan);
639
640 /* take back lock */
641 atmel_spi_lock(as);
642 return 0;
643
644err_dma:
645 spi_writel(as, IDR, SPI_BIT(OVRES));
646 atmel_spi_stop_dma(as);
647err_exit:
648 atmel_spi_lock(as);
649 return -ENOMEM;
650}
651
Silvester Erdeg154443c2008-02-06 01:38:12 -0800652static void atmel_spi_next_xfer_data(struct spi_master *master,
653 struct spi_transfer *xfer,
654 dma_addr_t *tx_dma,
655 dma_addr_t *rx_dma,
656 u32 *plen)
657{
658 struct atmel_spi *as = spi_master_get_devdata(master);
659 u32 len = *plen;
660
661 /* use scratch buffer only when rx or tx data is unspecified */
662 if (xfer->rx_buf)
Ben Nizette6aed4ee2009-12-14 22:20:20 -0800663 *rx_dma = xfer->rx_dma + xfer->len - *plen;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800664 else {
665 *rx_dma = as->buffer_dma;
666 if (len > BUFFER_SIZE)
667 len = BUFFER_SIZE;
668 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800669
Silvester Erdeg154443c2008-02-06 01:38:12 -0800670 if (xfer->tx_buf)
Ben Nizette6aed4ee2009-12-14 22:20:20 -0800671 *tx_dma = xfer->tx_dma + xfer->len - *plen;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800672 else {
673 *tx_dma = as->buffer_dma;
674 if (len > BUFFER_SIZE)
675 len = BUFFER_SIZE;
676 memset(as->buffer, 0, len);
677 dma_sync_single_for_device(&as->pdev->dev,
678 as->buffer_dma, len, DMA_TO_DEVICE);
679 }
680
681 *plen = len;
682}
683
Richard Genoudd3b72c72013-11-07 10:34:06 +0100684static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
685 struct spi_device *spi,
686 struct spi_transfer *xfer)
687{
688 u32 scbr, csr;
689 unsigned long bus_hz;
690
691 /* v1 chips start out at half the peripheral bus speed. */
692 bus_hz = clk_get_rate(as->clk);
693 if (!atmel_spi_is_v2(as))
694 bus_hz /= 2;
695
696 /*
697 * Calculate the lowest divider that satisfies the
698 * constraint, assuming div32/fdiv/mbz == 0.
699 */
700 if (xfer->speed_hz)
701 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
702 else
703 /*
704 * This can happend if max_speed is null.
705 * In this case, we set the lowest possible speed
706 */
707 scbr = 0xff;
708
709 /*
710 * If the resulting divider doesn't fit into the
711 * register bitfield, we can't satisfy the constraint.
712 */
713 if (scbr >= (1 << SPI_SCBR_SIZE)) {
714 dev_err(&spi->dev,
715 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
716 xfer->speed_hz, scbr, bus_hz/255);
717 return -EINVAL;
718 }
719 if (scbr == 0) {
720 dev_err(&spi->dev,
721 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
722 xfer->speed_hz, scbr, bus_hz);
723 return -EINVAL;
724 }
725 csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
726 csr = SPI_BFINS(SCBR, scbr, csr);
727 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
728
729 return 0;
730}
731
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800732/*
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800733 * Submit next transfer for PDC.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800734 * lock is held, spi irq is blocked
735 */
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800736static void atmel_spi_pdc_next_xfer(struct spi_master *master,
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800737 struct spi_message *msg,
738 struct spi_transfer *xfer)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800739{
740 struct atmel_spi *as = spi_master_get_devdata(master);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800741 u32 len;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800742 dma_addr_t tx_dma, rx_dma;
743
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800744 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
Silvester Erdeg154443c2008-02-06 01:38:12 -0800745
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800746 len = as->current_remaining_bytes;
747 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
748 as->current_remaining_bytes -= len;
Gerard Kamdc329442008-08-04 13:41:12 -0700749
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800750 spi_writel(as, RPR, rx_dma);
751 spi_writel(as, TPR, tx_dma);
752
753 if (msg->spi->bits_per_word > 8)
754 len >>= 1;
755 spi_writel(as, RCR, len);
756 spi_writel(as, TCR, len);
757
758 dev_dbg(&msg->spi->dev,
759 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
760 xfer, xfer->len, xfer->tx_buf,
761 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
762 (unsigned long long)xfer->rx_dma);
763
764 if (as->current_remaining_bytes) {
765 len = as->current_remaining_bytes;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800766 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800767 as->current_remaining_bytes -= len;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800768
769 spi_writel(as, RNPR, rx_dma);
770 spi_writel(as, TNPR, tx_dma);
771
772 if (msg->spi->bits_per_word > 8)
773 len >>= 1;
774 spi_writel(as, RNCR, len);
775 spi_writel(as, TNCR, len);
Haavard Skinnemoen8bacb212008-02-06 01:38:13 -0800776
777 dev_dbg(&msg->spi->dev,
Emil Goode2de024b2013-07-30 19:35:35 +0200778 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
779 xfer, xfer->len, xfer->tx_buf,
780 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
781 (unsigned long long)xfer->rx_dma);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800782 }
783
Silvester Erdeg154443c2008-02-06 01:38:12 -0800784 /* REVISIT: We're waiting for ENDRX before we start the next
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800785 * transfer because we need to handle some difficult timing
786 * issues otherwise. If we wait for ENDTX in one transfer and
787 * then starts waiting for ENDRX in the next, it's difficult
788 * to tell the difference between the ENDRX interrupt we're
789 * actually waiting for and the ENDRX interrupt of the
790 * previous transfer.
791 *
792 * It should be doable, though. Just not now...
793 */
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800794 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800795 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
796}
797
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800798/*
David Brownell8da08592007-07-17 04:04:07 -0700799 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
800 * - The buffer is either valid for CPU access, else NULL
Uwe Kleine-Königb5950762010-11-01 15:38:34 -0400801 * - If the buffer is valid, so is its DMA address
David Brownell8da08592007-07-17 04:04:07 -0700802 *
Uwe Kleine-Königb5950762010-11-01 15:38:34 -0400803 * This driver manages the dma address unless message->is_dma_mapped.
David Brownell8da08592007-07-17 04:04:07 -0700804 */
805static int
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800806atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
807{
David Brownell8da08592007-07-17 04:04:07 -0700808 struct device *dev = &as->pdev->dev;
809
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800810 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
David Brownell8da08592007-07-17 04:04:07 -0700811 if (xfer->tx_buf) {
Jean-Christophe PLAGNIOL-VILLARD214b5742010-11-20 14:52:53 +0800812 /* tx_buf is a const void* where we need a void * for the dma
813 * mapping */
814 void *nonconst_tx = (void *)xfer->tx_buf;
815
David Brownell8da08592007-07-17 04:04:07 -0700816 xfer->tx_dma = dma_map_single(dev,
Jean-Christophe PLAGNIOL-VILLARD214b5742010-11-20 14:52:53 +0800817 nonconst_tx, xfer->len,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800818 DMA_TO_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700819 if (dma_mapping_error(dev, xfer->tx_dma))
David Brownell8da08592007-07-17 04:04:07 -0700820 return -ENOMEM;
821 }
822 if (xfer->rx_buf) {
823 xfer->rx_dma = dma_map_single(dev,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800824 xfer->rx_buf, xfer->len,
825 DMA_FROM_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700826 if (dma_mapping_error(dev, xfer->rx_dma)) {
David Brownell8da08592007-07-17 04:04:07 -0700827 if (xfer->tx_buf)
828 dma_unmap_single(dev,
829 xfer->tx_dma, xfer->len,
830 DMA_TO_DEVICE);
831 return -ENOMEM;
832 }
833 }
834 return 0;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800835}
836
837static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
838 struct spi_transfer *xfer)
839{
840 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
Tony Jones49dce682007-10-16 01:27:48 -0700841 dma_unmap_single(master->dev.parent, xfer->tx_dma,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800842 xfer->len, DMA_TO_DEVICE);
843 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
Tony Jones49dce682007-10-16 01:27:48 -0700844 dma_unmap_single(master->dev.parent, xfer->rx_dma,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800845 xfer->len, DMA_FROM_DEVICE);
846}
847
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800848static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
849{
850 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
851}
852
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800853/* Called from IRQ
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800854 *
855 * Must update "current_remaining_bytes" to keep track of data
856 * to transfer.
857 */
858static void
859atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
860{
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800861 u8 *rxp;
Richard Genoudf557c982013-05-02 19:25:11 +0800862 u16 *rxp16;
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800863 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
864
865 if (xfer->rx_buf) {
Richard Genoudf557c982013-05-02 19:25:11 +0800866 if (xfer->bits_per_word > 8) {
867 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
868 *rxp16 = spi_readl(as, RDR);
869 } else {
870 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
871 *rxp = spi_readl(as, RDR);
872 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800873 } else {
874 spi_readl(as, RDR);
875 }
Richard Genoudf557c982013-05-02 19:25:11 +0800876 if (xfer->bits_per_word > 8) {
877 as->current_remaining_bytes -= 2;
878 if (as->current_remaining_bytes < 0)
879 as->current_remaining_bytes = 0;
880 } else {
881 as->current_remaining_bytes--;
882 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800883}
884
885/* Interrupt
886 *
887 * No need for locking in this Interrupt handler: done_status is the
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800888 * only information modified.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800889 */
890static irqreturn_t
891atmel_spi_pio_interrupt(int irq, void *dev_id)
892{
893 struct spi_master *master = dev_id;
894 struct atmel_spi *as = spi_master_get_devdata(master);
895 u32 status, pending, imr;
896 struct spi_transfer *xfer;
897 int ret = IRQ_NONE;
898
899 imr = spi_readl(as, IMR);
900 status = spi_readl(as, SR);
901 pending = status & imr;
902
903 if (pending & SPI_BIT(OVRES)) {
904 ret = IRQ_HANDLED;
905 spi_writel(as, IDR, SPI_BIT(OVRES));
906 dev_warn(master->dev.parent, "overrun\n");
907
908 /*
909 * When we get an overrun, we disregard the current
910 * transfer. Data will not be copied back from any
911 * bounce buffer and msg->actual_len will not be
912 * updated with the last xfer.
913 *
914 * We will also not process any remaning transfers in
915 * the message.
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800916 */
917 as->done_status = -EIO;
918 smp_wmb();
919
920 /* Clear any overrun happening while cleaning up */
921 spi_readl(as, SR);
922
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800923 complete(&as->xfer_completion);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800924
925 } else if (pending & SPI_BIT(RDRF)) {
926 atmel_spi_lock(as);
927
928 if (as->current_remaining_bytes) {
929 ret = IRQ_HANDLED;
930 xfer = as->current_transfer;
931 atmel_spi_pump_pio_data(as, xfer);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800932 if (!as->current_remaining_bytes)
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800933 spi_writel(as, IDR, pending);
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800934
935 complete(&as->xfer_completion);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800936 }
937
938 atmel_spi_unlock(as);
939 } else {
940 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
941 ret = IRQ_HANDLED;
942 spi_writel(as, IDR, pending);
943 }
944
945 return ret;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800946}
947
948static irqreturn_t
Nicolas Ferre1ccc4042013-04-03 13:59:19 +0800949atmel_spi_pdc_interrupt(int irq, void *dev_id)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800950{
951 struct spi_master *master = dev_id;
952 struct atmel_spi *as = spi_master_get_devdata(master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800953 u32 status, pending, imr;
954 int ret = IRQ_NONE;
955
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800956 imr = spi_readl(as, IMR);
957 status = spi_readl(as, SR);
958 pending = status & imr;
959
960 if (pending & SPI_BIT(OVRES)) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800961
962 ret = IRQ_HANDLED;
963
Gerard Kamdc329442008-08-04 13:41:12 -0700964 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800965 | SPI_BIT(OVRES)));
966
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800967 /* Clear any overrun happening while cleaning up */
968 spi_readl(as, SR);
969
Nicolas Ferre823cd042013-03-19 15:45:01 +0800970 as->done_status = -EIO;
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800971
972 complete(&as->xfer_completion);
973
Gerard Kamdc329442008-08-04 13:41:12 -0700974 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800975 ret = IRQ_HANDLED;
976
977 spi_writel(as, IDR, pending);
978
Wenyou Yang8090d6d2014-01-09 13:19:15 +0800979 complete(&as->xfer_completion);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800980 }
981
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800982 return ret;
983}
984
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800985static int atmel_spi_setup(struct spi_device *spi)
986{
987 struct atmel_spi *as;
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800988 struct atmel_spi_device *asd;
Richard Genoudd3b72c72013-11-07 10:34:06 +0100989 u32 csr;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800990 unsigned int bits = spi->bits_per_word;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800991 unsigned int npcs_pin;
992 int ret;
993
994 as = spi_master_get_devdata(spi->master);
995
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800996 if (spi->chip_select > spi->master->num_chipselect) {
997 dev_dbg(&spi->dev,
998 "setup: invalid chipselect %u (%u defined)\n",
999 spi->chip_select, spi->master->num_chipselect);
1000 return -EINVAL;
1001 }
1002
David Brownelldefbd3b2007-07-17 04:04:08 -07001003 /* see notes above re chipselect */
Wenyou Yangd4820b72013-03-19 15:42:15 +08001004 if (!atmel_spi_is_v2(as)
David Brownelldefbd3b2007-07-17 04:04:08 -07001005 && spi->chip_select == 0
1006 && (spi->mode & SPI_CS_HIGH)) {
1007 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1008 return -EINVAL;
1009 }
1010
Richard Genoudd3b72c72013-11-07 10:34:06 +01001011 csr = SPI_BF(BITS, bits - 8);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001012 if (spi->mode & SPI_CPOL)
1013 csr |= SPI_BIT(CPOL);
1014 if (!(spi->mode & SPI_CPHA))
1015 csr |= SPI_BIT(NCPHA);
1016
Haavard Skinnemoen1eed29d2008-02-06 01:38:11 -08001017 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1018 *
1019 * DLYBCT would add delays between words, slowing down transfers.
1020 * It could potentially be useful to cope with DMA bottlenecks, but
1021 * in those cases it's probably best to just use a lower bitrate.
1022 */
1023 csr |= SPI_BF(DLYBS, 0);
1024 csr |= SPI_BF(DLYBCT, 0);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001025
1026 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1027 npcs_pin = (unsigned int)spi->controller_data;
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001028
1029 if (gpio_is_valid(spi->cs_gpio))
1030 npcs_pin = spi->cs_gpio;
1031
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001032 asd = spi->controller_state;
1033 if (!asd) {
1034 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1035 if (!asd)
1036 return -ENOMEM;
1037
Kay Sievers6c7377a2009-03-24 16:38:21 -07001038 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001039 if (ret) {
1040 kfree(asd);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001041 return ret;
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001042 }
1043
1044 asd->npcs_pin = npcs_pin;
1045 spi->controller_state = asd;
David Brownell28735a72007-03-16 13:38:14 -08001046 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001047 }
1048
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001049 asd->csr = csr;
1050
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001051 dev_dbg(&spi->dev,
Richard Genoudd3b72c72013-11-07 10:34:06 +01001052 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1053 bits, spi->mode, spi->chip_select, csr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001054
Wenyou Yangd4820b72013-03-19 15:42:15 +08001055 if (!atmel_spi_is_v2(as))
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001056 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001057
1058 return 0;
1059}
1060
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001061static int atmel_spi_one_transfer(struct spi_master *master,
1062 struct spi_message *msg,
1063 struct spi_transfer *xfer)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001064{
1065 struct atmel_spi *as;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001066 struct spi_device *spi = msg->spi;
Matthias Bruggerb9d228f2010-10-13 17:51:02 +02001067 u8 bits;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001068 u32 len;
Matthias Bruggerb9d228f2010-10-13 17:51:02 +02001069 struct atmel_spi_device *asd;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001070 int timeout;
1071 int ret;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001072
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001073 as = spi_master_get_devdata(master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001074
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001075 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1076 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1077 return -EINVAL;
1078 }
1079
1080 if (xfer->bits_per_word) {
1081 asd = spi->controller_state;
1082 bits = (asd->csr >> 4) & 0xf;
1083 if (bits != xfer->bits_per_word - 8) {
1084 dev_dbg(&spi->dev,
1085 "you can't yet change bits_per_word in transfers\n");
1086 return -ENOPROTOOPT;
1087 }
1088 }
1089
1090 if (xfer->bits_per_word > 8) {
1091 if (xfer->len % 2) {
1092 dev_dbg(&spi->dev,
1093 "buffer len should be 16 bits aligned\n");
1094 return -EINVAL;
1095 }
1096 }
1097
1098 /*
1099 * DMA map early, for performance (empties dcache ASAP) and
1100 * better fault reporting.
1101 */
1102 if ((!msg->is_dma_mapped)
1103 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1104 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1105 return -ENOMEM;
1106 }
1107
1108 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1109
1110 as->done_status = 0;
1111 as->current_transfer = xfer;
1112 as->current_remaining_bytes = xfer->len;
1113 while (as->current_remaining_bytes) {
1114 reinit_completion(&as->xfer_completion);
1115
1116 if (as->use_pdc) {
1117 atmel_spi_pdc_next_xfer(master, msg, xfer);
1118 } else if (atmel_spi_use_dma(as, xfer)) {
1119 len = as->current_remaining_bytes;
1120 ret = atmel_spi_next_xfer_dma_submit(master,
1121 xfer, &len);
1122 if (ret) {
1123 dev_err(&spi->dev,
1124 "unable to use DMA, fallback to PIO\n");
1125 atmel_spi_next_xfer_pio(master, xfer);
1126 } else {
1127 as->current_remaining_bytes -= len;
1128 }
1129 } else {
1130 atmel_spi_next_xfer_pio(master, xfer);
1131 }
1132
1133 ret = wait_for_completion_timeout(&as->xfer_completion,
1134 SPI_DMA_TIMEOUT);
1135 if (WARN_ON(ret == 0)) {
1136 dev_err(&spi->dev,
1137 "spi trasfer timeout, err %d\n", ret);
1138 as->done_status = -EIO;
1139 } else {
1140 ret = 0;
1141 }
1142
1143 if (as->done_status)
1144 break;
1145 }
1146
1147 if (as->done_status) {
1148 if (as->use_pdc) {
1149 dev_warn(master->dev.parent,
1150 "overrun (%u/%u remaining)\n",
1151 spi_readl(as, TCR), spi_readl(as, RCR));
1152
1153 /*
1154 * Clean up DMA registers and make sure the data
1155 * registers are empty.
1156 */
1157 spi_writel(as, RNCR, 0);
1158 spi_writel(as, TNCR, 0);
1159 spi_writel(as, RCR, 0);
1160 spi_writel(as, TCR, 0);
1161 for (timeout = 1000; timeout; timeout--)
1162 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1163 break;
1164 if (!timeout)
1165 dev_warn(master->dev.parent,
1166 "timeout waiting for TXEMPTY");
1167 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1168 spi_readl(as, RDR);
1169
1170 /* Clear any overrun happening while cleaning up */
1171 spi_readl(as, SR);
1172
1173 } else if (atmel_spi_use_dma(as, xfer)) {
1174 atmel_spi_stop_dma(as);
1175 }
1176
1177 if (!msg->is_dma_mapped
1178 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1179 atmel_spi_dma_unmap_xfer(master, xfer);
1180
1181 return 0;
1182
1183 } else {
1184 /* only update length if no error */
1185 msg->actual_length += xfer->len;
1186 }
1187
1188 if (!msg->is_dma_mapped
1189 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1190 atmel_spi_dma_unmap_xfer(master, xfer);
1191
1192 if (xfer->delay_usecs)
1193 udelay(xfer->delay_usecs);
1194
1195 if (xfer->cs_change) {
1196 if (list_is_last(&xfer->transfer_list,
1197 &msg->transfers)) {
1198 as->keep_cs = true;
1199 } else {
1200 as->cs_active = !as->cs_active;
1201 if (as->cs_active)
1202 cs_activate(as, msg->spi);
1203 else
1204 cs_deactivate(as, msg->spi);
1205 }
1206 }
1207
1208 return 0;
1209}
1210
1211static int atmel_spi_transfer_one_message(struct spi_master *master,
1212 struct spi_message *msg)
1213{
1214 struct atmel_spi *as;
1215 struct spi_transfer *xfer;
1216 struct spi_device *spi = msg->spi;
1217 int ret = 0;
1218
1219 as = spi_master_get_devdata(master);
1220
1221 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1222 msg, dev_name(&spi->dev));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001223
Stanislaw Gruszka5b96f172009-01-15 13:50:44 -08001224 if (unlikely(list_empty(&msg->transfers)))
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001225 return -EINVAL;
1226
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001227 atmel_spi_lock(as);
1228 cs_activate(as, spi);
1229
1230 as->cs_active = true;
1231 as->keep_cs = false;
1232
1233 msg->status = 0;
1234 msg->actual_length = 0;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001235
1236 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001237 ret = atmel_spi_one_transfer(master, msg, xfer);
1238 if (ret)
1239 goto msg_done;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001240 }
1241
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001242 if (as->use_pdc)
1243 atmel_spi_disable_pdc_transfer(as);
1244
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001245 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001246 dev_dbg(&spi->dev,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001247 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
1248 xfer, xfer->len,
1249 xfer->tx_buf, xfer->tx_dma,
1250 xfer->rx_buf, xfer->rx_dma);
1251 }
1252
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001253msg_done:
1254 if (!as->keep_cs)
1255 cs_deactivate(as, msg->spi);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001256
Nicolas Ferre8aad7922013-04-03 13:58:36 +08001257 atmel_spi_unlock(as);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001258
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001259 msg->status = as->done_status;
1260 spi_finalize_current_message(spi->master);
1261
1262 return ret;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001263}
1264
David Brownellbb2d1c32007-02-20 13:58:19 -08001265static void atmel_spi_cleanup(struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001266{
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001267 struct atmel_spi_device *asd = spi->controller_state;
David Brownelldefbd3b2007-07-17 04:04:08 -07001268 unsigned gpio = (unsigned) spi->controller_data;
David Brownelldefbd3b2007-07-17 04:04:08 -07001269
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001270 if (!asd)
David Brownelldefbd3b2007-07-17 04:04:08 -07001271 return;
1272
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001273 spi->controller_state = NULL;
David Brownelldefbd3b2007-07-17 04:04:08 -07001274 gpio_free(gpio);
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -08001275 kfree(asd);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001276}
1277
Wenyou Yangd4820b72013-03-19 15:42:15 +08001278static inline unsigned int atmel_get_version(struct atmel_spi *as)
1279{
1280 return spi_readl(as, VERSION) & 0x00000fff;
1281}
1282
1283static void atmel_get_caps(struct atmel_spi *as)
1284{
1285 unsigned int version;
1286
1287 version = atmel_get_version(as);
1288 dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1289
1290 as->caps.is_spi2 = version > 0x121;
1291 as->caps.has_wdrbt = version >= 0x210;
1292 as->caps.has_dma_support = version >= 0x212;
1293}
1294
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001295/*-------------------------------------------------------------------------*/
1296
Grant Likelyfd4a3192012-12-07 16:57:14 +00001297static int atmel_spi_probe(struct platform_device *pdev)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001298{
1299 struct resource *regs;
1300 int irq;
1301 struct clk *clk;
1302 int ret;
1303 struct spi_master *master;
1304 struct atmel_spi *as;
1305
1306 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1307 if (!regs)
1308 return -ENXIO;
1309
1310 irq = platform_get_irq(pdev, 0);
1311 if (irq < 0)
1312 return irq;
1313
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001314 clk = devm_clk_get(&pdev->dev, "spi_clk");
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001315 if (IS_ERR(clk))
1316 return PTR_ERR(clk);
1317
1318 /* setup spi core then atmel-specific driver state */
1319 ret = -ENOMEM;
Sachin Kamata536d762013-09-10 17:06:27 +05301320 master = spi_alloc_master(&pdev->dev, sizeof(*as));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001321 if (!master)
1322 goto out_free;
1323
David Brownelle7db06b2009-06-17 16:26:04 -07001324 /* the spi->mode bits understood by this driver: */
1325 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
Stephen Warren24778be2013-05-21 20:36:35 -06001326 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001327 master->dev.of_node = pdev->dev.of_node;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001328 master->bus_num = pdev->id;
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001329 master->num_chipselect = master->dev.of_node ? 0 : 4;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001330 master->setup = atmel_spi_setup;
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001331 master->transfer_one_message = atmel_spi_transfer_one_message;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001332 master->cleanup = atmel_spi_cleanup;
1333 platform_set_drvdata(pdev, master);
1334
1335 as = spi_master_get_devdata(master);
1336
David Brownell8da08592007-07-17 04:04:07 -07001337 /*
1338 * Scratch buffer is used for throwaway rx and tx data.
1339 * It's coherent to minimize dcache pollution.
1340 */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001341 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1342 &as->buffer_dma, GFP_KERNEL);
1343 if (!as->buffer)
1344 goto out_free;
1345
1346 spin_lock_init(&as->lock);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001347
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001348 as->pdev = pdev;
Mark Brown31407472013-10-16 13:22:35 +01001349 as->regs = devm_ioremap_resource(&pdev->dev, regs);
Wei Yongjun543c9542013-10-21 11:12:02 +08001350 if (IS_ERR(as->regs)) {
1351 ret = PTR_ERR(as->regs);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001352 goto out_free_buffer;
Wei Yongjun543c9542013-10-21 11:12:02 +08001353 }
Nicolas Ferredfab30e2013-04-03 13:57:42 +08001354 as->phybase = regs->start;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001355 as->irq = irq;
1356 as->clk = clk;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001357
Wenyou Yang8090d6d2014-01-09 13:19:15 +08001358 init_completion(&as->xfer_completion);
1359
Wenyou Yangd4820b72013-03-19 15:42:15 +08001360 atmel_get_caps(as);
1361
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001362 as->use_dma = false;
1363 as->use_pdc = false;
1364 if (as->caps.has_dma_support) {
1365 if (atmel_spi_configure_dma(as) == 0)
1366 as->use_dma = true;
1367 } else {
1368 as->use_pdc = true;
1369 }
1370
1371 if (as->caps.has_dma_support && !as->use_dma)
1372 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1373
1374 if (as->use_pdc) {
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001375 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1376 0, dev_name(&pdev->dev), master);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001377 } else {
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001378 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1379 0, dev_name(&pdev->dev), master);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001380 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001381 if (ret)
1382 goto out_unmap_regs;
1383
1384 /* Initialize the hardware */
Boris BREZILLONdfec4a62013-07-16 17:16:22 +02001385 ret = clk_prepare_enable(clk);
1386 if (ret)
Sachin Kamatde8cc232013-09-10 17:06:26 +05301387 goto out_free_irq;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001388 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -08001389 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Wenyou Yangd4820b72013-03-19 15:42:15 +08001390 if (as->caps.has_wdrbt) {
1391 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1392 | SPI_BIT(MSTR));
1393 } else {
1394 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1395 }
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001396
1397 if (as->use_pdc)
1398 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001399 spi_writel(as, CR, SPI_BIT(SPIEN));
1400
1401 /* go! */
1402 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1403 (unsigned long)regs->start, irq);
1404
Jingoo Han9f87d6f2013-12-04 14:07:51 +09001405 ret = devm_spi_register_master(&pdev->dev, master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001406 if (ret)
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001407 goto out_free_dma;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001408
1409 return 0;
1410
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001411out_free_dma:
1412 if (as->use_dma)
1413 atmel_spi_release_dma(as);
1414
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001415 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -08001416 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Boris BREZILLONdfec4a62013-07-16 17:16:22 +02001417 clk_disable_unprepare(clk);
Sachin Kamatde8cc232013-09-10 17:06:26 +05301418out_free_irq:
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001419out_unmap_regs:
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001420out_free_buffer:
1421 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1422 as->buffer_dma);
1423out_free:
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001424 spi_master_put(master);
1425 return ret;
1426}
1427
Grant Likelyfd4a3192012-12-07 16:57:14 +00001428static int atmel_spi_remove(struct platform_device *pdev)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001429{
1430 struct spi_master *master = platform_get_drvdata(pdev);
1431 struct atmel_spi *as = spi_master_get_devdata(master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001432
1433 /* reset the hardware and block queue progress */
1434 spin_lock_irq(&as->lock);
Nicolas Ferre1ccc4042013-04-03 13:59:19 +08001435 if (as->use_dma) {
1436 atmel_spi_stop_dma(as);
1437 atmel_spi_release_dma(as);
1438 }
1439
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001440 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -08001441 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001442 spi_readl(as, SR);
1443 spin_unlock_irq(&as->lock);
1444
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001445 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1446 as->buffer_dma);
1447
Boris BREZILLONdfec4a62013-07-16 17:16:22 +02001448 clk_disable_unprepare(as->clk);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001449
1450 return 0;
1451}
1452
Jingoo Hanec60dd32013-09-09 17:54:12 +09001453#ifdef CONFIG_PM_SLEEP
1454static int atmel_spi_suspend(struct device *dev)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001455{
Jingoo Hanec60dd32013-09-09 17:54:12 +09001456 struct spi_master *master = dev_get_drvdata(dev);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001457 struct atmel_spi *as = spi_master_get_devdata(master);
1458
Boris BREZILLONdfec4a62013-07-16 17:16:22 +02001459 clk_disable_unprepare(as->clk);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001460 return 0;
1461}
1462
Jingoo Hanec60dd32013-09-09 17:54:12 +09001463static int atmel_spi_resume(struct device *dev)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001464{
Jingoo Hanec60dd32013-09-09 17:54:12 +09001465 struct spi_master *master = dev_get_drvdata(dev);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001466 struct atmel_spi *as = spi_master_get_devdata(master);
1467
Jingoo Hanec60dd32013-09-09 17:54:12 +09001468 clk_prepare_enable(as->clk);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001469 return 0;
1470}
1471
Jingoo Hanec60dd32013-09-09 17:54:12 +09001472static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume);
1473
1474#define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001475#else
Jingoo Hanec60dd32013-09-09 17:54:12 +09001476#define ATMEL_SPI_PM_OPS NULL
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001477#endif
1478
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001479#if defined(CONFIG_OF)
1480static const struct of_device_id atmel_spi_dt_ids[] = {
1481 { .compatible = "atmel,at91rm9200-spi" },
1482 { /* sentinel */ }
1483};
1484
1485MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1486#endif
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001487
1488static struct platform_driver atmel_spi_driver = {
1489 .driver = {
1490 .name = "atmel_spi",
1491 .owner = THIS_MODULE,
Jingoo Hanec60dd32013-09-09 17:54:12 +09001492 .pm = ATMEL_SPI_PM_OPS,
Jean-Christophe PLAGNIOL-VILLARD850a5b62012-11-23 13:44:39 +01001493 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001494 },
Jean-Christophe PLAGNIOL-VILLARD1cb201a2011-11-04 01:20:21 +08001495 .probe = atmel_spi_probe,
Grant Likely2deff8d2013-02-05 13:27:35 +00001496 .remove = atmel_spi_remove,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001497};
Grant Likely940ab882011-10-05 11:29:49 -06001498module_platform_driver(atmel_spi_driver);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001499
1500MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
Jean Delvaree05503e2011-05-18 16:49:24 +02001501MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001502MODULE_LICENSE("GPL");
Kay Sievers7e38c3c2008-04-10 21:29:20 -07001503MODULE_ALIAS("platform:atmel_spi");