blob: 8644d5372e7ff328f5f0fe10079648088d4634bd [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2** System Bus Adapter (SBA) I/O MMU manager
3**
4** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6** (c) Copyright 2000-2004 Hewlett-Packard Company
7**
8** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
9**
10** This program is free software; you can redistribute it and/or modify
11** it under the terms of the GNU General Public License as published by
12** the Free Software Foundation; either version 2 of the License, or
13** (at your option) any later version.
14**
15**
16** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17** J5000/J7000/N-class/L-class machines and their successors.
18**
19** FIXME: add DMA hint support programming in both sba and lba modules.
20*/
21
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/types.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/slab.h>
26#include <linux/init.h>
27
28#include <linux/mm.h>
29#include <linux/string.h>
30#include <linux/pci.h>
FUJITA Tomonorib61e8f42007-10-23 09:30:28 +020031#include <linux/scatterlist.h>
FUJITA Tomonori46663442008-03-04 14:29:28 -080032#include <linux/iommu-helper.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
34#include <asm/byteorder.h>
35#include <asm/io.h>
36#include <asm/dma.h> /* for DMA_CHUNK_SIZE */
37
38#include <asm/hardware.h> /* for register_parisc_driver() stuff */
39
40#include <linux/proc_fs.h>
Kyle McMartin7ec14e42006-02-06 10:10:15 -070041#include <linux/seq_file.h>
Paul Gortmaker6caddf02011-08-11 13:24:07 -040042#include <linux/module.h>
Kyle McMartin7ec14e42006-02-06 10:10:15 -070043
Kyle McMartin1790cf92006-08-24 21:32:49 -040044#include <asm/ropes.h>
Kyle McMartin6f034952006-08-13 22:18:57 -040045#include <asm/mckinley.h> /* for proc_mckinley_root */
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <asm/runway.h> /* for proc_runway_root */
47#include <asm/pdc.h> /* for PDC_MODEL_* */
48#include <asm/pdcpat.h> /* for is_pdc_pat() */
49#include <asm/parisc-device.h>
50
Linus Torvalds1da177e2005-04-16 15:20:36 -070051#define MODULE_NAME "SBA"
52
Linus Torvalds1da177e2005-04-16 15:20:36 -070053/*
54** The number of debug flags is a clue - this code is fragile.
55** Don't even think about messing with it unless you have
56** plenty of 710's to sacrifice to the computer gods. :^)
57*/
58#undef DEBUG_SBA_INIT
59#undef DEBUG_SBA_RUN
60#undef DEBUG_SBA_RUN_SG
61#undef DEBUG_SBA_RESOURCE
62#undef ASSERT_PDIR_SANITY
63#undef DEBUG_LARGE_SG_ENTRIES
64#undef DEBUG_DMB_TRAP
65
66#ifdef DEBUG_SBA_INIT
67#define DBG_INIT(x...) printk(x)
68#else
69#define DBG_INIT(x...)
70#endif
71
72#ifdef DEBUG_SBA_RUN
73#define DBG_RUN(x...) printk(x)
74#else
75#define DBG_RUN(x...)
76#endif
77
78#ifdef DEBUG_SBA_RUN_SG
79#define DBG_RUN_SG(x...) printk(x)
80#else
81#define DBG_RUN_SG(x...)
82#endif
83
84
85#ifdef DEBUG_SBA_RESOURCE
86#define DBG_RES(x...) printk(x)
87#else
88#define DBG_RES(x...)
89#endif
90
Linus Torvalds1da177e2005-04-16 15:20:36 -070091#define SBA_INLINE __inline__
92
Linus Torvalds1da177e2005-04-16 15:20:36 -070093#define DEFAULT_DMA_HINT_REG 0
94
Kyle McMartin08a64362006-08-24 21:33:40 -040095struct sba_device *sba_list;
96EXPORT_SYMBOL_GPL(sba_list);
Linus Torvalds1da177e2005-04-16 15:20:36 -070097
98static unsigned long ioc_needs_fdc = 0;
99
100/* global count of IOMMUs in the system */
101static unsigned int global_ioc_cnt = 0;
102
103/* PA8700 (Piranha 2.2) bug workaround */
104static unsigned long piranha_bad_128k = 0;
105
106/* Looks nice and keeps the compiler happy */
107#define SBA_DEV(d) ((struct sba_device *) (d))
108
Kyle McMartin08a64362006-08-24 21:33:40 -0400109#ifdef CONFIG_AGP_PARISC
110#define SBA_AGP_SUPPORT
111#endif /*CONFIG_AGP_PARISC*/
112
Grant Grundler64908ad2005-10-21 22:37:20 -0400113#ifdef SBA_AGP_SUPPORT
Kyle McMartin08a64362006-08-24 21:33:40 -0400114static int sba_reserve_agpgart = 1;
Randy Dunlap29a1e1d2007-02-05 16:33:59 -0800115module_param(sba_reserve_agpgart, int, 0444);
Kyle McMartin08a64362006-08-24 21:33:40 -0400116MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117#endif
118
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119
120/************************************
121** SBA register read and write support
122**
123** BE WARNED: register writes are posted.
124** (ie follow writes which must reach HW with a read)
125**
126** Superdome (in particular, REO) allows only 64-bit CSR accesses.
127*/
Grant Grundler40d78de2006-05-11 00:31:31 -0600128#define READ_REG32(addr) readl(addr)
129#define READ_REG64(addr) readq(addr)
130#define WRITE_REG32(val, addr) writel((val), (addr))
131#define WRITE_REG64(val, addr) writeq((val), (addr))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
Grant Grundler64908ad2005-10-21 22:37:20 -0400133#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134#define READ_REG(addr) READ_REG64(addr)
135#define WRITE_REG(value, addr) WRITE_REG64(value, addr)
136#else
137#define READ_REG(addr) READ_REG32(addr)
138#define WRITE_REG(value, addr) WRITE_REG32(value, addr)
139#endif
140
141#ifdef DEBUG_SBA_INIT
142
Grant Grundler64908ad2005-10-21 22:37:20 -0400143/* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144
145/**
146 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
147 * @hpa: base address of the sba
148 *
149 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
150 * IO Adapter (aka Bus Converter).
151 */
152static void
153sba_dump_ranges(void __iomem *hpa)
154{
155 DBG_INIT("SBA at 0x%p\n", hpa);
156 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
157 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
158 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
159 DBG_INIT("\n");
160 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
161 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
162 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
163}
164
165/**
166 * sba_dump_tlb - debugging only - print IOMMU operating parameters
167 * @hpa: base address of the IOMMU
168 *
169 * Print the size/location of the IO MMU PDIR.
170 */
171static void sba_dump_tlb(void __iomem *hpa)
172{
173 DBG_INIT("IO TLB at 0x%p\n", hpa);
174 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
175 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
176 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
177 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
178 DBG_INIT("\n");
179}
180#else
181#define sba_dump_ranges(x)
182#define sba_dump_tlb(x)
Grant Grundler64908ad2005-10-21 22:37:20 -0400183#endif /* DEBUG_SBA_INIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184
185
186#ifdef ASSERT_PDIR_SANITY
187
188/**
189 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
190 * @ioc: IO MMU structure which owns the pdir we are interested in.
191 * @msg: text to print ont the output line.
192 * @pide: pdir index.
193 *
194 * Print one entry of the IO MMU PDIR in human readable form.
195 */
196static void
197sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
198{
199 /* start printing from lowest pde in rval */
200 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
201 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
202 uint rcnt;
203
204 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
205 msg,
206 rptr, pide & (BITS_PER_LONG - 1), *rptr);
207
208 rcnt = 0;
209 while (rcnt < BITS_PER_LONG) {
210 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
211 (rcnt == (pide & (BITS_PER_LONG - 1)))
212 ? " -->" : " ",
213 rcnt, ptr, *ptr );
214 rcnt++;
215 ptr++;
216 }
217 printk(KERN_DEBUG "%s", msg);
218}
219
220
221/**
222 * sba_check_pdir - debugging only - consistency checker
223 * @ioc: IO MMU structure which owns the pdir we are interested in.
224 * @msg: text to print ont the output line.
225 *
226 * Verify the resource map and pdir state is consistent
227 */
228static int
229sba_check_pdir(struct ioc *ioc, char *msg)
230{
231 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
232 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
233 u64 *pptr = ioc->pdir_base; /* pdir ptr */
234 uint pide = 0;
235
236 while (rptr < rptr_end) {
237 u32 rval = *rptr;
238 int rcnt = 32; /* number of bits we might check */
239
240 while (rcnt) {
241 /* Get last byte and highest bit from that */
242 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
243 if ((rval ^ pde) & 0x80000000)
244 {
245 /*
246 ** BUMMER! -- res_map != pdir --
247 ** Dump rval and matching pdir entries
248 */
249 sba_dump_pdir_entry(ioc, msg, pide);
250 return(1);
251 }
252 rcnt--;
253 rval <<= 1; /* try the next bit */
254 pptr++;
255 pide++;
256 }
257 rptr++; /* look at next word of res_map */
258 }
259 /* It'd be nice if we always got here :^) */
260 return 0;
261}
262
263
264/**
265 * sba_dump_sg - debugging only - print Scatter-Gather list
266 * @ioc: IO MMU structure which owns the pdir we are interested in.
267 * @startsg: head of the SG list
268 * @nents: number of entries in SG list
269 *
270 * print the SG list so we can verify it's correct by hand.
271 */
272static void
273sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
274{
275 while (nents-- > 0) {
276 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
277 nents,
278 (unsigned long) sg_dma_address(startsg),
279 sg_dma_len(startsg),
280 sg_virt_addr(startsg), startsg->length);
281 startsg++;
282 }
283}
284
285#endif /* ASSERT_PDIR_SANITY */
286
287
288
289
290/**************************************************************
291*
292* I/O Pdir Resource Management
293*
294* Bits set in the resource map are in use.
295* Each bit can represent a number of pages.
296* LSbs represent lower addresses (IOVA's).
297*
298***************************************************************/
299#define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
300
301/* Convert from IOVP to IOVA and vice versa. */
302
303#ifdef ZX1_SUPPORT
304/* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
305#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
306#define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
307#else
308/* only support Astro and ancestors. Saves a few cycles in key places */
309#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
310#define SBA_IOVP(ioc,iova) (iova)
311#endif
312
313#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
314
315#define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
316#define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
317
FUJITA Tomonori56ee0cf2008-03-10 20:43:24 +0900318static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr,
319 unsigned int bitshiftcnt)
FUJITA Tomonori46663442008-03-04 14:29:28 -0800320{
321 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3)
322 + bitshiftcnt;
323}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324
325/**
326 * sba_search_bitmap - find free space in IO PDIR resource bitmap
327 * @ioc: IO MMU structure which owns the pdir we are interested in.
328 * @bits_wanted: number of entries we need.
329 *
330 * Find consecutive free bits in resource bitmap.
331 * Each bit represents one entry in the IO Pdir.
332 * Cool perf optimization: search for log2(size) bits at a time.
333 */
334static SBA_INLINE unsigned long
FUJITA Tomonori46663442008-03-04 14:29:28 -0800335sba_search_bitmap(struct ioc *ioc, struct device *dev,
336 unsigned long bits_wanted)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337{
338 unsigned long *res_ptr = ioc->res_hint;
339 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
FUJITA Tomonori46663442008-03-04 14:29:28 -0800340 unsigned long pide = ~0UL, tpide;
341 unsigned long boundary_size;
342 unsigned long shift;
343 int ret;
344
FUJITA Tomonori4a0d3f32008-03-05 17:09:30 +0900345 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
346 1ULL << IOVP_SHIFT) >> IOVP_SHIFT;
FUJITA Tomonori46663442008-03-04 14:29:28 -0800347
348#if defined(ZX1_SUPPORT)
349 BUG_ON(ioc->ibase & ~IOVP_MASK);
350 shift = ioc->ibase >> IOVP_SHIFT;
351#else
352 shift = 0;
353#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354
355 if (bits_wanted > (BITS_PER_LONG/2)) {
356 /* Search word at a time - no mask needed */
357 for(; res_ptr < res_end; ++res_ptr) {
FUJITA Tomonori46663442008-03-04 14:29:28 -0800358 tpide = ptr_to_pide(ioc, res_ptr, 0);
359 ret = iommu_is_span_boundary(tpide, bits_wanted,
360 shift,
361 boundary_size);
362 if ((*res_ptr == 0) && !ret) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363 *res_ptr = RESMAP_MASK(bits_wanted);
FUJITA Tomonori46663442008-03-04 14:29:28 -0800364 pide = tpide;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365 break;
366 }
367 }
368 /* point to the next word on next pass */
369 res_ptr++;
370 ioc->res_bitshift = 0;
371 } else {
372 /*
373 ** Search the resource bit map on well-aligned values.
374 ** "o" is the alignment.
375 ** We need the alignment to invalidate I/O TLB using
376 ** SBA HW features in the unmap path.
377 */
378 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
Milind Arun Choudhary3cb1d952007-03-06 02:44:13 -0800379 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380 unsigned long mask;
381
382 if (bitshiftcnt >= BITS_PER_LONG) {
383 bitshiftcnt = 0;
384 res_ptr++;
385 }
386 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
387
Harvey Harrisona8043ec2008-05-14 16:21:56 -0700388 DBG_RES("%s() o %ld %p", __func__, o, res_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389 while(res_ptr < res_end)
390 {
391 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
392 WARN_ON(mask == 0);
FUJITA Tomonori46663442008-03-04 14:29:28 -0800393 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt);
394 ret = iommu_is_span_boundary(tpide, bits_wanted,
395 shift,
396 boundary_size);
397 if ((((*res_ptr) & mask) == 0) && !ret) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398 *res_ptr |= mask; /* mark resources busy! */
FUJITA Tomonori46663442008-03-04 14:29:28 -0800399 pide = tpide;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400 break;
401 }
402 mask >>= o;
403 bitshiftcnt += o;
404 if (mask == 0) {
405 mask = RESMAP_MASK(bits_wanted);
406 bitshiftcnt=0;
407 res_ptr++;
408 }
409 }
410 /* look in the same word on the next pass */
411 ioc->res_bitshift = bitshiftcnt + bits_wanted;
412 }
413
414 /* wrapped ? */
415 if (res_end <= res_ptr) {
416 ioc->res_hint = (unsigned long *) ioc->res_map;
417 ioc->res_bitshift = 0;
418 } else {
419 ioc->res_hint = res_ptr;
420 }
421 return (pide);
422}
423
424
425/**
426 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
427 * @ioc: IO MMU structure which owns the pdir we are interested in.
428 * @size: number of bytes to create a mapping for
429 *
430 * Given a size, find consecutive unmarked and then mark those bits in the
431 * resource bit map.
432 */
433static int
FUJITA Tomonori7c8cda62008-03-04 14:29:28 -0800434sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435{
436 unsigned int pages_needed = size >> IOVP_SHIFT;
437#ifdef SBA_COLLECT_STATS
438 unsigned long cr_start = mfctl(16);
439#endif
440 unsigned long pide;
441
FUJITA Tomonori46663442008-03-04 14:29:28 -0800442 pide = sba_search_bitmap(ioc, dev, pages_needed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443 if (pide >= (ioc->res_size << 3)) {
FUJITA Tomonori46663442008-03-04 14:29:28 -0800444 pide = sba_search_bitmap(ioc, dev, pages_needed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 if (pide >= (ioc->res_size << 3))
446 panic("%s: I/O MMU @ %p is out of mapping resources\n",
447 __FILE__, ioc->ioc_hpa);
448 }
449
450#ifdef ASSERT_PDIR_SANITY
451 /* verify the first enable bit is clear */
452 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
453 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
454 }
455#endif
456
457 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -0700458 __func__, size, pages_needed, pide,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
460 ioc->res_bitshift );
461
462#ifdef SBA_COLLECT_STATS
463 {
464 unsigned long cr_end = mfctl(16);
465 unsigned long tmp = cr_end - cr_start;
466 /* check for roll over */
467 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
468 }
469 ioc->avg_search[ioc->avg_idx++] = cr_start;
470 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
471
472 ioc->used_pages += pages_needed;
473#endif
474
475 return (pide);
476}
477
478
479/**
480 * sba_free_range - unmark bits in IO PDIR resource bitmap
481 * @ioc: IO MMU structure which owns the pdir we are interested in.
482 * @iova: IO virtual address which was previously allocated.
483 * @size: number of bytes to create a mapping for
484 *
485 * clear bits in the ioc's resource map
486 */
487static SBA_INLINE void
488sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
489{
490 unsigned long iovp = SBA_IOVP(ioc, iova);
491 unsigned int pide = PDIR_INDEX(iovp);
492 unsigned int ridx = pide >> 3; /* convert bit to byte address */
493 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
494
495 int bits_not_wanted = size >> IOVP_SHIFT;
496
497 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
498 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
499
500 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -0700501 __func__, (uint) iova, size,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502 bits_not_wanted, m, pide, res_ptr, *res_ptr);
503
504#ifdef SBA_COLLECT_STATS
505 ioc->used_pages -= bits_not_wanted;
506#endif
507
508 *res_ptr &= ~m;
509}
510
511
512/**************************************************************
513*
514* "Dynamic DMA Mapping" support (aka "Coherent I/O")
515*
516***************************************************************/
517
Grant Grundler64908ad2005-10-21 22:37:20 -0400518#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519#define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
520#endif
521
522typedef unsigned long space_t;
523#define KERNEL_SPACE 0
524
525/**
526 * sba_io_pdir_entry - fill in one IO PDIR entry
527 * @pdir_ptr: pointer to IO PDIR entry
528 * @sid: process Space ID - currently only support KERNEL_SPACE
529 * @vba: Virtual CPU address of buffer to map
530 * @hint: DMA hint set to use for this mapping
531 *
532 * SBA Mapping Routine
533 *
534 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
535 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
536 * pdir_ptr (arg0).
537 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
538 * for Astro/Ike looks like:
539 *
540 *
541 * 0 19 51 55 63
542 * +-+---------------------+----------------------------------+----+--------+
543 * |V| U | PPN[43:12] | U | VI |
544 * +-+---------------------+----------------------------------+----+--------+
545 *
546 * Pluto is basically identical, supports fewer physical address bits:
547 *
548 * 0 23 51 55 63
549 * +-+------------------------+-------------------------------+----+--------+
550 * |V| U | PPN[39:12] | U | VI |
551 * +-+------------------------+-------------------------------+----+--------+
552 *
553 * V == Valid Bit (Most Significant Bit is bit 0)
554 * U == Unused
555 * PPN == Physical Page Number
556 * VI == Virtual Index (aka Coherent Index)
557 *
558 * LPA instruction output is put into PPN field.
559 * LCI (Load Coherence Index) instruction provides the "VI" bits.
560 *
561 * We pre-swap the bytes since PCX-W is Big Endian and the
562 * IOMMU uses little endian for the pdir.
563 */
564
Adrian Bunkdf8e5bc2008-12-02 03:28:16 +0000565static void SBA_INLINE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700566sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
567 unsigned long hint)
568{
569 u64 pa; /* physical address */
570 register unsigned ci; /* coherent index */
571
572 pa = virt_to_phys(vba);
573 pa &= IOVP_MASK;
574
575 mtsp(sid,1);
576 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
577 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
578
Kyle McMartin983daee2006-08-25 12:28:24 -0400579 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
581
582 /*
583 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
584 * (bit #61, big endian), we have to flush and sync every time
585 * IO-PDIR is changed in Ike/Astro.
586 */
Grant Grundler64908ad2005-10-21 22:37:20 -0400587 if (ioc_needs_fdc)
588 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700589}
590
591
592/**
593 * sba_mark_invalid - invalidate one or more IO PDIR entries
594 * @ioc: IO MMU structure which owns the pdir we are interested in.
595 * @iova: IO Virtual Address mapped earlier
596 * @byte_cnt: number of bytes this mapping covers.
597 *
598 * Marking the IO PDIR entry(ies) as Invalid and invalidate
599 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
600 * is to purge stale entries in the IO TLB when unmapping entries.
601 *
602 * The PCOM register supports purging of multiple pages, with a minium
603 * of 1 page and a maximum of 2GB. Hardware requires the address be
604 * aligned to the size of the range being purged. The size of the range
605 * must be a power of 2. The "Cool perf optimization" in the
606 * allocation routine helps keep that true.
607 */
608static SBA_INLINE void
609sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
610{
611 u32 iovp = (u32) SBA_IOVP(ioc,iova);
Grant Grundler64908ad2005-10-21 22:37:20 -0400612 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700613
614#ifdef ASSERT_PDIR_SANITY
Grant Grundler64908ad2005-10-21 22:37:20 -0400615 /* Assert first pdir entry is set.
616 **
617 ** Even though this is a big-endian machine, the entries
618 ** in the iopdir are little endian. That's why we look at
619 ** the byte at +7 instead of at +0.
620 */
621 if (0x80 != (((u8 *) pdir_ptr)[7])) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
623 }
624#endif
625
Grant Grundler64908ad2005-10-21 22:37:20 -0400626 if (byte_cnt > IOVP_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 {
Grant Grundler64908ad2005-10-21 22:37:20 -0400628#if 0
629 unsigned long entries_per_cacheline = ioc_needs_fdc ?
630 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
631 - (unsigned long) pdir_ptr;
632 : 262144;
633#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634
Grant Grundler64908ad2005-10-21 22:37:20 -0400635 /* set "size" field for PCOM */
636 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638 do {
639 /* clear I/O Pdir entry "valid" bit first */
Grant Grundler64908ad2005-10-21 22:37:20 -0400640 ((u8 *) pdir_ptr)[7] = 0;
641 if (ioc_needs_fdc) {
642 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
643#if 0
644 entries_per_cacheline = L1_CACHE_SHIFT - 3;
645#endif
646 }
647 pdir_ptr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648 byte_cnt -= IOVP_SIZE;
Grant Grundler64908ad2005-10-21 22:37:20 -0400649 } while (byte_cnt > IOVP_SIZE);
650 } else
651 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
652
653 /*
654 ** clear I/O PDIR entry "valid" bit.
655 ** We have to R/M/W the cacheline regardless how much of the
656 ** pdir entry that we clobber.
657 ** The rest of the entry would be useful for debugging if we
658 ** could dump core on HPMC.
659 */
660 ((u8 *) pdir_ptr)[7] = 0;
661 if (ioc_needs_fdc)
662 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663
664 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
665}
666
667/**
668 * sba_dma_supported - PCI driver can query DMA support
669 * @dev: instance of PCI owned by the driver that's asking
670 * @mask: number of address bits this PCI device can handle
671 *
Paul Bolle395cf962011-08-15 02:02:26 +0200672 * See Documentation/DMA-API-HOWTO.txt
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673 */
674static int sba_dma_supported( struct device *dev, u64 mask)
675{
676 struct ioc *ioc;
Grant Grundler64908ad2005-10-21 22:37:20 -0400677
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678 if (dev == NULL) {
679 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
680 BUG();
681 return(0);
682 }
683
Paul Bolle395cf962011-08-15 02:02:26 +0200684 /* Documentation/DMA-API-HOWTO.txt tells drivers to try 64-bit
Randy Dunlap5872fb92009-01-29 16:28:02 -0800685 * first, then fall back to 32-bit if that fails.
Grant Grundler64908ad2005-10-21 22:37:20 -0400686 * We are just "encouraging" 32-bit DMA masks here since we can
687 * never allow IOMMU bypass unless we add special support for ZX1.
688 */
689 if (mask > ~0U)
690 return 0;
691
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692 ioc = GET_IOC(dev);
693
Grant Grundler64908ad2005-10-21 22:37:20 -0400694 /*
695 * check if mask is >= than the current max IO Virt Address
696 * The max IO Virt address will *always* < 30 bits.
697 */
698 return((int)(mask >= (ioc->ibase - 1 +
699 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700}
701
702
703/**
704 * sba_map_single - map one buffer and return IOVA for DMA
705 * @dev: instance of PCI owned by the driver that's asking.
706 * @addr: driver buffer to map.
707 * @size: number of bytes to map in driver buffer.
708 * @direction: R/W or both.
709 *
Paul Bolle395cf962011-08-15 02:02:26 +0200710 * See Documentation/DMA-API-HOWTO.txt
Linus Torvalds1da177e2005-04-16 15:20:36 -0700711 */
712static dma_addr_t
713sba_map_single(struct device *dev, void *addr, size_t size,
714 enum dma_data_direction direction)
715{
716 struct ioc *ioc;
717 unsigned long flags;
718 dma_addr_t iovp;
719 dma_addr_t offset;
720 u64 *pdir_start;
721 int pide;
722
723 ioc = GET_IOC(dev);
724
725 /* save offset bits */
726 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
727
728 /* round up to nearest IOVP_SIZE */
729 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
730
731 spin_lock_irqsave(&ioc->res_lock, flags);
732#ifdef ASSERT_PDIR_SANITY
733 sba_check_pdir(ioc,"Check before sba_map_single()");
734#endif
735
736#ifdef SBA_COLLECT_STATS
737 ioc->msingle_calls++;
738 ioc->msingle_pages += size >> IOVP_SHIFT;
739#endif
FUJITA Tomonori7c8cda62008-03-04 14:29:28 -0800740 pide = sba_alloc_range(ioc, dev, size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741 iovp = (dma_addr_t) pide << IOVP_SHIFT;
742
743 DBG_RUN("%s() 0x%p -> 0x%lx\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -0700744 __func__, addr, (long) iovp | offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745
746 pdir_start = &(ioc->pdir_base[pide]);
747
748 while (size > 0) {
749 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
750
751 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
752 pdir_start,
753 (u8) (((u8 *) pdir_start)[7]),
754 (u8) (((u8 *) pdir_start)[6]),
755 (u8) (((u8 *) pdir_start)[5]),
756 (u8) (((u8 *) pdir_start)[4]),
757 (u8) (((u8 *) pdir_start)[3]),
758 (u8) (((u8 *) pdir_start)[2]),
759 (u8) (((u8 *) pdir_start)[1]),
760 (u8) (((u8 *) pdir_start)[0])
761 );
762
763 addr += IOVP_SIZE;
764 size -= IOVP_SIZE;
765 pdir_start++;
766 }
Grant Grundler64908ad2005-10-21 22:37:20 -0400767
768 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
769 if (ioc_needs_fdc)
770 asm volatile("sync" : : );
771
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772#ifdef ASSERT_PDIR_SANITY
773 sba_check_pdir(ioc,"Check after sba_map_single()");
774#endif
775 spin_unlock_irqrestore(&ioc->res_lock, flags);
Grant Grundler64908ad2005-10-21 22:37:20 -0400776
777 /* form complete address */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
779}
780
781
782/**
783 * sba_unmap_single - unmap one IOVA and free resources
784 * @dev: instance of PCI owned by the driver that's asking.
785 * @iova: IOVA of driver buffer previously mapped.
786 * @size: number of bytes mapped in driver buffer.
787 * @direction: R/W or both.
788 *
Paul Bolle395cf962011-08-15 02:02:26 +0200789 * See Documentation/DMA-API-HOWTO.txt
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 */
791static void
792sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
793 enum dma_data_direction direction)
794{
795 struct ioc *ioc;
796#if DELAYED_RESOURCE_CNT > 0
797 struct sba_dma_pair *d;
798#endif
799 unsigned long flags;
800 dma_addr_t offset;
801
Harvey Harrisona8043ec2008-05-14 16:21:56 -0700802 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700803
804 ioc = GET_IOC(dev);
805 offset = iova & ~IOVP_MASK;
806 iova ^= offset; /* clear offset bits */
807 size += offset;
Milind Arun Choudhary3cb1d952007-03-06 02:44:13 -0800808 size = ALIGN(size, IOVP_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809
810 spin_lock_irqsave(&ioc->res_lock, flags);
811
812#ifdef SBA_COLLECT_STATS
813 ioc->usingle_calls++;
814 ioc->usingle_pages += size >> IOVP_SHIFT;
815#endif
816
817 sba_mark_invalid(ioc, iova, size);
818
819#if DELAYED_RESOURCE_CNT > 0
820 /* Delaying when we re-use a IO Pdir entry reduces the number
821 * of MMIO reads needed to flush writes to the PCOM register.
822 */
823 d = &(ioc->saved[ioc->saved_cnt]);
824 d->iova = iova;
825 d->size = size;
826 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
827 int cnt = ioc->saved_cnt;
828 while (cnt--) {
829 sba_free_range(ioc, d->iova, d->size);
830 d--;
831 }
832 ioc->saved_cnt = 0;
Grant Grundler64908ad2005-10-21 22:37:20 -0400833
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
835 }
836#else /* DELAYED_RESOURCE_CNT == 0 */
837 sba_free_range(ioc, iova, size);
Grant Grundler64908ad2005-10-21 22:37:20 -0400838
839 /* If fdc's were issued, force fdc's to be visible now */
840 if (ioc_needs_fdc)
841 asm volatile("sync" : : );
842
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
844#endif /* DELAYED_RESOURCE_CNT == 0 */
Grant Grundler64908ad2005-10-21 22:37:20 -0400845
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846 spin_unlock_irqrestore(&ioc->res_lock, flags);
847
848 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
849 ** For Astro based systems this isn't a big deal WRT performance.
850 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
851 ** we don't need the syncdma. The issue here is I/O MMU cachelines
852 ** are *not* coherent in all cases. May be hwrev dependent.
853 ** Need to investigate more.
854 asm volatile("syncdma");
855 */
856}
857
858
859/**
860 * sba_alloc_consistent - allocate/map shared mem for DMA
861 * @hwdev: instance of PCI owned by the driver that's asking.
862 * @size: number of bytes mapped in driver buffer.
863 * @dma_handle: IOVA of new buffer.
864 *
Paul Bolle395cf962011-08-15 02:02:26 +0200865 * See Documentation/DMA-API-HOWTO.txt
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866 */
867static void *sba_alloc_consistent(struct device *hwdev, size_t size,
Al Viro5c1fb412005-10-21 03:21:28 -0400868 dma_addr_t *dma_handle, gfp_t gfp)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869{
870 void *ret;
871
872 if (!hwdev) {
873 /* only support PCI */
874 *dma_handle = 0;
Matthew Wilcoxc2c47982006-10-26 10:06:07 -0600875 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 }
877
878 ret = (void *) __get_free_pages(gfp, get_order(size));
879
880 if (ret) {
881 memset(ret, 0, size);
882 *dma_handle = sba_map_single(hwdev, ret, size, 0);
883 }
884
885 return ret;
886}
887
888
889/**
890 * sba_free_consistent - free/unmap shared mem for DMA
891 * @hwdev: instance of PCI owned by the driver that's asking.
892 * @size: number of bytes mapped in driver buffer.
893 * @vaddr: virtual address IOVA of "consistent" buffer.
894 * @dma_handler: IO virtual address of "consistent" buffer.
895 *
Paul Bolle395cf962011-08-15 02:02:26 +0200896 * See Documentation/DMA-API-HOWTO.txt
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897 */
898static void
899sba_free_consistent(struct device *hwdev, size_t size, void *vaddr,
900 dma_addr_t dma_handle)
901{
902 sba_unmap_single(hwdev, dma_handle, size, 0);
903 free_pages((unsigned long) vaddr, get_order(size));
904}
905
906
907/*
908** Since 0 is a valid pdir_base index value, can't use that
909** to determine if a value is valid or not. Use a flag to indicate
910** the SG list entry contains a valid pdir index.
911*/
912#define PIDE_FLAG 0x80000000UL
913
914#ifdef SBA_COLLECT_STATS
915#define IOMMU_MAP_STATS
916#endif
917#include "iommu-helpers.h"
918
919#ifdef DEBUG_LARGE_SG_ENTRIES
920int dump_run_sg = 0;
921#endif
922
923
924/**
925 * sba_map_sg - map Scatter/Gather list
926 * @dev: instance of PCI owned by the driver that's asking.
927 * @sglist: array of buffer/length pairs
928 * @nents: number of entries in list
929 * @direction: R/W or both.
930 *
Paul Bolle395cf962011-08-15 02:02:26 +0200931 * See Documentation/DMA-API-HOWTO.txt
Linus Torvalds1da177e2005-04-16 15:20:36 -0700932 */
933static int
934sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
935 enum dma_data_direction direction)
936{
937 struct ioc *ioc;
938 int coalesced, filled = 0;
939 unsigned long flags;
940
Harvey Harrisona8043ec2008-05-14 16:21:56 -0700941 DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942
943 ioc = GET_IOC(dev);
944
945 /* Fast path single entry scatterlists. */
946 if (nents == 1) {
947 sg_dma_address(sglist) = sba_map_single(dev,
948 (void *)sg_virt_addr(sglist),
949 sglist->length, direction);
950 sg_dma_len(sglist) = sglist->length;
951 return 1;
952 }
953
954 spin_lock_irqsave(&ioc->res_lock, flags);
955
956#ifdef ASSERT_PDIR_SANITY
957 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
958 {
959 sba_dump_sg(ioc, sglist, nents);
960 panic("Check before sba_map_sg()");
961 }
962#endif
963
964#ifdef SBA_COLLECT_STATS
965 ioc->msg_calls++;
966#endif
967
968 /*
969 ** First coalesce the chunks and allocate I/O pdir space
970 **
971 ** If this is one DMA stream, we can properly map using the
972 ** correct virtual address associated with each DMA page.
973 ** w/o this association, we wouldn't have coherent DMA!
974 ** Access to the virtual address is what forces a two pass algorithm.
975 */
FUJITA Tomonorid1b51632008-02-04 22:28:03 -0800976 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700977
978 /*
979 ** Program the I/O Pdir
980 **
981 ** map the virtual addresses to the I/O Pdir
982 ** o dma_address will contain the pdir index
983 ** o dma_len will contain the number of bytes to map
984 ** o address contains the virtual address.
985 */
986 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
987
Grant Grundler64908ad2005-10-21 22:37:20 -0400988 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
989 if (ioc_needs_fdc)
990 asm volatile("sync" : : );
991
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992#ifdef ASSERT_PDIR_SANITY
993 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
994 {
995 sba_dump_sg(ioc, sglist, nents);
996 panic("Check after sba_map_sg()\n");
997 }
998#endif
999
1000 spin_unlock_irqrestore(&ioc->res_lock, flags);
1001
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001002 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003
1004 return filled;
1005}
1006
1007
1008/**
1009 * sba_unmap_sg - unmap Scatter/Gather list
1010 * @dev: instance of PCI owned by the driver that's asking.
1011 * @sglist: array of buffer/length pairs
1012 * @nents: number of entries in list
1013 * @direction: R/W or both.
1014 *
Paul Bolle395cf962011-08-15 02:02:26 +02001015 * See Documentation/DMA-API-HOWTO.txt
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016 */
1017static void
1018sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1019 enum dma_data_direction direction)
1020{
1021 struct ioc *ioc;
1022#ifdef ASSERT_PDIR_SANITY
1023 unsigned long flags;
1024#endif
1025
1026 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001027 __func__, nents, sg_virt_addr(sglist), sglist->length);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028
1029 ioc = GET_IOC(dev);
1030
1031#ifdef SBA_COLLECT_STATS
1032 ioc->usg_calls++;
1033#endif
1034
1035#ifdef ASSERT_PDIR_SANITY
1036 spin_lock_irqsave(&ioc->res_lock, flags);
1037 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1038 spin_unlock_irqrestore(&ioc->res_lock, flags);
1039#endif
1040
1041 while (sg_dma_len(sglist) && nents--) {
1042
1043 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction);
1044#ifdef SBA_COLLECT_STATS
1045 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1046 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1047#endif
1048 ++sglist;
1049 }
1050
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001051 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052
1053#ifdef ASSERT_PDIR_SANITY
1054 spin_lock_irqsave(&ioc->res_lock, flags);
1055 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1056 spin_unlock_irqrestore(&ioc->res_lock, flags);
1057#endif
1058
1059}
1060
1061static struct hppa_dma_ops sba_ops = {
1062 .dma_supported = sba_dma_supported,
1063 .alloc_consistent = sba_alloc_consistent,
1064 .alloc_noncoherent = sba_alloc_consistent,
1065 .free_consistent = sba_free_consistent,
1066 .map_single = sba_map_single,
1067 .unmap_single = sba_unmap_single,
1068 .map_sg = sba_map_sg,
1069 .unmap_sg = sba_unmap_sg,
1070 .dma_sync_single_for_cpu = NULL,
1071 .dma_sync_single_for_device = NULL,
1072 .dma_sync_sg_for_cpu = NULL,
1073 .dma_sync_sg_for_device = NULL,
1074};
1075
1076
1077/**************************************************************************
1078**
1079** SBA PAT PDC support
1080**
1081** o call pdc_pat_cell_module()
1082** o store ranges in PCI "resource" structures
1083**
1084**************************************************************************/
1085
1086static void
1087sba_get_pat_resources(struct sba_device *sba_dev)
1088{
1089#if 0
1090/*
1091** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1092** PAT PDC to program the SBA/LBA directed range registers...this
1093** burden may fall on the LBA code since it directly supports the
1094** PCI subsystem. It's not clear yet. - ggg
1095*/
1096PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1097 FIXME : ???
1098PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1099 Tells where the dvi bits are located in the address.
1100PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1101 FIXME : ???
1102#endif
1103}
1104
1105
1106/**************************************************************
1107*
1108* Initialization and claim
1109*
1110***************************************************************/
1111#define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1112#define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1113static void *
1114sba_alloc_pdir(unsigned int pdir_size)
1115{
1116 unsigned long pdir_base;
1117 unsigned long pdir_order = get_order(pdir_size);
1118
1119 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
Grant Grundler64908ad2005-10-21 22:37:20 -04001120 if (NULL == (void *) pdir_base) {
1121 panic("%s() could not allocate I/O Page Table\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001122 __func__);
Grant Grundler64908ad2005-10-21 22:37:20 -04001123 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124
1125 /* If this is not PA8700 (PCX-W2)
1126 ** OR newer than ver 2.2
1127 ** OR in a system that doesn't need VINDEX bits from SBA,
1128 **
1129 ** then we aren't exposed to the HW bug.
1130 */
1131 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1132 || (boot_cpu_data.pdc.versions > 0x202)
1133 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1134 return (void *) pdir_base;
1135
1136 /*
1137 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1138 *
1139 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1140 * Ike/Astro can cause silent data corruption. This is only
1141 * a problem if the I/O PDIR is located in memory such that
1142 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1143 *
1144 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1145 * right physical address, we can either avoid (IOPDIR <= 1MB)
1146 * or minimize (2MB IO Pdir) the problem if we restrict the
1147 * IO Pdir to a maximum size of 2MB-128K (1902K).
1148 *
1149 * Because we always allocate 2^N sized IO pdirs, either of the
1150 * "bad" regions will be the last 128K if at all. That's easy
1151 * to test for.
1152 *
1153 */
1154 if (pdir_order <= (19-12)) {
1155 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1156 /* allocate a new one on 512k alignment */
1157 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1158 /* release original */
1159 free_pages(pdir_base, pdir_order);
1160
1161 pdir_base = new_pdir;
1162
1163 /* release excess */
1164 while (pdir_order < (19-12)) {
1165 new_pdir += pdir_size;
1166 free_pages(new_pdir, pdir_order);
1167 pdir_order +=1;
1168 pdir_size <<=1;
1169 }
1170 }
1171 } else {
1172 /*
1173 ** 1MB or 2MB Pdir
1174 ** Needs to be aligned on an "odd" 1MB boundary.
1175 */
1176 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1177
1178 /* release original */
1179 free_pages( pdir_base, pdir_order);
1180
1181 /* release first 1MB */
1182 free_pages(new_pdir, 20-12);
1183
1184 pdir_base = new_pdir + 1024*1024;
1185
1186 if (pdir_order > (20-12)) {
1187 /*
1188 ** 2MB Pdir.
1189 **
1190 ** Flag tells init_bitmap() to mark bad 128k as used
1191 ** and to reduce the size by 128k.
1192 */
1193 piranha_bad_128k = 1;
1194
1195 new_pdir += 3*1024*1024;
1196 /* release last 1MB */
1197 free_pages(new_pdir, 20-12);
1198
1199 /* release unusable 128KB */
1200 free_pages(new_pdir - 128*1024 , 17-12);
1201
1202 pdir_size -= 128*1024;
1203 }
1204 }
1205
1206 memset((void *) pdir_base, 0, pdir_size);
1207 return (void *) pdir_base;
1208}
1209
James Bottomleybfe4f4f2009-01-09 18:57:06 -06001210struct ibase_data_struct {
1211 struct ioc *ioc;
1212 int ioc_num;
1213};
1214
1215static int setup_ibase_imask_callback(struct device *dev, void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216{
James Bottomleybfe4f4f2009-01-09 18:57:06 -06001217 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
1218 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1219 struct parisc_device *lba = to_parisc_device(dev);
1220 struct ibase_data_struct *ibd = data;
1221 int rope_num = (lba->hpa.start >> 13) & 0xf;
1222 if (rope_num >> 3 == ibd->ioc_num)
1223 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask);
1224 return 0;
Matthew Wilcox56583742005-10-21 22:33:38 -04001225}
1226
1227/* setup Mercury or Elroy IBASE/IMASK registers. */
1228static void
1229setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1230{
James Bottomleybfe4f4f2009-01-09 18:57:06 -06001231 struct ibase_data_struct ibase_data = {
1232 .ioc = ioc,
1233 .ioc_num = ioc_num,
1234 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07001235
James Bottomleybfe4f4f2009-01-09 18:57:06 -06001236 device_for_each_child(&sba->dev, &ibase_data,
1237 setup_ibase_imask_callback);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001238}
1239
James Bottomleybfe4f4f2009-01-09 18:57:06 -06001240#ifdef SBA_AGP_SUPPORT
1241static int
1242sba_ioc_find_quicksilver(struct device *dev, void *data)
1243{
1244 int *agp_found = data;
1245 struct parisc_device *lba = to_parisc_device(dev);
1246
1247 if (IS_QUICKSILVER(lba))
1248 *agp_found = 1;
1249 return 0;
1250}
1251#endif
1252
Linus Torvalds1da177e2005-04-16 15:20:36 -07001253static void
1254sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1255{
1256 u32 iova_space_mask;
1257 u32 iova_space_size;
1258 int iov_order, tcnfg;
Grant Grundler64908ad2005-10-21 22:37:20 -04001259#ifdef SBA_AGP_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001260 int agp_found = 0;
1261#endif
1262 /*
1263 ** Firmware programs the base and size of a "safe IOVA space"
1264 ** (one that doesn't overlap memory or LMMIO space) in the
1265 ** IBASE and IMASK registers.
1266 */
1267 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1268 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1269
1270 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1271 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1272 iova_space_size /= 2;
1273 }
1274
1275 /*
1276 ** iov_order is always based on a 1GB IOVA space since we want to
1277 ** turn on the other half for AGP GART.
1278 */
1279 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1280 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1281
Grant Grundler40d78de2006-05-11 00:31:31 -06001282 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001283 __func__, ioc->ioc_hpa, iova_space_size >> 20,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001284 iov_order + PAGE_SHIFT);
1285
1286 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1287 get_order(ioc->pdir_size));
1288 if (!ioc->pdir_base)
1289 panic("Couldn't allocate I/O Page Table\n");
1290
1291 memset(ioc->pdir_base, 0, ioc->pdir_size);
1292
1293 DBG_INIT("%s() pdir %p size %x\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001294 __func__, ioc->pdir_base, ioc->pdir_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001295
Grant Grundler64908ad2005-10-21 22:37:20 -04001296#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001297 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1298 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1299
1300 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1301 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1302#endif
1303
1304 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1305 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1306
1307 /* build IMASK for IOC and Elroy */
1308 iova_space_mask = 0xffffffff;
1309 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1310 ioc->imask = iova_space_mask;
1311#ifdef ZX1_SUPPORT
1312 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1313#endif
1314 sba_dump_tlb(ioc->ioc_hpa);
1315
1316 setup_ibase_imask(sba, ioc, ioc_num);
1317
1318 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1319
Grant Grundler64908ad2005-10-21 22:37:20 -04001320#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001321 /*
1322 ** Setting the upper bits makes checking for bypass addresses
1323 ** a little faster later on.
1324 */
1325 ioc->imask |= 0xFFFFFFFF00000000UL;
1326#endif
1327
1328 /* Set I/O PDIR Page size to system page size */
1329 switch (PAGE_SHIFT) {
1330 case 12: tcnfg = 0; break; /* 4K */
1331 case 13: tcnfg = 1; break; /* 8K */
1332 case 14: tcnfg = 2; break; /* 16K */
1333 case 16: tcnfg = 3; break; /* 64K */
1334 default:
1335 panic(__FILE__ "Unsupported system page size %d",
1336 1 << PAGE_SHIFT);
1337 break;
1338 }
1339 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1340
1341 /*
1342 ** Program the IOC's ibase and enable IOVA translation
1343 ** Bit zero == enable bit.
1344 */
1345 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1346
1347 /*
1348 ** Clear I/O TLB of any possible entries.
1349 ** (Yes. This is a bit paranoid...but so what)
1350 */
1351 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1352
Grant Grundler64908ad2005-10-21 22:37:20 -04001353#ifdef SBA_AGP_SUPPORT
Kyle McMartin08a64362006-08-24 21:33:40 -04001354
Linus Torvalds1da177e2005-04-16 15:20:36 -07001355 /*
1356 ** If an AGP device is present, only use half of the IOV space
1357 ** for PCI DMA. Unfortunately we can't know ahead of time
1358 ** whether GART support will actually be used, for now we
1359 ** can just key on any AGP device found in the system.
1360 ** We program the next pdir index after we stop w/ a key for
1361 ** the GART code to handshake on.
1362 */
James Bottomleybfe4f4f2009-01-09 18:57:06 -06001363 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001364
Kyle McMartin08a64362006-08-24 21:33:40 -04001365 if (agp_found && sba_reserve_agpgart) {
1366 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001367 __func__, (iova_space_size/2) >> 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368 ioc->pdir_size /= 2;
Kyle McMartin08a64362006-08-24 21:33:40 -04001369 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370 }
Kyle McMartin08a64362006-08-24 21:33:40 -04001371#endif /*SBA_AGP_SUPPORT*/
Linus Torvalds1da177e2005-04-16 15:20:36 -07001372}
1373
1374static void
1375sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1376{
1377 u32 iova_space_size, iova_space_mask;
1378 unsigned int pdir_size, iov_order;
1379
1380 /*
1381 ** Determine IOVA Space size from memory size.
1382 **
1383 ** Ideally, PCI drivers would register the maximum number
1384 ** of DMA they can have outstanding for each device they
1385 ** own. Next best thing would be to guess how much DMA
1386 ** can be outstanding based on PCI Class/sub-class. Both
1387 ** methods still require some "extra" to support PCI
1388 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1389 **
1390 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1391 ** for DMA hints - ergo only 30 bits max.
1392 */
1393
Jan Beulich44813742009-09-21 17:03:05 -07001394 iova_space_size = (u32) (totalram_pages/global_ioc_cnt);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001395
1396 /* limit IOVA space size to 1MB-1GB */
1397 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1398 iova_space_size = 1 << (20 - PAGE_SHIFT);
1399 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001400 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1401 iova_space_size = 1 << (30 - PAGE_SHIFT);
1402 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001403
1404 /*
1405 ** iova space must be log2() in size.
1406 ** thus, pdir/res_map will also be log2().
1407 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1408 */
1409 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1410
1411 /* iova_space_size is now bytes, not pages */
1412 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1413
1414 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1415
1416 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001417 __func__,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001418 ioc->ioc_hpa,
Jan Beulich44813742009-09-21 17:03:05 -07001419 (unsigned long) totalram_pages >> (20 - PAGE_SHIFT),
Linus Torvalds1da177e2005-04-16 15:20:36 -07001420 iova_space_size>>20,
1421 iov_order + PAGE_SHIFT);
1422
1423 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1424
1425 DBG_INIT("%s() pdir %p size %x\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001426 __func__, ioc->pdir_base, pdir_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427
Grant Grundler64908ad2005-10-21 22:37:20 -04001428#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429 /* FIXME : DMA HINTs not used */
1430 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1431 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1432
1433 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1434 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1435#endif
1436
1437 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1438
1439 /* build IMASK for IOC and Elroy */
1440 iova_space_mask = 0xffffffff;
1441 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1442
1443 /*
1444 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1445 ** ibase=0, imask=0xFE000000, size=0x2000000.
1446 */
1447 ioc->ibase = 0;
1448 ioc->imask = iova_space_mask; /* save it */
1449#ifdef ZX1_SUPPORT
1450 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1451#endif
1452
1453 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001454 __func__, ioc->ibase, ioc->imask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001455
1456 /*
1457 ** FIXME: Hint registers are programmed with default hint
1458 ** values during boot, so hints should be sane even if we
1459 ** can't reprogram them the way drivers want.
1460 */
1461
1462 setup_ibase_imask(sba, ioc, ioc_num);
1463
1464 /*
1465 ** Program the IOC's ibase and enable IOVA translation
1466 */
1467 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1468 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1469
1470 /* Set I/O PDIR Page size to 4K */
1471 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
1472
1473 /*
1474 ** Clear I/O TLB of any possible entries.
1475 ** (Yes. This is a bit paranoid...but so what)
1476 */
1477 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1478
1479 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1480
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001481 DBG_INIT("%s() DONE\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482}
1483
1484
1485
1486/**************************************************************************
1487**
1488** SBA initialization code (HW and SW)
1489**
1490** o identify SBA chip itself
1491** o initialize SBA chip modes (HardFail)
1492** o initialize SBA chip modes (HardFail)
1493** o FIXME: initialize DMA hints for reasonable defaults
1494**
1495**************************************************************************/
1496
Helge Deller5076c152006-03-27 12:52:15 -07001497static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498{
Helge Deller5076c152006-03-27 12:52:15 -07001499 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001500}
1501
1502static void sba_hw_init(struct sba_device *sba_dev)
1503{
1504 int i;
1505 int num_ioc;
1506 u64 ioc_ctl;
1507
1508 if (!is_pdc_pat()) {
1509 /* Shutdown the USB controller on Astro-based workstations.
1510 ** Once we reprogram the IOMMU, the next DMA performed by
1511 ** USB will HPMC the box. USB is only enabled if a
1512 ** keyboard is present and found.
1513 **
1514 ** With serial console, j6k v5.0 firmware says:
1515 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1516 **
1517 ** FIXME: Using GFX+USB console at power up but direct
1518 ** linux to serial console is still broken.
1519 ** USB could generate DMA so we must reset USB.
1520 ** The proper sequence would be:
1521 ** o block console output
1522 ** o reset USB device
1523 ** o reprogram serial port
1524 ** o unblock console output
1525 */
1526 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1527 pdc_io_reset_devices();
1528 }
1529
1530 }
1531
1532
1533#if 0
1534printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1535 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1536
1537 /*
1538 ** Need to deal with DMA from LAN.
1539 ** Maybe use page zero boot device as a handle to talk
1540 ** to PDC about which device to shutdown.
1541 **
1542 ** Netbooting, j6k v5.0 firmware says:
1543 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1544 ** ARGH! invalid class.
1545 */
1546 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1547 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1548 pdc_io_reset();
1549 }
1550#endif
1551
Kyle McMartin1b240f42006-08-24 21:30:19 -04001552 if (!IS_PLUTO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1554 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001555 __func__, sba_dev->sba_hpa, ioc_ctl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1557 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1558 /* j6700 v1.6 firmware sets 0x294f */
1559 /* A500 firmware sets 0x4d */
1560
1561 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1562
1563#ifdef DEBUG_SBA_INIT
1564 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1565 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1566#endif
1567 } /* if !PLUTO */
1568
Kyle McMartin1b240f42006-08-24 21:30:19 -04001569 if (IS_ASTRO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001570 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001571 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1572 num_ioc = 1;
1573
1574 sba_dev->chip_resv.name = "Astro Intr Ack";
1575 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1576 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1577 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
Eric Sesterhennb7494552006-03-24 18:52:10 +01001578 BUG_ON(err < 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001579
Kyle McMartin1b240f42006-08-24 21:30:19 -04001580 } else if (IS_PLUTO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001581 int err;
1582
Linus Torvalds1da177e2005-04-16 15:20:36 -07001583 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1584 num_ioc = 1;
1585
1586 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1587 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1588 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1589 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1590 WARN_ON(err < 0);
1591
1592 sba_dev->iommu_resv.name = "IOVA Space";
1593 sba_dev->iommu_resv.start = 0x40000000UL;
1594 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1595 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1596 WARN_ON(err < 0);
1597 } else {
Matthew Wilcox78860892006-09-12 05:19:15 -06001598 /* IKE, REO */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1600 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1601 num_ioc = 2;
1602
1603 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1604 }
Matthew Wilcox78860892006-09-12 05:19:15 -06001605 /* XXX: What about Reo Grande? */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001606
1607 sba_dev->num_ioc = num_ioc;
1608 for (i = 0; i < num_ioc; i++) {
Grant Grundler40d78de2006-05-11 00:31:31 -06001609 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
Grant Grundlerb312c332006-03-30 07:13:21 +00001610 unsigned int j;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611
Grant Grundlerb312c332006-03-30 07:13:21 +00001612 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
1613
1614 /*
1615 * Clear ROPE(N)_CONFIG AO bit.
1616 * Disables "NT Ordering" (~= !"Relaxed Ordering")
1617 * Overrides bit 1 in DMA Hint Sets.
1618 * Improves netperf UDP_STREAM by ~10% for bcm5701.
1619 */
Kyle McMartin1b240f42006-08-24 21:30:19 -04001620 if (IS_PLUTO(sba_dev->dev)) {
Grant Grundler40d78de2006-05-11 00:31:31 -06001621 void __iomem *rope_cfg;
1622 unsigned long cfg_val;
Grant Grundlerb312c332006-03-30 07:13:21 +00001623
1624 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
1625 cfg_val = READ_REG(rope_cfg);
1626 cfg_val &= ~IOC_ROPE_AO;
1627 WRITE_REG(cfg_val, rope_cfg);
1628 }
1629
1630 /*
1631 ** Make sure the box crashes on rope errors.
1632 */
1633 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
1634 }
1635
1636 /* flush out the last writes */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001637 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1638
1639 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1640 i,
1641 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1642 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1643 );
1644 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1645 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1646 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1647 );
1648
Kyle McMartin1b240f42006-08-24 21:30:19 -04001649 if (IS_PLUTO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001650 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1651 } else {
1652 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1653 }
1654 }
1655}
1656
1657static void
1658sba_common_init(struct sba_device *sba_dev)
1659{
1660 int i;
1661
1662 /* add this one to the head of the list (order doesn't matter)
1663 ** This will be useful for debugging - especially if we get coredumps
1664 */
1665 sba_dev->next = sba_list;
1666 sba_list = sba_dev;
1667
1668 for(i=0; i< sba_dev->num_ioc; i++) {
1669 int res_size;
1670#ifdef DEBUG_DMB_TRAP
1671 extern void iterate_pages(unsigned long , unsigned long ,
1672 void (*)(pte_t * , unsigned long),
1673 unsigned long );
1674 void set_data_memory_break(pte_t * , unsigned long);
1675#endif
1676 /* resource map size dictated by pdir_size */
1677 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1678
1679 /* Second part of PIRANHA BUG */
1680 if (piranha_bad_128k) {
1681 res_size -= (128*1024)/sizeof(u64);
1682 }
1683
1684 res_size >>= 3; /* convert bit count to byte count */
1685 DBG_INIT("%s() res_size 0x%x\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001686 __func__, res_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001687
1688 sba_dev->ioc[i].res_size = res_size;
1689 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1690
1691#ifdef DEBUG_DMB_TRAP
1692 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1693 set_data_memory_break, 0);
1694#endif
1695
1696 if (NULL == sba_dev->ioc[i].res_map)
1697 {
1698 panic("%s:%s() could not allocate resource map\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001699 __FILE__, __func__ );
Linus Torvalds1da177e2005-04-16 15:20:36 -07001700 }
1701
1702 memset(sba_dev->ioc[i].res_map, 0, res_size);
1703 /* next available IOVP - circular search */
1704 sba_dev->ioc[i].res_hint = (unsigned long *)
1705 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1706
1707#ifdef ASSERT_PDIR_SANITY
1708 /* Mark first bit busy - ie no IOVA 0 */
1709 sba_dev->ioc[i].res_map[0] = 0x80;
1710 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1711#endif
1712
1713 /* Third (and last) part of PIRANHA BUG */
1714 if (piranha_bad_128k) {
1715 /* region from +1408K to +1536 is un-usable. */
1716
1717 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1718 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1719 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1720 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1721
1722 /* mark that part of the io pdir busy */
1723 while (p_start < p_end)
1724 *p_start++ = -1;
1725
1726 }
1727
1728#ifdef DEBUG_DMB_TRAP
1729 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1730 set_data_memory_break, 0);
1731 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1732 set_data_memory_break, 0);
1733#endif
1734
1735 DBG_INIT("%s() %d res_map %x %p\n",
Harvey Harrisona8043ec2008-05-14 16:21:56 -07001736 __func__, i, res_size, sba_dev->ioc[i].res_map);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001737 }
1738
1739 spin_lock_init(&sba_dev->sba_lock);
1740 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1741
1742#ifdef DEBUG_SBA_INIT
1743 /*
1744 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1745 * (bit #61, big endian), we have to flush and sync every time
1746 * IO-PDIR is changed in Ike/Astro.
1747 */
Kyle McMartin692086e2006-05-30 17:50:29 +00001748 if (ioc_needs_fdc) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001749 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1750 } else {
1751 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1752 }
1753#endif
1754}
1755
1756#ifdef CONFIG_PROC_FS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001757static int sba_proc_info(struct seq_file *m, void *p)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001758{
1759 struct sba_device *sba_dev = sba_list;
1760 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1761 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001762#ifdef SBA_COLLECT_STATS
1763 unsigned long avg = 0, min, max;
1764#endif
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001765 int i, len = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001767 len += seq_printf(m, "%s rev %d.%d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001768 sba_dev->name,
1769 (sba_dev->hw_rev & 0x7) + 1,
1770 (sba_dev->hw_rev & 0x18) >> 3
1771 );
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001772 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001773 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1774 total_pages);
1775
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001776 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1777 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001778
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001779 len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001780 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1781 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1782 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)
1783 );
1784
1785 for (i=0; i<4; i++)
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001786 len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001787 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1788 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1789 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)
1790 );
1791
1792#ifdef SBA_COLLECT_STATS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001793 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001794 total_pages - ioc->used_pages, ioc->used_pages,
1795 (int) (ioc->used_pages * 100 / total_pages));
1796
1797 min = max = ioc->avg_search[0];
1798 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1799 avg += ioc->avg_search[i];
1800 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1801 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1802 }
1803 avg /= SBA_SEARCH_SAMPLE;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001804 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1805 min, avg, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001806
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001807 len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1808 ioc->msingle_calls, ioc->msingle_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001809 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1810
1811 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1812 min = ioc->usingle_calls;
1813 max = ioc->usingle_pages - ioc->usg_pages;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001814 len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1815 min, max, (int) ((max * 1000)/min));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001816
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001817 len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1818 ioc->msg_calls, ioc->msg_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001819 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
1820
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001821 len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1822 ioc->usg_calls, ioc->usg_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001823 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
1824#endif
1825
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001826 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001827}
1828
Linus Torvalds1da177e2005-04-16 15:20:36 -07001829static int
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001830sba_proc_open(struct inode *i, struct file *f)
1831{
1832 return single_open(f, &sba_proc_info, NULL);
1833}
1834
Arjan van de Vend54b1fd2007-02-12 00:55:34 -08001835static const struct file_operations sba_proc_fops = {
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001836 .owner = THIS_MODULE,
1837 .open = sba_proc_open,
1838 .read = seq_read,
1839 .llseek = seq_lseek,
1840 .release = single_release,
1841};
1842
1843static int
1844sba_proc_bitmap_info(struct seq_file *m, void *p)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001845{
1846 struct sba_device *sba_dev = sba_list;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001847 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001848 unsigned int *res_ptr = (unsigned int *)ioc->res_map;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001849 int i, len = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001850
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001851 for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001852 if ((i & 7) == 0)
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001853 len += seq_printf(m, "\n ");
1854 len += seq_printf(m, " %08x", *res_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001855 }
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001856 len += seq_printf(m, "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001857
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001858 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001859}
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001860
1861static int
1862sba_proc_bitmap_open(struct inode *i, struct file *f)
1863{
1864 return single_open(f, &sba_proc_bitmap_info, NULL);
1865}
1866
Arjan van de Vend54b1fd2007-02-12 00:55:34 -08001867static const struct file_operations sba_proc_bitmap_fops = {
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001868 .owner = THIS_MODULE,
1869 .open = sba_proc_bitmap_open,
1870 .read = seq_read,
1871 .llseek = seq_lseek,
1872 .release = single_release,
1873};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001874#endif /* CONFIG_PROC_FS */
1875
1876static struct parisc_device_id sba_tbl[] = {
1877 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1878 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1879 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1880 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1881 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
1882 { 0, }
1883};
1884
Adrian Bunkdf8e5bc2008-12-02 03:28:16 +00001885static int sba_driver_callback(struct parisc_device *);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886
1887static struct parisc_driver sba_driver = {
1888 .name = MODULE_NAME,
1889 .id_table = sba_tbl,
1890 .probe = sba_driver_callback,
1891};
1892
1893/*
1894** Determine if sba should claim this chip (return 0) or not (return 1).
1895** If so, initialize the chip and tell other partners in crime they
1896** have work to do.
1897*/
Adrian Bunkdf8e5bc2008-12-02 03:28:16 +00001898static int sba_driver_callback(struct parisc_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001899{
1900 struct sba_device *sba_dev;
1901 u32 func_class;
1902 int i;
1903 char *version;
Helge Deller5076c152006-03-27 12:52:15 -07001904 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
Denis V. Lunev0fd68942008-04-29 01:02:32 -07001905#ifdef CONFIG_PROC_FS
1906 struct proc_dir_entry *root;
1907#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001908
1909 sba_dump_ranges(sba_addr);
1910
1911 /* Read HW Rev First */
1912 func_class = READ_REG(sba_addr + SBA_FCLASS);
1913
Kyle McMartin1b240f42006-08-24 21:30:19 -04001914 if (IS_ASTRO(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001915 unsigned long fclass;
1916 static char astro_rev[]="Astro ?.?";
1917
1918 /* Astro is broken...Read HW Rev First */
1919 fclass = READ_REG(sba_addr);
1920
1921 astro_rev[6] = '1' + (char) (fclass & 0x7);
1922 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1923 version = astro_rev;
1924
Kyle McMartin1b240f42006-08-24 21:30:19 -04001925 } else if (IS_IKE(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001926 static char ike_rev[] = "Ike rev ?";
1927 ike_rev[8] = '0' + (char) (func_class & 0xff);
1928 version = ike_rev;
Kyle McMartin1b240f42006-08-24 21:30:19 -04001929 } else if (IS_PLUTO(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001930 static char pluto_rev[]="Pluto ?.?";
1931 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
1932 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
1933 version = pluto_rev;
1934 } else {
1935 static char reo_rev[] = "REO rev ?";
1936 reo_rev[8] = '0' + (char) (func_class & 0xff);
1937 version = reo_rev;
1938 }
1939
1940 if (!global_ioc_cnt) {
1941 global_ioc_cnt = count_parisc_driver(&sba_driver);
1942
1943 /* Astro and Pluto have one IOC per SBA */
Kyle McMartin1b240f42006-08-24 21:30:19 -04001944 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001945 global_ioc_cnt *= 2;
1946 }
1947
Kyle McMartine9a03992007-10-18 00:04:00 -07001948 printk(KERN_INFO "%s found %s at 0x%llx\n",
1949 MODULE_NAME, version, (unsigned long long)dev->hpa.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001950
Helge Dellercb6fc182006-01-17 12:40:40 -07001951 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001952 if (!sba_dev) {
1953 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
1954 return -ENOMEM;
1955 }
1956
1957 parisc_set_drvdata(dev, sba_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001958
1959 for(i=0; i<MAX_IOC; i++)
1960 spin_lock_init(&(sba_dev->ioc[i].res_lock));
1961
1962 sba_dev->dev = dev;
1963 sba_dev->hw_rev = func_class;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001964 sba_dev->name = dev->name;
1965 sba_dev->sba_hpa = sba_addr;
1966
1967 sba_get_pat_resources(sba_dev);
1968 sba_hw_init(sba_dev);
1969 sba_common_init(sba_dev);
1970
1971 hppa_dma_ops = &sba_ops;
1972
1973#ifdef CONFIG_PROC_FS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001974 switch (dev->id.hversion) {
1975 case PLUTO_MCKINLEY_PORT:
1976 root = proc_mckinley_root;
1977 break;
1978 case ASTRO_RUNWAY_PORT:
1979 case IKE_MERCED_PORT:
1980 default:
1981 root = proc_runway_root;
1982 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001983 }
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001984
Denis V. Lunev0fd68942008-04-29 01:02:32 -07001985 proc_create("sba_iommu", 0, root, &sba_proc_fops);
1986 proc_create("sba_iommu-bitmap", 0, root, &sba_proc_bitmap_fops);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001987#endif
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001988
Linus Torvalds1da177e2005-04-16 15:20:36 -07001989 parisc_has_iommu();
1990 return 0;
1991}
1992
1993/*
1994** One time initialization to let the world know the SBA was found.
1995** This is the only routine which is NOT static.
1996** Must be called exactly once before pci_init().
1997*/
1998void __init sba_init(void)
1999{
2000 register_parisc_driver(&sba_driver);
2001}
2002
2003
2004/**
2005 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
2006 * @dev: The parisc device.
2007 *
2008 * Returns the appropriate IOMMU data for the given parisc PCI controller.
2009 * This is cached and used later for PCI DMA Mapping.
2010 */
2011void * sba_get_iommu(struct parisc_device *pci_hba)
2012{
2013 struct parisc_device *sba_dev = parisc_parent(pci_hba);
Greg Kroah-Hartmand18dbfa2009-05-04 12:40:54 -07002014 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002015 char t = sba_dev->id.hw_type;
2016 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2017
2018 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2019
2020 return &(sba->ioc[iocnum]);
2021}
2022
2023
2024/**
2025 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2026 * @pa_dev: The parisc device.
2027 * @r: resource PCI host controller wants start/end fields assigned.
2028 *
2029 * For the given parisc PCI controller, determine if any direct ranges
2030 * are routed down the corresponding rope.
2031 */
2032void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2033{
2034 struct parisc_device *sba_dev = parisc_parent(pci_hba);
Greg Kroah-Hartmand18dbfa2009-05-04 12:40:54 -07002035 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002036 char t = sba_dev->id.hw_type;
2037 int i;
2038 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2039
Eric Sesterhennb7494552006-03-24 18:52:10 +01002040 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002041
2042 r->start = r->end = 0;
2043
2044 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2045 for (i=0; i<4; i++) {
2046 int base, size;
2047 void __iomem *reg = sba->sba_hpa + i*0x18;
2048
2049 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2050 if ((base & 1) == 0)
2051 continue; /* not enabled */
2052
2053 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2054
2055 if ((size & (ROPES_PER_IOC-1)) != rope)
2056 continue; /* directed down different rope */
2057
2058 r->start = (base & ~1UL) | PCI_F_EXTEND;
2059 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2060 r->end = r->start + size;
Matthew Wilcoxca0844e2009-06-26 17:44:18 +00002061 r->flags = IORESOURCE_MEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002062 }
2063}
2064
2065
2066/**
2067 * sba_distributed_lmmio - return portion of distributed LMMIO range
2068 * @pa_dev: The parisc device.
2069 * @r: resource PCI host controller wants start/end fields assigned.
2070 *
2071 * For the given parisc PCI controller, return portion of distributed LMMIO
2072 * range. The distributed LMMIO is always present and it's just a question
2073 * of the base address and size of the range.
2074 */
2075void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2076{
2077 struct parisc_device *sba_dev = parisc_parent(pci_hba);
Greg Kroah-Hartmand18dbfa2009-05-04 12:40:54 -07002078 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002079 char t = sba_dev->id.hw_type;
2080 int base, size;
2081 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2082
Eric Sesterhennb7494552006-03-24 18:52:10 +01002083 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002084
2085 r->start = r->end = 0;
2086
2087 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2088 if ((base & 1) == 0) {
2089 BUG(); /* Gah! Distr Range wasn't enabled! */
2090 return;
2091 }
2092
2093 r->start = (base & ~1UL) | PCI_F_EXTEND;
2094
2095 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2096 r->start += rope * (size + 1); /* adjust base for this rope */
2097 r->end = r->start + size;
Matthew Wilcoxca0844e2009-06-26 17:44:18 +00002098 r->flags = IORESOURCE_MEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002099}