Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 1 | /* |
| 2 | * r8a7790 processor support |
| 3 | * |
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2013 Magnus Damm |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <linux/irq.h> |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 22 | #include <linux/kernel.h> |
| 23 | #include <linux/of_platform.h> |
Laurent Pinchart | 43ca9cb | 2013-04-08 11:36:17 +0200 | [diff] [blame] | 24 | #include <linux/platform_data/gpio-rcar.h> |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 25 | #include <linux/platform_data/irq-renesas-irqc.h> |
Magnus Damm | 99ade1a | 2013-06-28 20:27:04 +0900 | [diff] [blame] | 26 | #include <linux/serial_sci.h> |
| 27 | #include <linux/sh_timer.h> |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 28 | #include <mach/common.h> |
| 29 | #include <mach/irqs.h> |
| 30 | #include <mach/r8a7790.h> |
| 31 | #include <asm/mach/arch.h> |
| 32 | |
Kuninori Morimoto | f9094c5 | 2013-06-12 02:03:59 +0000 | [diff] [blame] | 33 | static struct resource pfc_resources[] __initdata = { |
Magnus Damm | 69e351d | 2013-03-28 00:50:03 +0900 | [diff] [blame] | 34 | DEFINE_RES_MEM(0xe6060000, 0x250), |
| 35 | }; |
| 36 | |
Laurent Pinchart | 43ca9cb | 2013-04-08 11:36:17 +0200 | [diff] [blame] | 37 | #define R8A7790_GPIO(idx) \ |
Kuninori Morimoto | f9094c5 | 2013-06-12 02:03:59 +0000 | [diff] [blame] | 38 | static struct resource r8a7790_gpio##idx##_resources[] __initdata = { \ |
Laurent Pinchart | 43ca9cb | 2013-04-08 11:36:17 +0200 | [diff] [blame] | 39 | DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ |
| 40 | DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ |
| 41 | }; \ |
| 42 | \ |
Kuninori Morimoto | f9094c5 | 2013-06-12 02:03:59 +0000 | [diff] [blame] | 43 | static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \ |
Laurent Pinchart | 43ca9cb | 2013-04-08 11:36:17 +0200 | [diff] [blame] | 44 | .gpio_base = 32 * (idx), \ |
| 45 | .irq_base = 0, \ |
| 46 | .number_of_pins = 32, \ |
| 47 | .pctl_name = "pfc-r8a7790", \ |
Simon Horman | d93906b8 | 2013-05-13 17:53:52 +0900 | [diff] [blame] | 48 | .has_both_edge_trigger = 1, \ |
Laurent Pinchart | 43ca9cb | 2013-04-08 11:36:17 +0200 | [diff] [blame] | 49 | }; \ |
| 50 | |
| 51 | R8A7790_GPIO(0); |
| 52 | R8A7790_GPIO(1); |
| 53 | R8A7790_GPIO(2); |
| 54 | R8A7790_GPIO(3); |
| 55 | R8A7790_GPIO(4); |
| 56 | R8A7790_GPIO(5); |
| 57 | |
| 58 | #define r8a7790_register_gpio(idx) \ |
| 59 | platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \ |
| 60 | r8a7790_gpio##idx##_resources, \ |
| 61 | ARRAY_SIZE(r8a7790_gpio##idx##_resources), \ |
| 62 | &r8a7790_gpio##idx##_platform_data, \ |
| 63 | sizeof(r8a7790_gpio##idx##_platform_data)) |
| 64 | |
Magnus Damm | 69e351d | 2013-03-28 00:50:03 +0900 | [diff] [blame] | 65 | void __init r8a7790_pinmux_init(void) |
| 66 | { |
| 67 | platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, |
| 68 | ARRAY_SIZE(pfc_resources)); |
Laurent Pinchart | 43ca9cb | 2013-04-08 11:36:17 +0200 | [diff] [blame] | 69 | r8a7790_register_gpio(0); |
| 70 | r8a7790_register_gpio(1); |
| 71 | r8a7790_register_gpio(2); |
| 72 | r8a7790_register_gpio(3); |
| 73 | r8a7790_register_gpio(4); |
| 74 | r8a7790_register_gpio(5); |
Magnus Damm | 69e351d | 2013-03-28 00:50:03 +0900 | [diff] [blame] | 75 | } |
| 76 | |
Magnus Damm | 55d9fab | 2013-03-28 00:49:44 +0900 | [diff] [blame] | 77 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ |
| 78 | .type = scif_type, \ |
| 79 | .mapbase = baseaddr, \ |
| 80 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
| 81 | .irqs = SCIx_IRQ_MUXED(irq) |
| 82 | |
| 83 | #define SCIFA_DATA(index, baseaddr, irq) \ |
| 84 | [index] = { \ |
| 85 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ |
| 86 | .scbrr_algo_id = SCBRR_ALGO_4, \ |
| 87 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ |
| 88 | } |
| 89 | |
| 90 | #define SCIFB_DATA(index, baseaddr, irq) \ |
| 91 | [index] = { \ |
| 92 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ |
| 93 | .scbrr_algo_id = SCBRR_ALGO_4, \ |
| 94 | .scscr = SCSCR_RE | SCSCR_TE, \ |
| 95 | } |
| 96 | |
| 97 | #define SCIF_DATA(index, baseaddr, irq) \ |
| 98 | [index] = { \ |
| 99 | SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ |
| 100 | .scbrr_algo_id = SCBRR_ALGO_2, \ |
Ulrich Hecht | c972f02 | 2013-05-31 17:57:04 +0200 | [diff] [blame] | 101 | .scscr = SCSCR_RE | SCSCR_TE, \ |
Magnus Damm | 55d9fab | 2013-03-28 00:49:44 +0900 | [diff] [blame] | 102 | } |
| 103 | |
Ulrich Hecht | d44f830 | 2013-05-31 17:57:02 +0200 | [diff] [blame] | 104 | #define HSCIF_DATA(index, baseaddr, irq) \ |
| 105 | [index] = { \ |
| 106 | SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ |
| 107 | .scbrr_algo_id = SCBRR_ALGO_6, \ |
| 108 | .scscr = SCSCR_RE | SCSCR_TE, \ |
| 109 | } |
| 110 | |
| 111 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, |
| 112 | HSCIF0, HSCIF1 }; |
Magnus Damm | 55d9fab | 2013-03-28 00:49:44 +0900 | [diff] [blame] | 113 | |
Kuninori Morimoto | f9094c5 | 2013-06-12 02:03:59 +0000 | [diff] [blame] | 114 | static struct plat_sci_port scif[] __initdata = { |
Magnus Damm | 55d9fab | 2013-03-28 00:49:44 +0900 | [diff] [blame] | 115 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ |
| 116 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ |
| 117 | SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ |
| 118 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ |
| 119 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ |
| 120 | SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ |
| 121 | SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ |
| 122 | SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ |
Ulrich Hecht | d44f830 | 2013-05-31 17:57:02 +0200 | [diff] [blame] | 123 | HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */ |
| 124 | HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */ |
Magnus Damm | 55d9fab | 2013-03-28 00:49:44 +0900 | [diff] [blame] | 125 | }; |
| 126 | |
| 127 | static inline void r8a7790_register_scif(int idx) |
| 128 | { |
| 129 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], |
| 130 | sizeof(struct plat_sci_port)); |
| 131 | } |
| 132 | |
Kuninori Morimoto | f9094c5 | 2013-06-12 02:03:59 +0000 | [diff] [blame] | 133 | static struct renesas_irqc_config irqc0_data __initdata = { |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 134 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ |
| 135 | }; |
| 136 | |
Kuninori Morimoto | f9094c5 | 2013-06-12 02:03:59 +0000 | [diff] [blame] | 137 | static struct resource irqc0_resources[] __initdata = { |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 138 | DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ |
| 139 | DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ |
| 140 | DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ |
| 141 | DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ |
| 142 | DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ |
| 143 | }; |
| 144 | |
| 145 | #define r8a7790_register_irqc(idx) \ |
| 146 | platform_device_register_resndata(&platform_bus, "renesas_irqc", \ |
| 147 | idx, irqc##idx##_resources, \ |
| 148 | ARRAY_SIZE(irqc##idx##_resources), \ |
| 149 | &irqc##idx##_data, \ |
| 150 | sizeof(struct renesas_irqc_config)) |
| 151 | |
Simon Horman | 0b8eeba | 2013-06-26 16:22:21 +0900 | [diff] [blame] | 152 | static struct resource thermal_resources[] __initdata = { |
| 153 | DEFINE_RES_MEM(0xe61f0000, 0x14), |
| 154 | DEFINE_RES_MEM(0xe61f0100, 0x38), |
| 155 | DEFINE_RES_IRQ(gic_spi(69)), |
| 156 | }; |
| 157 | |
| 158 | #define r8a7790_register_thermal() \ |
| 159 | platform_device_register_simple("rcar_thermal", -1, \ |
| 160 | thermal_resources, \ |
| 161 | ARRAY_SIZE(thermal_resources)) |
| 162 | |
Magnus Damm | 99ade1a | 2013-06-28 20:27:04 +0900 | [diff] [blame] | 163 | static struct sh_timer_config cmt00_platform_data = { |
| 164 | .name = "CMT00", |
| 165 | .timer_bit = 0, |
| 166 | .clockevent_rating = 80, |
| 167 | }; |
| 168 | |
| 169 | static struct resource cmt00_resources[] = { |
| 170 | DEFINE_RES_MEM(0xffca0510, 0x0c), |
| 171 | DEFINE_RES_MEM(0xffca0500, 0x04), |
| 172 | DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */ |
| 173 | }; |
| 174 | |
| 175 | #define r8a7790_register_cmt(idx) \ |
| 176 | platform_device_register_resndata(&platform_bus, "sh_cmt", \ |
| 177 | idx, cmt##idx##_resources, \ |
| 178 | ARRAY_SIZE(cmt##idx##_resources), \ |
| 179 | &cmt##idx##_platform_data, \ |
| 180 | sizeof(struct sh_timer_config)) |
| 181 | |
Simon Horman | 6dace67 | 2013-06-28 13:42:16 +0900 | [diff] [blame^] | 182 | void __init r8a7790_add_dt_devices(void) |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 183 | { |
Magnus Damm | 55d9fab | 2013-03-28 00:49:44 +0900 | [diff] [blame] | 184 | r8a7790_register_scif(SCIFA0); |
| 185 | r8a7790_register_scif(SCIFA1); |
| 186 | r8a7790_register_scif(SCIFB0); |
| 187 | r8a7790_register_scif(SCIFB1); |
| 188 | r8a7790_register_scif(SCIFB2); |
| 189 | r8a7790_register_scif(SCIFA2); |
| 190 | r8a7790_register_scif(SCIF0); |
| 191 | r8a7790_register_scif(SCIF1); |
Ulrich Hecht | d44f830 | 2013-05-31 17:57:02 +0200 | [diff] [blame] | 192 | r8a7790_register_scif(HSCIF0); |
| 193 | r8a7790_register_scif(HSCIF1); |
Simon Horman | 6dace67 | 2013-06-28 13:42:16 +0900 | [diff] [blame^] | 194 | r8a7790_register_cmt(00); |
| 195 | } |
| 196 | |
| 197 | void __init r8a7790_add_standard_devices(void) |
| 198 | { |
| 199 | r8a7790_add_dt_devices(); |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 200 | r8a7790_register_irqc(0); |
Simon Horman | 0b8eeba | 2013-06-26 16:22:21 +0900 | [diff] [blame] | 201 | r8a7790_register_thermal(); |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 202 | } |
| 203 | |
Magnus Damm | 512e53b | 2013-07-12 01:22:19 +0900 | [diff] [blame] | 204 | #define MODEMR 0xe6160060 |
| 205 | |
| 206 | u32 __init r8a7790_read_mode_pins(void) |
| 207 | { |
| 208 | void __iomem *modemr = ioremap_nocache(MODEMR, 4); |
| 209 | u32 mode; |
| 210 | |
| 211 | BUG_ON(!modemr); |
| 212 | mode = ioread32(modemr); |
| 213 | iounmap(modemr); |
| 214 | |
| 215 | return mode; |
| 216 | } |
| 217 | |
Magnus Damm | 81b9d53 | 2013-07-12 01:22:29 +0900 | [diff] [blame] | 218 | #define CNTCR 0 |
| 219 | #define CNTFID0 0x20 |
| 220 | |
Magnus Damm | ab5fdfd | 2013-04-08 10:23:28 +0900 | [diff] [blame] | 221 | void __init r8a7790_timer_init(void) |
| 222 | { |
Magnus Damm | 81b9d53 | 2013-07-12 01:22:29 +0900 | [diff] [blame] | 223 | #ifdef CONFIG_ARM_ARCH_TIMER |
| 224 | u32 mode = r8a7790_read_mode_pins(); |
| 225 | void __iomem *base; |
| 226 | int extal_mhz = 0; |
| 227 | u32 freq; |
Magnus Damm | ab5fdfd | 2013-04-08 10:23:28 +0900 | [diff] [blame] | 228 | |
Magnus Damm | 81b9d53 | 2013-07-12 01:22:29 +0900 | [diff] [blame] | 229 | /* At Linux boot time the r8a7790 arch timer comes up |
| 230 | * with the counter disabled. Moreover, it may also report |
| 231 | * a potentially incorrect fixed 13 MHz frequency. To be |
| 232 | * correct these registers need to be updated to use the |
| 233 | * frequency EXTAL / 2 which can be determined by the MD pins. |
| 234 | */ |
| 235 | |
| 236 | switch (mode & (MD(14) | MD(13))) { |
| 237 | case 0: |
| 238 | extal_mhz = 15; |
| 239 | break; |
| 240 | case MD(13): |
| 241 | extal_mhz = 20; |
| 242 | break; |
| 243 | case MD(14): |
| 244 | extal_mhz = 26; |
| 245 | break; |
| 246 | case MD(13) | MD(14): |
| 247 | extal_mhz = 30; |
| 248 | break; |
| 249 | } |
| 250 | |
| 251 | /* The arch timer frequency equals EXTAL / 2 */ |
| 252 | freq = extal_mhz * (1000000 / 2); |
| 253 | |
| 254 | /* Remap "armgcnt address map" space */ |
| 255 | base = ioremap(0xe6080000, PAGE_SIZE); |
| 256 | |
| 257 | /* Update registers with correct frequency */ |
| 258 | iowrite32(freq, base + CNTFID0); |
| 259 | asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); |
| 260 | |
| 261 | /* make sure arch timer is started by setting bit 0 of CNTCR */ |
| 262 | iowrite32(1, base + CNTCR); |
| 263 | iounmap(base); |
| 264 | #endif /* CONFIG_ARM_ARCH_TIMER */ |
Magnus Damm | ab5fdfd | 2013-04-08 10:23:28 +0900 | [diff] [blame] | 265 | |
| 266 | shmobile_timer_init(); |
| 267 | } |
| 268 | |
Magnus Damm | 8333d8c | 2013-06-28 20:27:13 +0900 | [diff] [blame] | 269 | void __init r8a7790_init_delay(void) |
| 270 | { |
| 271 | #ifndef CONFIG_ARM_ARCH_TIMER |
| 272 | shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */ |
| 273 | #endif |
| 274 | } |
| 275 | |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 276 | #ifdef CONFIG_USE_OF |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 277 | |
| 278 | static const char *r8a7790_boards_compat_dt[] __initdata = { |
| 279 | "renesas,r8a7790", |
| 280 | NULL, |
| 281 | }; |
| 282 | |
| 283 | DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") |
Magnus Damm | 8333d8c | 2013-06-28 20:27:13 +0900 | [diff] [blame] | 284 | .init_early = r8a7790_init_delay, |
Magnus Damm | ab5fdfd | 2013-04-08 10:23:28 +0900 | [diff] [blame] | 285 | .init_time = r8a7790_timer_init, |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 286 | .dt_compat = r8a7790_boards_compat_dt, |
| 287 | MACHINE_END |
| 288 | #endif /* CONFIG_USE_OF */ |