Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/omap2/dss/dss.c |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> |
| 6 | * |
| 7 | * Some code and ideas taken from drivers/video/omap/ driver |
| 8 | * by Imre Deak. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License version 2 as published by |
| 12 | * the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 17 | * more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along with |
| 20 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
| 23 | #define DSS_SUBSYS_NAME "DSS" |
| 24 | |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/err.h> |
| 28 | #include <linux/delay.h> |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 29 | #include <linux/seq_file.h> |
| 30 | #include <linux/clk.h> |
| 31 | |
| 32 | #include <plat/display.h> |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 33 | #include <plat/clock.h> |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 34 | #include "dss.h" |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame^] | 35 | #include "dss_features.h" |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 36 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 37 | #define DSS_SZ_REGS SZ_512 |
| 38 | |
| 39 | struct dss_reg { |
| 40 | u16 idx; |
| 41 | }; |
| 42 | |
| 43 | #define DSS_REG(idx) ((const struct dss_reg) { idx }) |
| 44 | |
| 45 | #define DSS_REVISION DSS_REG(0x0000) |
| 46 | #define DSS_SYSCONFIG DSS_REG(0x0010) |
| 47 | #define DSS_SYSSTATUS DSS_REG(0x0014) |
| 48 | #define DSS_IRQSTATUS DSS_REG(0x0018) |
| 49 | #define DSS_CONTROL DSS_REG(0x0040) |
| 50 | #define DSS_SDI_CONTROL DSS_REG(0x0044) |
| 51 | #define DSS_PLL_CONTROL DSS_REG(0x0048) |
| 52 | #define DSS_SDI_STATUS DSS_REG(0x005C) |
| 53 | |
| 54 | #define REG_GET(idx, start, end) \ |
| 55 | FLD_GET(dss_read_reg(idx), start, end) |
| 56 | |
| 57 | #define REG_FLD_MOD(idx, val, start, end) \ |
| 58 | dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) |
| 59 | |
| 60 | static struct { |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 61 | struct platform_device *pdev; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 62 | void __iomem *base; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 63 | int ctx_id; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 64 | |
| 65 | struct clk *dpll4_m4_ck; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 66 | struct clk *dss_ick; |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 67 | struct clk *dss_fck; |
| 68 | struct clk *dss_sys_clk; |
| 69 | struct clk *dss_tv_fck; |
| 70 | struct clk *dss_video_fck; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 71 | unsigned num_clks_enabled; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 72 | |
| 73 | unsigned long cache_req_pck; |
| 74 | unsigned long cache_prate; |
| 75 | struct dss_clock_info cache_dss_cinfo; |
| 76 | struct dispc_clock_info cache_dispc_cinfo; |
| 77 | |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 78 | enum dss_clk_source dsi_clk_source; |
| 79 | enum dss_clk_source dispc_clk_source; |
| 80 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 81 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; |
| 82 | } dss; |
| 83 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 84 | static void dss_clk_enable_all_no_ctx(void); |
| 85 | static void dss_clk_disable_all_no_ctx(void); |
| 86 | static void dss_clk_enable_no_ctx(enum dss_clock clks); |
| 87 | static void dss_clk_disable_no_ctx(enum dss_clock clks); |
| 88 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 89 | static int _omap_dss_wait_reset(void); |
| 90 | |
| 91 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) |
| 92 | { |
| 93 | __raw_writel(val, dss.base + idx.idx); |
| 94 | } |
| 95 | |
| 96 | static inline u32 dss_read_reg(const struct dss_reg idx) |
| 97 | { |
| 98 | return __raw_readl(dss.base + idx.idx); |
| 99 | } |
| 100 | |
| 101 | #define SR(reg) \ |
| 102 | dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) |
| 103 | #define RR(reg) \ |
| 104 | dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) |
| 105 | |
| 106 | void dss_save_context(void) |
| 107 | { |
| 108 | if (cpu_is_omap24xx()) |
| 109 | return; |
| 110 | |
| 111 | SR(SYSCONFIG); |
| 112 | SR(CONTROL); |
| 113 | |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame^] | 114 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 115 | OMAP_DISPLAY_TYPE_SDI) { |
| 116 | SR(SDI_CONTROL); |
| 117 | SR(PLL_CONTROL); |
| 118 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | void dss_restore_context(void) |
| 122 | { |
| 123 | if (_omap_dss_wait_reset()) |
| 124 | DSSERR("DSS not coming out of reset after sleep\n"); |
| 125 | |
| 126 | RR(SYSCONFIG); |
| 127 | RR(CONTROL); |
| 128 | |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame^] | 129 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 130 | OMAP_DISPLAY_TYPE_SDI) { |
| 131 | RR(SDI_CONTROL); |
| 132 | RR(PLL_CONTROL); |
| 133 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 134 | } |
| 135 | |
| 136 | #undef SR |
| 137 | #undef RR |
| 138 | |
| 139 | void dss_sdi_init(u8 datapairs) |
| 140 | { |
| 141 | u32 l; |
| 142 | |
| 143 | BUG_ON(datapairs > 3 || datapairs < 1); |
| 144 | |
| 145 | l = dss_read_reg(DSS_SDI_CONTROL); |
| 146 | l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ |
| 147 | l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ |
| 148 | l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ |
| 149 | dss_write_reg(DSS_SDI_CONTROL, l); |
| 150 | |
| 151 | l = dss_read_reg(DSS_PLL_CONTROL); |
| 152 | l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ |
| 153 | l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ |
| 154 | l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ |
| 155 | dss_write_reg(DSS_PLL_CONTROL, l); |
| 156 | } |
| 157 | |
| 158 | int dss_sdi_enable(void) |
| 159 | { |
| 160 | unsigned long timeout; |
| 161 | |
| 162 | dispc_pck_free_enable(1); |
| 163 | |
| 164 | /* Reset SDI PLL */ |
| 165 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ |
| 166 | udelay(1); /* wait 2x PCLK */ |
| 167 | |
| 168 | /* Lock SDI PLL */ |
| 169 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ |
| 170 | |
| 171 | /* Waiting for PLL lock request to complete */ |
| 172 | timeout = jiffies + msecs_to_jiffies(500); |
| 173 | while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { |
| 174 | if (time_after_eq(jiffies, timeout)) { |
| 175 | DSSERR("PLL lock request timed out\n"); |
| 176 | goto err1; |
| 177 | } |
| 178 | } |
| 179 | |
| 180 | /* Clearing PLL_GO bit */ |
| 181 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); |
| 182 | |
| 183 | /* Waiting for PLL to lock */ |
| 184 | timeout = jiffies + msecs_to_jiffies(500); |
| 185 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { |
| 186 | if (time_after_eq(jiffies, timeout)) { |
| 187 | DSSERR("PLL lock timed out\n"); |
| 188 | goto err1; |
| 189 | } |
| 190 | } |
| 191 | |
| 192 | dispc_lcd_enable_signal(1); |
| 193 | |
| 194 | /* Waiting for SDI reset to complete */ |
| 195 | timeout = jiffies + msecs_to_jiffies(500); |
| 196 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { |
| 197 | if (time_after_eq(jiffies, timeout)) { |
| 198 | DSSERR("SDI reset timed out\n"); |
| 199 | goto err2; |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | return 0; |
| 204 | |
| 205 | err2: |
| 206 | dispc_lcd_enable_signal(0); |
| 207 | err1: |
| 208 | /* Reset SDI PLL */ |
| 209 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ |
| 210 | |
| 211 | dispc_pck_free_enable(0); |
| 212 | |
| 213 | return -ETIMEDOUT; |
| 214 | } |
| 215 | |
| 216 | void dss_sdi_disable(void) |
| 217 | { |
| 218 | dispc_lcd_enable_signal(0); |
| 219 | |
| 220 | dispc_pck_free_enable(0); |
| 221 | |
| 222 | /* Reset SDI PLL */ |
| 223 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ |
| 224 | } |
| 225 | |
| 226 | void dss_dump_clocks(struct seq_file *s) |
| 227 | { |
| 228 | unsigned long dpll4_ck_rate; |
| 229 | unsigned long dpll4_m4_ck_rate; |
| 230 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 231 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 232 | |
| 233 | dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 234 | dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); |
| 235 | |
| 236 | seq_printf(s, "- DSS -\n"); |
| 237 | |
| 238 | seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); |
| 239 | |
Kishore Y | ac01bb7 | 2010-04-25 16:27:19 +0530 | [diff] [blame] | 240 | if (cpu_is_omap3630()) |
| 241 | seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n", |
| 242 | dpll4_ck_rate, |
| 243 | dpll4_ck_rate / dpll4_m4_ck_rate, |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 244 | dss_clk_get_rate(DSS_CLK_FCK)); |
Kishore Y | ac01bb7 | 2010-04-25 16:27:19 +0530 | [diff] [blame] | 245 | else |
| 246 | seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n", |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 247 | dpll4_ck_rate, |
| 248 | dpll4_ck_rate / dpll4_m4_ck_rate, |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 249 | dss_clk_get_rate(DSS_CLK_FCK)); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 250 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 251 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | void dss_dump_regs(struct seq_file *s) |
| 255 | { |
| 256 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) |
| 257 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 258 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 259 | |
| 260 | DUMPREG(DSS_REVISION); |
| 261 | DUMPREG(DSS_SYSCONFIG); |
| 262 | DUMPREG(DSS_SYSSTATUS); |
| 263 | DUMPREG(DSS_IRQSTATUS); |
| 264 | DUMPREG(DSS_CONTROL); |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame^] | 265 | |
| 266 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 267 | OMAP_DISPLAY_TYPE_SDI) { |
| 268 | DUMPREG(DSS_SDI_CONTROL); |
| 269 | DUMPREG(DSS_PLL_CONTROL); |
| 270 | DUMPREG(DSS_SDI_STATUS); |
| 271 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 272 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 273 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 274 | #undef DUMPREG |
| 275 | } |
| 276 | |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 277 | void dss_select_dispc_clk_source(enum dss_clk_source clk_src) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 278 | { |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 279 | int b; |
| 280 | |
| 281 | BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK && |
| 282 | clk_src != DSS_SRC_DSS1_ALWON_FCLK); |
| 283 | |
| 284 | b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; |
| 285 | |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 286 | if (clk_src == DSS_SRC_DSI1_PLL_FCLK) |
| 287 | dsi_wait_dsi1_pll_active(); |
| 288 | |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 289 | REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ |
| 290 | |
| 291 | dss.dispc_clk_source = clk_src; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 292 | } |
| 293 | |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 294 | void dss_select_dsi_clk_source(enum dss_clk_source clk_src) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 295 | { |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 296 | int b; |
| 297 | |
| 298 | BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK && |
| 299 | clk_src != DSS_SRC_DSS1_ALWON_FCLK); |
| 300 | |
| 301 | b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; |
| 302 | |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 303 | if (clk_src == DSS_SRC_DSI2_PLL_FCLK) |
| 304 | dsi_wait_dsi2_pll_active(); |
| 305 | |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 306 | REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ |
| 307 | |
| 308 | dss.dsi_clk_source = clk_src; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 309 | } |
| 310 | |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 311 | enum dss_clk_source dss_get_dispc_clk_source(void) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 312 | { |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 313 | return dss.dispc_clk_source; |
| 314 | } |
| 315 | |
| 316 | enum dss_clk_source dss_get_dsi_clk_source(void) |
| 317 | { |
| 318 | return dss.dsi_clk_source; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | /* calculate clock rates using dividers in cinfo */ |
| 322 | int dss_calc_clock_rates(struct dss_clock_info *cinfo) |
| 323 | { |
| 324 | unsigned long prate; |
| 325 | |
Kishore Y | ac01bb7 | 2010-04-25 16:27:19 +0530 | [diff] [blame] | 326 | if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) || |
| 327 | cinfo->fck_div == 0) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 328 | return -EINVAL; |
| 329 | |
| 330 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 331 | |
| 332 | cinfo->fck = prate / cinfo->fck_div; |
| 333 | |
| 334 | return 0; |
| 335 | } |
| 336 | |
| 337 | int dss_set_clock_div(struct dss_clock_info *cinfo) |
| 338 | { |
| 339 | unsigned long prate; |
| 340 | int r; |
| 341 | |
| 342 | if (cpu_is_omap34xx()) { |
| 343 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 344 | DSSDBG("dpll4_m4 = %ld\n", prate); |
| 345 | |
| 346 | r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div); |
| 347 | if (r) |
| 348 | return r; |
| 349 | } |
| 350 | |
| 351 | DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); |
| 352 | |
| 353 | return 0; |
| 354 | } |
| 355 | |
| 356 | int dss_get_clock_div(struct dss_clock_info *cinfo) |
| 357 | { |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 358 | cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 359 | |
| 360 | if (cpu_is_omap34xx()) { |
| 361 | unsigned long prate; |
| 362 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
Kishore Y | ac01bb7 | 2010-04-25 16:27:19 +0530 | [diff] [blame] | 363 | if (cpu_is_omap3630()) |
| 364 | cinfo->fck_div = prate / (cinfo->fck); |
| 365 | else |
| 366 | cinfo->fck_div = prate / (cinfo->fck / 2); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 367 | } else { |
| 368 | cinfo->fck_div = 0; |
| 369 | } |
| 370 | |
| 371 | return 0; |
| 372 | } |
| 373 | |
| 374 | unsigned long dss_get_dpll4_rate(void) |
| 375 | { |
| 376 | if (cpu_is_omap34xx()) |
| 377 | return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 378 | else |
| 379 | return 0; |
| 380 | } |
| 381 | |
| 382 | int dss_calc_clock_div(bool is_tft, unsigned long req_pck, |
| 383 | struct dss_clock_info *dss_cinfo, |
| 384 | struct dispc_clock_info *dispc_cinfo) |
| 385 | { |
| 386 | unsigned long prate; |
| 387 | struct dss_clock_info best_dss; |
| 388 | struct dispc_clock_info best_dispc; |
| 389 | |
| 390 | unsigned long fck; |
| 391 | |
| 392 | u16 fck_div; |
| 393 | |
| 394 | int match = 0; |
| 395 | int min_fck_per_pck; |
| 396 | |
| 397 | prate = dss_get_dpll4_rate(); |
| 398 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 399 | fck = dss_clk_get_rate(DSS_CLK_FCK); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 400 | if (req_pck == dss.cache_req_pck && |
| 401 | ((cpu_is_omap34xx() && prate == dss.cache_prate) || |
| 402 | dss.cache_dss_cinfo.fck == fck)) { |
| 403 | DSSDBG("dispc clock info found from cache.\n"); |
| 404 | *dss_cinfo = dss.cache_dss_cinfo; |
| 405 | *dispc_cinfo = dss.cache_dispc_cinfo; |
| 406 | return 0; |
| 407 | } |
| 408 | |
| 409 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; |
| 410 | |
| 411 | if (min_fck_per_pck && |
| 412 | req_pck * min_fck_per_pck > DISPC_MAX_FCK) { |
| 413 | DSSERR("Requested pixel clock not possible with the current " |
| 414 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " |
| 415 | "the constraint off.\n"); |
| 416 | min_fck_per_pck = 0; |
| 417 | } |
| 418 | |
| 419 | retry: |
| 420 | memset(&best_dss, 0, sizeof(best_dss)); |
| 421 | memset(&best_dispc, 0, sizeof(best_dispc)); |
| 422 | |
| 423 | if (cpu_is_omap24xx()) { |
| 424 | struct dispc_clock_info cur_dispc; |
| 425 | /* XXX can we change the clock on omap2? */ |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 426 | fck = dss_clk_get_rate(DSS_CLK_FCK); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 427 | fck_div = 1; |
| 428 | |
| 429 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); |
| 430 | match = 1; |
| 431 | |
| 432 | best_dss.fck = fck; |
| 433 | best_dss.fck_div = fck_div; |
| 434 | |
| 435 | best_dispc = cur_dispc; |
| 436 | |
| 437 | goto found; |
| 438 | } else if (cpu_is_omap34xx()) { |
Kishore Y | ac01bb7 | 2010-04-25 16:27:19 +0530 | [diff] [blame] | 439 | for (fck_div = (cpu_is_omap3630() ? 32 : 16); |
| 440 | fck_div > 0; --fck_div) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 441 | struct dispc_clock_info cur_dispc; |
| 442 | |
Kishore Y | ac01bb7 | 2010-04-25 16:27:19 +0530 | [diff] [blame] | 443 | if (cpu_is_omap3630()) |
| 444 | fck = prate / fck_div; |
| 445 | else |
| 446 | fck = prate / fck_div * 2; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 447 | |
| 448 | if (fck > DISPC_MAX_FCK) |
| 449 | continue; |
| 450 | |
| 451 | if (min_fck_per_pck && |
| 452 | fck < req_pck * min_fck_per_pck) |
| 453 | continue; |
| 454 | |
| 455 | match = 1; |
| 456 | |
| 457 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); |
| 458 | |
| 459 | if (abs(cur_dispc.pck - req_pck) < |
| 460 | abs(best_dispc.pck - req_pck)) { |
| 461 | |
| 462 | best_dss.fck = fck; |
| 463 | best_dss.fck_div = fck_div; |
| 464 | |
| 465 | best_dispc = cur_dispc; |
| 466 | |
| 467 | if (cur_dispc.pck == req_pck) |
| 468 | goto found; |
| 469 | } |
| 470 | } |
| 471 | } else { |
| 472 | BUG(); |
| 473 | } |
| 474 | |
| 475 | found: |
| 476 | if (!match) { |
| 477 | if (min_fck_per_pck) { |
| 478 | DSSERR("Could not find suitable clock settings.\n" |
| 479 | "Turning FCK/PCK constraint off and" |
| 480 | "trying again.\n"); |
| 481 | min_fck_per_pck = 0; |
| 482 | goto retry; |
| 483 | } |
| 484 | |
| 485 | DSSERR("Could not find suitable clock settings.\n"); |
| 486 | |
| 487 | return -EINVAL; |
| 488 | } |
| 489 | |
| 490 | if (dss_cinfo) |
| 491 | *dss_cinfo = best_dss; |
| 492 | if (dispc_cinfo) |
| 493 | *dispc_cinfo = best_dispc; |
| 494 | |
| 495 | dss.cache_req_pck = req_pck; |
| 496 | dss.cache_prate = prate; |
| 497 | dss.cache_dss_cinfo = best_dss; |
| 498 | dss.cache_dispc_cinfo = best_dispc; |
| 499 | |
| 500 | return 0; |
| 501 | } |
| 502 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 503 | static int _omap_dss_wait_reset(void) |
| 504 | { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 505 | int t = 0; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 506 | |
| 507 | while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 508 | if (++t > 1000) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 509 | DSSERR("soft reset failed\n"); |
| 510 | return -ENODEV; |
| 511 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 512 | udelay(1); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 513 | } |
| 514 | |
| 515 | return 0; |
| 516 | } |
| 517 | |
| 518 | static int _omap_dss_reset(void) |
| 519 | { |
| 520 | /* Soft reset */ |
| 521 | REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1); |
| 522 | return _omap_dss_wait_reset(); |
| 523 | } |
| 524 | |
| 525 | void dss_set_venc_output(enum omap_dss_venc_type type) |
| 526 | { |
| 527 | int l = 0; |
| 528 | |
| 529 | if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) |
| 530 | l = 0; |
| 531 | else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) |
| 532 | l = 1; |
| 533 | else |
| 534 | BUG(); |
| 535 | |
| 536 | /* venc out selection. 0 = comp, 1 = svideo */ |
| 537 | REG_FLD_MOD(DSS_CONTROL, l, 6, 6); |
| 538 | } |
| 539 | |
| 540 | void dss_set_dac_pwrdn_bgz(bool enable) |
| 541 | { |
| 542 | REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ |
| 543 | } |
| 544 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 545 | static int dss_init(bool skip_init) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 546 | { |
| 547 | int r; |
| 548 | u32 rev; |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 549 | struct resource *dss_mem; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 550 | |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 551 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); |
| 552 | if (!dss_mem) { |
| 553 | DSSERR("can't get IORESOURCE_MEM DSS\n"); |
| 554 | r = -EINVAL; |
| 555 | goto fail0; |
| 556 | } |
| 557 | dss.base = ioremap(dss_mem->start, resource_size(dss_mem)); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 558 | if (!dss.base) { |
| 559 | DSSERR("can't ioremap DSS\n"); |
| 560 | r = -ENOMEM; |
| 561 | goto fail0; |
| 562 | } |
| 563 | |
| 564 | if (!skip_init) { |
| 565 | /* disable LCD and DIGIT output. This seems to fix the synclost |
| 566 | * problem that we get, if the bootloader starts the DSS and |
| 567 | * the kernel resets it */ |
| 568 | omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); |
| 569 | |
| 570 | /* We need to wait here a bit, otherwise we sometimes start to |
| 571 | * get synclost errors, and after that only power cycle will |
| 572 | * restore DSS functionality. I have no idea why this happens. |
| 573 | * And we have to wait _before_ resetting the DSS, but after |
| 574 | * enabling clocks. |
| 575 | */ |
| 576 | msleep(50); |
| 577 | |
| 578 | _omap_dss_reset(); |
| 579 | } |
| 580 | |
| 581 | /* autoidle */ |
| 582 | REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); |
| 583 | |
| 584 | /* Select DPLL */ |
| 585 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); |
| 586 | |
| 587 | #ifdef CONFIG_OMAP2_DSS_VENC |
| 588 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ |
| 589 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ |
| 590 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ |
| 591 | #endif |
| 592 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 593 | if (cpu_is_omap34xx()) { |
| 594 | dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); |
| 595 | if (IS_ERR(dss.dpll4_m4_ck)) { |
| 596 | DSSERR("Failed to get dpll4_m4_ck\n"); |
| 597 | r = PTR_ERR(dss.dpll4_m4_ck); |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 598 | goto fail1; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 599 | } |
| 600 | } |
| 601 | |
Tomi Valkeinen | ce619e1 | 2010-03-12 12:46:05 +0200 | [diff] [blame] | 602 | dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK; |
| 603 | dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK; |
| 604 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 605 | dss_save_context(); |
| 606 | |
| 607 | rev = dss_read_reg(DSS_REVISION); |
| 608 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", |
| 609 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
| 610 | |
| 611 | return 0; |
| 612 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 613 | fail1: |
| 614 | iounmap(dss.base); |
| 615 | fail0: |
| 616 | return r; |
| 617 | } |
| 618 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 619 | static void dss_exit(void) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 620 | { |
| 621 | if (cpu_is_omap34xx()) |
| 622 | clk_put(dss.dpll4_m4_ck); |
| 623 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 624 | iounmap(dss.base); |
| 625 | } |
| 626 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 627 | /* CONTEXT */ |
| 628 | static int dss_get_ctx_id(void) |
| 629 | { |
| 630 | struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; |
| 631 | int r; |
| 632 | |
| 633 | if (!pdata->board_data->get_last_off_on_transaction_id) |
| 634 | return 0; |
| 635 | r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev); |
| 636 | if (r < 0) { |
| 637 | dev_err(&dss.pdev->dev, "getting transaction ID failed, " |
| 638 | "will force context restore\n"); |
| 639 | r = -1; |
| 640 | } |
| 641 | return r; |
| 642 | } |
| 643 | |
| 644 | int dss_need_ctx_restore(void) |
| 645 | { |
| 646 | int id = dss_get_ctx_id(); |
| 647 | |
| 648 | if (id < 0 || id != dss.ctx_id) { |
| 649 | DSSDBG("ctx id %d -> id %d\n", |
| 650 | dss.ctx_id, id); |
| 651 | dss.ctx_id = id; |
| 652 | return 1; |
| 653 | } else { |
| 654 | return 0; |
| 655 | } |
| 656 | } |
| 657 | |
| 658 | static void save_all_ctx(void) |
| 659 | { |
| 660 | DSSDBG("save context\n"); |
| 661 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 662 | dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 663 | |
| 664 | dss_save_context(); |
| 665 | dispc_save_context(); |
| 666 | #ifdef CONFIG_OMAP2_DSS_DSI |
| 667 | dsi_save_context(); |
| 668 | #endif |
| 669 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 670 | dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 671 | } |
| 672 | |
| 673 | static void restore_all_ctx(void) |
| 674 | { |
| 675 | DSSDBG("restore context\n"); |
| 676 | |
| 677 | dss_clk_enable_all_no_ctx(); |
| 678 | |
| 679 | dss_restore_context(); |
| 680 | dispc_restore_context(); |
| 681 | #ifdef CONFIG_OMAP2_DSS_DSI |
| 682 | dsi_restore_context(); |
| 683 | #endif |
| 684 | |
| 685 | dss_clk_disable_all_no_ctx(); |
| 686 | } |
| 687 | |
| 688 | static int dss_get_clock(struct clk **clock, const char *clk_name) |
| 689 | { |
| 690 | struct clk *clk; |
| 691 | |
| 692 | clk = clk_get(&dss.pdev->dev, clk_name); |
| 693 | |
| 694 | if (IS_ERR(clk)) { |
| 695 | DSSERR("can't get clock %s", clk_name); |
| 696 | return PTR_ERR(clk); |
| 697 | } |
| 698 | |
| 699 | *clock = clk; |
| 700 | |
| 701 | DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); |
| 702 | |
| 703 | return 0; |
| 704 | } |
| 705 | |
| 706 | static int dss_get_clocks(void) |
| 707 | { |
| 708 | int r; |
| 709 | |
| 710 | dss.dss_ick = NULL; |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 711 | dss.dss_fck = NULL; |
| 712 | dss.dss_sys_clk = NULL; |
| 713 | dss.dss_tv_fck = NULL; |
| 714 | dss.dss_video_fck = NULL; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 715 | |
| 716 | r = dss_get_clock(&dss.dss_ick, "ick"); |
| 717 | if (r) |
| 718 | goto err; |
| 719 | |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 720 | r = dss_get_clock(&dss.dss_fck, "fck"); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 721 | if (r) |
| 722 | goto err; |
| 723 | |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 724 | r = dss_get_clock(&dss.dss_sys_clk, "sys_clk"); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 725 | if (r) |
| 726 | goto err; |
| 727 | |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 728 | r = dss_get_clock(&dss.dss_tv_fck, "tv_clk"); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 729 | if (r) |
| 730 | goto err; |
| 731 | |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 732 | r = dss_get_clock(&dss.dss_video_fck, "video_clk"); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 733 | if (r) |
| 734 | goto err; |
| 735 | |
| 736 | return 0; |
| 737 | |
| 738 | err: |
| 739 | if (dss.dss_ick) |
| 740 | clk_put(dss.dss_ick); |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 741 | if (dss.dss_fck) |
| 742 | clk_put(dss.dss_fck); |
| 743 | if (dss.dss_sys_clk) |
| 744 | clk_put(dss.dss_sys_clk); |
| 745 | if (dss.dss_tv_fck) |
| 746 | clk_put(dss.dss_tv_fck); |
| 747 | if (dss.dss_video_fck) |
| 748 | clk_put(dss.dss_video_fck); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 749 | |
| 750 | return r; |
| 751 | } |
| 752 | |
| 753 | static void dss_put_clocks(void) |
| 754 | { |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 755 | if (dss.dss_video_fck) |
| 756 | clk_put(dss.dss_video_fck); |
| 757 | clk_put(dss.dss_tv_fck); |
| 758 | clk_put(dss.dss_fck); |
| 759 | clk_put(dss.dss_sys_clk); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 760 | clk_put(dss.dss_ick); |
| 761 | } |
| 762 | |
| 763 | unsigned long dss_clk_get_rate(enum dss_clock clk) |
| 764 | { |
| 765 | switch (clk) { |
| 766 | case DSS_CLK_ICK: |
| 767 | return clk_get_rate(dss.dss_ick); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 768 | case DSS_CLK_FCK: |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 769 | return clk_get_rate(dss.dss_fck); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 770 | case DSS_CLK_SYSCK: |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 771 | return clk_get_rate(dss.dss_sys_clk); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 772 | case DSS_CLK_TVFCK: |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 773 | return clk_get_rate(dss.dss_tv_fck); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 774 | case DSS_CLK_VIDFCK: |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 775 | return clk_get_rate(dss.dss_video_fck); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 776 | } |
| 777 | |
| 778 | BUG(); |
| 779 | return 0; |
| 780 | } |
| 781 | |
| 782 | static unsigned count_clk_bits(enum dss_clock clks) |
| 783 | { |
| 784 | unsigned num_clks = 0; |
| 785 | |
| 786 | if (clks & DSS_CLK_ICK) |
| 787 | ++num_clks; |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 788 | if (clks & DSS_CLK_FCK) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 789 | ++num_clks; |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 790 | if (clks & DSS_CLK_SYSCK) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 791 | ++num_clks; |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 792 | if (clks & DSS_CLK_TVFCK) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 793 | ++num_clks; |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 794 | if (clks & DSS_CLK_VIDFCK) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 795 | ++num_clks; |
| 796 | |
| 797 | return num_clks; |
| 798 | } |
| 799 | |
| 800 | static void dss_clk_enable_no_ctx(enum dss_clock clks) |
| 801 | { |
| 802 | unsigned num_clks = count_clk_bits(clks); |
| 803 | |
| 804 | if (clks & DSS_CLK_ICK) |
| 805 | clk_enable(dss.dss_ick); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 806 | if (clks & DSS_CLK_FCK) |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 807 | clk_enable(dss.dss_fck); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 808 | if (clks & DSS_CLK_SYSCK) |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 809 | clk_enable(dss.dss_sys_clk); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 810 | if (clks & DSS_CLK_TVFCK) |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 811 | clk_enable(dss.dss_tv_fck); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 812 | if (clks & DSS_CLK_VIDFCK) |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 813 | clk_enable(dss.dss_video_fck); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 814 | |
| 815 | dss.num_clks_enabled += num_clks; |
| 816 | } |
| 817 | |
| 818 | void dss_clk_enable(enum dss_clock clks) |
| 819 | { |
| 820 | bool check_ctx = dss.num_clks_enabled == 0; |
| 821 | |
| 822 | dss_clk_enable_no_ctx(clks); |
| 823 | |
| 824 | if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) |
| 825 | restore_all_ctx(); |
| 826 | } |
| 827 | |
| 828 | static void dss_clk_disable_no_ctx(enum dss_clock clks) |
| 829 | { |
| 830 | unsigned num_clks = count_clk_bits(clks); |
| 831 | |
| 832 | if (clks & DSS_CLK_ICK) |
| 833 | clk_disable(dss.dss_ick); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 834 | if (clks & DSS_CLK_FCK) |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 835 | clk_disable(dss.dss_fck); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 836 | if (clks & DSS_CLK_SYSCK) |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 837 | clk_disable(dss.dss_sys_clk); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 838 | if (clks & DSS_CLK_TVFCK) |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 839 | clk_disable(dss.dss_tv_fck); |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 840 | if (clks & DSS_CLK_VIDFCK) |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 841 | clk_disable(dss.dss_video_fck); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 842 | |
| 843 | dss.num_clks_enabled -= num_clks; |
| 844 | } |
| 845 | |
| 846 | void dss_clk_disable(enum dss_clock clks) |
| 847 | { |
| 848 | if (cpu_is_omap34xx()) { |
| 849 | unsigned num_clks = count_clk_bits(clks); |
| 850 | |
| 851 | BUG_ON(dss.num_clks_enabled < num_clks); |
| 852 | |
| 853 | if (dss.num_clks_enabled == num_clks) |
| 854 | save_all_ctx(); |
| 855 | } |
| 856 | |
| 857 | dss_clk_disable_no_ctx(clks); |
| 858 | } |
| 859 | |
| 860 | static void dss_clk_enable_all_no_ctx(void) |
| 861 | { |
| 862 | enum dss_clock clks; |
| 863 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 864 | clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 865 | if (cpu_is_omap34xx()) |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 866 | clks |= DSS_CLK_VIDFCK; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 867 | dss_clk_enable_no_ctx(clks); |
| 868 | } |
| 869 | |
| 870 | static void dss_clk_disable_all_no_ctx(void) |
| 871 | { |
| 872 | enum dss_clock clks; |
| 873 | |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 874 | clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 875 | if (cpu_is_omap34xx()) |
Archit Taneja | 6af9cd1 | 2011-01-31 16:27:44 +0000 | [diff] [blame] | 876 | clks |= DSS_CLK_VIDFCK; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 877 | dss_clk_disable_no_ctx(clks); |
| 878 | } |
| 879 | |
| 880 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) |
| 881 | /* CLOCKS */ |
| 882 | static void core_dump_clocks(struct seq_file *s) |
| 883 | { |
| 884 | int i; |
| 885 | struct clk *clocks[5] = { |
| 886 | dss.dss_ick, |
Archit Taneja | c7642f6 | 2011-01-31 16:27:45 +0000 | [diff] [blame] | 887 | dss.dss_fck, |
| 888 | dss.dss_sys_clk, |
| 889 | dss.dss_tv_fck, |
| 890 | dss.dss_video_fck |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 891 | }; |
| 892 | |
| 893 | seq_printf(s, "- CORE -\n"); |
| 894 | |
| 895 | seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled); |
| 896 | |
| 897 | for (i = 0; i < 5; i++) { |
| 898 | if (!clocks[i]) |
| 899 | continue; |
| 900 | seq_printf(s, "%-15s\t%lu\t%d\n", |
| 901 | clocks[i]->name, |
| 902 | clk_get_rate(clocks[i]), |
| 903 | clocks[i]->usecount); |
| 904 | } |
| 905 | } |
| 906 | #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ |
| 907 | |
| 908 | /* DEBUGFS */ |
| 909 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) |
| 910 | void dss_debug_dump_clocks(struct seq_file *s) |
| 911 | { |
| 912 | core_dump_clocks(s); |
| 913 | dss_dump_clocks(s); |
| 914 | dispc_dump_clocks(s); |
| 915 | #ifdef CONFIG_OMAP2_DSS_DSI |
| 916 | dsi_dump_clocks(s); |
| 917 | #endif |
| 918 | } |
| 919 | #endif |
| 920 | |
| 921 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 922 | /* DSS HW IP initialisation */ |
| 923 | static int omap_dsshw_probe(struct platform_device *pdev) |
| 924 | { |
| 925 | int r; |
| 926 | int skip_init = 0; |
| 927 | |
| 928 | dss.pdev = pdev; |
| 929 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 930 | r = dss_get_clocks(); |
| 931 | if (r) |
| 932 | goto err_clocks; |
| 933 | |
| 934 | dss_clk_enable_all_no_ctx(); |
| 935 | |
| 936 | dss.ctx_id = dss_get_ctx_id(); |
| 937 | DSSDBG("initial ctx id %u\n", dss.ctx_id); |
| 938 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 939 | #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT |
| 940 | /* DISPC_CONTROL */ |
| 941 | if (omap_readl(0x48050440) & 1) /* LCD enabled? */ |
| 942 | skip_init = 1; |
| 943 | #endif |
| 944 | |
| 945 | r = dss_init(skip_init); |
| 946 | if (r) { |
| 947 | DSSERR("Failed to initialize DSS\n"); |
| 948 | goto err_dss; |
| 949 | } |
| 950 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 951 | dss_clk_disable_all_no_ctx(); |
| 952 | return 0; |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 953 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 954 | err_dss: |
| 955 | dss_clk_disable_all_no_ctx(); |
| 956 | dss_put_clocks(); |
| 957 | err_clocks: |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 958 | return r; |
| 959 | } |
| 960 | |
| 961 | static int omap_dsshw_remove(struct platform_device *pdev) |
| 962 | { |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 963 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 964 | dss_exit(); |
| 965 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 966 | /* |
| 967 | * As part of hwmod changes, DSS is not the only controller of dss |
| 968 | * clocks; hwmod framework itself will also enable clocks during hwmod |
| 969 | * init for dss, and autoidle is set in h/w for DSS. Hence, there's no |
| 970 | * need to disable clocks if their usecounts > 1. |
| 971 | */ |
| 972 | WARN_ON(dss.num_clks_enabled > 0); |
| 973 | |
| 974 | dss_put_clocks(); |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 975 | return 0; |
| 976 | } |
| 977 | |
| 978 | static struct platform_driver omap_dsshw_driver = { |
| 979 | .probe = omap_dsshw_probe, |
| 980 | .remove = omap_dsshw_remove, |
| 981 | .driver = { |
| 982 | .name = "omapdss_dss", |
| 983 | .owner = THIS_MODULE, |
| 984 | }, |
| 985 | }; |
| 986 | |
| 987 | int dss_init_platform_driver(void) |
| 988 | { |
| 989 | return platform_driver_register(&omap_dsshw_driver); |
| 990 | } |
| 991 | |
| 992 | void dss_uninit_platform_driver(void) |
| 993 | { |
| 994 | return platform_driver_unregister(&omap_dsshw_driver); |
| 995 | } |