blob: 15e8e7469ffde434cc9694722fafe9967a8d8b63 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Arun Chandran92980402014-10-10 12:31:24 +01003 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01004 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Riku Voipio957e3fa2014-12-12 16:57:44 -08005 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07006 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +01007 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +01008 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +02009 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010010 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000011 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000012 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000013 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000014 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000015 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010016 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000017 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010018 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000019 select ARM_GIC_V3_ITS if PCI_MSI
Will Deaconadace892013-05-08 17:29:24 +010020 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000021 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070022 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000023 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000024 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070025 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010026 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010027 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000028 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070029 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010030 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
Arnd Bergmanncb61f672014-11-19 14:09:07 +010032 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070033 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010034 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000035 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010037 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010038 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010040 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010041 select HAVE_ARCH_AUDITSYSCALL
Jiang Liu9732caf2014-01-07 22:17:13 +080042 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000043 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000044 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010045 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070046 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010047 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010048 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010049 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070050 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070051 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010052 select HAVE_DMA_API_DEBUG
53 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000054 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010055 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000056 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010057 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090058 select HAVE_FUNCTION_TRACER
59 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010060 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010061 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010062 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000063 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010064 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010065 select HAVE_PERF_REGS
66 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070067 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010068 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010069 select IRQ_DOMAIN
Catalin Marinasfea2aca2012-10-16 11:26:57 +010070 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010071 select NO_BOOTMEM
72 select OF
73 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010074 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010075 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000076 select POWER_RESET
77 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010078 select RTC_LIB
79 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070080 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070081 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010082 help
83 ARM 64-bit (AArch64) Linux support.
84
85config 64BIT
86 def_bool y
87
88config ARCH_PHYS_ADDR_T_64BIT
89 def_bool y
90
91config MMU
92 def_bool y
93
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070094config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +010095 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010096
97config STACKTRACE_SUPPORT
98 def_bool y
99
100config LOCKDEP_SUPPORT
101 def_bool y
102
103config TRACE_IRQFLAGS_SUPPORT
104 def_bool y
105
Will Deaconc209f792014-03-14 17:47:05 +0000106config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100107 def_bool y
108
109config GENERIC_HWEIGHT
110 def_bool y
111
112config GENERIC_CSUM
113 def_bool y
114
115config GENERIC_CALIBRATE_DELAY
116 def_bool y
117
Catalin Marinas19e76402014-02-27 12:09:22 +0000118config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100119 def_bool y
120
Steve Capper29e56942014-10-09 15:29:25 -0700121config HAVE_GENERIC_RCU_GUP
122 def_bool y
123
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100124config ARCH_DMA_ADDR_T_64BIT
125 def_bool y
126
127config NEED_DMA_MAP_STATE
128 def_bool y
129
130config NEED_SG_DMA_LENGTH
131 def_bool y
132
133config SWIOTLB
134 def_bool y
135
136config IOMMU_HELPER
137 def_bool SWIOTLB
138
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100139config KERNEL_MODE_NEON
140 def_bool y
141
Rob Herring92cc15f2014-04-18 17:19:59 -0500142config FIX_EARLYCON_MEM
143 def_bool y
144
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100145source "init/Kconfig"
146
147source "kernel/Kconfig.freezer"
148
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100149menu "Platform selection"
150
Alim Akhtar6f56eef2014-11-22 22:41:52 +0900151config ARCH_EXYNOS
152 bool
153 help
154 This enables support for Samsung Exynos SoC family
155
156config ARCH_EXYNOS7
157 bool "ARMv8 based Samsung Exynos7"
158 select ARCH_EXYNOS
159 select COMMON_CLK_SAMSUNG
160 select HAVE_S3C2410_WATCHDOG if WATCHDOG
161 select HAVE_S3C_RTC if RTC_CLASS
162 select PINCTRL
163 select PINCTRL_EXYNOS
164
165 help
166 This enables support for Samsung Exynos7 SoC family
167
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700168config ARCH_SEATTLE
169 bool "AMD Seattle SoC Family"
170 help
171 This enables support for AMD Seattle SOC Family
172
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530173config ARCH_THUNDER
174 bool "Cavium Inc. Thunder SoC Family"
175 help
176 This enables support for Cavium's Thunder Family of SoCs.
177
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100178config ARCH_VEXPRESS
179 bool "ARMv8 software model (Versatile Express)"
180 select ARCH_REQUIRE_GPIOLIB
181 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000182 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100183 select VEXPRESS_CONFIG
184 help
185 This enables support for the ARMv8 software model (Versatile
186 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100187
Vinayak Kale15942852013-04-24 10:06:57 +0100188config ARCH_XGENE
189 bool "AppliedMicro X-Gene SOC Family"
190 help
191 This enables support for AppliedMicro X-Gene SOC Family
192
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100193endmenu
194
195menu "Bus support"
196
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100197config PCI
198 bool "PCI support"
199 help
200 This feature enables support for PCI bus system. If you say Y
201 here, the kernel will include drivers and infrastructure code
202 to support PCI bus devices.
203
204config PCI_DOMAINS
205 def_bool PCI
206
207config PCI_DOMAINS_GENERIC
208 def_bool PCI
209
210config PCI_SYSCALL
211 def_bool PCI
212
213source "drivers/pci/Kconfig"
214source "drivers/pci/pcie/Kconfig"
215source "drivers/pci/hotplug/Kconfig"
216
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100217endmenu
218
219menu "Kernel Features"
220
Andre Przywarac0a01b82014-11-14 15:54:12 +0000221menu "ARM errata workarounds via the alternatives framework"
222
223config ARM64_ERRATUM_826319
224 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
225 default y
226 help
227 This option adds an alternative code sequence to work around ARM
228 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
229 AXI master interface and an L2 cache.
230
231 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
232 and is unable to accept a certain write via this interface, it will
233 not progress on read data presented on the read data channel and the
234 system can deadlock.
235
236 The workaround promotes data cache clean instructions to
237 data cache clean-and-invalidate.
238 Please note that this does not necessarily enable the workaround,
239 as it depends on the alternative framework, which will only patch
240 the kernel if an affected CPU is detected.
241
242 If unsure, say Y.
243
244config ARM64_ERRATUM_827319
245 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
246 default y
247 help
248 This option adds an alternative code sequence to work around ARM
249 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
250 master interface and an L2 cache.
251
252 Under certain conditions this erratum can cause a clean line eviction
253 to occur at the same time as another transaction to the same address
254 on the AMBA 5 CHI interface, which can cause data corruption if the
255 interconnect reorders the two transactions.
256
257 The workaround promotes data cache clean instructions to
258 data cache clean-and-invalidate.
259 Please note that this does not necessarily enable the workaround,
260 as it depends on the alternative framework, which will only patch
261 the kernel if an affected CPU is detected.
262
263 If unsure, say Y.
264
265config ARM64_ERRATUM_824069
266 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
267 default y
268 help
269 This option adds an alternative code sequence to work around ARM
270 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
271 to a coherent interconnect.
272
273 If a Cortex-A53 processor is executing a store or prefetch for
274 write instruction at the same time as a processor in another
275 cluster is executing a cache maintenance operation to the same
276 address, then this erratum might cause a clean cache line to be
277 incorrectly marked as dirty.
278
279 The workaround promotes data cache clean instructions to
280 data cache clean-and-invalidate.
281 Please note that this option does not necessarily enable the
282 workaround, as it depends on the alternative framework, which will
283 only patch the kernel if an affected CPU is detected.
284
285 If unsure, say Y.
286
287config ARM64_ERRATUM_819472
288 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
289 default y
290 help
291 This option adds an alternative code sequence to work around ARM
292 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
293 present when it is connected to a coherent interconnect.
294
295 If the processor is executing a load and store exclusive sequence at
296 the same time as a processor in another cluster is executing a cache
297 maintenance operation to the same address, then this erratum might
298 cause data corruption.
299
300 The workaround promotes data cache clean instructions to
301 data cache clean-and-invalidate.
302 Please note that this does not necessarily enable the workaround,
303 as it depends on the alternative framework, which will only patch
304 the kernel if an affected CPU is detected.
305
306 If unsure, say Y.
307
308config ARM64_ERRATUM_832075
309 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
310 default y
311 help
312 This option adds an alternative code sequence to work around ARM
313 erratum 832075 on Cortex-A57 parts up to r1p2.
314
315 Affected Cortex-A57 parts might deadlock when exclusive load/store
316 instructions to Write-Back memory are mixed with Device loads.
317
318 The workaround is to promote device loads to use Load-Acquire
319 semantics.
320 Please note that this does not necessarily enable the workaround,
321 as it depends on the alternative framework, which will only patch
322 the kernel if an affected CPU is detected.
323
324 If unsure, say Y.
325
326endmenu
327
328
Jungseok Leee41ceed2014-05-12 10:40:38 +0100329choice
330 prompt "Page size"
331 default ARM64_4K_PAGES
332 help
333 Page size (translation granule) configuration.
334
335config ARM64_4K_PAGES
336 bool "4KB"
337 help
338 This feature enables 4KB pages support.
339
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100340config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100341 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100342 help
343 This feature enables 64KB pages support (4KB by default)
344 allowing only two levels of page tables and faster TLB
345 look-up. AArch32 emulation is not available when this feature
346 is enabled.
347
Jungseok Leee41ceed2014-05-12 10:40:38 +0100348endchoice
349
350choice
351 prompt "Virtual address space size"
352 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
353 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
354 help
355 Allows choosing one of multiple possible virtual address
356 space sizes. The level of translation table is determined by
357 a combination of page size and virtual address space size.
358
359config ARM64_VA_BITS_39
360 bool "39-bit"
361 depends on ARM64_4K_PAGES
362
363config ARM64_VA_BITS_42
364 bool "42-bit"
365 depends on ARM64_64K_PAGES
366
Jungseok Leec79b9542014-05-12 18:40:51 +0900367config ARM64_VA_BITS_48
368 bool "48-bit"
Christoffer Dall04f905a2014-10-10 11:14:30 +0100369 depends on !ARM_SMMU
Jungseok Leec79b9542014-05-12 18:40:51 +0900370
Jungseok Leee41ceed2014-05-12 10:40:38 +0100371endchoice
372
373config ARM64_VA_BITS
374 int
375 default 39 if ARM64_VA_BITS_39
376 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900377 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100378
Catalin Marinasabe669d2014-07-15 15:37:21 +0100379config ARM64_PGTABLE_LEVELS
380 int
381 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
Catalin Marinas383c2792014-07-21 15:54:50 +0100382 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
Catalin Marinasabe669d2014-07-15 15:37:21 +0100383 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
384 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
Jungseok Leec79b9542014-05-12 18:40:51 +0900385
Will Deacona8720132013-10-11 14:52:19 +0100386config CPU_BIG_ENDIAN
387 bool "Build big-endian kernel"
388 help
389 Say Y if you plan on running a kernel in big-endian mode.
390
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100391config SMP
392 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100393 help
394 This enables support for systems with more than one CPU. If
395 you say N here, the kernel will run on single and
396 multiprocessor machines, but will use only one CPU of a
397 multiprocessor machine. If you say Y here, the kernel will run
398 on many, but not all, single processor machines. On a single
399 processor machine, the kernel will run faster if you say N
400 here.
401
402 If you don't know what to do here, say N.
403
Mark Brownf6e763b2014-03-04 07:51:17 +0000404config SCHED_MC
405 bool "Multi-core scheduler support"
406 depends on SMP
407 help
408 Multi-core scheduler support improves the CPU scheduler's decision
409 making when dealing with multi-core CPU chips at a cost of slightly
410 increased overhead in some places. If unsure say N here.
411
412config SCHED_SMT
413 bool "SMT scheduler support"
414 depends on SMP
415 help
416 Improves the CPU scheduler's decision making when dealing with
417 MultiThreading at a cost of slightly increased overhead in some
418 places. If unsure say N here.
419
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100420config NR_CPUS
Robert Richtere3672642014-09-08 12:44:48 +0100421 int "Maximum number of CPUs (2-64)"
422 range 2 64
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100423 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100424 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100425 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100426
Mark Rutland9327e2c2013-10-24 20:30:18 +0100427config HOTPLUG_CPU
428 bool "Support for hot-pluggable CPUs"
429 depends on SMP
430 help
431 Say Y here to experiment with turning CPUs off and on. CPUs
432 can be controlled through /sys/devices/system/cpu.
433
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100434source kernel/Kconfig.preempt
435
436config HZ
437 int
438 default 100
439
440config ARCH_HAS_HOLES_MEMORYMODEL
441 def_bool y if SPARSEMEM
442
443config ARCH_SPARSEMEM_ENABLE
444 def_bool y
445 select SPARSEMEM_VMEMMAP_ENABLE
446
447config ARCH_SPARSEMEM_DEFAULT
448 def_bool ARCH_SPARSEMEM_ENABLE
449
450config ARCH_SELECT_MEMORY_MODEL
451 def_bool ARCH_SPARSEMEM_ENABLE
452
453config HAVE_ARCH_PFN_VALID
454 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
455
456config HW_PERF_EVENTS
457 bool "Enable hardware performance counter support for perf events"
458 depends on PERF_EVENTS
459 default y
460 help
461 Enable hardware performance counter support for perf events. If
462 disabled, perf events will use software events only.
463
Steve Capper084bd292013-04-10 13:48:00 +0100464config SYS_SUPPORTS_HUGETLBFS
465 def_bool y
466
467config ARCH_WANT_GENERAL_HUGETLB
468 def_bool y
469
470config ARCH_WANT_HUGE_PMD_SHARE
471 def_bool y if !ARM64_64K_PAGES
472
Steve Capperaf074842013-04-19 16:23:57 +0100473config HAVE_ARCH_TRANSPARENT_HUGEPAGE
474 def_bool y
475
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100476config ARCH_HAS_CACHE_LINE_SIZE
477 def_bool y
478
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100479source "mm/Kconfig"
480
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000481config SECCOMP
482 bool "Enable seccomp to safely compute untrusted bytecode"
483 ---help---
484 This kernel feature is useful for number crunching applications
485 that may need to compute untrusted bytecode during their
486 execution. By using pipes or other transports made available to
487 the process as file descriptors supporting the read/write
488 syscalls, it's possible to isolate those applications in
489 their own address space using seccomp. Once seccomp is
490 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
491 and the task is only allowed to execute a few safe syscalls
492 defined by each seccomp mode.
493
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000494config XEN_DOM0
495 def_bool y
496 depends on XEN
497
498config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700499 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000500 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000501 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000502 help
503 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
504
Steve Capperd03bb142013-04-25 15:19:21 +0100505config FORCE_MAX_ZONEORDER
506 int
507 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
508 default "11"
509
Will Deacon1b907f42014-11-20 16:51:10 +0000510menuconfig ARMV8_DEPRECATED
511 bool "Emulate deprecated/obsolete ARMv8 instructions"
512 depends on COMPAT
513 help
514 Legacy software support may require certain instructions
515 that have been deprecated or obsoleted in the architecture.
516
517 Enable this config to enable selective emulation of these
518 features.
519
520 If unsure, say Y
521
522if ARMV8_DEPRECATED
523
524config SWP_EMULATION
525 bool "Emulate SWP/SWPB instructions"
526 help
527 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
528 they are always undefined. Say Y here to enable software
529 emulation of these instructions for userspace using LDXR/STXR.
530
531 In some older versions of glibc [<=2.8] SWP is used during futex
532 trylock() operations with the assumption that the code will not
533 be preempted. This invalid assumption may be more likely to fail
534 with SWP emulation enabled, leading to deadlock of the user
535 application.
536
537 NOTE: when accessing uncached shared regions, LDXR/STXR rely
538 on an external transaction monitoring block called a global
539 monitor to maintain update atomicity. If your system does not
540 implement a global monitor, this option can cause programs that
541 perform SWP operations to uncached memory to deadlock.
542
543 If unsure, say Y
544
545config CP15_BARRIER_EMULATION
546 bool "Emulate CP15 Barrier instructions"
547 help
548 The CP15 barrier instructions - CP15ISB, CP15DSB, and
549 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
550 strongly recommended to use the ISB, DSB, and DMB
551 instructions instead.
552
553 Say Y here to enable software emulation of these
554 instructions for AArch32 userspace code. When this option is
555 enabled, CP15 barrier usage is traced which can help
556 identify software that needs updating.
557
558 If unsure, say Y
559
560endif
561
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100562endmenu
563
564menu "Boot options"
565
566config CMDLINE
567 string "Default kernel command string"
568 default ""
569 help
570 Provide a set of default command-line options at build time by
571 entering them here. As a minimum, you should specify the the
572 root device (e.g. root=/dev/nfs).
573
574config CMDLINE_FORCE
575 bool "Always use the default kernel command string"
576 help
577 Always use the default kernel command string, even if the boot
578 loader passes other arguments to the kernel.
579 This is useful if you cannot or don't want to change the
580 command-line options your boot loader passes to the kernel.
581
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200582config EFI_STUB
583 bool
584
Mark Salterf84d0272014-04-15 21:59:30 -0400585config EFI
586 bool "UEFI runtime support"
587 depends on OF && !CPU_BIG_ENDIAN
588 select LIBFDT
589 select UCS2_STRING
590 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200591 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200592 select EFI_STUB
593 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400594 default y
595 help
596 This option provides support for runtime services provided
597 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400598 clock, and platform reset). A UEFI stub is also provided to
599 allow the kernel to be booted as an EFI application. This
600 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400601
Yi Lid1ae8c02014-10-04 23:46:43 +0800602config DMI
603 bool "Enable support for SMBIOS (DMI) tables"
604 depends on EFI
605 default y
606 help
607 This enables SMBIOS/DMI feature for systems.
608
609 This option is only useful on systems that have UEFI firmware.
610 However, even with this option, the resultant kernel should
611 continue to boot on existing non-UEFI platforms.
612
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100613endmenu
614
615menu "Userspace binary formats"
616
617source "fs/Kconfig.binfmt"
618
619config COMPAT
620 bool "Kernel support for 32-bit EL0"
621 depends on !ARM64_64K_PAGES
622 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700623 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500624 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500625 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100626 help
627 This option enables support for a 32-bit EL0 running under a 64-bit
628 kernel at EL1. AArch32-specific components such as system calls,
629 the user helper functions, VFP support and the ptrace interface are
630 handled appropriately by the kernel.
631
632 If you want to execute 32-bit userspace applications, say Y.
633
634config SYSVIPC_COMPAT
635 def_bool y
636 depends on COMPAT && SYSVIPC
637
638endmenu
639
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000640menu "Power management options"
641
642source "kernel/power/Kconfig"
643
644config ARCH_SUSPEND_POSSIBLE
645 def_bool y
646
647config ARM64_CPU_SUSPEND
648 def_bool PM_SLEEP
649
650endmenu
651
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100652menu "CPU Power Management"
653
654source "drivers/cpuidle/Kconfig"
655
Rob Herring52e7e812014-02-24 11:27:57 +0900656source "drivers/cpufreq/Kconfig"
657
658endmenu
659
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100660source "net/Kconfig"
661
662source "drivers/Kconfig"
663
Mark Salterf84d0272014-04-15 21:59:30 -0400664source "drivers/firmware/Kconfig"
665
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100666source "fs/Kconfig"
667
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100668source "arch/arm64/kvm/Kconfig"
669
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100670source "arch/arm64/Kconfig.debug"
671
672source "security/Kconfig"
673
674source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800675if CRYPTO
676source "arch/arm64/crypto/Kconfig"
677endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100678
679source "lib/Kconfig"