Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/delay.h> |
| 14 | #include <linux/highmem.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/dma-mapping.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/scatterlist.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/blkdev.h> |
| 22 | |
| 23 | #include <linux/mmc/mmc.h> |
| 24 | #include <linux/mmc/host.h> |
| 25 | #include <linux/mmc/card.h> |
| 26 | |
| 27 | #include "cmdq_hci.h" |
| 28 | |
| 29 | #define DCMD_SLOT 31 |
| 30 | #define NUM_SLOTS 32 |
| 31 | |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 32 | /* 1 sec */ |
| 33 | #define HALT_TIMEOUT_MS 1000 |
| 34 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 35 | static inline struct mmc_request *get_req_by_tag(struct cmdq_host *cq_host, |
| 36 | unsigned int tag) |
| 37 | { |
| 38 | return cq_host->mrq_slot[tag]; |
| 39 | } |
| 40 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 41 | static inline u8 *get_desc(struct cmdq_host *cq_host, u8 tag) |
| 42 | { |
| 43 | return cq_host->desc_base + (tag * cq_host->slot_sz); |
| 44 | } |
| 45 | |
| 46 | static inline u8 *get_link_desc(struct cmdq_host *cq_host, u8 tag) |
| 47 | { |
| 48 | u8 *desc = get_desc(cq_host, tag); |
| 49 | |
| 50 | return desc + cq_host->task_desc_len; |
| 51 | } |
| 52 | |
| 53 | static inline dma_addr_t get_trans_desc_dma(struct cmdq_host *cq_host, u8 tag) |
| 54 | { |
| 55 | return cq_host->trans_desc_dma_base + |
| 56 | (cq_host->mmc->max_segs * tag * |
| 57 | cq_host->trans_desc_len); |
| 58 | } |
| 59 | |
| 60 | static inline u8 *get_trans_desc(struct cmdq_host *cq_host, u8 tag) |
| 61 | { |
| 62 | return cq_host->trans_desc_base + |
| 63 | (cq_host->trans_desc_len * cq_host->mmc->max_segs * tag); |
| 64 | } |
| 65 | |
| 66 | static void setup_trans_desc(struct cmdq_host *cq_host, u8 tag) |
| 67 | { |
| 68 | u8 *link_temp; |
| 69 | dma_addr_t trans_temp; |
| 70 | |
| 71 | link_temp = get_link_desc(cq_host, tag); |
| 72 | trans_temp = get_trans_desc_dma(cq_host, tag); |
| 73 | |
| 74 | memset(link_temp, 0, cq_host->link_desc_len); |
| 75 | if (cq_host->link_desc_len > 8) |
| 76 | *(link_temp + 8) = 0; |
| 77 | |
| 78 | if (tag == DCMD_SLOT) { |
| 79 | *link_temp = VALID(0) | ACT(0) | END(1); |
| 80 | return; |
| 81 | } |
| 82 | |
| 83 | *link_temp = VALID(1) | ACT(0x6) | END(0); |
| 84 | |
| 85 | if (cq_host->dma64) { |
| 86 | __le64 *data_addr = (__le64 __force *)(link_temp + 4); |
| 87 | data_addr[0] = cpu_to_le64(trans_temp); |
| 88 | } else { |
| 89 | __le32 *data_addr = (__le32 __force *)(link_temp + 4); |
| 90 | data_addr[0] = cpu_to_le32(trans_temp); |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | static void cmdq_clear_set_irqs(struct cmdq_host *cq_host, u32 clear, u32 set) |
| 95 | { |
| 96 | u32 ier; |
| 97 | |
| 98 | ier = cmdq_readl(cq_host, CQISTE); |
| 99 | ier &= ~clear; |
| 100 | ier |= set; |
| 101 | cmdq_writel(cq_host, ier, CQISTE); |
| 102 | cmdq_writel(cq_host, ier, CQISGE); |
| 103 | /* ensure the writes are done */ |
| 104 | mb(); |
| 105 | } |
| 106 | |
| 107 | |
| 108 | #define DRV_NAME "cmdq-host" |
| 109 | |
| 110 | static void cmdq_dump_debug_ram(struct cmdq_host *cq_host) |
| 111 | { |
| 112 | int i = 0; |
| 113 | |
| 114 | pr_err("---- Debug RAM dump ----\n"); |
| 115 | pr_err(DRV_NAME ": Debug RAM wrap-around: 0x%08x | Debug RAM overlap: 0x%08x\n", |
| 116 | cmdq_readl(cq_host, CQ_CMD_DBG_RAM_WA), |
| 117 | cmdq_readl(cq_host, CQ_CMD_DBG_RAM_OL)); |
| 118 | |
| 119 | while (i < 16) { |
| 120 | pr_err(DRV_NAME ": Debug RAM dump [%d]: 0x%08x\n", i, |
| 121 | cmdq_readl(cq_host, CQ_CMD_DBG_RAM + (0x4 * i))); |
| 122 | i++; |
| 123 | } |
| 124 | pr_err("-------------------------\n"); |
| 125 | } |
| 126 | |
| 127 | static void cmdq_dumpregs(struct cmdq_host *cq_host) |
| 128 | { |
| 129 | struct mmc_host *mmc = cq_host->mmc; |
| 130 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 131 | pr_err(DRV_NAME ": ========== REGISTER DUMP (%s)==========\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 132 | mmc_hostname(mmc)); |
| 133 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 134 | pr_err(DRV_NAME ": Caps: 0x%08x | Version: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 135 | cmdq_readl(cq_host, CQCAP), |
| 136 | cmdq_readl(cq_host, CQVER)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 137 | pr_err(DRV_NAME ": Queing config: 0x%08x | Queue Ctrl: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 138 | cmdq_readl(cq_host, CQCFG), |
| 139 | cmdq_readl(cq_host, CQCTL)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 140 | pr_err(DRV_NAME ": Int stat: 0x%08x | Int enab: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 141 | cmdq_readl(cq_host, CQIS), |
| 142 | cmdq_readl(cq_host, CQISTE)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 143 | pr_err(DRV_NAME ": Int sig: 0x%08x | Int Coal: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 144 | cmdq_readl(cq_host, CQISGE), |
| 145 | cmdq_readl(cq_host, CQIC)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 146 | pr_err(DRV_NAME ": TDL base: 0x%08x | TDL up32: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 147 | cmdq_readl(cq_host, CQTDLBA), |
| 148 | cmdq_readl(cq_host, CQTDLBAU)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 149 | pr_err(DRV_NAME ": Doorbell: 0x%08x | Comp Notif: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 150 | cmdq_readl(cq_host, CQTDBR), |
| 151 | cmdq_readl(cq_host, CQTCN)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 152 | pr_err(DRV_NAME ": Dev queue: 0x%08x | Dev Pend: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 153 | cmdq_readl(cq_host, CQDQS), |
| 154 | cmdq_readl(cq_host, CQDPT)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 155 | pr_err(DRV_NAME ": Task clr: 0x%08x | Send stat 1: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 156 | cmdq_readl(cq_host, CQTCLR), |
| 157 | cmdq_readl(cq_host, CQSSC1)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 158 | pr_err(DRV_NAME ": Send stat 2: 0x%08x | DCMD resp: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 159 | cmdq_readl(cq_host, CQSSC2), |
| 160 | cmdq_readl(cq_host, CQCRDCT)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 161 | pr_err(DRV_NAME ": Resp err mask: 0x%08x | Task err: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 162 | cmdq_readl(cq_host, CQRMEM), |
| 163 | cmdq_readl(cq_host, CQTERRI)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 164 | pr_err(DRV_NAME ": Resp idx 0x%08x | Resp arg: 0x%08x\n", |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 165 | cmdq_readl(cq_host, CQCRI), |
| 166 | cmdq_readl(cq_host, CQCRA)); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 167 | pr_err(DRV_NAME ": ===========================================\n"); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 168 | |
| 169 | cmdq_dump_debug_ram(cq_host); |
| 170 | if (cq_host->ops->dump_vendor_regs) |
| 171 | cq_host->ops->dump_vendor_regs(mmc); |
| 172 | } |
| 173 | |
| 174 | /** |
| 175 | * The allocated descriptor table for task, link & transfer descritors |
| 176 | * looks like: |
| 177 | * |----------| |
| 178 | * |task desc | |->|----------| |
| 179 | * |----------| | |trans desc| |
| 180 | * |link desc-|->| |----------| |
| 181 | * |----------| . |
| 182 | * . . |
| 183 | * no. of slots max-segs |
| 184 | * . |----------| |
| 185 | * |----------| |
| 186 | * The idea here is to create the [task+trans] table and mark & point the |
| 187 | * link desc to the transfer desc table on a per slot basis. |
| 188 | */ |
| 189 | static int cmdq_host_alloc_tdl(struct cmdq_host *cq_host) |
| 190 | { |
| 191 | |
| 192 | size_t desc_size; |
| 193 | size_t data_size; |
| 194 | int i = 0; |
| 195 | |
| 196 | /* task descriptor can be 64/128 bit irrespective of arch */ |
| 197 | if (cq_host->caps & CMDQ_TASK_DESC_SZ_128) { |
| 198 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCFG) | |
| 199 | CQ_TASK_DESC_SZ, CQCFG); |
| 200 | cq_host->task_desc_len = 16; |
| 201 | } else { |
| 202 | cq_host->task_desc_len = 8; |
| 203 | } |
| 204 | |
| 205 | /* |
| 206 | * 96 bits length of transfer desc instead of 128 bits which means |
| 207 | * ADMA would expect next valid descriptor at the 96th bit |
| 208 | * or 128th bit |
| 209 | */ |
| 210 | if (cq_host->dma64) { |
| 211 | if (cq_host->quirks & CMDQ_QUIRK_SHORT_TXFR_DESC_SZ) |
| 212 | cq_host->trans_desc_len = 12; |
| 213 | else |
| 214 | cq_host->trans_desc_len = 16; |
| 215 | cq_host->link_desc_len = 16; |
| 216 | } else { |
| 217 | cq_host->trans_desc_len = 8; |
| 218 | cq_host->link_desc_len = 8; |
| 219 | } |
| 220 | |
| 221 | /* total size of a slot: 1 task & 1 transfer (link) */ |
| 222 | cq_host->slot_sz = cq_host->task_desc_len + cq_host->link_desc_len; |
| 223 | |
| 224 | desc_size = cq_host->slot_sz * cq_host->num_slots; |
| 225 | |
| 226 | data_size = cq_host->trans_desc_len * cq_host->mmc->max_segs * |
| 227 | (cq_host->num_slots - 1); |
| 228 | |
| 229 | pr_info("%s: desc_size: %d data_sz: %d slot-sz: %d\n", __func__, |
| 230 | (int)desc_size, (int)data_size, cq_host->slot_sz); |
| 231 | |
| 232 | /* |
| 233 | * allocate a dma-mapped chunk of memory for the descriptors |
| 234 | * allocate a dma-mapped chunk of memory for link descriptors |
| 235 | * setup each link-desc memory offset per slot-number to |
| 236 | * the descriptor table. |
| 237 | */ |
| 238 | cq_host->desc_base = dmam_alloc_coherent(mmc_dev(cq_host->mmc), |
| 239 | desc_size, |
| 240 | &cq_host->desc_dma_base, |
| 241 | GFP_KERNEL); |
| 242 | cq_host->trans_desc_base = dmam_alloc_coherent(mmc_dev(cq_host->mmc), |
| 243 | data_size, |
| 244 | &cq_host->trans_desc_dma_base, |
| 245 | GFP_KERNEL); |
| 246 | if (!cq_host->desc_base || !cq_host->trans_desc_base) |
| 247 | return -ENOMEM; |
| 248 | |
| 249 | pr_info("desc-base: 0x%p trans-base: 0x%p\n desc_dma 0x%llx trans_dma: 0x%llx\n", |
| 250 | cq_host->desc_base, cq_host->trans_desc_base, |
| 251 | (unsigned long long)cq_host->desc_dma_base, |
| 252 | (unsigned long long) cq_host->trans_desc_dma_base); |
| 253 | |
| 254 | for (; i < (cq_host->num_slots); i++) |
| 255 | setup_trans_desc(cq_host, i); |
| 256 | |
| 257 | return 0; |
| 258 | } |
| 259 | |
| 260 | static int cmdq_enable(struct mmc_host *mmc) |
| 261 | { |
| 262 | int err = 0; |
| 263 | u32 cqcfg; |
| 264 | bool dcmd_enable; |
| 265 | struct cmdq_host *cq_host = mmc_cmdq_private(mmc); |
| 266 | |
| 267 | if (!cq_host || !mmc->card || !mmc_card_cmdq(mmc->card)) { |
| 268 | err = -EINVAL; |
| 269 | goto out; |
| 270 | } |
| 271 | |
| 272 | if (cq_host->enabled) |
| 273 | goto out; |
| 274 | |
| 275 | cqcfg = cmdq_readl(cq_host, CQCFG); |
| 276 | if (cqcfg & 0x1) { |
| 277 | pr_info("%s: %s: cq_host is already enabled\n", |
| 278 | mmc_hostname(mmc), __func__); |
| 279 | WARN_ON(1); |
| 280 | goto out; |
| 281 | } |
| 282 | |
| 283 | if (cq_host->quirks & CMDQ_QUIRK_NO_DCMD) |
| 284 | dcmd_enable = false; |
| 285 | else |
| 286 | dcmd_enable = true; |
| 287 | |
| 288 | cqcfg = ((cq_host->caps & CMDQ_TASK_DESC_SZ_128 ? CQ_TASK_DESC_SZ : 0) | |
| 289 | (dcmd_enable ? CQ_DCMD : 0)); |
| 290 | |
| 291 | cmdq_writel(cq_host, cqcfg, CQCFG); |
| 292 | /* enable CQ_HOST */ |
| 293 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCFG) | CQ_ENABLE, |
| 294 | CQCFG); |
| 295 | |
| 296 | if (!cq_host->desc_base || |
| 297 | !cq_host->trans_desc_base) { |
| 298 | err = cmdq_host_alloc_tdl(cq_host); |
| 299 | if (err) |
| 300 | goto out; |
| 301 | cmdq_writel(cq_host, lower_32_bits(cq_host->desc_dma_base), |
| 302 | CQTDLBA); |
| 303 | cmdq_writel(cq_host, upper_32_bits(cq_host->desc_dma_base), |
| 304 | CQTDLBAU); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | /* |
| 308 | * disable all vendor interrupts |
| 309 | * enable CMDQ interrupts |
| 310 | * enable the vendor error interrupts |
| 311 | */ |
| 312 | if (cq_host->ops->clear_set_irqs) |
| 313 | cq_host->ops->clear_set_irqs(mmc, true); |
| 314 | |
| 315 | cmdq_clear_set_irqs(cq_host, 0x0, CQ_INT_ALL); |
| 316 | |
| 317 | /* cq_host would use this rca to address the card */ |
| 318 | cmdq_writel(cq_host, mmc->card->rca, CQSSC2); |
| 319 | |
| 320 | /* send QSR at lesser intervals than the default */ |
| 321 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQSSC1) | SEND_QSR_INTERVAL, |
| 322 | CQSSC1); |
| 323 | |
| 324 | /* ensure the writes are done before enabling CQE */ |
| 325 | mb(); |
| 326 | |
| 327 | cq_host->enabled = true; |
| 328 | |
| 329 | if (cq_host->ops->set_block_size) |
| 330 | cq_host->ops->set_block_size(cq_host->mmc); |
| 331 | |
| 332 | if (cq_host->ops->set_data_timeout) |
| 333 | cq_host->ops->set_data_timeout(mmc, 0xf); |
| 334 | |
| 335 | if (cq_host->ops->clear_set_dumpregs) |
| 336 | cq_host->ops->clear_set_dumpregs(mmc, 1); |
| 337 | |
| 338 | out: |
| 339 | return err; |
| 340 | } |
| 341 | |
| 342 | static void cmdq_disable(struct mmc_host *mmc, bool soft) |
| 343 | { |
| 344 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 345 | |
| 346 | if (soft) { |
| 347 | cmdq_writel(cq_host, cmdq_readl( |
| 348 | cq_host, CQCFG) & ~(CQ_ENABLE), |
| 349 | CQCFG); |
| 350 | } |
| 351 | |
| 352 | cq_host->enabled = false; |
| 353 | } |
| 354 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 355 | static void cmdq_reset(struct mmc_host *mmc, bool soft) |
| 356 | { |
| 357 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 358 | unsigned int cqcfg; |
| 359 | unsigned int tdlba; |
| 360 | unsigned int tdlbau; |
| 361 | unsigned int rca; |
| 362 | int ret; |
| 363 | |
| 364 | cqcfg = cmdq_readl(cq_host, CQCFG); |
| 365 | tdlba = cmdq_readl(cq_host, CQTDLBA); |
| 366 | tdlbau = cmdq_readl(cq_host, CQTDLBAU); |
| 367 | rca = cmdq_readl(cq_host, CQSSC2); |
| 368 | |
| 369 | cmdq_disable(mmc, true); |
| 370 | |
| 371 | if (cq_host->ops->reset) { |
| 372 | ret = cq_host->ops->reset(mmc); |
| 373 | if (ret) { |
| 374 | pr_crit("%s: reset CMDQ controller: failed\n", |
| 375 | mmc_hostname(mmc)); |
| 376 | BUG(); |
| 377 | } |
| 378 | } |
| 379 | |
| 380 | cmdq_writel(cq_host, tdlba, CQTDLBA); |
| 381 | cmdq_writel(cq_host, tdlbau, CQTDLBAU); |
| 382 | |
| 383 | if (cq_host->ops->clear_set_irqs) |
| 384 | cq_host->ops->clear_set_irqs(mmc, true); |
| 385 | |
| 386 | cmdq_clear_set_irqs(cq_host, 0x0, CQ_INT_ALL); |
| 387 | |
| 388 | /* cq_host would use this rca to address the card */ |
| 389 | cmdq_writel(cq_host, rca, CQSSC2); |
| 390 | |
| 391 | /* ensure the writes are done before enabling CQE */ |
| 392 | mb(); |
| 393 | |
| 394 | cmdq_writel(cq_host, cqcfg, CQCFG); |
| 395 | cq_host->enabled = true; |
| 396 | } |
| 397 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 398 | static void cmdq_prep_task_desc(struct mmc_request *mrq, |
| 399 | u64 *data, bool intr, bool qbr) |
| 400 | { |
| 401 | struct mmc_cmdq_req *cmdq_req = mrq->cmdq_req; |
| 402 | u32 req_flags = cmdq_req->cmdq_req_flags; |
| 403 | |
| 404 | pr_debug("%s: %s: data-tag: 0x%08x - dir: %d - prio: %d - cnt: 0x%08x - addr: 0x%llx\n", |
| 405 | mmc_hostname(mrq->host), __func__, |
| 406 | !!(req_flags & DAT_TAG), !!(req_flags & DIR), |
| 407 | !!(req_flags & PRIO), cmdq_req->data.blocks, |
| 408 | (u64)mrq->cmdq_req->blk_addr); |
| 409 | |
| 410 | *data = VALID(1) | |
| 411 | END(1) | |
| 412 | INT(intr) | |
| 413 | ACT(0x5) | |
| 414 | FORCED_PROG(!!(req_flags & FORCED_PRG)) | |
| 415 | CONTEXT(mrq->cmdq_req->ctx_id) | |
| 416 | DATA_TAG(!!(req_flags & DAT_TAG)) | |
| 417 | DATA_DIR(!!(req_flags & DIR)) | |
| 418 | PRIORITY(!!(req_flags & PRIO)) | |
| 419 | QBAR(qbr) | |
| 420 | REL_WRITE(!!(req_flags & REL_WR)) | |
| 421 | BLK_COUNT(mrq->cmdq_req->data.blocks) | |
| 422 | BLK_ADDR((u64)mrq->cmdq_req->blk_addr); |
| 423 | } |
| 424 | |
| 425 | static int cmdq_dma_map(struct mmc_host *host, struct mmc_request *mrq) |
| 426 | { |
| 427 | int sg_count; |
| 428 | struct mmc_data *data = mrq->data; |
| 429 | |
| 430 | if (!data) |
| 431 | return -EINVAL; |
| 432 | |
| 433 | sg_count = dma_map_sg(mmc_dev(host), data->sg, |
| 434 | data->sg_len, |
| 435 | (data->flags & MMC_DATA_WRITE) ? |
| 436 | DMA_TO_DEVICE : DMA_FROM_DEVICE); |
| 437 | if (!sg_count) { |
| 438 | pr_err("%s: sg-len: %d\n", __func__, data->sg_len); |
| 439 | return -ENOMEM; |
| 440 | } |
| 441 | |
| 442 | return sg_count; |
| 443 | } |
| 444 | |
| 445 | static void cmdq_set_tran_desc(u8 *desc, |
| 446 | dma_addr_t addr, int len, bool end) |
| 447 | { |
| 448 | __le64 *dataddr = (__le64 __force *)(desc + 4); |
| 449 | __le32 *attr = (__le32 __force *)desc; |
| 450 | |
| 451 | *attr = (VALID(1) | |
| 452 | END(end ? 1 : 0) | |
| 453 | INT(0) | |
| 454 | ACT(0x4) | |
| 455 | DAT_LENGTH(len)); |
| 456 | |
| 457 | dataddr[0] = cpu_to_le64(addr); |
| 458 | } |
| 459 | |
| 460 | static int cmdq_prep_tran_desc(struct mmc_request *mrq, |
| 461 | struct cmdq_host *cq_host, int tag) |
| 462 | { |
| 463 | struct mmc_data *data = mrq->data; |
| 464 | int i, sg_count, len; |
| 465 | bool end = false; |
| 466 | dma_addr_t addr; |
| 467 | u8 *desc; |
| 468 | struct scatterlist *sg; |
| 469 | |
| 470 | sg_count = cmdq_dma_map(mrq->host, mrq); |
| 471 | if (sg_count < 0) { |
| 472 | pr_err("%s: %s: unable to map sg lists, %d\n", |
| 473 | mmc_hostname(mrq->host), __func__, sg_count); |
| 474 | return sg_count; |
| 475 | } |
| 476 | |
| 477 | desc = get_trans_desc(cq_host, tag); |
| 478 | memset(desc, 0, cq_host->trans_desc_len * cq_host->mmc->max_segs); |
| 479 | |
| 480 | for_each_sg(data->sg, sg, sg_count, i) { |
| 481 | addr = sg_dma_address(sg); |
| 482 | len = sg_dma_len(sg); |
| 483 | |
| 484 | if ((i+1) == sg_count) |
| 485 | end = true; |
| 486 | cmdq_set_tran_desc(desc, addr, len, end); |
| 487 | desc += cq_host->trans_desc_len; |
| 488 | } |
| 489 | |
| 490 | pr_debug("%s: req: 0x%p tag: %d calc_trans_des: 0x%p sg-cnt: %d\n", |
| 491 | __func__, mrq->req, tag, desc, sg_count); |
| 492 | |
| 493 | return 0; |
| 494 | } |
| 495 | |
| 496 | static void cmdq_prep_dcmd_desc(struct mmc_host *mmc, |
| 497 | struct mmc_request *mrq) |
| 498 | { |
| 499 | u64 *task_desc = NULL; |
| 500 | u64 data = 0; |
| 501 | u8 resp_type; |
| 502 | u8 *desc; |
| 503 | __le64 *dataddr; |
| 504 | struct cmdq_host *cq_host = mmc_cmdq_private(mmc); |
| 505 | u8 timing; |
| 506 | |
| 507 | if (!(mrq->cmd->flags & MMC_RSP_PRESENT)) { |
| 508 | resp_type = 0x0; |
| 509 | timing = 0x1; |
| 510 | } else { |
Sahitya Tummala | 72bd840 | 2015-05-29 13:27:38 +0530 | [diff] [blame^] | 511 | if (mrq->cmd->flags & MMC_RSP_BUSY) { |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 512 | resp_type = 0x3; |
| 513 | timing = 0x0; |
| 514 | } else { |
| 515 | resp_type = 0x2; |
| 516 | timing = 0x1; |
| 517 | } |
| 518 | } |
| 519 | |
| 520 | task_desc = (__le64 __force *)get_desc(cq_host, cq_host->dcmd_slot); |
| 521 | memset(task_desc, 0, cq_host->task_desc_len); |
| 522 | data |= (VALID(1) | |
| 523 | END(1) | |
| 524 | INT(1) | |
| 525 | QBAR(1) | |
| 526 | ACT(0x5) | |
| 527 | CMD_INDEX(mrq->cmd->opcode) | |
| 528 | CMD_TIMING(timing) | RESP_TYPE(resp_type)); |
| 529 | *task_desc |= data; |
| 530 | desc = (u8 *)task_desc; |
| 531 | pr_debug("cmdq: dcmd: cmd: %d timing: %d resp: %d\n", |
| 532 | mrq->cmd->opcode, timing, resp_type); |
| 533 | dataddr = (__le64 __force *)(desc + 4); |
| 534 | dataddr[0] = cpu_to_le64((u64)mrq->cmd->arg); |
| 535 | |
| 536 | } |
| 537 | |
| 538 | static int cmdq_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 539 | { |
| 540 | int err; |
| 541 | u64 data = 0; |
| 542 | u64 *task_desc = NULL; |
| 543 | u32 tag = mrq->cmdq_req->tag; |
| 544 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 545 | |
| 546 | if (!cq_host->enabled) { |
| 547 | pr_err("%s: CMDQ host not enabled yet !!!\n", |
| 548 | mmc_hostname(mmc)); |
| 549 | err = -EINVAL; |
| 550 | goto out; |
| 551 | } |
| 552 | |
| 553 | if (mrq->cmdq_req->cmdq_req_flags & DCMD) { |
| 554 | cmdq_prep_dcmd_desc(mmc, mrq); |
| 555 | cq_host->mrq_slot[DCMD_SLOT] = mrq; |
| 556 | cmdq_writel(cq_host, 1 << DCMD_SLOT, CQTDBR); |
| 557 | return 0; |
| 558 | } |
| 559 | |
| 560 | task_desc = (__le64 __force *)get_desc(cq_host, tag); |
| 561 | |
| 562 | cmdq_prep_task_desc(mrq, &data, 1, |
| 563 | (mrq->cmdq_req->cmdq_req_flags & QBR)); |
| 564 | *task_desc = cpu_to_le64(data); |
| 565 | |
| 566 | err = cmdq_prep_tran_desc(mrq, cq_host, tag); |
| 567 | if (err) { |
| 568 | pr_err("%s: %s: failed to setup tx desc: %d\n", |
| 569 | mmc_hostname(mmc), __func__, err); |
| 570 | return err; |
| 571 | } |
| 572 | |
| 573 | BUG_ON(cmdq_readl(cq_host, CQTDBR) & (1 << tag)); |
| 574 | |
| 575 | cq_host->mrq_slot[tag] = mrq; |
| 576 | if (cq_host->ops->set_tranfer_params) |
| 577 | cq_host->ops->set_tranfer_params(mmc); |
| 578 | |
| 579 | cmdq_writel(cq_host, 1 << tag, CQTDBR); |
| 580 | |
| 581 | out: |
| 582 | return err; |
| 583 | } |
| 584 | |
| 585 | static void cmdq_finish_data(struct mmc_host *mmc, unsigned int tag) |
| 586 | { |
| 587 | struct mmc_request *mrq; |
| 588 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 589 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 590 | mrq = get_req_by_tag(cq_host, tag); |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 591 | mrq->done(mrq); |
| 592 | } |
| 593 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 594 | irqreturn_t cmdq_irq(struct mmc_host *mmc, int err) |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 595 | { |
| 596 | u32 status; |
| 597 | unsigned long tag = 0, comp_status; |
| 598 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 599 | unsigned long err_info = 0; |
| 600 | struct mmc_request *mrq; |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 601 | |
| 602 | status = cmdq_readl(cq_host, CQIS); |
| 603 | cmdq_writel(cq_host, status, CQIS); |
| 604 | |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 605 | if (!status && !err) |
| 606 | return IRQ_NONE; |
| 607 | |
| 608 | if (err || (status & CQIS_RED)) { |
| 609 | err_info = cmdq_readl(cq_host, CQTERRI); |
| 610 | pr_err("%s: err: %d status: 0x%08x task-err-info (0x%08lx)\n", |
| 611 | mmc_hostname(mmc), err, status, err_info); |
| 612 | |
| 613 | cmdq_dumpregs(cq_host); |
| 614 | |
| 615 | if (err_info & CQ_RMEFV) { |
| 616 | tag = GET_CMD_ERR_TAG(err_info); |
| 617 | pr_err("%s: CMD err tag: %lu\n", __func__, tag); |
| 618 | |
| 619 | mrq = get_req_by_tag(cq_host, tag); |
| 620 | /* CMD44/45/46/47 will not have a valid cmd */ |
| 621 | if (mrq->cmd) |
| 622 | mrq->cmd->error = err; |
| 623 | else |
| 624 | mrq->data->error = err; |
| 625 | } else { |
| 626 | tag = GET_DAT_ERR_TAG(err_info); |
| 627 | pr_err("%s: Dat err tag: %lu\n", __func__, tag); |
| 628 | mrq = get_req_by_tag(cq_host, tag); |
| 629 | mrq->data->error = err; |
| 630 | } |
| 631 | |
| 632 | tag = 0; |
| 633 | /* |
| 634 | * CQE detected a response error from device |
| 635 | * In most cases, this would require a reset. |
| 636 | */ |
| 637 | if (status & CQIS_RED) { |
| 638 | mrq->cmdq_req->resp_err = true; |
| 639 | pr_err("%s: Response error (0x%08x) from card !!!", |
| 640 | mmc_hostname(mmc), status); |
| 641 | } else { |
| 642 | mrq->cmdq_req->resp_idx = cmdq_readl(cq_host, CQCRI); |
| 643 | mrq->cmdq_req->resp_arg = cmdq_readl(cq_host, CQCRA); |
| 644 | } |
| 645 | |
| 646 | mmc->err_mrq = mrq; |
| 647 | cmdq_finish_data(mmc, tag); |
| 648 | } |
| 649 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 650 | if (status & CQIS_TCC) { |
| 651 | /* read QCTCN and complete the request */ |
| 652 | comp_status = cmdq_readl(cq_host, CQTCN); |
| 653 | if (!comp_status) |
| 654 | goto out; |
| 655 | |
| 656 | for_each_set_bit(tag, &comp_status, cq_host->num_slots) { |
| 657 | /* complete the corresponding mrq */ |
| 658 | pr_debug("%s: completing tag -> %lu\n", |
| 659 | mmc_hostname(mmc), tag); |
| 660 | cmdq_finish_data(mmc, tag); |
| 661 | } |
| 662 | cmdq_writel(cq_host, comp_status, CQTCN); |
| 663 | } |
| 664 | |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 665 | if (status & CQIS_HAC) { |
| 666 | /* halt is completed, wakeup waiting thread */ |
| 667 | complete(&cq_host->halt_comp); |
| 668 | } |
| 669 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 670 | out: |
| 671 | return IRQ_HANDLED; |
| 672 | } |
| 673 | EXPORT_SYMBOL(cmdq_irq); |
| 674 | |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 675 | /* May sleep */ |
| 676 | static int cmdq_halt(struct mmc_host *mmc, bool halt) |
| 677 | { |
| 678 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 679 | u32 val; |
| 680 | |
| 681 | if (halt) { |
| 682 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCTL) | HALT, |
| 683 | CQCTL); |
| 684 | val = wait_for_completion_timeout(&cq_host->halt_comp, |
| 685 | msecs_to_jiffies(HALT_TIMEOUT_MS)); |
| 686 | /* halt done: re-enable legacy interrupts */ |
| 687 | if (cq_host->ops->clear_set_irqs) |
| 688 | cq_host->ops->clear_set_irqs(mmc, false); |
| 689 | |
| 690 | return val ? 0 : -ETIMEDOUT; |
| 691 | } else { |
| 692 | if (cq_host->ops->clear_set_irqs) |
| 693 | cq_host->ops->clear_set_irqs(mmc, true); |
| 694 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCTL) & ~HALT, |
| 695 | CQCTL); |
| 696 | } |
| 697 | |
| 698 | return 0; |
| 699 | } |
| 700 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 701 | static void cmdq_post_req(struct mmc_host *host, struct mmc_request *mrq, |
| 702 | int err) |
| 703 | { |
| 704 | struct mmc_data *data = mrq->data; |
| 705 | |
| 706 | if (data) { |
| 707 | data->error = err; |
| 708 | dma_unmap_sg(mmc_dev(host), data->sg, data->sg_len, |
| 709 | (data->flags & MMC_DATA_READ) ? |
| 710 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 711 | if (err) |
| 712 | data->bytes_xfered = 0; |
| 713 | else |
| 714 | data->bytes_xfered = blk_rq_bytes(mrq->req); |
| 715 | } |
| 716 | } |
| 717 | |
Asutosh Das | fa8836b | 2015-03-02 23:14:05 +0530 | [diff] [blame] | 718 | static void cmdq_dumpstate(struct mmc_host *mmc) |
| 719 | { |
| 720 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 721 | |
| 722 | cmdq_dumpregs(cq_host); |
| 723 | } |
| 724 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 725 | static const struct mmc_cmdq_host_ops cmdq_host_ops = { |
| 726 | .enable = cmdq_enable, |
| 727 | .disable = cmdq_disable, |
| 728 | .request = cmdq_request, |
| 729 | .post_req = cmdq_post_req, |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame] | 730 | .halt = cmdq_halt, |
Asutosh Das | 02e3086 | 2015-05-20 16:52:04 +0530 | [diff] [blame] | 731 | .reset = cmdq_reset, |
Asutosh Das | fa8836b | 2015-03-02 23:14:05 +0530 | [diff] [blame] | 732 | .dumpstate = cmdq_dumpstate, |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 733 | }; |
| 734 | |
| 735 | struct cmdq_host *cmdq_pltfm_init(struct platform_device *pdev) |
| 736 | { |
| 737 | struct cmdq_host *cq_host; |
| 738 | struct resource *cmdq_memres = NULL; |
| 739 | |
| 740 | /* check and setup CMDQ interface */ |
| 741 | cmdq_memres = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 742 | "cmdq_mem"); |
| 743 | if (!cmdq_memres) { |
| 744 | dev_dbg(&pdev->dev, "CMDQ not supported\n"); |
| 745 | return ERR_PTR(-EINVAL); |
| 746 | } |
| 747 | |
| 748 | cq_host = kzalloc(sizeof(*cq_host), GFP_KERNEL); |
| 749 | if (!cq_host) { |
| 750 | dev_err(&pdev->dev, "failed to allocate memory for CMDQ\n"); |
| 751 | return ERR_PTR(-ENOMEM); |
| 752 | } |
| 753 | cq_host->mmio = devm_ioremap(&pdev->dev, |
| 754 | cmdq_memres->start, |
| 755 | resource_size(cmdq_memres)); |
| 756 | if (!cq_host->mmio) { |
| 757 | dev_err(&pdev->dev, "failed to remap cmdq regs\n"); |
| 758 | kfree(cq_host); |
| 759 | return ERR_PTR(-EBUSY); |
| 760 | } |
| 761 | dev_dbg(&pdev->dev, "CMDQ ioremap: done\n"); |
| 762 | |
| 763 | return cq_host; |
| 764 | } |
| 765 | EXPORT_SYMBOL(cmdq_pltfm_init); |
| 766 | |
| 767 | int cmdq_init(struct cmdq_host *cq_host, struct mmc_host *mmc, |
| 768 | bool dma64) |
| 769 | { |
| 770 | int err = 0; |
| 771 | |
| 772 | cq_host->dma64 = dma64; |
| 773 | cq_host->mmc = mmc; |
| 774 | cq_host->mmc->cmdq_private = cq_host; |
| 775 | |
| 776 | cq_host->num_slots = NUM_SLOTS; |
| 777 | cq_host->dcmd_slot = DCMD_SLOT; |
| 778 | |
| 779 | mmc->cmdq_ops = &cmdq_host_ops; |
| 780 | |
| 781 | cq_host->mrq_slot = kzalloc(sizeof(cq_host->mrq_slot) * |
| 782 | cq_host->num_slots, GFP_KERNEL); |
| 783 | if (!cq_host->mrq_slot) |
| 784 | return -ENOMEM; |
| 785 | |
| 786 | init_completion(&cq_host->halt_comp); |
| 787 | return err; |
| 788 | } |
| 789 | EXPORT_SYMBOL(cmdq_init); |