Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 12 | #include <linux/debugfs.h> |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 13 | #include <uapi/drm/sde_drm.h> |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 14 | #include "sde_kms.h" |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 15 | #include "sde_fence.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 16 | #include "sde_formats.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 17 | #include "sde_hw_sspp.h" |
| 18 | |
| 19 | #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) |
| 20 | #define PHASE_STEP_SHIFT 21 |
| 21 | #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) |
| 22 | #define PHASE_RESIDUAL 15 |
| 23 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 24 | #define SHARP_STRENGTH_DEFAULT 32 |
| 25 | #define SHARP_EDGE_THR_DEFAULT 112 |
| 26 | #define SHARP_SMOOTH_THR_DEFAULT 8 |
| 27 | #define SHARP_NOISE_THR_DEFAULT 2 |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 28 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 29 | #define SDE_NAME_SIZE 12 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 30 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 31 | #define SDE_STATE_CACHE_SIZE 2 |
| 32 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 33 | struct sde_plane { |
| 34 | struct drm_plane base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 35 | |
| 36 | int mmu_id; |
| 37 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 38 | struct mutex lock; |
| 39 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 40 | enum sde_sspp pipe; |
| 41 | uint32_t features; /* capabilities from catalog */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 42 | uint32_t nformats; |
| 43 | uint32_t formats[32]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 44 | |
| 45 | struct sde_hw_pipe *pipe_hw; |
| 46 | struct sde_hw_pipe_cfg pipe_cfg; |
| 47 | struct sde_hw_pixel_ext pixel_ext; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 48 | struct sde_hw_sharp_cfg sharp_cfg; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 49 | struct sde_hw_scaler3_cfg scaler3_cfg; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 50 | |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 51 | struct sde_csc_cfg csc_cfg; |
| 52 | struct sde_csc_cfg *csc_ptr; |
| 53 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 54 | const struct sde_sspp_sub_blks *pipe_sblk; |
| 55 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 56 | char pipe_name[SDE_NAME_SIZE]; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 57 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 58 | /* cache property default values (for reset) */ |
| 59 | uint64_t property_defaults[PLANE_PROP_COUNT]; |
| 60 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 61 | /* cache for unused plane state structures */ |
| 62 | struct sde_plane_state *state_cache[SDE_STATE_CACHE_SIZE]; |
| 63 | int state_cache_size; |
| 64 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 65 | /* debugfs related stuff */ |
| 66 | struct dentry *debugfs_root; |
| 67 | struct sde_debugfs_regset32 debugfs_src; |
| 68 | struct sde_debugfs_regset32 debugfs_scaler; |
| 69 | struct sde_debugfs_regset32 debugfs_csc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 70 | }; |
| 71 | #define to_sde_plane(x) container_of(x, struct sde_plane, base) |
| 72 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 73 | static bool sde_plane_enabled(struct drm_plane_state *state) |
| 74 | { |
| 75 | return state->fb && state->crtc; |
| 76 | } |
| 77 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 78 | /* helper to update a state's sync fence pointer from the property */ |
| 79 | static void _sde_plane_update_sync_fence(struct drm_plane *plane, |
| 80 | struct sde_plane_state *pstate, uint64_t fd) |
| 81 | { |
| 82 | if (!plane || !pstate) |
| 83 | return; |
| 84 | |
| 85 | /* clear previous reference */ |
| 86 | if (pstate->sync_fence) |
| 87 | sde_sync_put(pstate->sync_fence); |
| 88 | |
| 89 | /* get fence pointer for later */ |
| 90 | pstate->sync_fence = sde_sync_get(fd); |
| 91 | |
| 92 | DBG("0x%llX", fd); |
| 93 | } |
| 94 | |
| 95 | void *sde_plane_get_sync_fence(struct drm_plane *plane) |
| 96 | { |
| 97 | struct sde_plane_state *pstate; |
| 98 | void *ret = NULL; |
| 99 | |
| 100 | if (!plane) { |
| 101 | DRM_ERROR("Invalid plane\n"); |
| 102 | } else if (!plane->state) { |
| 103 | DRM_ERROR("Invalid plane state\n"); |
| 104 | } else { |
| 105 | pstate = to_sde_plane_state(plane->state); |
| 106 | ret = pstate->sync_fence; |
| 107 | |
| 108 | DBG("%s", to_sde_plane(plane)->pipe_name); |
| 109 | } |
| 110 | |
| 111 | return ret; |
| 112 | } |
| 113 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 114 | static void _sde_plane_set_scanout(struct drm_plane *plane, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 115 | struct sde_plane_state *pstate, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 116 | struct sde_hw_pipe_cfg *pipe_cfg, struct drm_framebuffer *fb) |
| 117 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 118 | struct sde_plane *psde; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 119 | unsigned int shift; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 120 | int i; |
| 121 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 122 | if (!plane || !pstate || !pipe_cfg || !fb) |
| 123 | return; |
| 124 | |
| 125 | psde = to_sde_plane(plane); |
| 126 | |
| 127 | if (psde->pipe_hw && psde->pipe_hw->ops.setup_sourceaddress) { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 128 | /* stride */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 129 | if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) & |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 130 | BIT(SDE_DRM_DEINTERLACE)) |
| 131 | shift = 1; |
| 132 | else |
| 133 | shift = 0; |
| 134 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 135 | i = min_t(int, ARRAY_SIZE(fb->pitches), SDE_MAX_PLANES); |
| 136 | while (i) { |
| 137 | --i; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 138 | pipe_cfg->src.ystride[i] = fb->pitches[i] << shift; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | /* address */ |
| 142 | for (i = 0; i < ARRAY_SIZE(pipe_cfg->addr.plane); ++i) |
| 143 | pipe_cfg->addr.plane[i] = msm_framebuffer_iova(fb, |
| 144 | psde->mmu_id, i); |
| 145 | |
| 146 | /* hw driver */ |
| 147 | psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg); |
| 148 | } |
| 149 | } |
| 150 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 151 | static void _sde_plane_setup_scaler3(struct drm_plane *plane, |
| 152 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, |
| 153 | struct sde_hw_scaler3_cfg *scale_cfg, |
| 154 | struct sde_mdp_format_params *fmt, |
| 155 | uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) |
| 156 | { |
| 157 | } |
| 158 | |
| 159 | static void _sde_plane_setup_scaler2(struct drm_plane *plane, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 160 | uint32_t src, uint32_t dst, uint32_t *phase_steps, |
| 161 | enum sde_hw_filter *filter, struct sde_mdp_format_params *fmt, |
| 162 | uint32_t chroma_subsampling) |
| 163 | { |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 164 | /* calculate phase steps, leave init phase as zero */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 165 | phase_steps[SDE_SSPP_COMP_0] = |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 166 | mult_frac(1 << PHASE_STEP_SHIFT, src, dst); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 167 | phase_steps[SDE_SSPP_COMP_1_2] = |
| 168 | phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling; |
| 169 | phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2]; |
| 170 | phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 171 | |
| 172 | /* calculate scaler config, if necessary */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 173 | if (fmt->is_yuv || src != dst) { |
| 174 | filter[SDE_SSPP_COMP_3] = |
| 175 | (src <= dst) ? SDE_MDP_SCALE_FILTER_BIL : |
| 176 | SDE_MDP_SCALE_FILTER_PCMN; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 177 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 178 | if (fmt->is_yuv) { |
| 179 | filter[SDE_SSPP_COMP_0] = SDE_MDP_SCALE_FILTER_CA; |
| 180 | filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3]; |
| 181 | } else { |
| 182 | filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3]; |
| 183 | filter[SDE_SSPP_COMP_1_2] = |
| 184 | SDE_MDP_SCALE_FILTER_NEAREST; |
| 185 | } |
| 186 | } else { |
| 187 | /* disable scaler */ |
| 188 | filter[SDE_SSPP_COMP_0] = SDE_MDP_SCALE_FILTER_MAX; |
| 189 | filter[SDE_SSPP_COMP_1_2] = SDE_MDP_SCALE_FILTER_MAX; |
| 190 | filter[SDE_SSPP_COMP_3] = SDE_MDP_SCALE_FILTER_MAX; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 191 | } |
| 192 | } |
| 193 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 194 | static void _sde_plane_setup_pixel_ext(struct drm_plane *plane, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 195 | uint32_t src, uint32_t dst, uint32_t decimated_src, |
| 196 | uint32_t *phase_steps, uint32_t *out_src, int *out_edge1, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 197 | int *out_edge2, enum sde_hw_filter *filter, |
| 198 | struct sde_mdp_format_params *fmt, uint32_t chroma_subsampling, |
| 199 | bool post_compare) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 200 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 201 | int64_t edge1, edge2, caf; |
| 202 | uint32_t src_work; |
| 203 | int i, tmp; |
| 204 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 205 | if (plane && phase_steps && out_src && out_edge1 && |
| 206 | out_edge2 && filter && fmt) { |
| 207 | /* handle CAF for YUV formats */ |
| 208 | if (fmt->is_yuv && SDE_MDP_SCALE_FILTER_CA == *filter) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 209 | caf = PHASE_STEP_UNIT_SCALE; |
| 210 | else |
| 211 | caf = 0; |
| 212 | |
| 213 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 214 | src_work = decimated_src; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 215 | if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 216 | src_work /= chroma_subsampling; |
| 217 | if (post_compare) |
| 218 | src = src_work; |
| 219 | if (!(fmt->is_yuv) && (src == dst)) { |
| 220 | /* unity */ |
| 221 | edge1 = 0; |
| 222 | edge2 = 0; |
| 223 | } else if (dst >= src) { |
| 224 | /* upscale */ |
| 225 | edge1 = (1 << PHASE_RESIDUAL); |
| 226 | edge1 -= caf; |
| 227 | edge2 = (1 << PHASE_RESIDUAL); |
| 228 | edge2 += (dst - 1) * *(phase_steps + i); |
| 229 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 230 | edge2 += caf; |
| 231 | edge2 = -(edge2); |
| 232 | } else { |
| 233 | /* downscale */ |
| 234 | edge1 = 0; |
| 235 | edge2 = (dst - 1) * *(phase_steps + i); |
| 236 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 237 | edge2 += *(phase_steps + i); |
| 238 | edge2 = -(edge2); |
| 239 | } |
| 240 | |
| 241 | /* only enable CAF for luma plane */ |
| 242 | caf = 0; |
| 243 | |
| 244 | /* populate output arrays */ |
| 245 | *(out_src + i) = src_work; |
| 246 | |
| 247 | /* edge updates taken from __pxl_extn_helper */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 248 | if (edge1 >= 0) { |
| 249 | tmp = (uint32_t)edge1; |
| 250 | tmp >>= PHASE_STEP_SHIFT; |
| 251 | *(out_edge1 + i) = -tmp; |
| 252 | } else { |
| 253 | tmp = (uint32_t)(-edge1); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 254 | *(out_edge1 + i) = |
| 255 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 256 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 257 | } |
| 258 | if (edge2 >= 0) { |
| 259 | tmp = (uint32_t)edge2; |
| 260 | tmp >>= PHASE_STEP_SHIFT; |
| 261 | *(out_edge2 + i) = -tmp; |
| 262 | } else { |
| 263 | tmp = (uint32_t)(-edge2); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 264 | *(out_edge2 + i) = |
| 265 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 266 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 267 | } |
| 268 | } |
| 269 | } |
| 270 | } |
| 271 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 272 | static void *_sde_plane_get_blob(struct sde_plane_state *pstate, |
| 273 | enum msm_mdp_plane_property property, size_t *byte_len) |
| 274 | { |
| 275 | struct drm_property_blob *blob; |
| 276 | size_t len = 0; |
| 277 | void *ret = 0; |
| 278 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 279 | if (!pstate || (property >= PLANE_PROP_BLOBCOUNT)) { |
| 280 | DRM_ERROR("Invalid argument(s)\n"); |
| 281 | } else { |
| 282 | blob = pstate->property_blobs[property]; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 283 | if (blob) { |
| 284 | len = blob->length; |
| 285 | ret = &blob->data; |
| 286 | } |
| 287 | } |
| 288 | |
| 289 | if (byte_len) |
| 290 | *byte_len = len; |
| 291 | |
| 292 | return ret; |
| 293 | } |
| 294 | |
| 295 | /** |
| 296 | * _sde_plane_verify_blob - verify incoming blob is big enough to contain |
| 297 | * sub-structure |
| 298 | * @blob_ptr: Pointer to start of incoming blob data |
| 299 | * @blob_size: Size of incoming blob data, in bytes |
| 300 | * @sub_ptr: Pointer to start of desired sub-structure |
| 301 | * @sub_size: Required size of sub-structure, in bytes |
| 302 | */ |
| 303 | static int _sde_plane_verify_blob(void *blob_ptr, |
| 304 | size_t blob_size, |
| 305 | void *sub_ptr, |
| 306 | size_t sub_size) |
| 307 | { |
| 308 | /* |
| 309 | * Use the blob size provided by drm to check if there are enough |
| 310 | * bytes from the start of versioned sub-structures to the end of |
| 311 | * blob data: |
| 312 | * |
| 313 | * e.g., |
| 314 | * blob_ptr --> struct blob_data { |
| 315 | * uint32_t version; |
| 316 | * sub_ptr --> struct blob_data_v1 v1; |
| 317 | * sub_ptr + sub_size --> struct blob_stuff more_stuff; |
| 318 | * blob_ptr + blob_size --> }; |
| 319 | * |
| 320 | * It's important to check the actual number of bytes from the start |
| 321 | * of the sub-structure to the end of the blob data, and not just rely |
| 322 | * on something like, |
| 323 | * |
| 324 | * sizeof(blob) - sizeof(blob->version) >= sizeof(sub-struct) |
| 325 | * |
| 326 | * This is because the start of the sub-structure can vary based on |
| 327 | * how the compiler pads the overall structure. |
| 328 | */ |
| 329 | if (blob_ptr && sub_ptr) |
| 330 | /* return zero if end of blob >= end of sub-struct */ |
| 331 | return ((unsigned char *)blob_ptr + blob_size) < |
| 332 | ((unsigned char *)sub_ptr + sub_size); |
| 333 | return -EINVAL; |
| 334 | } |
| 335 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 336 | static void _sde_plane_setup_csc(struct sde_plane *psde, |
| 337 | struct sde_plane_state *pstate, |
| 338 | struct sde_mdp_format_params *fmt) |
| 339 | { |
| 340 | static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = { |
| 341 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 342 | /* S15.16 format */ |
| 343 | 0x00012A00, 0x00000000, 0x00019880, |
| 344 | 0x00012A00, 0xFFFF9B80, 0xFFFF3000, |
| 345 | 0x00012A00, 0x00020480, 0x00000000, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 346 | }, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 347 | /* signed bias */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 348 | { 0xfff0, 0xff80, 0xff80,}, |
| 349 | { 0x0, 0x0, 0x0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 350 | /* unsigned clamp */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 351 | { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 352 | { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 353 | }; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 354 | static const struct sde_csc_cfg sde_csc_NOP = { |
| 355 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 356 | /* identity matrix, S15.16 format */ |
| 357 | 0x10000, 0x00000, 0x00000, |
| 358 | 0x00000, 0x10000, 0x00000, |
| 359 | 0x00000, 0x00000, 0x10000, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 360 | }, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 361 | /* signed bias */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 362 | { 0x0, 0x0, 0x0,}, |
| 363 | { 0x0, 0x0, 0x0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 364 | /* unsigned clamp */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 365 | { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,}, |
| 366 | { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,}, |
| 367 | }; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 368 | struct sde_drm_csc *csc = NULL; |
| 369 | size_t csc_size = 0; |
| 370 | bool user_blob = false; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 371 | |
| 372 | if (!psde->pipe_hw->ops.setup_csc) |
| 373 | return; |
| 374 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 375 | /* check for user space override */ |
| 376 | csc = _sde_plane_get_blob(pstate, PLANE_PROP_CSC, &csc_size); |
| 377 | if (csc) { |
| 378 | struct sde_csc_cfg cfg; |
| 379 | int i; |
| 380 | |
| 381 | /* user space override */ |
| 382 | memcpy(&cfg, &sde_csc_NOP, sizeof(struct sde_csc_cfg)); |
| 383 | switch (csc->version) { |
| 384 | case SDE_DRM_CSC_V1: |
| 385 | if (!_sde_plane_verify_blob(csc, |
| 386 | csc_size, |
| 387 | &csc->v1, |
| 388 | sizeof(struct sde_drm_csc_v1))) { |
| 389 | for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i) |
| 390 | cfg.csc_mv[i] = |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 391 | csc->v1.ctm_coeff[i] >> 16; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 392 | for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) { |
| 393 | cfg.csc_pre_bv[i] = |
| 394 | csc->v1.pre_bias[i]; |
| 395 | cfg.csc_post_bv[i] = |
| 396 | csc->v1.post_bias[i]; |
| 397 | } |
| 398 | for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) { |
| 399 | cfg.csc_pre_lv[i] = |
| 400 | csc->v1.pre_clamp[i]; |
| 401 | cfg.csc_post_lv[i] = |
| 402 | csc->v1.post_clamp[i]; |
| 403 | } |
| 404 | user_blob = true; |
| 405 | } |
| 406 | break; |
| 407 | default: |
| 408 | break; |
| 409 | } |
| 410 | |
| 411 | if (!user_blob) |
| 412 | DRM_ERROR("Invalid csc blob, v%lld\n", csc->version); |
| 413 | else |
| 414 | psde->pipe_hw->ops.setup_csc(psde->pipe_hw, |
| 415 | (struct sde_csc_cfg *)&cfg); |
| 416 | } |
| 417 | |
| 418 | if (user_blob) { |
| 419 | DBG("User blobs override for CSC"); |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 420 | psde->csc_ptr = &psde->csc_cfg; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 421 | /* revert to kernel default */ |
| 422 | } else if (fmt->is_yuv) { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 423 | psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 424 | } else { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 425 | psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_NOP; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 426 | } |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 427 | |
| 428 | psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 429 | } |
| 430 | |
| 431 | static int _sde_plane_mode_set(struct drm_plane *plane, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 432 | struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 433 | int crtc_x, int crtc_y, |
| 434 | unsigned int crtc_w, unsigned int crtc_h, |
| 435 | uint32_t src_x, uint32_t src_y, |
| 436 | uint32_t src_w, uint32_t src_h) |
| 437 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 438 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 439 | struct sde_plane_state *pstate; |
| 440 | const struct mdp_format *format; |
| 441 | uint32_t nplanes, pix_format, tmp; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 442 | uint32_t chroma_subsmpl_h, chroma_subsmpl_v; |
| 443 | uint32_t src_fmt_flags; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 444 | int i; |
| 445 | struct sde_mdp_format_params *fmt; |
| 446 | struct sde_hw_pixel_ext *pe; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 447 | size_t sc_u_size = 0; |
| 448 | struct sde_drm_scaler *sc_u = NULL; |
| 449 | struct sde_drm_scaler_v1 *sc_u1 = NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 450 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 451 | DBG(""); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 452 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 453 | if (!plane || !plane->state) { |
| 454 | DRM_ERROR("Invalid plane/state\n"); |
| 455 | return -EINVAL; |
| 456 | } |
| 457 | if (!crtc || !fb) { |
| 458 | DRM_ERROR("Invalid crtc/fb\n"); |
| 459 | return -EINVAL; |
| 460 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 461 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 462 | psde = to_sde_plane(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 463 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 464 | nplanes = drm_format_num_planes(fb->pixel_format); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 465 | |
| 466 | format = to_mdp_format(msm_framebuffer_format(fb)); |
| 467 | pix_format = format->base.pixel_format; |
| 468 | |
| 469 | /* src values are in Q16 fixed point, convert to integer */ |
| 470 | src_x = src_x >> 16; |
| 471 | src_y = src_y >> 16; |
| 472 | src_w = src_w >> 16; |
| 473 | src_h = src_h >> 16; |
| 474 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 475 | DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", psde->pipe_name, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 476 | fb->base.id, src_x, src_y, src_w, src_h, |
| 477 | crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); |
| 478 | |
| 479 | /* update format configuration */ |
| 480 | memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg)); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 481 | src_fmt_flags = 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 482 | |
| 483 | psde->pipe_cfg.src.format = sde_mdp_get_format_params(pix_format, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 484 | fb->modifier[0]); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 485 | psde->pipe_cfg.src.width = fb->width; |
| 486 | psde->pipe_cfg.src.height = fb->height; |
| 487 | psde->pipe_cfg.src.num_planes = nplanes; |
| 488 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 489 | _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb); |
| 490 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 491 | /* flags */ |
| 492 | DBG("Flags 0x%llX, rotation 0x%llX", |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 493 | sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG), |
| 494 | sde_plane_get_property(pstate, PLANE_PROP_ROTATION)); |
| 495 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 496 | BIT(DRM_REFLECT_X)) |
| 497 | src_fmt_flags |= SDE_SSPP_FLIP_LR; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 498 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 499 | BIT(DRM_REFLECT_Y)) |
| 500 | src_fmt_flags |= SDE_SSPP_FLIP_UD; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 501 | if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) & |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 502 | BIT(SDE_DRM_DEINTERLACE)) { |
| 503 | src_h /= 2; |
| 504 | src_y = DIV_ROUND_UP(src_y, 2); |
| 505 | src_y &= ~0x1; |
| 506 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 507 | |
| 508 | psde->pipe_cfg.src_rect.x = src_x; |
| 509 | psde->pipe_cfg.src_rect.y = src_y; |
| 510 | psde->pipe_cfg.src_rect.w = src_w; |
| 511 | psde->pipe_cfg.src_rect.h = src_h; |
| 512 | |
| 513 | psde->pipe_cfg.dst_rect.x = crtc_x; |
| 514 | psde->pipe_cfg.dst_rect.y = crtc_y; |
| 515 | psde->pipe_cfg.dst_rect.w = crtc_w; |
| 516 | psde->pipe_cfg.dst_rect.h = crtc_h; |
| 517 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 518 | /* get sde pixel format definition */ |
| 519 | fmt = psde->pipe_cfg.src.format; |
| 520 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 521 | pe = &(psde->pixel_ext); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 522 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 523 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 524 | /* get scaler config from user space */ |
| 525 | sc_u = _sde_plane_get_blob(pstate, PLANE_PROP_SCALER, &sc_u_size); |
| 526 | if (sc_u) { |
| 527 | switch (sc_u->version) { |
| 528 | case SDE_DRM_SCALER_V1: |
| 529 | if (!_sde_plane_verify_blob(sc_u, |
| 530 | sc_u_size, |
| 531 | &sc_u->v1, |
| 532 | sizeof(*sc_u1))) |
| 533 | sc_u1 = &sc_u->v1; |
| 534 | break; |
| 535 | default: |
| 536 | DBG("Unrecognized scaler blob v%lld", sc_u->version); |
| 537 | break; |
| 538 | } |
| 539 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 540 | |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 541 | /* decimation */ |
| 542 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_DECIMATE)) { |
| 543 | psde->pipe_cfg.horz_decimation = sc_u1->horz_decimate; |
| 544 | psde->pipe_cfg.vert_decimation = sc_u1->vert_decimate; |
| 545 | } |
| 546 | |
| 547 | /* don't chroma subsample if decimating */ |
| 548 | chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : |
| 549 | drm_format_horz_chroma_subsampling(pix_format); |
| 550 | chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : |
| 551 | drm_format_vert_chroma_subsampling(pix_format); |
| 552 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 553 | /* update scaler */ |
| 554 | if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) { |
| 555 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_3)) |
| 556 | DBG("QSEED3 blob detected"); |
| 557 | else |
| 558 | _sde_plane_setup_scaler3(plane, src_w, src_h, crtc_w, |
| 559 | crtc_h, &psde->scaler3_cfg, fmt, |
| 560 | chroma_subsmpl_h, chroma_subsmpl_v); |
| 561 | } else { |
| 562 | /* always calculate basic scaler config */ |
| 563 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_2)) { |
| 564 | /* populate from user space */ |
| 565 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 566 | pe->init_phase_x[i] = sc_u1->init_phase_x[i]; |
| 567 | pe->phase_step_x[i] = sc_u1->phase_step_x[i]; |
| 568 | pe->init_phase_y[i] = sc_u1->init_phase_y[i]; |
| 569 | pe->phase_step_y[i] = sc_u1->phase_step_y[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 570 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 571 | pe->horz_filter[i] = sc_u1->horz_filter[i]; |
| 572 | pe->vert_filter[i] = sc_u1->vert_filter[i]; |
| 573 | } |
| 574 | } else { |
| 575 | /* calculate phase steps */ |
| 576 | _sde_plane_setup_scaler2(plane, src_w, crtc_w, |
| 577 | pe->phase_step_x, |
| 578 | pe->horz_filter, fmt, chroma_subsmpl_h); |
| 579 | _sde_plane_setup_scaler2(plane, src_h, crtc_h, |
| 580 | pe->phase_step_y, |
| 581 | pe->vert_filter, fmt, chroma_subsmpl_v); |
| 582 | } |
| 583 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 584 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 585 | /* update pixel extensions */ |
| 586 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_PIX_EXT)) { |
| 587 | /* populate from user space */ |
| 588 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 589 | pe->num_ext_pxls_left[i] = sc_u1->lr.num_pxls_start[i]; |
| 590 | pe->num_ext_pxls_right[i] = sc_u1->lr.num_pxls_end[i]; |
| 591 | pe->left_ftch[i] = sc_u1->lr.ftch_start[i]; |
| 592 | pe->right_ftch[i] = sc_u1->lr.ftch_end[i]; |
| 593 | pe->left_rpt[i] = sc_u1->lr.rpt_start[i]; |
| 594 | pe->right_rpt[i] = sc_u1->lr.rpt_end[i]; |
| 595 | pe->roi_w[i] = sc_u1->lr.roi[i]; |
| 596 | |
| 597 | pe->num_ext_pxls_top[i] = sc_u1->tb.num_pxls_start[i]; |
| 598 | pe->num_ext_pxls_btm[i] = sc_u1->tb.num_pxls_end[i]; |
| 599 | pe->top_ftch[i] = sc_u1->tb.ftch_start[i]; |
| 600 | pe->btm_ftch[i] = sc_u1->tb.ftch_end[i]; |
| 601 | pe->top_rpt[i] = sc_u1->tb.rpt_start[i]; |
| 602 | pe->btm_rpt[i] = sc_u1->tb.rpt_end[i]; |
| 603 | pe->roi_h[i] = sc_u1->tb.roi[i]; |
| 604 | } |
| 605 | } else { |
| 606 | /* calculate left/right/top/bottom pixel extensions */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 607 | tmp = DECIMATED_DIMENSION(src_w, |
| 608 | psde->pipe_cfg.horz_decimation); |
| 609 | if (fmt->is_yuv) |
| 610 | tmp &= ~0x1; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 611 | _sde_plane_setup_pixel_ext(plane, src_w, crtc_w, tmp, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 612 | pe->phase_step_x, |
| 613 | pe->roi_w, |
| 614 | pe->num_ext_pxls_left, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 615 | pe->num_ext_pxls_right, pe->horz_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 616 | chroma_subsmpl_h, 0); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 617 | |
| 618 | tmp = DECIMATED_DIMENSION(src_h, |
| 619 | psde->pipe_cfg.vert_decimation); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 620 | _sde_plane_setup_pixel_ext(plane, src_h, crtc_h, tmp, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 621 | pe->phase_step_y, |
| 622 | pe->roi_h, |
| 623 | pe->num_ext_pxls_top, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 624 | pe->num_ext_pxls_btm, pe->vert_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 625 | chroma_subsmpl_v, 1); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 626 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 627 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 628 | if (pe->num_ext_pxls_left[i] >= 0) |
| 629 | pe->left_rpt[i] = |
| 630 | pe->num_ext_pxls_left[i]; |
| 631 | else |
| 632 | pe->left_ftch[i] = |
| 633 | pe->num_ext_pxls_left[i]; |
| 634 | |
| 635 | if (pe->num_ext_pxls_right[i] >= 0) |
| 636 | pe->right_rpt[i] = |
| 637 | pe->num_ext_pxls_right[i]; |
| 638 | else |
| 639 | pe->right_ftch[i] = |
| 640 | pe->num_ext_pxls_right[i]; |
| 641 | |
| 642 | if (pe->num_ext_pxls_top[i] >= 0) |
| 643 | pe->top_rpt[i] = |
| 644 | pe->num_ext_pxls_top[i]; |
| 645 | else |
| 646 | pe->top_ftch[i] = |
| 647 | pe->num_ext_pxls_top[i]; |
| 648 | |
| 649 | if (pe->num_ext_pxls_btm[i] >= 0) |
| 650 | pe->btm_rpt[i] = |
| 651 | pe->num_ext_pxls_btm[i]; |
| 652 | else |
| 653 | pe->btm_ftch[i] = |
| 654 | pe->num_ext_pxls_btm[i]; |
| 655 | } |
| 656 | } |
| 657 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 658 | if (psde->pipe_hw->ops.setup_format) |
| 659 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 660 | &psde->pipe_cfg, src_fmt_flags); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 661 | if (psde->pipe_hw->ops.setup_rects) |
| 662 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
| 663 | &psde->pipe_cfg, &psde->pixel_ext); |
| 664 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 665 | /* update sharpening */ |
| 666 | psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT; |
| 667 | psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT; |
| 668 | psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT; |
| 669 | psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT; |
| 670 | |
| 671 | if (psde->pipe_hw->ops.setup_sharpening) |
| 672 | psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw, |
| 673 | &psde->sharp_cfg); |
| 674 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 675 | /* update csc */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 676 | if (fmt->is_yuv) |
| 677 | _sde_plane_setup_csc(psde, pstate, fmt); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 678 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 679 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 680 | } |
| 681 | |
| 682 | static int sde_plane_prepare_fb(struct drm_plane *plane, |
| 683 | const struct drm_plane_state *new_state) |
| 684 | { |
| 685 | struct drm_framebuffer *fb = new_state->fb; |
| 686 | struct sde_plane *psde = to_sde_plane(plane); |
| 687 | |
| 688 | if (!new_state->fb) |
| 689 | return 0; |
| 690 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 691 | DBG("%s: FB[%u]", psde->pipe_name, fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 692 | return msm_framebuffer_prepare(fb, psde->mmu_id); |
| 693 | } |
| 694 | |
| 695 | static void sde_plane_cleanup_fb(struct drm_plane *plane, |
| 696 | const struct drm_plane_state *old_state) |
| 697 | { |
| 698 | struct drm_framebuffer *fb = old_state->fb; |
| 699 | struct sde_plane *psde = to_sde_plane(plane); |
| 700 | |
| 701 | if (!fb) |
| 702 | return; |
| 703 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 704 | DBG("%s: FB[%u]", psde->pipe_name, fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 705 | msm_framebuffer_cleanup(fb, psde->mmu_id); |
| 706 | } |
| 707 | |
| 708 | static int sde_plane_atomic_check(struct drm_plane *plane, |
| 709 | struct drm_plane_state *state) |
| 710 | { |
| 711 | struct sde_plane *psde = to_sde_plane(plane); |
| 712 | struct drm_plane_state *old_state = plane->state; |
| 713 | const struct mdp_format *format; |
| 714 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 715 | DBG("%s: check (%d -> %d)", psde->pipe_name, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 716 | sde_plane_enabled(old_state), sde_plane_enabled(state)); |
| 717 | |
| 718 | if (sde_plane_enabled(state)) { |
| 719 | /* CIFIX: don't use mdp format? */ |
| 720 | format = to_mdp_format(msm_framebuffer_format(state->fb)); |
| 721 | if (MDP_FORMAT_IS_YUV(format) && |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 722 | (!(psde->features & SDE_SSPP_SCALER) || |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 723 | !(psde->features & BIT(SDE_SSPP_CSC)))) { |
Lloyd Atkinson | d49de56 | 2016-05-30 13:23:48 -0400 | [diff] [blame] | 724 | DRM_ERROR("Pipe doesn't support YUV\n"); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 725 | |
| 726 | return -EINVAL; |
| 727 | } |
| 728 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 729 | if (!(psde->features & SDE_SSPP_SCALER) && |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 730 | (((state->src_w >> 16) != state->crtc_w) || |
| 731 | ((state->src_h >> 16) != state->crtc_h))) { |
Lloyd Atkinson | d49de56 | 2016-05-30 13:23:48 -0400 | [diff] [blame] | 732 | DRM_ERROR( |
| 733 | "Unsupported Pipe scaling (%dx%d -> %dx%d)\n", |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 734 | state->src_w >> 16, state->src_h >> 16, |
| 735 | state->crtc_w, state->crtc_h); |
| 736 | |
| 737 | return -EINVAL; |
| 738 | } |
| 739 | } |
| 740 | |
| 741 | if (sde_plane_enabled(state) && sde_plane_enabled(old_state)) { |
| 742 | /* we cannot change SMP block configuration during scanout: */ |
| 743 | bool full_modeset = false; |
| 744 | |
| 745 | if (state->fb->pixel_format != old_state->fb->pixel_format) { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 746 | DBG("%s: pixel_format change!", psde->pipe_name); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 747 | full_modeset = true; |
| 748 | } |
| 749 | if (state->src_w != old_state->src_w) { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 750 | DBG("%s: src_w change!", psde->pipe_name); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 751 | full_modeset = true; |
| 752 | } |
| 753 | if (to_sde_plane_state(old_state)->pending) { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 754 | DBG("%s: still pending!", psde->pipe_name); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 755 | full_modeset = true; |
| 756 | } |
| 757 | if (full_modeset) { |
| 758 | struct drm_crtc_state *crtc_state = |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 759 | drm_atomic_get_crtc_state(state->state, |
| 760 | state->crtc); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 761 | crtc_state->mode_changed = true; |
| 762 | to_sde_plane_state(state)->mode_changed = true; |
| 763 | } |
| 764 | } else { |
| 765 | to_sde_plane_state(state)->mode_changed = true; |
| 766 | } |
| 767 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 768 | return 0; |
| 769 | } |
| 770 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 771 | static void sde_plane_atomic_update(struct drm_plane *plane, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 772 | struct drm_plane_state *old_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 773 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 774 | struct sde_plane *sde_plane; |
| 775 | struct drm_plane_state *state; |
| 776 | struct sde_plane_state *pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 777 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 778 | if (!plane || !plane->state) { |
| 779 | DRM_ERROR("Invalid plane/state\n"); |
| 780 | return; |
| 781 | } |
| 782 | |
| 783 | sde_plane = to_sde_plane(plane); |
| 784 | state = plane->state; |
| 785 | pstate = to_sde_plane_state(state); |
| 786 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 787 | DBG("%s: update", sde_plane->pipe_name); |
| 788 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 789 | if (!sde_plane_enabled(state)) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 790 | pstate->pending = true; |
| 791 | } else if (pstate->mode_changed) { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 792 | int ret; |
| 793 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 794 | pstate->pending = true; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 795 | ret = _sde_plane_mode_set(plane, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 796 | state->crtc, state->fb, |
| 797 | state->crtc_x, state->crtc_y, |
| 798 | state->crtc_w, state->crtc_h, |
| 799 | state->src_x, state->src_y, |
| 800 | state->src_w, state->src_h); |
| 801 | /* atomic_check should have ensured that this doesn't fail */ |
| 802 | WARN_ON(ret < 0); |
| 803 | } else { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 804 | _sde_plane_set_scanout(plane, pstate, |
| 805 | &sde_plane->pipe_cfg, state->fb); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 806 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 807 | } |
| 808 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 809 | static inline struct drm_property **_sde_plane_get_property_entry( |
| 810 | struct drm_device *dev, enum msm_mdp_plane_property property) |
| 811 | { |
| 812 | struct msm_drm_private *priv; |
| 813 | |
| 814 | if (!dev || !dev->dev_private || (property >= PLANE_PROP_COUNT)) |
| 815 | return NULL; |
| 816 | |
| 817 | priv = dev->dev_private; |
| 818 | |
| 819 | return &(priv->plane_property[property]); |
| 820 | } |
| 821 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 822 | static void _sde_plane_install_range_property(struct drm_plane *plane, |
| 823 | struct drm_device *dev, const char *name, |
| 824 | uint64_t min, uint64_t max, uint64_t init, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 825 | enum msm_mdp_plane_property property) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 826 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 827 | struct drm_property **prop; |
| 828 | |
| 829 | prop = _sde_plane_get_property_entry(dev, property); |
| 830 | if (plane && name && prop) { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 831 | /* only create the property once */ |
| 832 | if (*prop == 0) { |
| 833 | *prop = drm_property_create_range(dev, |
| 834 | 0 /* flags */, name, min, max); |
| 835 | if (*prop == 0) |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 836 | DRM_ERROR("Create %s property failed\n", name); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 837 | } |
| 838 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 839 | /* save init value for later */ |
| 840 | to_sde_plane(plane)->property_defaults[property] = init; |
| 841 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 842 | /* always attach property, if created */ |
| 843 | if (*prop) |
| 844 | drm_object_attach_property(&plane->base, *prop, init); |
| 845 | } |
| 846 | } |
| 847 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 848 | static void _sde_plane_install_rotation_property(struct drm_plane *plane, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 849 | struct drm_device *dev, enum msm_mdp_plane_property property) |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 850 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 851 | struct sde_plane *psde; |
| 852 | struct drm_property **prop; |
| 853 | |
| 854 | prop = _sde_plane_get_property_entry(dev, property); |
| 855 | if (plane && prop) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 856 | /* only create the property once */ |
| 857 | if (*prop == 0) { |
| 858 | *prop = drm_mode_create_rotation_property(dev, |
| 859 | BIT(DRM_REFLECT_X) | |
| 860 | BIT(DRM_REFLECT_Y)); |
| 861 | if (*prop == 0) |
| 862 | DRM_ERROR("Create rotation property failed\n"); |
| 863 | } |
| 864 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 865 | /* save init value for later */ |
| 866 | psde = to_sde_plane(plane); |
| 867 | psde->property_defaults[property] = 0; |
| 868 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 869 | /* always attach property, if created */ |
| 870 | if (*prop) |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 871 | drm_object_attach_property(&plane->base, *prop, |
| 872 | psde->property_defaults[property]); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 873 | } |
| 874 | } |
| 875 | |
| 876 | static void _sde_plane_install_enum_property(struct drm_plane *plane, |
| 877 | struct drm_device *dev, const char *name, int is_bitmask, |
| 878 | const struct drm_prop_enum_list *values, int num_values, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 879 | enum msm_mdp_plane_property property) |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 880 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 881 | struct sde_plane *psde; |
| 882 | struct drm_property **prop; |
| 883 | |
| 884 | prop = _sde_plane_get_property_entry(dev, property); |
| 885 | if (plane && name && prop && values && num_values) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 886 | /* only create the property once */ |
| 887 | if (*prop == 0) { |
| 888 | /* 'bitmask' is a special type of 'enum' */ |
| 889 | if (is_bitmask) |
| 890 | *prop = drm_property_create_bitmask(dev, |
| 891 | DRM_MODE_PROP_BITMASK, name, |
| 892 | values, num_values, -1); |
| 893 | else |
| 894 | *prop = drm_property_create_enum(dev, |
| 895 | DRM_MODE_PROP_ENUM, name, |
| 896 | values, num_values); |
| 897 | if (*prop == 0) |
| 898 | DRM_ERROR("Create %s property failed\n", name); |
| 899 | } |
| 900 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 901 | /* save init value for later */ |
| 902 | psde = to_sde_plane(plane); |
| 903 | psde->property_defaults[property] = 0; |
| 904 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 905 | /* always attach property, if created */ |
| 906 | if (*prop) |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 907 | drm_object_attach_property(&plane->base, *prop, |
| 908 | psde->property_defaults[property]); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 909 | } |
| 910 | } |
| 911 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 912 | static void _sde_plane_install_blob_property(struct drm_plane *plane, |
| 913 | struct drm_device *dev, const char *name, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 914 | enum msm_mdp_plane_property property) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 915 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 916 | struct sde_plane *psde; |
| 917 | struct drm_property **prop; |
| 918 | |
| 919 | prop = _sde_plane_get_property_entry(dev, property); |
| 920 | if (plane && name && prop && (property < PLANE_PROP_BLOBCOUNT)) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 921 | /* only create the property once */ |
| 922 | if (*prop == 0) { |
| 923 | /* use 'create' for blob property place holder */ |
| 924 | *prop = drm_property_create(dev, |
| 925 | DRM_MODE_PROP_BLOB, name, 0); |
| 926 | if (*prop == 0) |
| 927 | DRM_ERROR("Create %s property failed\n", name); |
| 928 | } |
| 929 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 930 | /* save init value for later */ |
| 931 | psde = to_sde_plane(plane); |
| 932 | psde->property_defaults[property] = 0; |
| 933 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 934 | /* always attach property, if created */ |
| 935 | if (*prop) |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 936 | drm_object_attach_property(&plane->base, *prop, |
| 937 | psde->property_defaults[property]); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 938 | } |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 939 | } |
| 940 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 941 | static int _sde_plane_get_property_index(struct drm_plane *plane, |
| 942 | struct drm_property *property) |
| 943 | { |
| 944 | struct drm_property **prop_array; |
| 945 | int idx = PLANE_PROP_COUNT; |
| 946 | |
| 947 | if (!plane) { |
| 948 | DRM_ERROR("Invalid plane\n"); |
| 949 | } else if (!plane->dev || !plane->dev->dev_private) { |
| 950 | /* don't access dev_private if !dev */ |
| 951 | DRM_ERROR("Invalid device\n"); |
| 952 | } else if (!property) { |
| 953 | DRM_ERROR("Incoming property is NULL\n"); |
| 954 | } else { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 955 | prop_array = _sde_plane_get_property_entry(plane->dev, 0); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 956 | if (!prop_array) |
| 957 | /* should never hit this */ |
| 958 | DRM_ERROR("Invalid property array\n"); |
| 959 | |
| 960 | /* linear search is okay */ |
| 961 | for (idx = 0; idx < PLANE_PROP_COUNT; ++idx) { |
| 962 | if (prop_array[idx] == property) |
| 963 | break; |
| 964 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 965 | |
| 966 | if (idx == PLANE_PROP_COUNT) |
| 967 | DRM_ERROR("Invalid property pointer\n"); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 968 | } |
| 969 | |
| 970 | return idx; |
| 971 | } |
| 972 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 973 | /* helper to install properties which are common to planes and crtcs */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 974 | static void _sde_plane_install_properties(struct drm_plane *plane, |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 975 | struct drm_mode_object *obj, |
| 976 | struct sde_mdss_cfg *catalog) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 977 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 978 | static const struct drm_prop_enum_list e_blend_op[] = { |
| 979 | {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"}, |
| 980 | {SDE_DRM_BLEND_OP_OPAQUE, "opaque"}, |
| 981 | {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"}, |
| 982 | {SDE_DRM_BLEND_OP_COVERAGE, "coverage"} |
| 983 | }; |
| 984 | static const struct drm_prop_enum_list e_src_config[] = { |
| 985 | {SDE_DRM_DEINTERLACE, "deinterlace"} |
| 986 | }; |
| 987 | struct sde_plane *psde = to_sde_plane(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 988 | struct drm_device *dev = plane->dev; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 989 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 990 | DBG(""); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 991 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 992 | if (!psde || !psde->pipe_sblk || !catalog) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 993 | DRM_ERROR("Failed to identify catalog definition\n"); |
| 994 | return; |
| 995 | } |
| 996 | |
| 997 | /* range properties */ |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 998 | _sde_plane_install_range_property(plane, dev, "zpos", 0, 255, |
| 999 | plane->type == DRM_PLANE_TYPE_PRIMARY ? |
| 1000 | STAGE_BASE : STAGE0 + drm_plane_index(plane), |
| 1001 | PLANE_PROP_ZPOS); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1002 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1003 | _sde_plane_install_range_property(plane, dev, "alpha", 0, 255, 255, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1004 | PLANE_PROP_ALPHA); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1005 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1006 | _sde_plane_install_range_property(plane, dev, "sync_fence", 0, ~0, ~0, |
| 1007 | PLANE_PROP_SYNC_FENCE); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1008 | |
| 1009 | /* standard properties */ |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1010 | _sde_plane_install_rotation_property(plane, dev, PLANE_PROP_ROTATION); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1011 | |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 1012 | /* enum/bitmask properties */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1013 | _sde_plane_install_enum_property(plane, dev, "blend_op", 0, |
| 1014 | e_blend_op, ARRAY_SIZE(e_blend_op), |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1015 | PLANE_PROP_BLEND_OP); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1016 | _sde_plane_install_enum_property(plane, dev, "src_config", 1, |
| 1017 | e_src_config, ARRAY_SIZE(e_src_config), |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1018 | PLANE_PROP_SRC_CONFIG); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1019 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1020 | /* blob properties */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1021 | if (psde->features & SDE_SSPP_SCALER) |
| 1022 | _sde_plane_install_blob_property(plane, dev, "scaler", |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1023 | PLANE_PROP_SCALER); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1024 | if (psde->features & BIT(SDE_SSPP_CSC)) |
| 1025 | _sde_plane_install_blob_property(plane, dev, "csc", |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1026 | PLANE_PROP_CSC); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1027 | } |
| 1028 | |
| 1029 | static int sde_plane_atomic_set_property(struct drm_plane *plane, |
| 1030 | struct drm_plane_state *state, struct drm_property *property, |
| 1031 | uint64_t val) |
| 1032 | { |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1033 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1034 | struct sde_plane_state *pstate; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1035 | struct drm_property_blob *blob, **pr_blob; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1036 | int idx, ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1037 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1038 | idx = _sde_plane_get_property_index(plane, property); |
| 1039 | if (!state) { |
| 1040 | DRM_ERROR("Invalid state\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1041 | } else if (idx >= PLANE_PROP_COUNT) { |
| 1042 | DRM_ERROR("Invalid property\n"); |
| 1043 | } else { |
| 1044 | psde = to_sde_plane(plane); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1045 | pstate = to_sde_plane_state(state); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1046 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1047 | DBG("%s: %d <= %d", psde->pipe_name, idx, (int)val); |
| 1048 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1049 | /* extra handling for incoming properties */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1050 | if ((property->flags & DRM_MODE_PROP_BLOB) && |
| 1051 | (idx < PLANE_PROP_BLOBCOUNT)) { |
| 1052 | /* DRM lookup also takes a reference */ |
| 1053 | blob = drm_property_lookup_blob(plane->dev, |
| 1054 | (uint32_t)val); |
| 1055 | if (!blob) { |
| 1056 | DRM_ERROR("Blob not found\n"); |
| 1057 | val = 0; |
| 1058 | } else { |
| 1059 | DBG("Blob %u saved", blob->base.id); |
| 1060 | val = blob->base.id; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1061 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1062 | /* save blobs for later */ |
| 1063 | pr_blob = &pstate->property_blobs[idx]; |
| 1064 | /* need to clear previous reference */ |
| 1065 | if (*pr_blob) |
| 1066 | drm_property_unreference_blob(*pr_blob); |
| 1067 | *pr_blob = blob; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1068 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1069 | } else if (idx == PLANE_PROP_SYNC_FENCE) { |
| 1070 | _sde_plane_update_sync_fence(plane, pstate, val); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1071 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1072 | pstate->property_values[idx] = val; |
| 1073 | ret = 0; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1074 | } |
| 1075 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1076 | return ret; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1077 | } |
| 1078 | |
| 1079 | static int sde_plane_set_property(struct drm_plane *plane, |
| 1080 | struct drm_property *property, uint64_t val) |
| 1081 | { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1082 | DBG(""); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1083 | |
| 1084 | if (!plane) |
| 1085 | return -EINVAL; |
| 1086 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1087 | return sde_plane_atomic_set_property(plane, |
| 1088 | plane->state, property, val); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1089 | } |
| 1090 | |
| 1091 | static int sde_plane_atomic_get_property(struct drm_plane *plane, |
| 1092 | const struct drm_plane_state *state, |
| 1093 | struct drm_property *property, uint64_t *val) |
| 1094 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1095 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1096 | int idx, ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1097 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1098 | idx = _sde_plane_get_property_index(plane, property); |
| 1099 | if (!state) { |
| 1100 | DRM_ERROR("Invalid state\n"); |
| 1101 | } else if (!val) { |
| 1102 | DRM_ERROR("Value pointer is NULL\n"); |
| 1103 | } else if (idx < PLANE_PROP_COUNT) { |
| 1104 | pstate = to_sde_plane_state(state); |
| 1105 | |
| 1106 | *val = pstate->property_values[idx]; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1107 | DBG("%d 0x%llX", idx, *val); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1108 | ret = 0; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1109 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1110 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1111 | return ret; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1112 | } |
| 1113 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1114 | static struct sde_plane_state *sde_plane_alloc_state(struct drm_plane *plane) |
| 1115 | { |
| 1116 | struct sde_plane *psde; |
| 1117 | struct sde_plane_state *pstate; |
| 1118 | |
| 1119 | if (!plane) |
| 1120 | return NULL; |
| 1121 | |
| 1122 | psde = to_sde_plane(plane); |
| 1123 | pstate = NULL; |
| 1124 | |
| 1125 | mutex_lock(&psde->lock); |
| 1126 | if (psde->state_cache_size) |
| 1127 | pstate = psde->state_cache[--(psde->state_cache_size)]; |
| 1128 | mutex_unlock(&psde->lock); |
| 1129 | |
| 1130 | if (!pstate) |
| 1131 | pstate = kmalloc(sizeof(struct sde_plane_state), GFP_KERNEL); |
| 1132 | |
| 1133 | return pstate; |
| 1134 | } |
| 1135 | |
| 1136 | static void sde_plane_free_state(struct drm_plane *plane, |
| 1137 | struct sde_plane_state *pstate) |
| 1138 | { |
| 1139 | struct sde_plane *psde; |
| 1140 | |
| 1141 | if (!plane || !pstate) |
| 1142 | return; |
| 1143 | |
| 1144 | psde = to_sde_plane(plane); |
| 1145 | |
| 1146 | mutex_lock(&psde->lock); |
| 1147 | if (psde->state_cache_size < SDE_STATE_CACHE_SIZE) { |
| 1148 | psde->state_cache[(psde->state_cache_size)++] = pstate; |
| 1149 | mutex_unlock(&psde->lock); |
| 1150 | } else { |
| 1151 | mutex_unlock(&psde->lock); |
| 1152 | kfree(pstate); |
| 1153 | } |
| 1154 | } |
| 1155 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1156 | static void sde_plane_destroy(struct drm_plane *plane) |
| 1157 | { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1158 | struct sde_plane *psde; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1159 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1160 | DBG(""); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1161 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1162 | if (plane) { |
| 1163 | psde = to_sde_plane(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1164 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1165 | debugfs_remove_recursive(psde->debugfs_root); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1166 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1167 | mutex_destroy(&psde->lock); |
| 1168 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1169 | drm_plane_helper_disable(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1170 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1171 | /* this will destroy the states as well */ |
| 1172 | drm_plane_cleanup(plane); |
| 1173 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1174 | if (psde->pipe_hw) |
| 1175 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 1176 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1177 | /* free state cache */ |
| 1178 | while (psde->state_cache_size > 0) |
| 1179 | kfree(psde->state_cache[--(psde->state_cache_size)]); |
| 1180 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1181 | kfree(psde); |
| 1182 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1183 | } |
| 1184 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1185 | static void sde_plane_destroy_state(struct drm_plane *plane, |
| 1186 | struct drm_plane_state *state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1187 | { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1188 | struct sde_plane_state *pstate; |
| 1189 | int i; |
| 1190 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1191 | if (!plane || !state) { |
| 1192 | DRM_ERROR("Invalid plane/state\n"); |
| 1193 | return; |
| 1194 | } |
| 1195 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1196 | pstate = to_sde_plane_state(state); |
| 1197 | |
| 1198 | DBG(""); |
| 1199 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1200 | /* remove ref count for frame buffers */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1201 | if (state->fb) |
| 1202 | drm_framebuffer_unreference(state->fb); |
| 1203 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1204 | /* remove ref count for fence */ |
| 1205 | if (pstate->sync_fence) |
| 1206 | sde_sync_put(pstate->sync_fence); |
| 1207 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1208 | /* remove ref count for blobs */ |
| 1209 | for (i = 0; i < PLANE_PROP_BLOBCOUNT; ++i) |
| 1210 | if (pstate->property_blobs[i]) |
| 1211 | drm_property_unreference_blob( |
| 1212 | pstate->property_blobs[i]); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1213 | sde_plane_free_state(plane, pstate); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1214 | } |
| 1215 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1216 | static struct drm_plane_state * |
| 1217 | sde_plane_duplicate_state(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1218 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1219 | struct sde_plane_state *pstate; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1220 | struct sde_plane_state *old_state; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1221 | int i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1222 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1223 | if (!plane || !plane->state) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1224 | return NULL; |
| 1225 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1226 | old_state = to_sde_plane_state(plane->state); |
| 1227 | pstate = sde_plane_alloc_state(plane); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1228 | |
| 1229 | DBG(""); |
| 1230 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1231 | if (!pstate) |
| 1232 | return NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1233 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1234 | memcpy(pstate, old_state, sizeof(*pstate)); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1235 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1236 | /* add ref count for frame buffer */ |
| 1237 | if (pstate->base.fb) |
| 1238 | drm_framebuffer_reference(pstate->base.fb); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1239 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1240 | /* add ref count for fence */ |
| 1241 | if (pstate->sync_fence) { |
| 1242 | pstate->sync_fence = 0; |
| 1243 | _sde_plane_update_sync_fence(plane, pstate, pstate-> |
| 1244 | property_values[PLANE_PROP_SYNC_FENCE]); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1245 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1246 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1247 | /* add ref count for blobs */ |
| 1248 | for (i = 0; i < PLANE_PROP_BLOBCOUNT; ++i) |
| 1249 | if (pstate->property_blobs[i]) |
| 1250 | drm_property_reference_blob( |
| 1251 | pstate->property_blobs[i]); |
| 1252 | |
| 1253 | pstate->mode_changed = false; |
| 1254 | pstate->pending = false; |
| 1255 | |
| 1256 | return &pstate->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1257 | } |
| 1258 | |
| 1259 | static void sde_plane_reset(struct drm_plane *plane) |
| 1260 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1261 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1262 | struct sde_plane_state *pstate; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1263 | int i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1264 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1265 | if (!plane) { |
| 1266 | DRM_ERROR("Invalid plane\n"); |
| 1267 | return; |
| 1268 | } |
| 1269 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1270 | psde = to_sde_plane(plane); |
| 1271 | DBG("%s", psde->pipe_name); |
| 1272 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1273 | /* remove previous state, if present */ |
| 1274 | if (plane->state) |
| 1275 | sde_plane_destroy_state(plane, plane->state); |
| 1276 | plane->state = 0; |
| 1277 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1278 | pstate = sde_plane_alloc_state(plane); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1279 | if (!pstate) { |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1280 | DRM_ERROR("Failed to (re)allocate plane state\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1281 | return; |
| 1282 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1283 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1284 | memset(pstate, 0, sizeof(*pstate)); |
| 1285 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1286 | /* assign default property values */ |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1287 | for (i = 0; i < PLANE_PROP_COUNT; ++i) |
| 1288 | pstate->property_values[i] = psde->property_defaults[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1289 | |
| 1290 | pstate->base.plane = plane; |
| 1291 | |
| 1292 | plane->state = &pstate->base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1293 | } |
| 1294 | |
| 1295 | static const struct drm_plane_funcs sde_plane_funcs = { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1296 | .update_plane = drm_atomic_helper_update_plane, |
| 1297 | .disable_plane = drm_atomic_helper_disable_plane, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1298 | .destroy = sde_plane_destroy, |
| 1299 | .set_property = sde_plane_set_property, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1300 | .atomic_set_property = sde_plane_atomic_set_property, |
| 1301 | .atomic_get_property = sde_plane_atomic_get_property, |
| 1302 | .reset = sde_plane_reset, |
| 1303 | .atomic_duplicate_state = sde_plane_duplicate_state, |
| 1304 | .atomic_destroy_state = sde_plane_destroy_state, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1305 | }; |
| 1306 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1307 | static const struct drm_plane_helper_funcs sde_plane_helper_funcs = { |
| 1308 | .prepare_fb = sde_plane_prepare_fb, |
| 1309 | .cleanup_fb = sde_plane_cleanup_fb, |
| 1310 | .atomic_check = sde_plane_atomic_check, |
| 1311 | .atomic_update = sde_plane_atomic_update, |
| 1312 | }; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1313 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1314 | enum sde_sspp sde_plane_pipe(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1315 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1316 | struct sde_plane *sde_plane = to_sde_plane(plane); |
| 1317 | |
| 1318 | return sde_plane->pipe; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1319 | } |
| 1320 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1321 | static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms) |
| 1322 | { |
| 1323 | const struct sde_sspp_sub_blks *sblk = 0; |
| 1324 | const struct sde_sspp_cfg *cfg = 0; |
| 1325 | |
| 1326 | if (psde && psde->pipe_hw) |
| 1327 | cfg = psde->pipe_hw->cap; |
| 1328 | if (cfg) |
| 1329 | sblk = cfg->sblk; |
| 1330 | |
| 1331 | if (kms && sblk) { |
| 1332 | /* create overall sub-directory for the pipe */ |
| 1333 | psde->debugfs_root = |
| 1334 | debugfs_create_dir(psde->pipe_name, |
| 1335 | sde_debugfs_get_root(kms)); |
| 1336 | if (psde->debugfs_root) { |
| 1337 | /* don't error check these */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1338 | debugfs_create_x32("features", 0644, |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1339 | psde->debugfs_root, &psde->features); |
| 1340 | |
| 1341 | /* add register dump support */ |
| 1342 | sde_debugfs_setup_regset32(&psde->debugfs_src, |
| 1343 | sblk->src_blk.base + cfg->base, |
| 1344 | sblk->src_blk.len, |
| 1345 | kms->mmio); |
| 1346 | sde_debugfs_create_regset32("src_blk", 0444, |
| 1347 | psde->debugfs_root, &psde->debugfs_src); |
| 1348 | |
| 1349 | sde_debugfs_setup_regset32(&psde->debugfs_scaler, |
| 1350 | sblk->scaler_blk.base + cfg->base, |
| 1351 | sblk->scaler_blk.len, |
| 1352 | kms->mmio); |
| 1353 | sde_debugfs_create_regset32("scaler_blk", 0444, |
| 1354 | psde->debugfs_root, |
| 1355 | &psde->debugfs_scaler); |
| 1356 | |
| 1357 | sde_debugfs_setup_regset32(&psde->debugfs_csc, |
| 1358 | sblk->csc_blk.base + cfg->base, |
| 1359 | sblk->csc_blk.len, |
| 1360 | kms->mmio); |
| 1361 | sde_debugfs_create_regset32("csc_blk", 0444, |
| 1362 | psde->debugfs_root, &psde->debugfs_csc); |
| 1363 | } |
| 1364 | } |
| 1365 | } |
| 1366 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1367 | /* initialize plane */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1368 | struct drm_plane *sde_plane_init(struct drm_device *dev, |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1369 | uint32_t pipe, bool primary_plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1370 | { |
| 1371 | struct drm_plane *plane = NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1372 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1373 | struct msm_drm_private *priv; |
| 1374 | struct sde_kms *kms; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1375 | enum drm_plane_type type; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1376 | int ret = -EINVAL; |
| 1377 | |
| 1378 | if (!dev) { |
| 1379 | DRM_ERROR("[%u]Device is NULL\n", pipe); |
| 1380 | goto exit; |
| 1381 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1382 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1383 | priv = dev->dev_private; |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1384 | if (!priv) { |
| 1385 | DRM_ERROR("[%u]Private data is NULL\n", pipe); |
| 1386 | goto exit; |
| 1387 | } |
| 1388 | |
| 1389 | if (!priv->kms) { |
| 1390 | DRM_ERROR("[%u]Invalid KMS reference\n", pipe); |
| 1391 | goto exit; |
| 1392 | } |
| 1393 | kms = to_sde_kms(priv->kms); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1394 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1395 | if (!kms->catalog) { |
| 1396 | DRM_ERROR("[%u]Invalid catalog reference\n", pipe); |
| 1397 | goto exit; |
| 1398 | } |
| 1399 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1400 | /* create and zero local structure */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1401 | psde = kzalloc(sizeof(*psde), GFP_KERNEL); |
| 1402 | if (!psde) { |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1403 | DRM_ERROR("[%u]Failed to allocate local plane struct\n", pipe); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1404 | ret = -ENOMEM; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1405 | goto exit; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1406 | } |
| 1407 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1408 | /* cache local stuff for later */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1409 | plane = &psde->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1410 | psde->pipe = pipe; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1411 | psde->mmu_id = kms->mmu_id; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1412 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1413 | /* initialize underlying h/w driver */ |
| 1414 | psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog); |
| 1415 | if (IS_ERR(psde->pipe_hw)) { |
| 1416 | DRM_ERROR("[%u]SSPP init failed\n", pipe); |
| 1417 | ret = PTR_ERR(psde->pipe_hw); |
| 1418 | goto clean_plane; |
| 1419 | } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) { |
| 1420 | DRM_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); |
| 1421 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1422 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1423 | |
| 1424 | /* cache features mask for later */ |
| 1425 | psde->features = psde->pipe_hw->cap->features; |
| 1426 | psde->pipe_sblk = psde->pipe_hw->cap->sblk; |
| 1427 | |
| 1428 | /* add plane to DRM framework */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1429 | psde->nformats = mdp_get_formats(psde->formats, |
| 1430 | ARRAY_SIZE(psde->formats), |
| 1431 | !(psde->features & BIT(SDE_SSPP_CSC)) || |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1432 | !(psde->features & SDE_SSPP_SCALER)); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1433 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1434 | if (!psde->nformats) { |
| 1435 | DRM_ERROR("[%u]No valid formats for plane\n", pipe); |
| 1436 | goto clean_sspp; |
| 1437 | } |
| 1438 | |
| 1439 | if (psde->features & BIT(SDE_SSPP_CURSOR)) |
| 1440 | type = DRM_PLANE_TYPE_CURSOR; |
| 1441 | else if (primary_plane) |
| 1442 | type = DRM_PLANE_TYPE_PRIMARY; |
| 1443 | else |
| 1444 | type = DRM_PLANE_TYPE_OVERLAY; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1445 | ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs, |
| 1446 | psde->formats, psde->nformats, |
| 1447 | type); |
| 1448 | if (ret) |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1449 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1450 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1451 | /* success! finalize initialization */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1452 | drm_plane_helper_add(plane, &sde_plane_helper_funcs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1453 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1454 | _sde_plane_install_properties(plane, &plane->base, kms->catalog); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1455 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1456 | /* save user friendly pipe name for later */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1457 | snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1458 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame^] | 1459 | mutex_init(&psde->lock); |
| 1460 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1461 | _sde_plane_init_debugfs(psde, kms); |
| 1462 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1463 | DRM_INFO("[%u]Successfully created %s\n", pipe, psde->pipe_name); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1464 | return plane; |
| 1465 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1466 | clean_sspp: |
| 1467 | if (psde && psde->pipe_hw) |
| 1468 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 1469 | clean_plane: |
| 1470 | kfree(psde); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1471 | exit: |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1472 | return ERR_PTR(ret); |
| 1473 | } |