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Mike Frysinger09e1f702008-08-06 17:15:27 +08001/*
2 * Common Blackfin startup code
3 *
4 * Copyright 2004-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#include <linux/linkage.h>
12#include <linux/init.h>
13#include <asm/blackfin.h>
Mike Frysinger67618fd2008-08-06 17:18:31 +080014#include <asm/thread_info.h>
Mike Frysinger09e1f702008-08-06 17:15:27 +080015#include <asm/trace.h>
Graf Yang6b3087c2009-01-07 23:14:39 +080016#include <asm/asm-offsets.h>
Mike Frysinger09e1f702008-08-06 17:15:27 +080017
Mike Frysinger17e89bc2008-08-06 17:23:50 +080018__INIT
19
20#define INITIAL_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
21
22ENTRY(__start)
23 /* R0: argument of command line string, passed from uboot, save it */
24 R7 = R0;
25 /* Enable Cycle Counter and Nesting Of Interrupts */
26#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
27 R0 = SYSCFG_SNEN;
28#else
29 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
30#endif
31 SYSCFG = R0;
32 R0 = 0;
33
34 /* Clear Out All the data and pointer Registers */
35 R1 = R0;
36 R2 = R0;
37 R3 = R0;
38 R4 = R0;
39 R5 = R0;
40 R6 = R0;
41
42 P0 = R0;
43 P1 = R0;
44 P2 = R0;
45 P3 = R0;
46 P4 = R0;
47 P5 = R0;
48
49 LC0 = r0;
50 LC1 = r0;
51 L0 = r0;
52 L1 = r0;
53 L2 = r0;
54 L3 = r0;
55
56 /* Clear Out All the DAG Registers */
57 B0 = r0;
58 B1 = r0;
59 B2 = r0;
60 B3 = r0;
61
62 I0 = r0;
63 I1 = r0;
64 I2 = r0;
65 I3 = r0;
66
67 M0 = r0;
68 M1 = r0;
69 M2 = r0;
70 M3 = r0;
71
Robin Getz9df10282008-10-08 18:03:33 +080072 /*
73 * Clear ITEST_COMMAND and DTEST_COMMAND registers,
74 * Leaving these as non-zero can confuse the emulator
75 */
76 p0.L = LO(DTEST_COMMAND);
77 p0.H = HI(DTEST_COMMAND);
78 [p0] = R0;
79 [p0 + (ITEST_COMMAND - DTEST_COMMAND)] = R0;
80 CSYNC;
81
Mike Frysinger17e89bc2008-08-06 17:23:50 +080082 trace_buffer_init(p0,r0);
83 P0 = R1;
84 R0 = R1;
85
86 /* Turn off the icache */
87 p0.l = LO(IMEM_CONTROL);
88 p0.h = HI(IMEM_CONTROL);
89 R1 = [p0];
90 R0 = ~ENICPLB;
91 R0 = R0 & R1;
92 [p0] = R0;
93 SSYNC;
94
95 /* Turn off the dcache */
96 p0.l = LO(DMEM_CONTROL);
97 p0.h = HI(DMEM_CONTROL);
98 R1 = [p0];
99 R0 = ~ENDCPLB;
100 R0 = R0 & R1;
101 [p0] = R0;
102 SSYNC;
103
Robin Getz0c7a6b22008-10-08 16:27:12 +0800104 /* in case of double faults, save a few things */
105 p0.l = _init_retx;
106 p0.h = _init_retx;
Robin Getzcd8fb8d2008-08-14 14:44:33 +0800107 R0 = RETX;
108 [P0] = R0;
109
Robin Getz0c7a6b22008-10-08 16:27:12 +0800110#ifdef CONFIG_DEBUG_DOUBLEFAULT
111 /* Only save these if we are storing them,
112 * This happens here, since L1 gets clobbered
113 * below
114 */
Graf Yang6b3087c2009-01-07 23:14:39 +0800115 GET_PDA(p0, r0);
116 r7 = [p0 + PDA_RETX];
Robin Getz0c7a6b22008-10-08 16:27:12 +0800117 p1.l = _init_saved_retx;
118 p1.h = _init_saved_retx;
Graf Yang6b3087c2009-01-07 23:14:39 +0800119 [p1] = r7;
Robin Getz0c7a6b22008-10-08 16:27:12 +0800120
Graf Yang6b3087c2009-01-07 23:14:39 +0800121 r7 = [p0 + PDA_DCPLB];
Robin Getz0c7a6b22008-10-08 16:27:12 +0800122 p1.l = _init_saved_dcplb_fault_addr;
123 p1.h = _init_saved_dcplb_fault_addr;
Graf Yang6b3087c2009-01-07 23:14:39 +0800124 [p1] = r7;
Robin Getz0c7a6b22008-10-08 16:27:12 +0800125
Graf Yang6b3087c2009-01-07 23:14:39 +0800126 r7 = [p0 + PDA_ICPLB];
Robin Getz0c7a6b22008-10-08 16:27:12 +0800127 p1.l = _init_saved_icplb_fault_addr;
128 p1.h = _init_saved_icplb_fault_addr;
Graf Yang6b3087c2009-01-07 23:14:39 +0800129 [p1] = r7;
Robin Getz0c7a6b22008-10-08 16:27:12 +0800130
Graf Yang6b3087c2009-01-07 23:14:39 +0800131 r7 = [p0 + PDA_SEQSTAT];
Robin Getz0c7a6b22008-10-08 16:27:12 +0800132 p1.l = _init_saved_seqstat;
133 p1.h = _init_saved_seqstat;
Graf Yang6b3087c2009-01-07 23:14:39 +0800134 [p1] = r7;
Robin Getz0c7a6b22008-10-08 16:27:12 +0800135#endif
136
Mike Frysinger17e89bc2008-08-06 17:23:50 +0800137 /* Initialize stack pointer */
138 sp.l = lo(INITIAL_STACK);
139 sp.h = hi(INITIAL_STACK);
140 fp = sp;
141 usp = sp;
142
143#ifdef CONFIG_EARLY_PRINTK
144 call _init_early_exception_vectors;
145#endif
146
147 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
Graf Yang5b04f272008-10-08 17:32:57 +0800148 call _bfin_relocate_l1_mem;
Mike Frysinger17e89bc2008-08-06 17:23:50 +0800149#ifdef CONFIG_BFIN_KERNEL_CLOCK
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800150 call _init_clocks;
Mike Frysinger17e89bc2008-08-06 17:23:50 +0800151#endif
152
153 /* This section keeps the processor in supervisor mode
154 * during kernel boot. Switches to user mode at end of boot.
155 * See page 3-9 of Hardware Reference manual for documentation.
156 */
157
158 /* EVT15 = _real_start */
159
160 p0.l = lo(EVT15);
161 p0.h = hi(EVT15);
162 p1.l = _real_start;
163 p1.h = _real_start;
164 [p0] = p1;
165 csync;
166
Mike Frysingerc2414bd2008-11-18 17:48:22 +0800167 r0 = EVT_IVG15 (z);
168 sti r0;
Mike Frysinger17e89bc2008-08-06 17:23:50 +0800169
170 raise 15;
171 p0.l = .LWAIT_HERE;
172 p0.h = .LWAIT_HERE;
173 reti = p0;
174#if ANOMALY_05000281
175 nop; nop; nop;
176#endif
177 rti;
178
179.LWAIT_HERE:
180 jump .LWAIT_HERE;
181ENDPROC(__start)
182
Mike Frysinger09e1f702008-08-06 17:15:27 +0800183/* A little BF561 glue ... */
184#ifndef WDOG_CTL
185# define WDOG_CTL WDOGA_CTL
186#endif
187
Mike Frysingerf9402602008-10-27 18:17:41 +0800188ENTRY(__init_clear_bss)
189 r2 = r2 - r1;
190 cc = r2 == 0;
191 if cc jump .L_bss_done;
192 r2 >>= 2;
193 p1 = r1;
194 p2 = r2;
195 lsetup (1f, 1f) lc0 = p2;
1961: [p1++] = r0;
197.L_bss_done:
198 rts;
199ENDPROC(__init_clear_bss)
200
Mike Frysinger09e1f702008-08-06 17:15:27 +0800201ENTRY(_real_start)
202 /* Enable nested interrupts */
203 [--sp] = reti;
204
205 /* watchdog off for now */
206 p0.l = lo(WDOG_CTL);
207 p0.h = hi(WDOG_CTL);
208 r0 = 0xAD6(z);
209 w[p0] = r0;
210 ssync;
211
Mike Frysingerf9402602008-10-27 18:17:41 +0800212 r0 = 0 (x);
213 /* Zero out all of the fun bss regions */
Graf Yangb4f5c582008-10-16 22:50:46 +0800214#if L1_DATA_A_LENGTH > 0
215 r1.l = __sbss_l1;
216 r1.h = __sbss_l1;
217 r2.l = __ebss_l1;
218 r2.h = __ebss_l1;
Mike Frysingerf9402602008-10-27 18:17:41 +0800219 call __init_clear_bss
Graf Yangb4f5c582008-10-16 22:50:46 +0800220#endif
Graf Yangb4f5c582008-10-16 22:50:46 +0800221#if L1_DATA_B_LENGTH > 0
222 r1.l = __sbss_b_l1;
223 r1.h = __sbss_b_l1;
224 r2.l = __ebss_b_l1;
225 r2.h = __ebss_b_l1;
Mike Frysingerf9402602008-10-27 18:17:41 +0800226 call __init_clear_bss
Graf Yangb4f5c582008-10-16 22:50:46 +0800227#endif
Graf Yangb4f5c582008-10-16 22:50:46 +0800228#if L2_LENGTH > 0
229 r1.l = __sbss_l2;
230 r1.h = __sbss_l2;
231 r2.l = __ebss_l2;
232 r2.h = __ebss_l2;
Mike Frysingerf9402602008-10-27 18:17:41 +0800233 call __init_clear_bss
Graf Yangb4f5c582008-10-16 22:50:46 +0800234#endif
Mike Frysinger09e1f702008-08-06 17:15:27 +0800235 r1.l = ___bss_start;
236 r1.h = ___bss_start;
237 r2.l = ___bss_stop;
238 r2.h = ___bss_stop;
Mike Frysingerf9402602008-10-27 18:17:41 +0800239 call __init_clear_bss
Mike Frysinger09e1f702008-08-06 17:15:27 +0800240
Mike Frysinger09e1f702008-08-06 17:15:27 +0800241 /* Pass the u-boot arguments to the global value command line */
242 R0 = R7;
243 call _cmdline_init;
244
245 /* Load the current thread pointer and stack */
246 sp.l = _init_thread_union;
247 sp.h = _init_thread_union;
248 p1 = THREAD_SIZE (z);
249 sp = sp + p1;
250 usp = sp;
251 fp = sp;
Graf Yang6b3087c2009-01-07 23:14:39 +0800252 sp += -12;
253 call _init_pda
254 sp += 12;
Mike Frysinger09e1f702008-08-06 17:15:27 +0800255 jump.l _start_kernel;
256ENDPROC(_real_start)
257
258__FINIT