Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | &soc { |
| 14 | mdss_mdp: qcom,mdss_mdp@ae00000 { |
| 15 | compatible = "qcom,sde-kms"; |
Lloyd Atkinson | 8f2bd8c | 2017-04-06 11:55:49 -0700 | [diff] [blame] | 16 | reg = <0x0ae00000 0x81d40>, |
Gopikrishnaiah Anandan | 608099b | 2017-08-16 19:21:23 -0700 | [diff] [blame] | 17 | <0x0aeb0000 0x2008>; |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 18 | reg-names = "mdp_phys", |
Gopikrishnaiah Anandan | 608099b | 2017-08-16 19:21:23 -0700 | [diff] [blame] | 19 | "vbif_phys"; |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 20 | |
Dhaval Patel | 2169d61 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 21 | clocks = |
| 22 | <&clock_gcc GCC_DISP_AHB_CLK>, |
| 23 | <&clock_gcc GCC_DISP_AXI_CLK>, |
| 24 | <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, |
Alan Kwong | d5e9534 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 25 | <&clock_dispcc DISP_CC_MDSS_AXI_CLK>, |
Dhaval Patel | 2169d61 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 26 | <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, |
| 27 | <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; |
Dhaval Patel | 2cd94b1 | 2017-04-21 19:39:53 -0700 | [diff] [blame] | 28 | clock-names = "gcc_iface", "gcc_bus", "iface_clk", |
| 29 | "bus_clk", "core_clk", "vsync_clk"; |
| 30 | clock-rate = <0 0 0 0 300000000 19200000 0>; |
Narendra Muppalla | 4efd344 | 2017-07-24 17:36:15 -0700 | [diff] [blame] | 31 | clock-max-rate = <0 0 0 0 412500000 19200000 0>; |
Alan Kwong | d5e9534 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 32 | |
Dhaval Patel | 2169d61 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 33 | sde-vdd-supply = <&mdss_core_gdsc>; |
Alan Kwong | d5e9534 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 34 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 35 | /* interrupt config */ |
Archana Sathyakumar | 00a36ab | 2017-03-03 14:38:26 -0700 | [diff] [blame] | 36 | interrupt-parent = <&pdc>; |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 37 | interrupts = <0 83 0>; |
| 38 | interrupt-controller; |
| 39 | #interrupt-cells = <1>; |
Patrick Daly | caf09c9 | 2017-04-18 16:30:52 -0700 | [diff] [blame] | 40 | iommus = <&apps_smmu 0x880 0x8>, |
| 41 | <&apps_smmu 0xc80 0x8>; |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 42 | |
Dhaval Patel | d0a8404 | 2016-12-01 14:50:47 -0800 | [diff] [blame] | 43 | #address-cells = <1>; |
| 44 | #size-cells = <0>; |
| 45 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 46 | /* hw blocks */ |
| 47 | qcom,sde-off = <0x1000>; |
Lloyd Atkinson | 216e306 | 2017-01-31 08:42:38 -0800 | [diff] [blame] | 48 | qcom,sde-len = <0x45C>; |
| 49 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 50 | qcom,sde-ctl-off = <0x2000 0x2200 0x2400 |
| 51 | 0x2600 0x2800>; |
Lloyd Atkinson | 216e306 | 2017-01-31 08:42:38 -0800 | [diff] [blame] | 52 | qcom,sde-ctl-size = <0xE4>; |
| 53 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 54 | qcom,sde-mixer-off = <0x45000 0x46000 0x47000 |
| 55 | 0x48000 0x49000 0x4a000>; |
Lloyd Atkinson | 216e306 | 2017-01-31 08:42:38 -0800 | [diff] [blame] | 56 | qcom,sde-mixer-size = <0x320>; |
| 57 | |
Rajesh Yadav | ec93afb | 2017-06-08 19:28:33 +0530 | [diff] [blame] | 58 | qcom,sde-dspp-top-off = <0x1300>; |
| 59 | qcom,sde-dspp-top-size = <0xc>; |
| 60 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 61 | qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; |
Ping Li | 2d6c5f9 | 2017-05-04 14:17:03 -0700 | [diff] [blame] | 62 | qcom,sde-dspp-size = <0x17e0>; |
Lloyd Atkinson | 216e306 | 2017-01-31 08:42:38 -0800 | [diff] [blame] | 63 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 64 | qcom,sde-wb-off = <0x66000>; |
Lloyd Atkinson | 216e306 | 2017-01-31 08:42:38 -0800 | [diff] [blame] | 65 | qcom,sde-wb-size = <0x2c8>; |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 66 | qcom,sde-wb-xin-id = <6>; |
| 67 | qcom,sde-wb-id = <2>; |
Steve Cohen | 76bc098 | 2017-06-20 13:19:04 -0400 | [diff] [blame] | 68 | qcom,sde-wb-clk-ctrl = <0x3b8 24>; |
| 69 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 70 | qcom,sde-intf-off = <0x6b000 0x6b800 |
| 71 | 0x6c000 0x6c800>; |
Lloyd Atkinson | 216e306 | 2017-01-31 08:42:38 -0800 | [diff] [blame] | 72 | qcom,sde-intf-size = <0x280>; |
| 73 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 74 | qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; |
| 75 | qcom,sde-pp-off = <0x71000 0x71800 |
| 76 | 0x72000 0x72800 0x73000>; |
| 77 | qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x1>; |
Lloyd Atkinson | 216e306 | 2017-01-31 08:42:38 -0800 | [diff] [blame] | 78 | qcom,sde-pp-size = <0xd4>; |
| 79 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 80 | qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0>; |
| 81 | qcom,sde-cdm-off = <0x7a200>; |
Lloyd Atkinson | 216e306 | 2017-01-31 08:42:38 -0800 | [diff] [blame] | 82 | qcom,sde-cdm-size = <0x224>; |
| 83 | |
| 84 | qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>; |
| 85 | qcom,sde-dsc-size = <0x140>; |
| 86 | |
Narendra Muppalla | a0826c6 | 2017-06-12 11:55:33 -0700 | [diff] [blame] | 87 | qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0 0x0>; |
Ping Li | c7dd65f | 2017-03-08 12:11:01 -0800 | [diff] [blame] | 88 | qcom,sde-dither-version = <0x00010000>; |
| 89 | qcom,sde-dither-size = <0x20>; |
| 90 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 91 | qcom,sde-sspp-type = "vig", "vig", "vig", "vig", |
| 92 | "dma", "dma", "dma", "dma"; |
| 93 | |
| 94 | qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 |
| 95 | 0x25000 0x27000 0x29000 0x2b000>; |
Lloyd Atkinson | 216e306 | 2017-01-31 08:42:38 -0800 | [diff] [blame] | 96 | qcom,sde-sspp-src-size = <0x1c8>; |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 97 | |
| 98 | qcom,sde-sspp-xin-id = <0 4 8 12 |
| 99 | 1 5 9 13>; |
Veera Sundaram Sankaran | 0ea57f6 | 2017-01-16 18:08:04 -0800 | [diff] [blame] | 100 | qcom,sde-sspp-excl-rect = <1 1 1 1 |
| 101 | 1 1 1 1>; |
Jeykumar Sankaran | 0751516 | 2017-05-16 13:02:33 -0700 | [diff] [blame] | 102 | qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>; |
| 103 | qcom,sde-smart-dma-rev = "smart_dma_v2"; |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 104 | |
Veera Sundaram Sankaran | 370b991 | 2017-01-10 18:03:42 -0800 | [diff] [blame] | 105 | qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>; |
| 106 | |
| 107 | qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 |
| 108 | 0xb0 0xc8 0xe0 0xf8 0x110>; |
| 109 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 110 | /* offsets are relative to "mdp_phys + qcom,sde-off */ |
| 111 | qcom,sde-sspp-clk-ctrl = |
| 112 | <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, |
| 113 | <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; |
| 114 | qcom,sde-sspp-csc-off = <0x1a00>; |
| 115 | qcom,sde-csc-type = "csc-10bit"; |
| 116 | qcom,sde-qseed-type = "qseedv3"; |
| 117 | qcom,sde-sspp-qseed-off = <0xa00>; |
| 118 | qcom,sde-mixer-linewidth = <2560>; |
| 119 | qcom,sde-sspp-linewidth = <2560>; |
Alan Kwong | d939be4 | 2017-03-08 19:37:38 -0800 | [diff] [blame] | 120 | qcom,sde-wb-linewidth = <4096>; |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 121 | qcom,sde-mixer-blendstages = <0xb>; |
| 122 | qcom,sde-highest-bank-bit = <0x2>; |
Clarence Ip | 03f2ffe | 2017-04-28 16:12:17 -0700 | [diff] [blame] | 123 | qcom,sde-ubwc-version = <0x200>; |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 124 | qcom,sde-panic-per-pipe; |
| 125 | qcom,sde-has-cdp; |
| 126 | qcom,sde-has-src-split; |
Veera Sundaram Sankaran | 0ea57f6 | 2017-01-16 18:08:04 -0800 | [diff] [blame] | 127 | qcom,sde-has-dim-layer; |
Veera Sundaram Sankaran | a92444a | 2017-04-07 15:48:07 -0700 | [diff] [blame] | 128 | qcom,sde-has-idle-pc; |
Alan Kwong | d5e9534 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 129 | qcom,sde-max-bw-low-kbps = <9600000>; |
| 130 | qcom,sde-max-bw-high-kbps = <9600000>; |
| 131 | qcom,sde-dram-channels = <2>; |
| 132 | qcom,sde-num-nrt-paths = <0>; |
Gopikrishnaiah Anandan | aaf6dcd | 2017-02-08 14:10:18 -0800 | [diff] [blame] | 133 | qcom,sde-dspp-ad-version = <0x00040000>; |
| 134 | qcom,sde-dspp-ad-off = <0x28000 0x27000>; |
Alan Kwong | d5e9534 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 135 | |
| 136 | qcom,sde-vbif-off = <0>; |
| 137 | qcom,sde-vbif-size = <0x1040>; |
| 138 | qcom,sde-vbif-id = <0>; |
Clarence Ip | 0b5f441 | 2017-05-17 11:29:24 -0400 | [diff] [blame] | 139 | qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; |
| 140 | qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; |
Veera Sundaram Sankaran | 0ea57f6 | 2017-01-16 18:08:04 -0800 | [diff] [blame] | 141 | |
Alan Kwong | 1641b0b | 2017-04-19 09:01:13 -0700 | [diff] [blame] | 142 | qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; |
| 143 | qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; |
| 144 | |
Alan Kwong | e67b379 | 2017-04-27 15:57:50 -0700 | [diff] [blame] | 145 | qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000 |
| 146 | 0x00000000>; |
| 147 | qcom,sde-safe-lut = <0xfffc 0xff00 0xffff 0xffff>; |
| 148 | qcom,sde-qos-lut-linear = |
| 149 | <4 0x00000000 0x00000357>, |
| 150 | <5 0x00000000 0x00003357>, |
| 151 | <6 0x00000000 0x00023357>, |
| 152 | <7 0x00000000 0x00223357>, |
| 153 | <8 0x00000000 0x02223357>, |
| 154 | <9 0x00000000 0x22223357>, |
| 155 | <10 0x00000002 0x22223357>, |
| 156 | <11 0x00000022 0x22223357>, |
| 157 | <12 0x00000222 0x22223357>, |
| 158 | <13 0x00002222 0x22223357>, |
| 159 | <14 0x00012222 0x22223357>, |
| 160 | <0 0x00112222 0x22223357>; |
| 161 | qcom,sde-qos-lut-macrotile = |
| 162 | <10 0x00000003 0x44556677>, |
| 163 | <11 0x00000033 0x44556677>, |
| 164 | <12 0x00000233 0x44556677>, |
| 165 | <13 0x00002233 0x44556677>, |
| 166 | <14 0x00012233 0x44556677>, |
| 167 | <0 0x00112233 0x44556677>; |
| 168 | qcom,sde-qos-lut-nrt = |
| 169 | <0 0x00000000 0x00000000>; |
| 170 | qcom,sde-qos-lut-cwb = |
| 171 | <0 0x75300000 0x00000000>; |
| 172 | |
Alan Kwong | 23ef3f39 | 2017-04-28 11:09:06 -0700 | [diff] [blame] | 173 | qcom,sde-cdp-setting = <1 1>, <1 0>; |
| 174 | |
Alan Kwong | 0018772 | 2017-02-04 19:09:17 -0800 | [diff] [blame] | 175 | qcom,sde-inline-rotator = <&mdss_rotator 0>; |
Veera Sundaram Sankaran | 5f9ef0d | 2017-05-24 18:49:53 -0700 | [diff] [blame] | 176 | qcom,sde-inline-rot-xin = <10 11>; |
| 177 | qcom,sde-inline-rot-xin-type = "sspp", "wb"; |
| 178 | |
| 179 | /* offsets are relative to "mdp_phys + qcom,sde-off */ |
| 180 | qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>; |
Alan Kwong | 0018772 | 2017-02-04 19:09:17 -0800 | [diff] [blame] | 181 | |
Gopikrishnaiah Anandan | cd47603 | 2017-03-27 12:33:00 -0700 | [diff] [blame] | 182 | |
Veera Sundaram Sankaran | 0ea57f6 | 2017-01-16 18:08:04 -0800 | [diff] [blame] | 183 | qcom,sde-sspp-vig-blocks { |
| 184 | qcom,sde-vig-csc-off = <0x1a00>; |
| 185 | qcom,sde-vig-qseed-off = <0xa00>; |
Lloyd Atkinson | 216e306 | 2017-01-31 08:42:38 -0800 | [diff] [blame] | 186 | qcom,sde-vig-qseed-size = <0xa0>; |
Veera Sundaram Sankaran | 0ea57f6 | 2017-01-16 18:08:04 -0800 | [diff] [blame] | 187 | }; |
Alan Kwong | d5e9534 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 188 | |
Gopikrishnaiah Anandan | cd47603 | 2017-03-27 12:33:00 -0700 | [diff] [blame] | 189 | qcom,sde-dspp-blocks { |
Rajesh Yadav | ec93afb | 2017-06-08 19:28:33 +0530 | [diff] [blame] | 190 | qcom,sde-dspp-igc = <0x0 0x00030001>; |
Gopikrishnaiah Anandan | cd47603 | 2017-03-27 12:33:00 -0700 | [diff] [blame] | 191 | qcom,sde-dspp-vlut = <0xa00 0x00010008>; |
| 192 | qcom,sde-dspp-gamut = <0x1000 0x00040000>; |
Rajesh Yadav | d490cb6 | 2017-07-04 13:20:42 +0530 | [diff] [blame] | 193 | qcom,sde-dspp-pcc = <0x1700 0x00040000>; |
Gopikrishnaiah Anandan | cd47603 | 2017-03-27 12:33:00 -0700 | [diff] [blame] | 194 | qcom,sde-dspp-gc = <0x17c0 0x00010008>; |
| 195 | }; |
| 196 | |
Alan Kwong | d5e9534 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 197 | qcom,platform-supply-entries { |
| 198 | #address-cells = <1>; |
| 199 | #size-cells = <0>; |
| 200 | |
| 201 | qcom,platform-supply-entry@0 { |
| 202 | reg = <0>; |
Dhaval Patel | 2169d61 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 203 | qcom,supply-name = "sde-vdd"; |
Alan Kwong | d5e9534 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 204 | qcom,supply-min-voltage = <0>; |
| 205 | qcom,supply-max-voltage = <0>; |
| 206 | qcom,supply-enable-load = <0>; |
| 207 | qcom,supply-disable-load = <0>; |
| 208 | }; |
| 209 | }; |
| 210 | |
Abhijit Kulkarni | 1774dac | 2017-05-01 10:51:02 -0700 | [diff] [blame] | 211 | smmu_sde_sec: qcom,smmu_sde_sec_cb { |
| 212 | compatible = "qcom,smmu_sde_sec"; |
| 213 | iommus = <&apps_smmu 0x881 0x8>, |
| 214 | <&apps_smmu 0xc81 0x8>; |
| 215 | }; |
| 216 | |
Alan Kwong | d5e9534 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 217 | /* data and reg bus scale settings */ |
| 218 | qcom,sde-data-bus { |
Alan Kwong | e9b257b | 2017-05-16 11:40:50 -0700 | [diff] [blame] | 219 | qcom,msm-bus,name = "mdss_sde_mnoc"; |
Alan Kwong | d5e9534 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 220 | qcom,msm-bus,num-cases = <3>; |
| 221 | qcom,msm-bus,num-paths = <2>; |
| 222 | qcom,msm-bus,vectors-KBps = |
Alan Kwong | e9b257b | 2017-05-16 11:40:50 -0700 | [diff] [blame] | 223 | <22 773 0 0>, <23 773 0 0>, |
| 224 | <22 773 0 6400000>, <23 773 0 6400000>, |
| 225 | <22 773 0 6400000>, <23 773 0 6400000>; |
| 226 | }; |
| 227 | |
| 228 | qcom,sde-llcc-bus { |
| 229 | qcom,msm-bus,name = "mdss_sde_llcc"; |
| 230 | qcom,msm-bus,num-cases = <3>; |
| 231 | qcom,msm-bus,num-paths = <1>; |
| 232 | qcom,msm-bus,vectors-KBps = |
| 233 | <132 770 0 0>, |
| 234 | <132 770 0 6400000>, |
| 235 | <132 770 0 6400000>; |
| 236 | }; |
| 237 | |
| 238 | qcom,sde-ebi-bus { |
| 239 | qcom,msm-bus,name = "mdss_sde_ebi"; |
| 240 | qcom,msm-bus,num-cases = <3>; |
| 241 | qcom,msm-bus,num-paths = <1>; |
| 242 | qcom,msm-bus,vectors-KBps = |
| 243 | <129 512 0 0>, |
| 244 | <129 512 0 6400000>, |
| 245 | <129 512 0 6400000>; |
Alan Kwong | d5e9534 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 246 | }; |
| 247 | |
| 248 | qcom,sde-reg-bus { |
| 249 | qcom,msm-bus,name = "mdss_reg"; |
| 250 | qcom,msm-bus,num-cases = <4>; |
| 251 | qcom,msm-bus,num-paths = <1>; |
| 252 | qcom,msm-bus,active-only; |
| 253 | qcom,msm-bus,vectors-KBps = |
| 254 | <1 590 0 0>, |
| 255 | <1 590 0 76800>, |
| 256 | <1 590 0 150000>, |
| 257 | <1 590 0 300000>; |
| 258 | }; |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 259 | }; |
Dhaval Patel | d0a8404 | 2016-12-01 14:50:47 -0800 | [diff] [blame] | 260 | |
| 261 | sde_rscc: qcom,sde_rscc@af20000 { |
Dhaval Patel | d0a8404 | 2016-12-01 14:50:47 -0800 | [diff] [blame] | 262 | cell-index = <0>; |
| 263 | compatible = "qcom,sde-rsc"; |
| 264 | reg = <0xaf20000 0x1c44>, |
| 265 | <0xaf30000 0x3fd4>; |
| 266 | reg-names = "drv", "wrapper"; |
| 267 | qcom,sde-rsc-version = <1>; |
| 268 | |
| 269 | vdd-supply = <&mdss_core_gdsc>; |
Dhaval Patel | 7556ced | 2017-02-10 19:53:10 -0800 | [diff] [blame] | 270 | clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, |
| 271 | <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; |
| 272 | clock-names = "vsync_clk", "iface_clk"; |
Dhaval Patel | 2169d61 | 2017-01-30 19:38:05 -0800 | [diff] [blame] | 273 | clock-rate = <0 0>; |
| 274 | |
Dhaval Patel | d0a8404 | 2016-12-01 14:50:47 -0800 | [diff] [blame] | 275 | qcom,sde-dram-channels = <2>; |
| 276 | |
Dhaval Patel | 7556ced | 2017-02-10 19:53:10 -0800 | [diff] [blame] | 277 | mboxes = <&disp_rsc 0>; |
| 278 | mbox-names = "disp_rsc"; |
| 279 | |
Dhaval Patel | d0a8404 | 2016-12-01 14:50:47 -0800 | [diff] [blame] | 280 | /* data and reg bus scale settings */ |
| 281 | qcom,sde-data-bus { |
Alan Kwong | e9b257b | 2017-05-16 11:40:50 -0700 | [diff] [blame] | 282 | qcom,msm-bus,name = "disp_rsc_mnoc"; |
Dhaval Patel | d0a8404 | 2016-12-01 14:50:47 -0800 | [diff] [blame] | 283 | qcom,msm-bus,active-only; |
| 284 | qcom,msm-bus,num-cases = <3>; |
| 285 | qcom,msm-bus,num-paths = <2>; |
| 286 | qcom,msm-bus,vectors-KBps = |
Alan Kwong | e9b257b | 2017-05-16 11:40:50 -0700 | [diff] [blame] | 287 | <20003 20515 0 0>, <20004 20515 0 0>, |
| 288 | <20003 20515 0 6400000>, <20004 20515 0 6400000>, |
| 289 | <20003 20515 0 6400000>, <20004 20515 0 6400000>; |
| 290 | }; |
| 291 | |
| 292 | qcom,sde-llcc-bus { |
| 293 | qcom,msm-bus,name = "disp_rsc_llcc"; |
| 294 | qcom,msm-bus,active-only; |
| 295 | qcom,msm-bus,num-cases = <3>; |
| 296 | qcom,msm-bus,num-paths = <1>; |
| 297 | qcom,msm-bus,vectors-KBps = |
| 298 | <20001 20513 0 0>, |
| 299 | <20001 20513 0 6400000>, |
| 300 | <20001 20513 0 6400000>; |
| 301 | }; |
| 302 | |
| 303 | qcom,sde-ebi-bus { |
| 304 | qcom,msm-bus,name = "disp_rsc_ebi"; |
| 305 | qcom,msm-bus,active-only; |
| 306 | qcom,msm-bus,num-cases = <3>; |
| 307 | qcom,msm-bus,num-paths = <1>; |
| 308 | qcom,msm-bus,vectors-KBps = |
| 309 | <20000 20512 0 0>, |
| 310 | <20000 20512 0 6400000>, |
| 311 | <20000 20512 0 6400000>; |
Dhaval Patel | d0a8404 | 2016-12-01 14:50:47 -0800 | [diff] [blame] | 312 | }; |
Clarence Ip | 3b5b5ed | 2017-01-24 09:59:03 -0800 | [diff] [blame] | 313 | }; |
Dhaval Patel | d0a8404 | 2016-12-01 14:50:47 -0800 | [diff] [blame] | 314 | |
Clarence Ip | 3b5b5ed | 2017-01-24 09:59:03 -0800 | [diff] [blame] | 315 | mdss_rotator: qcom,mdss_rotator@ae00000 { |
Clarence Ip | 3b5b5ed | 2017-01-24 09:59:03 -0800 | [diff] [blame] | 316 | compatible = "qcom,sde_rotator"; |
| 317 | reg = <0x0ae00000 0xac000>, |
| 318 | <0x0aeb8000 0x3000>; |
| 319 | reg-names = "mdp_phys", |
| 320 | "rot_vbif_phys"; |
| 321 | |
Alan Kwong | 0018772 | 2017-02-04 19:09:17 -0800 | [diff] [blame] | 322 | #list-cells = <1>; |
| 323 | |
Clarence Ip | 3b5b5ed | 2017-01-24 09:59:03 -0800 | [diff] [blame] | 324 | qcom,mdss-rot-mode = <1>; |
| 325 | qcom,mdss-highest-bank-bit = <0x2>; |
| 326 | |
| 327 | /* Bus Scale Settings */ |
| 328 | qcom,msm-bus,name = "mdss_rotator"; |
| 329 | qcom,msm-bus,num-cases = <3>; |
| 330 | qcom,msm-bus,num-paths = <1>; |
| 331 | qcom,msm-bus,vectors-KBps = |
| 332 | <25 512 0 0>, |
| 333 | <25 512 0 6400000>, |
| 334 | <25 512 0 6400000>; |
| 335 | |
| 336 | rot-vdd-supply = <&mdss_core_gdsc>; |
| 337 | qcom,supply-names = "rot-vdd"; |
| 338 | |
| 339 | clocks = |
| 340 | <&clock_gcc GCC_DISP_AHB_CLK>, |
| 341 | <&clock_gcc GCC_DISP_AXI_CLK>, |
| 342 | <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, |
Clarence Ip | 3b5b5ed | 2017-01-24 09:59:03 -0800 | [diff] [blame] | 343 | <&clock_dispcc DISP_CC_MDSS_ROT_CLK>, |
| 344 | <&clock_dispcc DISP_CC_MDSS_AXI_CLK>; |
| 345 | clock-names = "gcc_iface", "gcc_bus", |
Clarence Ip | 015924e | 2017-05-01 13:28:03 -0700 | [diff] [blame] | 346 | "iface_clk", "rot_clk", "axi_clk"; |
Clarence Ip | 3b5b5ed | 2017-01-24 09:59:03 -0800 | [diff] [blame] | 347 | |
| 348 | interrupt-parent = <&mdss_mdp>; |
| 349 | interrupts = <2 0>; |
| 350 | |
Veera Sundaram Sankaran | 0488349 | 2017-05-12 12:35:36 -0700 | [diff] [blame] | 351 | /* Offline rotator QoS setting */ |
Veera Sundaram Sankaran | f28be03 | 2017-04-20 08:16:41 -0700 | [diff] [blame] | 352 | qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; |
Alan Kwong | 8efe4a8 | 2017-06-30 16:05:50 -0400 | [diff] [blame] | 353 | qcom,mdss-rot-vbif-memtype = <3 3>; |
Veera Sundaram Sankaran | fd4b37d | 2017-05-11 12:44:38 -0700 | [diff] [blame] | 354 | qcom,mdss-rot-cdp-setting = <1 1>; |
Veera Sundaram Sankaran | 0488349 | 2017-05-12 12:35:36 -0700 | [diff] [blame] | 355 | qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; |
| 356 | qcom,mdss-rot-danger-lut = <0x0 0x0>; |
| 357 | qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; |
| 358 | |
| 359 | /* Inline rotator QoS Setting */ |
| 360 | /* setting default register values for RD - qos/danger/safe */ |
| 361 | qcom,mdss-inline-rot-qos-lut = <0x44556677 0x00112233 |
| 362 | 0x44556677 0x00112233>; |
| 363 | qcom,mdss-inline-rot-danger-lut = <0x0055aaff 0x0000ffff>; |
| 364 | qcom,mdss-inline-rot-safe-lut = <0x0000f000 0x0000ff00>; |
Clarence Ip | 3b5b5ed | 2017-01-24 09:59:03 -0800 | [diff] [blame] | 365 | |
| 366 | qcom,mdss-default-ot-rd-limit = <32>; |
| 367 | qcom,mdss-default-ot-wr-limit = <32>; |
| 368 | |
Alan Kwong | 0018772 | 2017-02-04 19:09:17 -0800 | [diff] [blame] | 369 | qcom,mdss-sbuf-headroom = <20>; |
| 370 | |
| 371 | cache-slice-names = "rotator"; |
| 372 | cache-slices = <&llcc 4>; |
| 373 | |
Veera Sundaram Sankaran | 0641803 | 2017-06-30 14:12:58 -0700 | [diff] [blame] | 374 | /* reg bus scale settings */ |
| 375 | rot_reg: qcom,rot-reg-bus { |
| 376 | qcom,msm-bus,name = "mdss_rot_reg"; |
| 377 | qcom,msm-bus,num-cases = <2>; |
| 378 | qcom,msm-bus,num-paths = <1>; |
| 379 | qcom,msm-bus,active-only; |
| 380 | qcom,msm-bus,vectors-KBps = |
| 381 | <1 590 0 0>, |
| 382 | <1 590 0 76800>; |
| 383 | }; |
| 384 | |
Clarence Ip | 3b5b5ed | 2017-01-24 09:59:03 -0800 | [diff] [blame] | 385 | smmu_rot_unsec: qcom,smmu_rot_unsec_cb { |
| 386 | compatible = "qcom,smmu_sde_rot_unsec"; |
Patrick Daly | c4aaa90 | 2017-04-24 12:45:11 -0700 | [diff] [blame] | 387 | iommus = <&apps_smmu 0x1090 0x0>; |
Clarence Ip | 3b5b5ed | 2017-01-24 09:59:03 -0800 | [diff] [blame] | 388 | }; |
| 389 | |
| 390 | smmu_rot_sec: qcom,smmu_rot_sec_cb { |
Clarence Ip | 3b5b5ed | 2017-01-24 09:59:03 -0800 | [diff] [blame] | 391 | compatible = "qcom,smmu_sde_rot_sec"; |
Patrick Daly | c4aaa90 | 2017-04-24 12:45:11 -0700 | [diff] [blame] | 392 | iommus = <&apps_smmu 0x1091 0x0>; |
Clarence Ip | 3b5b5ed | 2017-01-24 09:59:03 -0800 | [diff] [blame] | 393 | }; |
Dhaval Patel | d0a8404 | 2016-12-01 14:50:47 -0800 | [diff] [blame] | 394 | }; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 395 | |
| 396 | mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { |
Shashank Babu Chinta Venkata | afef820 | 2017-04-21 13:49:56 -0700 | [diff] [blame] | 397 | compatible = "qcom,dsi-ctrl-hw-v2.2"; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 398 | label = "dsi-ctrl-0"; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 399 | cell-index = <0>; |
Shashank Babu Chinta Venkata | afef820 | 2017-04-21 13:49:56 -0700 | [diff] [blame] | 400 | reg = <0xae94000 0x400>, |
| 401 | <0xaf08000 0x4>; |
| 402 | reg-names = "dsi_ctrl", "disp_cc_base"; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 403 | interrupt-parent = <&mdss_mdp>; |
| 404 | interrupts = <4 0>; |
| 405 | vdda-1p2-supply = <&pm8998_l26>; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 406 | clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, |
| 407 | <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, |
| 408 | <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, |
| 409 | <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, |
Shashank Babu Chinta Venkata | f84694c | 2017-04-05 12:14:18 -0700 | [diff] [blame] | 410 | <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, |
| 411 | <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 412 | clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", |
Shashank Babu Chinta Venkata | f84694c | 2017-04-05 12:14:18 -0700 | [diff] [blame] | 413 | "pixel_clk", "pixel_clk_rcg", |
| 414 | "esc_clk"; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 415 | |
| 416 | qcom,ctrl-supply-entries { |
| 417 | #address-cells = <1>; |
| 418 | #size-cells = <0>; |
Shashank Babu Chinta Venkata | f84694c | 2017-04-05 12:14:18 -0700 | [diff] [blame] | 419 | |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 420 | qcom,ctrl-supply-entry@0 { |
| 421 | reg = <0>; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 422 | qcom,supply-name = "vdda-1p2"; |
Shashank Babu Chinta Venkata | f84694c | 2017-04-05 12:14:18 -0700 | [diff] [blame] | 423 | qcom,supply-min-voltage = <1200000>; |
| 424 | qcom,supply-max-voltage = <1200000>; |
| 425 | qcom,supply-enable-load = <21800>; |
| 426 | qcom,supply-disable-load = <4>; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 427 | }; |
| 428 | }; |
| 429 | }; |
| 430 | |
| 431 | mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { |
Shashank Babu Chinta Venkata | afef820 | 2017-04-21 13:49:56 -0700 | [diff] [blame] | 432 | compatible = "qcom,dsi-ctrl-hw-v2.2"; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 433 | label = "dsi-ctrl-1"; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 434 | cell-index = <1>; |
Shashank Babu Chinta Venkata | afef820 | 2017-04-21 13:49:56 -0700 | [diff] [blame] | 435 | reg = <0xae96000 0x400>, |
| 436 | <0xaf08000 0x4>; |
| 437 | reg-names = "dsi_ctrl", "disp_cc_base"; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 438 | interrupt-parent = <&mdss_mdp>; |
| 439 | interrupts = <5 0>; |
| 440 | vdda-1p2-supply = <&pm8998_l26>; |
Shashank Babu Chinta Venkata | f84694c | 2017-04-05 12:14:18 -0700 | [diff] [blame] | 441 | clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, |
| 442 | <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, |
| 443 | <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, |
| 444 | <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>, |
| 445 | <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, |
| 446 | <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 447 | clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", |
Shashank Babu Chinta Venkata | f84694c | 2017-04-05 12:14:18 -0700 | [diff] [blame] | 448 | "pixel_clk", "pixel_clk_rcg", "esc_clk"; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 449 | qcom,ctrl-supply-entries { |
| 450 | #address-cells = <1>; |
| 451 | #size-cells = <0>; |
| 452 | |
| 453 | qcom,ctrl-supply-entry@0 { |
| 454 | reg = <0>; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 455 | qcom,supply-name = "vdda-1p2"; |
Shashank Babu Chinta Venkata | f84694c | 2017-04-05 12:14:18 -0700 | [diff] [blame] | 456 | qcom,supply-min-voltage = <1200000>; |
| 457 | qcom,supply-max-voltage = <1200000>; |
| 458 | qcom,supply-enable-load = <21800>; |
| 459 | qcom,supply-disable-load = <4>; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 460 | }; |
| 461 | }; |
| 462 | }; |
| 463 | |
| 464 | mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { |
| 465 | compatible = "qcom,dsi-phy-v3.0"; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 466 | label = "dsi-phy-0"; |
| 467 | cell-index = <0>; |
| 468 | reg = <0xae94400 0x7c0>; |
| 469 | reg-names = "dsi_phy"; |
| 470 | gdsc-supply = <&mdss_core_gdsc>; |
Shashank Babu Chinta Venkata | f84694c | 2017-04-05 12:14:18 -0700 | [diff] [blame] | 471 | vdda-0p9-supply = <&pm8998_l1>; |
Shashank Babu Chinta Venkata | 5292d19 | 2017-04-05 15:19:17 -0700 | [diff] [blame] | 472 | qcom,platform-strength-ctrl = [55 03 |
| 473 | 55 03 |
| 474 | 55 03 |
| 475 | 55 03 |
| 476 | 55 00]; |
| 477 | qcom,platform-lane-config = [00 00 00 00 |
| 478 | 00 00 00 00 |
| 479 | 00 00 00 00 |
| 480 | 00 00 00 00 |
| 481 | 00 00 00 80]; |
| 482 | qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 483 | qcom,phy-supply-entries { |
| 484 | #address-cells = <1>; |
| 485 | #size-cells = <0>; |
| 486 | qcom,phy-supply-entry@0 { |
| 487 | reg = <0>; |
Shashank Babu Chinta Venkata | f84694c | 2017-04-05 12:14:18 -0700 | [diff] [blame] | 488 | qcom,supply-name = "vdda-0p9"; |
| 489 | qcom,supply-min-voltage = <880000>; |
| 490 | qcom,supply-max-voltage = <880000>; |
| 491 | qcom,supply-enable-load = <36000>; |
| 492 | qcom,supply-disable-load = <32>; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 493 | }; |
| 494 | }; |
| 495 | }; |
| 496 | |
| 497 | mdss_dsi_phy1: qcom,mdss_dsi_phy0@ae96400 { |
| 498 | compatible = "qcom,dsi-phy-v3.0"; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 499 | label = "dsi-phy-1"; |
| 500 | cell-index = <1>; |
| 501 | reg = <0xae96400 0x7c0>; |
| 502 | reg-names = "dsi_phy"; |
| 503 | gdsc-supply = <&mdss_core_gdsc>; |
Shashank Babu Chinta Venkata | f84694c | 2017-04-05 12:14:18 -0700 | [diff] [blame] | 504 | vdda-0p9-supply = <&pm8998_l1>; |
Shashank Babu Chinta Venkata | 5292d19 | 2017-04-05 15:19:17 -0700 | [diff] [blame] | 505 | qcom,platform-strength-ctrl = [55 03 |
| 506 | 55 03 |
| 507 | 55 03 |
| 508 | 55 03 |
| 509 | 55 00]; |
| 510 | qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; |
| 511 | qcom,platform-lane-config = [00 00 00 00 |
| 512 | 00 00 00 00 |
| 513 | 00 00 00 00 |
| 514 | 00 00 00 00 |
| 515 | 00 00 00 80]; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 516 | qcom,phy-supply-entries { |
| 517 | #address-cells = <1>; |
| 518 | #size-cells = <0>; |
| 519 | qcom,phy-supply-entry@0 { |
| 520 | reg = <0>; |
Shashank Babu Chinta Venkata | f84694c | 2017-04-05 12:14:18 -0700 | [diff] [blame] | 521 | qcom,supply-name = "vdda-0p9"; |
| 522 | qcom,supply-min-voltage = <880000>; |
| 523 | qcom,supply-max-voltage = <880000>; |
| 524 | qcom,supply-enable-load = <36000>; |
| 525 | qcom,supply-disable-load = <32>; |
Shashank Babu Chinta Venkata | 24bdd05 | 2017-02-24 14:29:09 -0800 | [diff] [blame] | 526 | }; |
| 527 | }; |
| 528 | }; |
| 529 | |
Dhaval Patel | 6a5bd8b | 2016-10-10 14:12:10 -0700 | [diff] [blame] | 530 | }; |