Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Deepak Katragadda | 9abd794 | 2017-06-13 14:20:09 -0700 | [diff] [blame] | 14 | #define pr_fmt(fmt) "clk: %s: " fmt, __func__ |
| 15 | |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/of.h> |
| 21 | #include <linux/of_device.h> |
| 22 | #include <linux/clk.h> |
| 23 | #include <linux/clk-provider.h> |
| 24 | #include <linux/regmap.h> |
| 25 | #include <linux/mfd/syscon.h> |
| 26 | |
| 27 | #include "clk-debug.h" |
| 28 | |
| 29 | static struct measure_clk_data debug_mux_priv = { |
| 30 | .ctl_reg = 0x62024, |
| 31 | .status_reg = 0x62028, |
| 32 | .xo_div4_cbcr = 0x43008, |
| 33 | }; |
| 34 | |
| 35 | static const char *const debug_mux_parent_names[] = { |
| 36 | "cam_cc_bps_ahb_clk", |
| 37 | "cam_cc_bps_areg_clk", |
| 38 | "cam_cc_bps_axi_clk", |
| 39 | "cam_cc_bps_clk", |
| 40 | "cam_cc_camnoc_atb_clk", |
| 41 | "cam_cc_camnoc_axi_clk", |
| 42 | "cam_cc_cci_clk", |
| 43 | "cam_cc_cpas_ahb_clk", |
| 44 | "cam_cc_csi0phytimer_clk", |
| 45 | "cam_cc_csi1phytimer_clk", |
| 46 | "cam_cc_csi2phytimer_clk", |
| 47 | "cam_cc_csiphy0_clk", |
| 48 | "cam_cc_csiphy1_clk", |
| 49 | "cam_cc_csiphy2_clk", |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 50 | "cam_cc_csiphy3_clk", |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 51 | "cam_cc_fd_core_clk", |
| 52 | "cam_cc_fd_core_uar_clk", |
| 53 | "cam_cc_icp_apb_clk", |
| 54 | "cam_cc_icp_atb_clk", |
| 55 | "cam_cc_icp_clk", |
| 56 | "cam_cc_icp_cti_clk", |
| 57 | "cam_cc_icp_ts_clk", |
| 58 | "cam_cc_ife_0_axi_clk", |
| 59 | "cam_cc_ife_0_clk", |
| 60 | "cam_cc_ife_0_cphy_rx_clk", |
| 61 | "cam_cc_ife_0_csid_clk", |
| 62 | "cam_cc_ife_0_dsp_clk", |
| 63 | "cam_cc_ife_1_axi_clk", |
| 64 | "cam_cc_ife_1_clk", |
| 65 | "cam_cc_ife_1_cphy_rx_clk", |
| 66 | "cam_cc_ife_1_csid_clk", |
| 67 | "cam_cc_ife_1_dsp_clk", |
| 68 | "cam_cc_ife_lite_clk", |
| 69 | "cam_cc_ife_lite_cphy_rx_clk", |
| 70 | "cam_cc_ife_lite_csid_clk", |
| 71 | "cam_cc_ipe_0_ahb_clk", |
| 72 | "cam_cc_ipe_0_areg_clk", |
| 73 | "cam_cc_ipe_0_axi_clk", |
| 74 | "cam_cc_ipe_0_clk", |
| 75 | "cam_cc_ipe_1_ahb_clk", |
| 76 | "cam_cc_ipe_1_areg_clk", |
| 77 | "cam_cc_ipe_1_axi_clk", |
| 78 | "cam_cc_ipe_1_clk", |
| 79 | "cam_cc_jpeg_clk", |
| 80 | "cam_cc_lrme_clk", |
| 81 | "cam_cc_mclk0_clk", |
| 82 | "cam_cc_mclk1_clk", |
| 83 | "cam_cc_mclk2_clk", |
| 84 | "cam_cc_mclk3_clk", |
| 85 | "cam_cc_soc_ahb_clk", |
| 86 | "cam_cc_sys_tmr_clk", |
| 87 | "disp_cc_mdss_ahb_clk", |
| 88 | "disp_cc_mdss_axi_clk", |
| 89 | "disp_cc_mdss_byte0_clk", |
| 90 | "disp_cc_mdss_byte0_intf_clk", |
| 91 | "disp_cc_mdss_byte1_clk", |
| 92 | "disp_cc_mdss_byte1_intf_clk", |
| 93 | "disp_cc_mdss_dp_aux_clk", |
| 94 | "disp_cc_mdss_dp_crypto_clk", |
| 95 | "disp_cc_mdss_dp_link_clk", |
| 96 | "disp_cc_mdss_dp_link_intf_clk", |
| 97 | "disp_cc_mdss_dp_pixel1_clk", |
| 98 | "disp_cc_mdss_dp_pixel_clk", |
| 99 | "disp_cc_mdss_esc0_clk", |
| 100 | "disp_cc_mdss_esc1_clk", |
| 101 | "disp_cc_mdss_mdp_clk", |
| 102 | "disp_cc_mdss_mdp_lut_clk", |
| 103 | "disp_cc_mdss_pclk0_clk", |
| 104 | "disp_cc_mdss_pclk1_clk", |
| 105 | "disp_cc_mdss_qdss_at_clk", |
| 106 | "disp_cc_mdss_qdss_tsctr_div8_clk", |
| 107 | "disp_cc_mdss_rot_clk", |
| 108 | "disp_cc_mdss_rscc_ahb_clk", |
| 109 | "disp_cc_mdss_rscc_vsync_clk", |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 110 | "disp_cc_mdss_vsync_clk", |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 111 | "measure_only_snoc_clk", |
| 112 | "measure_only_cnoc_clk", |
| 113 | "measure_only_bimc_clk", |
| 114 | "measure_only_ipa_2x_clk", |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 115 | "gcc_aggre_noc_pcie_tbu_clk", |
| 116 | "gcc_aggre_ufs_card_axi_clk", |
| 117 | "gcc_aggre_ufs_phy_axi_clk", |
| 118 | "gcc_aggre_usb3_prim_axi_clk", |
| 119 | "gcc_aggre_usb3_sec_axi_clk", |
| 120 | "gcc_boot_rom_ahb_clk", |
| 121 | "gcc_camera_ahb_clk", |
| 122 | "gcc_camera_axi_clk", |
| 123 | "gcc_camera_xo_clk", |
| 124 | "gcc_ce1_ahb_clk", |
| 125 | "gcc_ce1_axi_clk", |
| 126 | "gcc_ce1_clk", |
| 127 | "gcc_cfg_noc_usb3_prim_axi_clk", |
| 128 | "gcc_cfg_noc_usb3_sec_axi_clk", |
| 129 | "gcc_cpuss_ahb_clk", |
| 130 | "gcc_cpuss_dvm_bus_clk", |
| 131 | "gcc_cpuss_gnoc_clk", |
| 132 | "gcc_cpuss_rbcpr_clk", |
| 133 | "gcc_ddrss_gpu_axi_clk", |
| 134 | "gcc_disp_ahb_clk", |
| 135 | "gcc_disp_axi_clk", |
| 136 | "gcc_disp_gpll0_clk_src", |
| 137 | "gcc_disp_gpll0_div_clk_src", |
| 138 | "gcc_disp_xo_clk", |
| 139 | "gcc_gp1_clk", |
| 140 | "gcc_gp2_clk", |
| 141 | "gcc_gp3_clk", |
| 142 | "gcc_gpu_cfg_ahb_clk", |
| 143 | "gcc_gpu_gpll0_clk_src", |
| 144 | "gcc_gpu_gpll0_div_clk_src", |
| 145 | "gcc_gpu_memnoc_gfx_clk", |
| 146 | "gcc_gpu_snoc_dvm_gfx_clk", |
| 147 | "gcc_mss_axis2_clk", |
| 148 | "gcc_mss_cfg_ahb_clk", |
| 149 | "gcc_mss_gpll0_div_clk_src", |
| 150 | "gcc_mss_mfab_axis_clk", |
| 151 | "gcc_mss_q6_memnoc_axi_clk", |
| 152 | "gcc_mss_snoc_axi_clk", |
| 153 | "gcc_pcie_0_aux_clk", |
| 154 | "gcc_pcie_0_cfg_ahb_clk", |
| 155 | "gcc_pcie_0_mstr_axi_clk", |
| 156 | "gcc_pcie_0_pipe_clk", |
| 157 | "gcc_pcie_0_slv_axi_clk", |
| 158 | "gcc_pcie_0_slv_q2a_axi_clk", |
| 159 | "gcc_pcie_1_aux_clk", |
| 160 | "gcc_pcie_1_cfg_ahb_clk", |
| 161 | "gcc_pcie_1_mstr_axi_clk", |
| 162 | "gcc_pcie_1_pipe_clk", |
| 163 | "gcc_pcie_1_slv_axi_clk", |
| 164 | "gcc_pcie_1_slv_q2a_axi_clk", |
| 165 | "gcc_pcie_phy_aux_clk", |
| 166 | "gcc_pcie_phy_refgen_clk", |
| 167 | "gcc_pdm2_clk", |
| 168 | "gcc_pdm_ahb_clk", |
| 169 | "gcc_pdm_xo4_clk", |
| 170 | "gcc_prng_ahb_clk", |
| 171 | "gcc_qmip_camera_ahb_clk", |
| 172 | "gcc_qmip_disp_ahb_clk", |
| 173 | "gcc_qmip_video_ahb_clk", |
| 174 | "gcc_qupv3_wrap0_core_2x_clk", |
| 175 | "gcc_qupv3_wrap0_core_clk", |
| 176 | "gcc_qupv3_wrap0_s0_clk", |
| 177 | "gcc_qupv3_wrap0_s1_clk", |
| 178 | "gcc_qupv3_wrap0_s2_clk", |
| 179 | "gcc_qupv3_wrap0_s3_clk", |
| 180 | "gcc_qupv3_wrap0_s4_clk", |
| 181 | "gcc_qupv3_wrap0_s5_clk", |
| 182 | "gcc_qupv3_wrap0_s6_clk", |
| 183 | "gcc_qupv3_wrap0_s7_clk", |
| 184 | "gcc_qupv3_wrap1_core_2x_clk", |
| 185 | "gcc_qupv3_wrap1_core_clk", |
| 186 | "gcc_qupv3_wrap1_s0_clk", |
| 187 | "gcc_qupv3_wrap1_s1_clk", |
| 188 | "gcc_qupv3_wrap1_s2_clk", |
| 189 | "gcc_qupv3_wrap1_s3_clk", |
| 190 | "gcc_qupv3_wrap1_s4_clk", |
| 191 | "gcc_qupv3_wrap1_s5_clk", |
| 192 | "gcc_qupv3_wrap1_s6_clk", |
| 193 | "gcc_qupv3_wrap1_s7_clk", |
| 194 | "gcc_qupv3_wrap_0_m_ahb_clk", |
| 195 | "gcc_qupv3_wrap_0_s_ahb_clk", |
| 196 | "gcc_qupv3_wrap_1_m_ahb_clk", |
| 197 | "gcc_qupv3_wrap_1_s_ahb_clk", |
| 198 | "gcc_sdcc2_ahb_clk", |
| 199 | "gcc_sdcc2_apps_clk", |
| 200 | "gcc_sdcc4_ahb_clk", |
| 201 | "gcc_sdcc4_apps_clk", |
| 202 | "gcc_sys_noc_cpuss_ahb_clk", |
| 203 | "gcc_tsif_ahb_clk", |
| 204 | "gcc_tsif_inactivity_timers_clk", |
| 205 | "gcc_tsif_ref_clk", |
| 206 | "gcc_ufs_card_ahb_clk", |
| 207 | "gcc_ufs_card_axi_clk", |
| 208 | "gcc_ufs_card_ice_core_clk", |
| 209 | "gcc_ufs_card_phy_aux_clk", |
| 210 | "gcc_ufs_card_rx_symbol_0_clk", |
| 211 | "gcc_ufs_card_rx_symbol_1_clk", |
| 212 | "gcc_ufs_card_tx_symbol_0_clk", |
| 213 | "gcc_ufs_card_unipro_core_clk", |
| 214 | "gcc_ufs_phy_ahb_clk", |
| 215 | "gcc_ufs_phy_axi_clk", |
| 216 | "gcc_ufs_phy_ice_core_clk", |
| 217 | "gcc_ufs_phy_phy_aux_clk", |
| 218 | "gcc_ufs_phy_rx_symbol_0_clk", |
| 219 | "gcc_ufs_phy_rx_symbol_1_clk", |
| 220 | "gcc_ufs_phy_tx_symbol_0_clk", |
| 221 | "gcc_ufs_phy_unipro_core_clk", |
| 222 | "gcc_usb30_prim_master_clk", |
| 223 | "gcc_usb30_prim_mock_utmi_clk", |
| 224 | "gcc_usb30_prim_sleep_clk", |
| 225 | "gcc_usb30_sec_master_clk", |
| 226 | "gcc_usb30_sec_mock_utmi_clk", |
| 227 | "gcc_usb30_sec_sleep_clk", |
| 228 | "gcc_usb3_prim_phy_aux_clk", |
| 229 | "gcc_usb3_prim_phy_com_aux_clk", |
| 230 | "gcc_usb3_prim_phy_pipe_clk", |
| 231 | "gcc_usb3_sec_phy_aux_clk", |
| 232 | "gcc_usb3_sec_phy_com_aux_clk", |
| 233 | "gcc_usb3_sec_phy_pipe_clk", |
| 234 | "gcc_usb_phy_cfg_ahb2phy_clk", |
| 235 | "gcc_video_ahb_clk", |
| 236 | "gcc_video_axi_clk", |
| 237 | "gcc_video_xo_clk", |
| 238 | "gpu_cc_acd_cxo_clk", |
| 239 | "gpu_cc_ahb_clk", |
| 240 | "gpu_cc_crc_ahb_clk", |
| 241 | "gpu_cc_cx_apb_clk", |
| 242 | "gpu_cc_cx_gfx3d_clk", |
| 243 | "gpu_cc_cx_gfx3d_slv_clk", |
| 244 | "gpu_cc_cx_gmu_clk", |
| 245 | "gpu_cc_cx_qdss_at_clk", |
| 246 | "gpu_cc_cx_qdss_trig_clk", |
| 247 | "gpu_cc_cx_qdss_tsctr_clk", |
| 248 | "gpu_cc_cx_snoc_dvm_clk", |
| 249 | "gpu_cc_cxo_aon_clk", |
| 250 | "gpu_cc_cxo_clk", |
Deepak Katragadda | 15d34db | 2017-06-01 11:19:23 -0700 | [diff] [blame] | 251 | "gpu_cc_gx_gfx3d_clk", |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 252 | "gpu_cc_gx_gmu_clk", |
| 253 | "gpu_cc_gx_qdss_tsctr_clk", |
| 254 | "gpu_cc_gx_vsense_clk", |
| 255 | "gpu_cc_rbcpr_ahb_clk", |
| 256 | "gpu_cc_rbcpr_clk", |
| 257 | "gpu_cc_sleep_clk", |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 258 | "video_cc_apb_clk", |
| 259 | "video_cc_at_clk", |
| 260 | "video_cc_qdss_trig_clk", |
| 261 | "video_cc_qdss_tsctr_div8_clk", |
| 262 | "video_cc_vcodec0_axi_clk", |
| 263 | "video_cc_vcodec0_core_clk", |
| 264 | "video_cc_vcodec1_axi_clk", |
| 265 | "video_cc_vcodec1_core_clk", |
| 266 | "video_cc_venus_ahb_clk", |
| 267 | "video_cc_venus_ctl_axi_clk", |
| 268 | "video_cc_venus_ctl_core_clk", |
Deepak Katragadda | bca4a87 | 2017-04-24 15:51:03 -0700 | [diff] [blame] | 269 | "l3_clk", |
| 270 | "pwrcl_clk", |
| 271 | "perfcl_clk", |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 272 | }; |
| 273 | |
| 274 | static struct clk_debug_mux gcc_debug_mux = { |
| 275 | .priv = &debug_mux_priv, |
| 276 | .debug_offset = 0x62008, |
| 277 | .post_div_offset = 0x62000, |
| 278 | .cbcr_offset = 0x62004, |
| 279 | .src_sel_mask = 0x3FF, |
| 280 | .src_sel_shift = 0, |
| 281 | .post_div_mask = 0xF, |
| 282 | .post_div_shift = 0, |
| 283 | MUX_SRC_LIST( |
| 284 | { "cam_cc_bps_ahb_clk", 0x46, 4, CAM_CC, |
| 285 | 0xE, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 286 | { "cam_cc_bps_areg_clk", 0x46, 4, CAM_CC, |
| 287 | 0xD, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 288 | { "cam_cc_bps_axi_clk", 0x46, 4, CAM_CC, |
| 289 | 0xC, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 290 | { "cam_cc_bps_clk", 0x46, 4, CAM_CC, |
| 291 | 0xB, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 292 | { "cam_cc_camnoc_atb_clk", 0x46, 4, CAM_CC, |
| 293 | 0x34, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 294 | { "cam_cc_camnoc_axi_clk", 0x46, 4, CAM_CC, |
| 295 | 0x2D, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 296 | { "cam_cc_cci_clk", 0x46, 4, CAM_CC, |
| 297 | 0x2A, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 298 | { "cam_cc_cpas_ahb_clk", 0x46, 4, CAM_CC, |
| 299 | 0x2C, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 300 | { "cam_cc_csi0phytimer_clk", 0x46, 4, CAM_CC, |
| 301 | 0x5, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 302 | { "cam_cc_csi1phytimer_clk", 0x46, 4, CAM_CC, |
| 303 | 0x7, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 304 | { "cam_cc_csi2phytimer_clk", 0x46, 4, CAM_CC, |
| 305 | 0x9, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 306 | { "cam_cc_csiphy0_clk", 0x46, 4, CAM_CC, |
| 307 | 0x6, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 308 | { "cam_cc_csiphy1_clk", 0x46, 4, CAM_CC, |
| 309 | 0x8, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 310 | { "cam_cc_csiphy2_clk", 0x46, 4, CAM_CC, |
| 311 | 0xA, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 312 | { "cam_cc_csiphy3_clk", 0x46, 4, CAM_CC, |
| 313 | 0x36, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 314 | { "cam_cc_fd_core_clk", 0x46, 4, CAM_CC, |
| 315 | 0x28, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 316 | { "cam_cc_fd_core_uar_clk", 0x46, 4, CAM_CC, |
| 317 | 0x29, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 318 | { "cam_cc_icp_apb_clk", 0x46, 4, CAM_CC, |
| 319 | 0x32, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 320 | { "cam_cc_icp_atb_clk", 0x46, 4, CAM_CC, |
| 321 | 0x2F, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 322 | { "cam_cc_icp_clk", 0x46, 4, CAM_CC, |
| 323 | 0x26, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 324 | { "cam_cc_icp_cti_clk", 0x46, 4, CAM_CC, |
| 325 | 0x30, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 326 | { "cam_cc_icp_ts_clk", 0x46, 4, CAM_CC, |
| 327 | 0x31, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 328 | { "cam_cc_ife_0_axi_clk", 0x46, 4, CAM_CC, |
| 329 | 0x1B, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 330 | { "cam_cc_ife_0_clk", 0x46, 4, CAM_CC, |
| 331 | 0x17, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 332 | { "cam_cc_ife_0_cphy_rx_clk", 0x46, 4, CAM_CC, |
| 333 | 0x1A, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 334 | { "cam_cc_ife_0_csid_clk", 0x46, 4, CAM_CC, |
| 335 | 0x19, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 336 | { "cam_cc_ife_0_dsp_clk", 0x46, 4, CAM_CC, |
| 337 | 0x18, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 338 | { "cam_cc_ife_1_axi_clk", 0x46, 4, CAM_CC, |
| 339 | 0x21, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 340 | { "cam_cc_ife_1_clk", 0x46, 4, CAM_CC, |
| 341 | 0x1D, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 342 | { "cam_cc_ife_1_cphy_rx_clk", 0x46, 4, CAM_CC, |
| 343 | 0x20, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 344 | { "cam_cc_ife_1_csid_clk", 0x46, 4, CAM_CC, |
| 345 | 0x1F, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 346 | { "cam_cc_ife_1_dsp_clk", 0x46, 4, CAM_CC, |
| 347 | 0x1E, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 348 | { "cam_cc_ife_lite_clk", 0x46, 4, CAM_CC, |
| 349 | 0x22, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 350 | { "cam_cc_ife_lite_cphy_rx_clk", 0x46, 4, CAM_CC, |
| 351 | 0x24, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 352 | { "cam_cc_ife_lite_csid_clk", 0x46, 4, CAM_CC, |
| 353 | 0x23, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 354 | { "cam_cc_ipe_0_ahb_clk", 0x46, 4, CAM_CC, |
| 355 | 0x12, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 356 | { "cam_cc_ipe_0_areg_clk", 0x46, 4, CAM_CC, |
| 357 | 0x11, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 358 | { "cam_cc_ipe_0_axi_clk", 0x46, 4, CAM_CC, |
| 359 | 0x10, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 360 | { "cam_cc_ipe_0_clk", 0x46, 4, CAM_CC, |
| 361 | 0xF, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 362 | { "cam_cc_ipe_1_ahb_clk", 0x46, 4, CAM_CC, |
| 363 | 0x16, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 364 | { "cam_cc_ipe_1_areg_clk", 0x46, 4, CAM_CC, |
| 365 | 0x15, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 366 | { "cam_cc_ipe_1_axi_clk", 0x46, 4, CAM_CC, |
| 367 | 0x14, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 368 | { "cam_cc_ipe_1_clk", 0x46, 4, CAM_CC, |
| 369 | 0x13, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 370 | { "cam_cc_jpeg_clk", 0x46, 4, CAM_CC, |
| 371 | 0x25, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 372 | { "cam_cc_lrme_clk", 0x46, 4, CAM_CC, |
| 373 | 0x2B, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 374 | { "cam_cc_mclk0_clk", 0x46, 4, CAM_CC, |
| 375 | 0x1, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 376 | { "cam_cc_mclk1_clk", 0x46, 4, CAM_CC, |
| 377 | 0x2, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 378 | { "cam_cc_mclk2_clk", 0x46, 4, CAM_CC, |
| 379 | 0x3, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 380 | { "cam_cc_mclk3_clk", 0x46, 4, CAM_CC, |
| 381 | 0x4, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 382 | { "cam_cc_soc_ahb_clk", 0x46, 4, CAM_CC, |
| 383 | 0x2E, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 384 | { "cam_cc_sys_tmr_clk", 0x46, 4, CAM_CC, |
| 385 | 0x33, 0xFF, 0, 0x3, 0, 1, 0xC000, 0xC004, 0xC008 }, |
| 386 | { "disp_cc_mdss_ahb_clk", 0x47, 4, DISP_CC, |
| 387 | 0x13, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 388 | { "disp_cc_mdss_axi_clk", 0x47, 4, DISP_CC, |
| 389 | 0x14, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 390 | { "disp_cc_mdss_byte0_clk", 0x47, 4, DISP_CC, |
| 391 | 0x7, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 392 | { "disp_cc_mdss_byte0_intf_clk", 0x47, 4, DISP_CC, |
| 393 | 0x8, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 394 | { "disp_cc_mdss_byte1_clk", 0x47, 4, DISP_CC, |
| 395 | 0x9, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 396 | { "disp_cc_mdss_byte1_intf_clk", 0x47, 4, DISP_CC, |
| 397 | 0xA, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 398 | { "disp_cc_mdss_dp_aux_clk", 0x47, 4, DISP_CC, |
| 399 | 0x12, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 400 | { "disp_cc_mdss_dp_crypto_clk", 0x47, 4, DISP_CC, |
| 401 | 0xF, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 402 | { "disp_cc_mdss_dp_link_clk", 0x47, 4, DISP_CC, |
| 403 | 0xD, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 404 | { "disp_cc_mdss_dp_link_intf_clk", 0x47, 4, DISP_CC, |
| 405 | 0xE, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 406 | { "disp_cc_mdss_dp_pixel1_clk", 0x47, 4, DISP_CC, |
| 407 | 0x11, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 408 | { "disp_cc_mdss_dp_pixel_clk", 0x47, 4, DISP_CC, |
| 409 | 0x10, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 410 | { "disp_cc_mdss_esc0_clk", 0x47, 4, DISP_CC, |
| 411 | 0xB, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 412 | { "disp_cc_mdss_esc1_clk", 0x47, 4, DISP_CC, |
| 413 | 0xC, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 414 | { "disp_cc_mdss_mdp_clk", 0x47, 4, DISP_CC, |
| 415 | 0x3, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 416 | { "disp_cc_mdss_mdp_lut_clk", 0x47, 4, DISP_CC, |
| 417 | 0x5, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 418 | { "disp_cc_mdss_pclk0_clk", 0x47, 4, DISP_CC, |
| 419 | 0x1, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 420 | { "disp_cc_mdss_pclk1_clk", 0x47, 4, DISP_CC, |
| 421 | 0x2, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 422 | { "disp_cc_mdss_qdss_at_clk", 0x47, 4, DISP_CC, |
| 423 | 0x15, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 424 | { "disp_cc_mdss_qdss_tsctr_div8_clk", 0x47, 4, DISP_CC, |
| 425 | 0x16, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 426 | { "disp_cc_mdss_rot_clk", 0x47, 4, DISP_CC, |
| 427 | 0x4, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 428 | { "disp_cc_mdss_rscc_ahb_clk", 0x47, 4, DISP_CC, |
| 429 | 0x17, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
| 430 | { "disp_cc_mdss_rscc_vsync_clk", 0x47, 4, DISP_CC, |
| 431 | 0x18, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 432 | { "disp_cc_mdss_vsync_clk", 0x47, 4, DISP_CC, |
| 433 | 0x6, 0xFF, 0, 0x3, 0, 1, 0x6000, 0x6008, 0x600C }, |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 434 | { "measure_only_snoc_clk", 0x7, 4, GCC, |
| 435 | 0x7, 0x3FFF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 436 | { "measure_only_cnoc_clk", 0x15, 4, GCC, |
| 437 | 0x7, 0x3FFF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 438 | { "measure_only_bimc_clk", 0xc2, 4, GCC, |
| 439 | 0x7, 0x3FFF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 440 | { "measure_only_ipa_2x_clk", 0x128, 4, GCC, |
| 441 | 0x7, 0x3FFF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 442 | { "gcc_aggre_noc_pcie_tbu_clk", 0x2D, 4, GCC, |
| 443 | 0x2D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 444 | { "gcc_aggre_ufs_card_axi_clk", 0x11E, 4, GCC, |
| 445 | 0x11E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 446 | { "gcc_aggre_ufs_phy_axi_clk", 0x11D, 4, GCC, |
| 447 | 0x11D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 448 | { "gcc_aggre_usb3_prim_axi_clk", 0x11B, 4, GCC, |
| 449 | 0x11B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 450 | { "gcc_aggre_usb3_sec_axi_clk", 0x11C, 4, GCC, |
| 451 | 0x11C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 452 | { "gcc_boot_rom_ahb_clk", 0x94, 4, GCC, |
| 453 | 0x94, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 454 | { "gcc_camera_ahb_clk", 0x3A, 4, GCC, |
| 455 | 0x3A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 456 | { "gcc_camera_axi_clk", 0x40, 4, GCC, |
| 457 | 0x40, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 458 | { "gcc_camera_xo_clk", 0x43, 4, GCC, |
| 459 | 0x43, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 460 | { "gcc_ce1_ahb_clk", 0xA9, 4, GCC, |
| 461 | 0xA9, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 462 | { "gcc_ce1_axi_clk", 0xA8, 4, GCC, |
| 463 | 0xA8, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 464 | { "gcc_ce1_clk", 0xA7, 4, GCC, |
| 465 | 0xA7, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 466 | { "gcc_cfg_noc_usb3_prim_axi_clk", 0x1D, 4, GCC, |
| 467 | 0x1D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 468 | { "gcc_cfg_noc_usb3_sec_axi_clk", 0x1E, 4, GCC, |
| 469 | 0x1E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 470 | { "gcc_cpuss_ahb_clk", 0xCE, 4, GCC, |
| 471 | 0xCE, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 472 | { "gcc_cpuss_dvm_bus_clk", 0xD3, 4, GCC, |
| 473 | 0xD3, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 474 | { "gcc_cpuss_gnoc_clk", 0xCF, 4, GCC, |
| 475 | 0xCF, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 476 | { "gcc_cpuss_rbcpr_clk", 0xD0, 4, GCC, |
| 477 | 0xD0, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 478 | { "gcc_ddrss_gpu_axi_clk", 0xBB, 4, GCC, |
| 479 | 0xBB, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 480 | { "gcc_disp_ahb_clk", 0x3B, 4, GCC, |
| 481 | 0x3B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 482 | { "gcc_disp_axi_clk", 0x41, 4, GCC, |
| 483 | 0x41, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 484 | { "gcc_disp_gpll0_clk_src", 0x4C, 4, GCC, |
| 485 | 0x4C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 486 | { "gcc_disp_gpll0_div_clk_src", 0x4D, 4, GCC, |
| 487 | 0x4D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 488 | { "gcc_disp_xo_clk", 0x44, 4, GCC, |
| 489 | 0x44, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 490 | { "gcc_gp1_clk", 0xDE, 4, GCC, |
| 491 | 0xDE, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 492 | { "gcc_gp2_clk", 0xDF, 4, GCC, |
| 493 | 0xDF, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 494 | { "gcc_gp3_clk", 0xE0, 4, GCC, |
| 495 | 0xE0, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 496 | { "gcc_gpu_cfg_ahb_clk", 0x142, 4, GCC, |
| 497 | 0x142, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 498 | { "gcc_gpu_gpll0_clk_src", 0x148, 4, GCC, |
| 499 | 0x148, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 500 | { "gcc_gpu_gpll0_div_clk_src", 0x149, 4, GCC, |
| 501 | 0x149, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 502 | { "gcc_gpu_memnoc_gfx_clk", 0x145, 4, GCC, |
| 503 | 0x145, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 504 | { "gcc_gpu_snoc_dvm_gfx_clk", 0x147, 4, GCC, |
| 505 | 0x147, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 506 | { "gcc_mss_axis2_clk", 0x12F, 4, GCC, |
| 507 | 0x12F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 508 | { "gcc_mss_cfg_ahb_clk", 0x12D, 4, GCC, |
| 509 | 0x12D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 510 | { "gcc_mss_gpll0_div_clk_src", 0x133, 4, GCC, |
| 511 | 0x133, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 512 | { "gcc_mss_mfab_axis_clk", 0x12E, 4, GCC, |
| 513 | 0x12E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 514 | { "gcc_mss_q6_memnoc_axi_clk", 0x135, 4, GCC, |
| 515 | 0x135, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 516 | { "gcc_mss_snoc_axi_clk", 0x134, 4, GCC, |
| 517 | 0x134, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 518 | { "gcc_pcie_0_aux_clk", 0xE5, 4, GCC, |
| 519 | 0xE5, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 520 | { "gcc_pcie_0_cfg_ahb_clk", 0xE4, 4, GCC, |
| 521 | 0xE4, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 522 | { "gcc_pcie_0_mstr_axi_clk", 0xE3, 4, GCC, |
| 523 | 0xE3, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 524 | { "gcc_pcie_0_pipe_clk", 0xE6, 4, GCC, |
| 525 | 0xE6, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 526 | { "gcc_pcie_0_slv_axi_clk", 0xE2, 4, GCC, |
| 527 | 0xE2, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 528 | { "gcc_pcie_0_slv_q2a_axi_clk", 0xE1, 4, GCC, |
| 529 | 0xE1, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 530 | { "gcc_pcie_1_aux_clk", 0xEC, 4, GCC, |
| 531 | 0xEC, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 532 | { "gcc_pcie_1_cfg_ahb_clk", 0xEB, 4, GCC, |
| 533 | 0xEB, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 534 | { "gcc_pcie_1_mstr_axi_clk", 0xEA, 4, GCC, |
| 535 | 0xEA, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 536 | { "gcc_pcie_1_pipe_clk", 0xED, 4, GCC, |
| 537 | 0xED, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 538 | { "gcc_pcie_1_slv_axi_clk", 0xE9, 4, GCC, |
| 539 | 0xE9, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 540 | { "gcc_pcie_1_slv_q2a_axi_clk", 0xE8, 4, GCC, |
| 541 | 0xE8, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 542 | { "gcc_pcie_phy_aux_clk", 0xEF, 4, GCC, |
| 543 | 0xEF, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 544 | { "gcc_pcie_phy_refgen_clk", 0x160, 4, GCC, |
| 545 | 0x160, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 546 | { "gcc_pdm2_clk", 0x8E, 4, GCC, |
| 547 | 0x8E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 548 | { "gcc_pdm_ahb_clk", 0x8C, 4, GCC, |
| 549 | 0x8C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 550 | { "gcc_pdm_xo4_clk", 0x8D, 4, GCC, |
| 551 | 0x8D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 552 | { "gcc_prng_ahb_clk", 0x8F, 4, GCC, |
| 553 | 0x8F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 554 | { "gcc_qmip_camera_ahb_clk", 0x3D, 4, GCC, |
| 555 | 0x3D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 556 | { "gcc_qmip_disp_ahb_clk", 0x3E, 4, GCC, |
| 557 | 0x3E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 558 | { "gcc_qmip_video_ahb_clk", 0x3C, 4, GCC, |
| 559 | 0x3C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 560 | { "gcc_qupv3_wrap0_core_2x_clk", 0x77, 4, GCC, |
| 561 | 0x77, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 562 | { "gcc_qupv3_wrap0_core_clk", 0x76, 4, GCC, |
| 563 | 0x76, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 564 | { "gcc_qupv3_wrap0_s0_clk", 0x78, 4, GCC, |
| 565 | 0x78, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 566 | { "gcc_qupv3_wrap0_s1_clk", 0x79, 4, GCC, |
| 567 | 0x79, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 568 | { "gcc_qupv3_wrap0_s2_clk", 0x7A, 4, GCC, |
| 569 | 0x7A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 570 | { "gcc_qupv3_wrap0_s3_clk", 0x7B, 4, GCC, |
| 571 | 0x7B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 572 | { "gcc_qupv3_wrap0_s4_clk", 0x7C, 4, GCC, |
| 573 | 0x7C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 574 | { "gcc_qupv3_wrap0_s5_clk", 0x7D, 4, GCC, |
| 575 | 0x7D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 576 | { "gcc_qupv3_wrap0_s6_clk", 0x7E, 4, GCC, |
| 577 | 0x7E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 578 | { "gcc_qupv3_wrap0_s7_clk", 0x7F, 4, GCC, |
| 579 | 0x7F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 580 | { "gcc_qupv3_wrap1_core_2x_clk", 0x80, 4, GCC, |
| 581 | 0x80, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 582 | { "gcc_qupv3_wrap1_core_clk", 0x81, 4, GCC, |
| 583 | 0x81, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 584 | { "gcc_qupv3_wrap1_s0_clk", 0x84, 4, GCC, |
| 585 | 0x84, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 586 | { "gcc_qupv3_wrap1_s1_clk", 0x85, 4, GCC, |
| 587 | 0x85, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 588 | { "gcc_qupv3_wrap1_s2_clk", 0x86, 4, GCC, |
| 589 | 0x86, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 590 | { "gcc_qupv3_wrap1_s3_clk", 0x87, 4, GCC, |
| 591 | 0x87, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 592 | { "gcc_qupv3_wrap1_s4_clk", 0x88, 4, GCC, |
| 593 | 0x88, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 594 | { "gcc_qupv3_wrap1_s5_clk", 0x89, 4, GCC, |
| 595 | 0x89, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 596 | { "gcc_qupv3_wrap1_s6_clk", 0x8A, 4, GCC, |
| 597 | 0x8A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 598 | { "gcc_qupv3_wrap1_s7_clk", 0x8B, 4, GCC, |
| 599 | 0x8B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 600 | { "gcc_qupv3_wrap_0_m_ahb_clk", 0x74, 4, GCC, |
| 601 | 0x74, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 602 | { "gcc_qupv3_wrap_0_s_ahb_clk", 0x75, 4, GCC, |
| 603 | 0x75, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 604 | { "gcc_qupv3_wrap_1_m_ahb_clk", 0x82, 4, GCC, |
| 605 | 0x82, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 606 | { "gcc_qupv3_wrap_1_s_ahb_clk", 0x83, 4, GCC, |
| 607 | 0x83, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 608 | { "gcc_sdcc2_ahb_clk", 0x71, 4, GCC, |
| 609 | 0x71, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 610 | { "gcc_sdcc2_apps_clk", 0x70, 4, GCC, |
| 611 | 0x70, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 612 | { "gcc_sdcc4_ahb_clk", 0x73, 4, GCC, |
| 613 | 0x73, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 614 | { "gcc_sdcc4_apps_clk", 0x72, 4, GCC, |
| 615 | 0x72, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 616 | { "gcc_sys_noc_cpuss_ahb_clk", 0xC, 4, GCC, |
| 617 | 0xC, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 618 | { "gcc_tsif_ahb_clk", 0x90, 4, GCC, |
| 619 | 0x90, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 620 | { "gcc_tsif_inactivity_timers_clk", 0x92, 4, GCC, |
| 621 | 0x92, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 622 | { "gcc_tsif_ref_clk", 0x91, 4, GCC, |
| 623 | 0x91, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 624 | { "gcc_ufs_card_ahb_clk", 0xF1, 4, GCC, |
| 625 | 0xF1, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 626 | { "gcc_ufs_card_axi_clk", 0xF0, 4, GCC, |
| 627 | 0xF0, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 628 | { "gcc_ufs_card_ice_core_clk", 0xF7, 4, GCC, |
| 629 | 0xF7, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 630 | { "gcc_ufs_card_phy_aux_clk", 0xF8, 4, GCC, |
| 631 | 0xF8, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 632 | { "gcc_ufs_card_rx_symbol_0_clk", 0xF3, 4, GCC, |
| 633 | 0xF3, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 634 | { "gcc_ufs_card_rx_symbol_1_clk", 0xF9, 4, GCC, |
| 635 | 0xF9, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 636 | { "gcc_ufs_card_tx_symbol_0_clk", 0xF2, 4, GCC, |
| 637 | 0xF2, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 638 | { "gcc_ufs_card_unipro_core_clk", 0xF6, 4, GCC, |
| 639 | 0xF6, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 640 | { "gcc_ufs_phy_ahb_clk", 0xFC, 4, GCC, |
| 641 | 0xFC, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 642 | { "gcc_ufs_phy_axi_clk", 0xFB, 4, GCC, |
| 643 | 0xFB, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 644 | { "gcc_ufs_phy_ice_core_clk", 0x102, 4, GCC, |
| 645 | 0x102, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 646 | { "gcc_ufs_phy_phy_aux_clk", 0x103, 4, GCC, |
| 647 | 0x103, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 648 | { "gcc_ufs_phy_rx_symbol_0_clk", 0xFE, 4, GCC, |
| 649 | 0xFE, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 650 | { "gcc_ufs_phy_rx_symbol_1_clk", 0x104, 4, GCC, |
| 651 | 0x104, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 652 | { "gcc_ufs_phy_tx_symbol_0_clk", 0xFD, 4, GCC, |
| 653 | 0xFD, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 654 | { "gcc_ufs_phy_unipro_core_clk", 0x101, 4, GCC, |
| 655 | 0x101, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 656 | { "gcc_usb30_prim_master_clk", 0x5F, 4, GCC, |
| 657 | 0x5F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 658 | { "gcc_usb30_prim_mock_utmi_clk", 0x61, 4, GCC, |
| 659 | 0x61, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 660 | { "gcc_usb30_prim_sleep_clk", 0x60, 4, GCC, |
| 661 | 0x60, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 662 | { "gcc_usb30_sec_master_clk", 0x65, 4, GCC, |
| 663 | 0x65, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 664 | { "gcc_usb30_sec_mock_utmi_clk", 0x67, 4, GCC, |
| 665 | 0x67, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 666 | { "gcc_usb30_sec_sleep_clk", 0x66, 4, GCC, |
| 667 | 0x66, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 668 | { "gcc_usb3_prim_phy_aux_clk", 0x62, 4, GCC, |
| 669 | 0x62, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 670 | { "gcc_usb3_prim_phy_com_aux_clk", 0x63, 4, GCC, |
| 671 | 0x63, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 672 | { "gcc_usb3_prim_phy_pipe_clk", 0x64, 4, GCC, |
| 673 | 0x64, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 674 | { "gcc_usb3_sec_phy_aux_clk", 0x68, 4, GCC, |
| 675 | 0x68, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 676 | { "gcc_usb3_sec_phy_com_aux_clk", 0x69, 4, GCC, |
| 677 | 0x69, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 678 | { "gcc_usb3_sec_phy_pipe_clk", 0x6A, 4, GCC, |
| 679 | 0x6A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 680 | { "gcc_usb_phy_cfg_ahb2phy_clk", 0x6F, 4, GCC, |
| 681 | 0x6F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 682 | { "gcc_video_ahb_clk", 0x39, 4, GCC, |
| 683 | 0x39, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 684 | { "gcc_video_axi_clk", 0x3F, 4, GCC, |
| 685 | 0x3F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 686 | { "gcc_video_xo_clk", 0x42, 4, GCC, |
| 687 | 0x42, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, |
| 688 | { "gpu_cc_acd_cxo_clk", 0x144, 4, GPU_CC, |
| 689 | 0x1F, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 690 | { "gpu_cc_ahb_clk", 0x144, 4, GPU_CC, |
| 691 | 0x11, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 692 | { "gpu_cc_crc_ahb_clk", 0x144, 4, GPU_CC, |
| 693 | 0x12, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 694 | { "gpu_cc_cx_apb_clk", 0x144, 4, GPU_CC, |
| 695 | 0x15, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 696 | { "gpu_cc_cx_gfx3d_clk", 0x144, 4, GPU_CC, |
| 697 | 0x1A, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 698 | { "gpu_cc_cx_gfx3d_slv_clk", 0x144, 4, GPU_CC, |
| 699 | 0x1B, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 700 | { "gpu_cc_cx_gmu_clk", 0x144, 4, GPU_CC, |
| 701 | 0x19, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 702 | { "gpu_cc_cx_qdss_at_clk", 0x144, 4, GPU_CC, |
| 703 | 0x13, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 704 | { "gpu_cc_cx_qdss_trig_clk", 0x144, 4, GPU_CC, |
| 705 | 0x18, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 706 | { "gpu_cc_cx_qdss_tsctr_clk", 0x144, 4, GPU_CC, |
| 707 | 0x14, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 708 | { "gpu_cc_cx_snoc_dvm_clk", 0x144, 4, GPU_CC, |
| 709 | 0x16, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 710 | { "gpu_cc_cxo_aon_clk", 0x144, 4, GPU_CC, |
| 711 | 0xB, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 712 | { "gpu_cc_cxo_clk", 0x144, 4, GPU_CC, |
| 713 | 0xA, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
Deepak Katragadda | 15d34db | 2017-06-01 11:19:23 -0700 | [diff] [blame] | 714 | { "gpu_cc_gx_gfx3d_clk", 0x144, 4, GPU_CC, |
| 715 | 0xC, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 716 | { "gpu_cc_gx_gmu_clk", 0x144, 4, GPU_CC, |
| 717 | 0x10, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 718 | { "gpu_cc_gx_qdss_tsctr_clk", 0x144, 4, GPU_CC, |
| 719 | 0xE, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 720 | { "gpu_cc_gx_vsense_clk", 0x144, 4, GPU_CC, |
| 721 | 0xD, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 722 | { "gpu_cc_rbcpr_ahb_clk", 0x144, 4, GPU_CC, |
| 723 | 0x1D, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 724 | { "gpu_cc_rbcpr_clk", 0x144, 4, GPU_CC, |
| 725 | 0x1C, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
| 726 | { "gpu_cc_sleep_clk", 0x144, 4, GPU_CC, |
| 727 | 0x17, 0xFF, 0, 0x3, 0, 1, 0x1568, 0x10FC, 0x1100 }, |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 728 | { "video_cc_apb_clk", 0x48, 4, VIDEO_CC, |
| 729 | 0x8, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 }, |
| 730 | { "video_cc_at_clk", 0x48, 4, VIDEO_CC, |
| 731 | 0xB, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 }, |
| 732 | { "video_cc_qdss_trig_clk", 0x48, 4, VIDEO_CC, |
| 733 | 0x7, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 }, |
| 734 | { "video_cc_qdss_tsctr_div8_clk", 0x48, 4, VIDEO_CC, |
| 735 | 0xA, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 }, |
| 736 | { "video_cc_vcodec0_axi_clk", 0x48, 4, VIDEO_CC, |
| 737 | 0x5, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 }, |
| 738 | { "video_cc_vcodec0_core_clk", 0x48, 4, VIDEO_CC, |
| 739 | 0x2, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 }, |
| 740 | { "video_cc_vcodec1_axi_clk", 0x48, 4, VIDEO_CC, |
| 741 | 0x6, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 }, |
| 742 | { "video_cc_vcodec1_core_clk", 0x48, 4, VIDEO_CC, |
| 743 | 0x3, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 }, |
| 744 | { "video_cc_venus_ahb_clk", 0x48, 4, VIDEO_CC, |
| 745 | 0x9, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 }, |
| 746 | { "video_cc_venus_ctl_axi_clk", 0x48, 4, VIDEO_CC, |
| 747 | 0x4, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 }, |
| 748 | { "video_cc_venus_ctl_core_clk", 0x48, 4, VIDEO_CC, |
| 749 | 0x1, 0x3F, 0, 0x7, 0, 1, 0xA4C, 0xA50, 0xA58 }, |
Deepak Katragadda | bca4a87 | 2017-04-24 15:51:03 -0700 | [diff] [blame] | 750 | { "l3_clk", 0xD6, 4, CPU, |
| 751 | 0x46, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 }, |
| 752 | { "pwrcl_clk", 0xD6, 4, CPU, |
| 753 | 0x44, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 }, |
| 754 | { "perfcl_clk", 0xD6, 4, CPU, |
| 755 | 0x45, 0x7F, 4, 0xf, 11, 1, 0x0, 0x0, U32_MAX, 16 }, |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 756 | ), |
| 757 | .hw.init = &(struct clk_init_data){ |
| 758 | .name = "gcc_debug_mux", |
| 759 | .ops = &clk_debug_mux_ops, |
| 760 | .parent_names = debug_mux_parent_names, |
| 761 | .num_parents = ARRAY_SIZE(debug_mux_parent_names), |
| 762 | .flags = CLK_IS_MEASURE, |
| 763 | }, |
| 764 | }; |
| 765 | |
| 766 | static const struct of_device_id clk_debug_match_table[] = { |
| 767 | { .compatible = "qcom,debugcc-sdm845" }, |
| 768 | {} |
| 769 | }; |
| 770 | |
| 771 | static int clk_debug_845_probe(struct platform_device *pdev) |
| 772 | { |
| 773 | struct clk *clk; |
| 774 | int ret = 0, count; |
| 775 | |
| 776 | clk = devm_clk_get(&pdev->dev, "xo_clk_src"); |
| 777 | if (IS_ERR(clk)) { |
| 778 | if (PTR_ERR(clk) != -EPROBE_DEFER) |
| 779 | dev_err(&pdev->dev, "Unable to get xo clock\n"); |
| 780 | return PTR_ERR(clk); |
| 781 | } |
| 782 | |
| 783 | debug_mux_priv.cxo = clk; |
| 784 | |
| 785 | ret = of_property_read_u32(pdev->dev.of_node, "qcom,cc-count", |
| 786 | &count); |
| 787 | if (ret < 0) { |
| 788 | dev_err(&pdev->dev, "Num of debug clock controller not specified\n"); |
| 789 | return ret; |
| 790 | } |
| 791 | |
| 792 | if (!count) { |
| 793 | dev_err(&pdev->dev, "Count of CC cannot be zero\n"); |
| 794 | return -EINVAL; |
| 795 | } |
| 796 | |
| 797 | gcc_debug_mux.regmap = devm_kzalloc(&pdev->dev, |
| 798 | sizeof(struct regmap *) * count, GFP_KERNEL); |
| 799 | if (!gcc_debug_mux.regmap) |
| 800 | return -ENOMEM; |
| 801 | |
| 802 | if (of_get_property(pdev->dev.of_node, "qcom,gcc", NULL)) { |
| 803 | gcc_debug_mux.regmap[GCC] = |
| 804 | syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 805 | "qcom,gcc"); |
| 806 | if (IS_ERR(gcc_debug_mux.regmap[GCC])) { |
| 807 | pr_err("Failed to map qcom,gcc\n"); |
| 808 | return PTR_ERR(gcc_debug_mux.regmap[GCC]); |
| 809 | } |
| 810 | } |
| 811 | |
| 812 | if (of_get_property(pdev->dev.of_node, "qcom,dispcc", NULL)) { |
| 813 | gcc_debug_mux.regmap[DISP_CC] = |
| 814 | syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 815 | "qcom,dispcc"); |
| 816 | if (IS_ERR(gcc_debug_mux.regmap[DISP_CC])) { |
| 817 | pr_err("Failed to map qcom,dispcc\n"); |
| 818 | return PTR_ERR(gcc_debug_mux.regmap[DISP_CC]); |
| 819 | } |
| 820 | } |
| 821 | |
| 822 | if (of_get_property(pdev->dev.of_node, "qcom,videocc", NULL)) { |
| 823 | gcc_debug_mux.regmap[VIDEO_CC] = |
| 824 | syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 825 | "qcom,videocc"); |
| 826 | if (IS_ERR(gcc_debug_mux.regmap[VIDEO_CC])) { |
| 827 | pr_err("Failed to map qcom,videocc\n"); |
| 828 | return PTR_ERR(gcc_debug_mux.regmap[VIDEO_CC]); |
| 829 | } |
| 830 | } |
| 831 | |
| 832 | if (of_get_property(pdev->dev.of_node, "qcom,camcc", NULL)) { |
| 833 | gcc_debug_mux.regmap[CAM_CC] = |
| 834 | syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 835 | "qcom,camcc"); |
| 836 | if (IS_ERR(gcc_debug_mux.regmap[CAM_CC])) { |
| 837 | pr_err("Failed to map qcom,camcc\n"); |
| 838 | return PTR_ERR(gcc_debug_mux.regmap[CAM_CC]); |
| 839 | } |
| 840 | } |
| 841 | |
| 842 | if (of_get_property(pdev->dev.of_node, "qcom,gpucc", NULL)) { |
| 843 | gcc_debug_mux.regmap[GPU_CC] = |
| 844 | syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 845 | "qcom,gpucc"); |
| 846 | if (IS_ERR(gcc_debug_mux.regmap[GPU_CC])) { |
| 847 | pr_err("Failed to map qcom,gpucc\n"); |
| 848 | return PTR_ERR(gcc_debug_mux.regmap[GPU_CC]); |
| 849 | } |
| 850 | } |
| 851 | |
Deepak Katragadda | bca4a87 | 2017-04-24 15:51:03 -0700 | [diff] [blame] | 852 | if (of_get_property(pdev->dev.of_node, "qcom,cpucc", NULL)) { |
| 853 | gcc_debug_mux.regmap[CPU] = |
| 854 | syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 855 | "qcom,cpucc"); |
| 856 | if (IS_ERR(gcc_debug_mux.regmap[CPU])) { |
| 857 | pr_err("Failed to map qcom,cpucc\n"); |
| 858 | return PTR_ERR(gcc_debug_mux.regmap[CPU]); |
| 859 | } |
| 860 | } |
| 861 | |
Deepak Katragadda | c617c38 | 2017-02-28 11:06:06 -0800 | [diff] [blame] | 862 | clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw); |
| 863 | if (IS_ERR(clk)) { |
| 864 | dev_err(&pdev->dev, "Unable to register GCC debug mux\n"); |
| 865 | return PTR_ERR(clk); |
| 866 | } |
| 867 | |
| 868 | ret = clk_debug_measure_register(&gcc_debug_mux.hw); |
| 869 | if (ret) |
| 870 | dev_err(&pdev->dev, "Could not register Measure clock\n"); |
| 871 | else |
| 872 | dev_info(&pdev->dev, "Registered debug mux successfully\n"); |
| 873 | |
| 874 | return ret; |
| 875 | } |
| 876 | |
| 877 | static struct platform_driver clk_debug_driver = { |
| 878 | .probe = clk_debug_845_probe, |
| 879 | .driver = { |
| 880 | .name = "debugcc-sdm845", |
| 881 | .of_match_table = clk_debug_match_table, |
| 882 | .owner = THIS_MODULE, |
| 883 | }, |
| 884 | }; |
| 885 | |
| 886 | int __init clk_debug_845_init(void) |
| 887 | { |
| 888 | return platform_driver_register(&clk_debug_driver); |
| 889 | } |
| 890 | fs_initcall(clk_debug_845_init); |
| 891 | |
| 892 | MODULE_DESCRIPTION("QTI DEBUG CC SDM845 Driver"); |
| 893 | MODULE_LICENSE("GPL v2"); |
| 894 | MODULE_ALIAS("platform:debugcc-sdm845"); |