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Juergen Beisert07bd1a62008-07-05 10:02:49 +02001/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
Dinh Nguyene24798e2010-04-22 16:28:42 +03006 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
Juergen Beisert07bd1a62008-07-05 10:02:49 +02007 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
Fabio Estevam18f92b12013-07-22 18:17:52 -030022#include <linux/err.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020023#include <linux/init.h>
Dinh Nguyena3484ff2010-10-23 09:12:48 -050024#include <linux/interrupt.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020025#include <linux/io.h>
26#include <linux/irq.h>
Shawn Guo1ab7ef12012-06-13 09:04:03 +080027#include <linux/irqdomain.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000028#include <linux/irqchip/chained_irq.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020029#include <linux/gpio.h>
Shawn Guob78d8e52011-06-06 00:07:55 +080030#include <linux/platform_device.h>
31#include <linux/slab.h>
Shawn Guo2ce420d2011-06-06 13:22:41 +080032#include <linux/basic_mmio_gpio.h>
Shawn Guo8937cb62011-07-07 00:37:43 +080033#include <linux/of.h>
34#include <linux/of_device.h>
Paul Gortmakerbb207ef2011-07-03 13:38:09 -040035#include <linux/module.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020036#include <asm-generic/bug.h>
37
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080038enum mxc_gpio_hwtype {
39 IMX1_GPIO, /* runs on i.mx1 */
40 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020041 IMX31_GPIO, /* runs on i.mx31 */
42 IMX35_GPIO, /* runs on all other i.mx */
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080043};
44
45/* device type dependent stuff */
46struct mxc_gpio_hwdata {
47 unsigned dr_reg;
48 unsigned gdir_reg;
49 unsigned psr_reg;
50 unsigned icr1_reg;
51 unsigned icr2_reg;
52 unsigned imr_reg;
53 unsigned isr_reg;
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020054 int edge_sel_reg;
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080055 unsigned low_level;
56 unsigned high_level;
57 unsigned rise_edge;
58 unsigned fall_edge;
59};
60
Shawn Guob78d8e52011-06-06 00:07:55 +080061struct mxc_gpio_port {
62 struct list_head node;
63 void __iomem *base;
64 int irq;
65 int irq_high;
Shawn Guo1ab7ef12012-06-13 09:04:03 +080066 struct irq_domain *domain;
Shawn Guo2ce420d2011-06-06 13:22:41 +080067 struct bgpio_chip bgc;
Shawn Guob78d8e52011-06-06 00:07:55 +080068 u32 both_edges;
Shawn Guob78d8e52011-06-06 00:07:55 +080069};
70
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080071static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
72 .dr_reg = 0x1c,
73 .gdir_reg = 0x00,
74 .psr_reg = 0x24,
75 .icr1_reg = 0x28,
76 .icr2_reg = 0x2c,
77 .imr_reg = 0x30,
78 .isr_reg = 0x34,
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020079 .edge_sel_reg = -EINVAL,
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080080 .low_level = 0x03,
81 .high_level = 0x02,
82 .rise_edge = 0x00,
83 .fall_edge = 0x01,
84};
85
86static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
87 .dr_reg = 0x00,
88 .gdir_reg = 0x04,
89 .psr_reg = 0x08,
90 .icr1_reg = 0x0c,
91 .icr2_reg = 0x10,
92 .imr_reg = 0x14,
93 .isr_reg = 0x18,
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020094 .edge_sel_reg = -EINVAL,
95 .low_level = 0x00,
96 .high_level = 0x01,
97 .rise_edge = 0x02,
98 .fall_edge = 0x03,
99};
100
101static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
102 .dr_reg = 0x00,
103 .gdir_reg = 0x04,
104 .psr_reg = 0x08,
105 .icr1_reg = 0x0c,
106 .icr2_reg = 0x10,
107 .imr_reg = 0x14,
108 .isr_reg = 0x18,
109 .edge_sel_reg = 0x1c,
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800110 .low_level = 0x00,
111 .high_level = 0x01,
112 .rise_edge = 0x02,
113 .fall_edge = 0x03,
114};
115
116static enum mxc_gpio_hwtype mxc_gpio_hwtype;
117static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
118
119#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
120#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
121#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
122#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
123#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
124#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
125#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200126#define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800127
128#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
129#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
130#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
131#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200132#define GPIO_INT_BOTH_EDGES 0x4
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800133
134static struct platform_device_id mxc_gpio_devtype[] = {
135 {
136 .name = "imx1-gpio",
137 .driver_data = IMX1_GPIO,
138 }, {
139 .name = "imx21-gpio",
140 .driver_data = IMX21_GPIO,
141 }, {
142 .name = "imx31-gpio",
143 .driver_data = IMX31_GPIO,
144 }, {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200145 .name = "imx35-gpio",
146 .driver_data = IMX35_GPIO,
147 }, {
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800148 /* sentinel */
149 }
150};
151
Shawn Guo8937cb62011-07-07 00:37:43 +0800152static const struct of_device_id mxc_gpio_dt_ids[] = {
153 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
154 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
155 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200156 { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
Shawn Guo8937cb62011-07-07 00:37:43 +0800157 { /* sentinel */ }
158};
159
Shawn Guob78d8e52011-06-06 00:07:55 +0800160/*
161 * MX2 has one interrupt *for all* gpio ports. The list is used
162 * to save the references to all ports, so that mx2_gpio_irq_handler
163 * can walk through all interrupt status registers.
164 */
165static LIST_HEAD(mxc_gpio_ports);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200166
167/* Note: This driver assumes 32 GPIOs are handled in one register */
168
Lennert Buytenhek4d935792010-11-29 11:16:23 +0100169static int gpio_set_irq_type(struct irq_data *d, u32 type)
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200170{
Shawn Guoe4ea9332011-06-07 16:25:37 +0800171 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
172 struct mxc_gpio_port *port = gc->private;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200173 u32 bit, val;
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800174 u32 gpio_idx = d->hwirq;
175 u32 gpio = port->bgc.gc.base + gpio_idx;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200176 int edge;
177 void __iomem *reg = port->base;
178
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800179 port->both_edges &= ~(1 << gpio_idx);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200180 switch (type) {
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100181 case IRQ_TYPE_EDGE_RISING:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200182 edge = GPIO_INT_RISE_EDGE;
183 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100184 case IRQ_TYPE_EDGE_FALLING:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200185 edge = GPIO_INT_FALL_EDGE;
186 break;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100187 case IRQ_TYPE_EDGE_BOTH:
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200188 if (GPIO_EDGE_SEL >= 0) {
189 edge = GPIO_INT_BOTH_EDGES;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100190 } else {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200191 val = gpio_get_value(gpio);
192 if (val) {
193 edge = GPIO_INT_LOW_LEV;
194 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
195 } else {
196 edge = GPIO_INT_HIGH_LEV;
197 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
198 }
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700199 port->both_edges |= 1 << gpio_idx;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100200 }
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100201 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100202 case IRQ_TYPE_LEVEL_LOW:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200203 edge = GPIO_INT_LOW_LEV;
204 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100205 case IRQ_TYPE_LEVEL_HIGH:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200206 edge = GPIO_INT_HIGH_LEV;
207 break;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100208 default:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200209 return -EINVAL;
210 }
211
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200212 if (GPIO_EDGE_SEL >= 0) {
213 val = readl(port->base + GPIO_EDGE_SEL);
214 if (edge == GPIO_INT_BOTH_EDGES)
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700215 writel(val | (1 << gpio_idx),
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200216 port->base + GPIO_EDGE_SEL);
217 else
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700218 writel(val & ~(1 << gpio_idx),
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200219 port->base + GPIO_EDGE_SEL);
220 }
221
222 if (edge != GPIO_INT_BOTH_EDGES) {
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700223 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
224 bit = gpio_idx & 0xf;
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200225 val = readl(reg) & ~(0x3 << (bit << 1));
226 writel(val | (edge << (bit << 1)), reg);
227 }
228
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800229 writel(1 << gpio_idx, port->base + GPIO_ISR);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200230
231 return 0;
232}
233
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100234static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
235{
236 void __iomem *reg = port->base;
237 u32 bit, val;
238 int edge;
239
240 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
241 bit = gpio & 0xf;
Shawn Guob78d8e52011-06-06 00:07:55 +0800242 val = readl(reg);
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100243 edge = (val >> (bit << 1)) & 3;
244 val &= ~(0x3 << (bit << 1));
Uwe Kleine-König3d40f7f2010-02-05 22:14:37 +0100245 if (edge == GPIO_INT_HIGH_LEV) {
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100246 edge = GPIO_INT_LOW_LEV;
247 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
Uwe Kleine-König3d40f7f2010-02-05 22:14:37 +0100248 } else if (edge == GPIO_INT_LOW_LEV) {
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100249 edge = GPIO_INT_HIGH_LEV;
250 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
Uwe Kleine-König3d40f7f2010-02-05 22:14:37 +0100251 } else {
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100252 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
253 gpio, edge);
254 return;
255 }
Shawn Guob78d8e52011-06-06 00:07:55 +0800256 writel(val | (edge << (bit << 1)), reg);
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100257}
258
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100259/* handle 32 interrupts in one status register */
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200260static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
261{
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100262 while (irq_stat != 0) {
263 int irqoffset = fls(irq_stat) - 1;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200264
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100265 if (port->both_edges & (1 << irqoffset))
266 mxc_flip_edge(port, irqoffset);
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100267
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800268 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100269
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100270 irq_stat &= ~(1 << irqoffset);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200271 }
272}
273
Paulius Zaleckascfca8b52008-11-14 11:01:38 +0100274/* MX1 and MX3 has one interrupt *per* gpio port */
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200275static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
276{
277 u32 irq_stat;
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100278 struct mxc_gpio_port *port = irq_get_handler_data(irq);
Shawn Guo0e44b6e2011-09-21 21:24:04 +0800279 struct irq_chip *chip = irq_get_chip(irq);
280
281 chained_irq_enter(chip, desc);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200282
Shawn Guob78d8e52011-06-06 00:07:55 +0800283 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
Sascha Hauere2c97e72009-04-21 12:39:59 +0200284
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200285 mxc_gpio_irq_handler(port, irq_stat);
Shawn Guo0e44b6e2011-09-21 21:24:04 +0800286
287 chained_irq_exit(chip, desc);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200288}
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200289
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200290/* MX2 has one interrupt *for all* gpio ports */
291static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
292{
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200293 u32 irq_msk, irq_stat;
Shawn Guob78d8e52011-06-06 00:07:55 +0800294 struct mxc_gpio_port *port;
Uwe Kleine-Königc0e811d2013-07-18 14:58:06 +0200295 struct irq_chip *chip = irq_get_chip(irq);
296
297 chained_irq_enter(chip, desc);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200298
299 /* walk through all interrupt status registers */
Shawn Guob78d8e52011-06-06 00:07:55 +0800300 list_for_each_entry(port, &mxc_gpio_ports, node) {
301 irq_msk = readl(port->base + GPIO_IMR);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200302 if (!irq_msk)
303 continue;
304
Shawn Guob78d8e52011-06-06 00:07:55 +0800305 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200306 if (irq_stat)
Shawn Guob78d8e52011-06-06 00:07:55 +0800307 mxc_gpio_irq_handler(port, irq_stat);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200308 }
Uwe Kleine-Königc0e811d2013-07-18 14:58:06 +0200309 chained_irq_exit(chip, desc);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200310}
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200311
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500312/*
313 * Set interrupt number "irq" in the GPIO as a wake-up source.
314 * While system is running, all registered GPIO interrupts need to have
315 * wake-up enabled. When system is suspended, only selected GPIO interrupts
316 * need to have wake-up enabled.
317 * @param irq interrupt source number
318 * @param enable enable as wake-up if equal to non-zero
319 * @return This function returns 0 on success.
320 */
Lennert Buytenhek4d935792010-11-29 11:16:23 +0100321static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500322{
Shawn Guoe4ea9332011-06-07 16:25:37 +0800323 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
324 struct mxc_gpio_port *port = gc->private;
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800325 u32 gpio_idx = d->hwirq;
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500326
327 if (enable) {
328 if (port->irq_high && (gpio_idx >= 16))
329 enable_irq_wake(port->irq_high);
330 else
331 enable_irq_wake(port->irq);
332 } else {
333 if (port->irq_high && (gpio_idx >= 16))
334 disable_irq_wake(port->irq_high);
335 else
336 disable_irq_wake(port->irq);
337 }
338
339 return 0;
340}
341
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800342static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
Shawn Guoe4ea9332011-06-07 16:25:37 +0800343{
344 struct irq_chip_generic *gc;
345 struct irq_chip_type *ct;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200346
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800347 gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
Shawn Guoe4ea9332011-06-07 16:25:37 +0800348 port->base, handle_level_irq);
349 gc->private = port;
350
351 ct = gc->chip_types;
Shawn Guo591567a2011-07-19 21:16:56 +0800352 ct->chip.irq_ack = irq_gc_ack_set_bit;
Shawn Guoe4ea9332011-06-07 16:25:37 +0800353 ct->chip.irq_mask = irq_gc_mask_clr_bit;
354 ct->chip.irq_unmask = irq_gc_mask_set_bit;
355 ct->chip.irq_set_type = gpio_set_irq_type;
Shawn Guo591567a2011-07-19 21:16:56 +0800356 ct->chip.irq_set_wake = gpio_set_wake_irq;
Shawn Guoe4ea9332011-06-07 16:25:37 +0800357 ct->regs.ack = GPIO_ISR;
358 ct->regs.mask = GPIO_IMR;
359
360 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
361 IRQ_NOREQUEST, 0);
362}
Thomas Gleixnerb5eee2f2011-04-04 14:29:58 +0200363
Bill Pemberton38363092012-11-19 13:22:34 -0500364static void mxc_gpio_get_hw(struct platform_device *pdev)
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800365{
Shawn Guo8937cb62011-07-07 00:37:43 +0800366 const struct of_device_id *of_id =
367 of_match_device(mxc_gpio_dt_ids, &pdev->dev);
368 enum mxc_gpio_hwtype hwtype;
369
370 if (of_id)
371 pdev->id_entry = of_id->data;
372 hwtype = pdev->id_entry->driver_data;
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800373
374 if (mxc_gpio_hwtype) {
375 /*
376 * The driver works with a reasonable presupposition,
377 * that is all gpio ports must be the same type when
378 * running on one soc.
379 */
380 BUG_ON(mxc_gpio_hwtype != hwtype);
381 return;
382 }
383
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200384 if (hwtype == IMX35_GPIO)
385 mxc_gpio_hwdata = &imx35_gpio_hwdata;
386 else if (hwtype == IMX31_GPIO)
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800387 mxc_gpio_hwdata = &imx31_gpio_hwdata;
388 else
389 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
390
391 mxc_gpio_hwtype = hwtype;
392}
393
Shawn Guo09ad8032011-08-14 00:14:02 +0800394static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
395{
396 struct bgpio_chip *bgc = to_bgpio_chip(gc);
397 struct mxc_gpio_port *port =
398 container_of(bgc, struct mxc_gpio_port, bgc);
399
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800400 return irq_find_mapping(port->domain, offset);
Shawn Guo09ad8032011-08-14 00:14:02 +0800401}
402
Bill Pemberton38363092012-11-19 13:22:34 -0500403static int mxc_gpio_probe(struct platform_device *pdev)
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200404{
Shawn Guo8937cb62011-07-07 00:37:43 +0800405 struct device_node *np = pdev->dev.of_node;
Shawn Guob78d8e52011-06-06 00:07:55 +0800406 struct mxc_gpio_port *port;
407 struct resource *iores;
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800408 int irq_base;
Shawn Guoe4ea9332011-06-07 16:25:37 +0800409 int err;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200410
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800411 mxc_gpio_get_hw(pdev);
412
Fabio Estevam8cd73e42013-07-08 17:14:39 -0300413 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
Shawn Guob78d8e52011-06-06 00:07:55 +0800414 if (!port)
415 return -ENOMEM;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200416
Shawn Guob78d8e52011-06-06 00:07:55 +0800417 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Fabio Estevam8cd73e42013-07-08 17:14:39 -0300418 port->base = devm_ioremap_resource(&pdev->dev, iores);
419 if (IS_ERR(port->base))
420 return PTR_ERR(port->base);
Baruch Siach14cb0de2010-07-06 14:03:22 +0300421
Shawn Guob78d8e52011-06-06 00:07:55 +0800422 port->irq_high = platform_get_irq(pdev, 1);
423 port->irq = platform_get_irq(pdev, 0);
Fabio Estevam8cd73e42013-07-08 17:14:39 -0300424 if (port->irq < 0)
Sachin Kamat5ea80e42013-12-21 13:05:57 +0530425 return port->irq;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200426
Shawn Guob78d8e52011-06-06 00:07:55 +0800427 /* disable the interrupt and clear the status */
428 writel(0, port->base + GPIO_IMR);
429 writel(~0, port->base + GPIO_ISR);
430
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800431 if (mxc_gpio_hwtype == IMX21_GPIO) {
Uwe Kleine-König33a4e982012-06-06 11:49:23 +0200432 /*
433 * Setup one handler for all GPIO interrupts. Actually setting
434 * the handler is needed only once, but doing it for every port
435 * is more robust and easier.
436 */
437 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
Shawn Guob78d8e52011-06-06 00:07:55 +0800438 } else {
439 /* setup one handler for each entry */
440 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
441 irq_set_handler_data(port->irq, port);
442 if (port->irq_high > 0) {
443 /* setup handler for GPIO 16 to 31 */
444 irq_set_chained_handler(port->irq_high,
445 mx3_gpio_irq_handler);
446 irq_set_handler_data(port->irq_high, port);
447 }
Sascha Hauer8afaada2009-06-15 12:36:25 +0200448 }
449
Shawn Guo2ce420d2011-06-06 13:22:41 +0800450 err = bgpio_init(&port->bgc, &pdev->dev, 4,
451 port->base + GPIO_PSR,
452 port->base + GPIO_DR, NULL,
Shawn Guo3e11f7b2012-05-19 21:34:58 +0800453 port->base + GPIO_GDIR, NULL, 0);
Shawn Guob78d8e52011-06-06 00:07:55 +0800454 if (err)
Fabio Estevam8cd73e42013-07-08 17:14:39 -0300455 goto out_bgio;
Shawn Guob78d8e52011-06-06 00:07:55 +0800456
Shawn Guo09ad8032011-08-14 00:14:02 +0800457 port->bgc.gc.to_irq = mxc_gpio_to_irq;
Shawn Guo7e6086d2012-08-05 14:01:26 +0800458 port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
459 pdev->id * 32;
Shawn Guo2ce420d2011-06-06 13:22:41 +0800460
461 err = gpiochip_add(&port->bgc.gc);
462 if (err)
463 goto out_bgpio_remove;
464
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800465 irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
466 if (irq_base < 0) {
467 err = irq_base;
468 goto out_gpiochip_remove;
469 }
470
471 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
472 &irq_domain_simple_ops, NULL);
473 if (!port->domain) {
474 err = -ENODEV;
475 goto out_irqdesc_free;
476 }
Shawn Guo8937cb62011-07-07 00:37:43 +0800477
478 /* gpio-mxc can be a generic irq chip */
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800479 mxc_gpio_init_gc(port, irq_base);
Shawn Guo8937cb62011-07-07 00:37:43 +0800480
Shawn Guob78d8e52011-06-06 00:07:55 +0800481 list_add_tail(&port->node, &mxc_gpio_ports);
482
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200483 return 0;
Shawn Guob78d8e52011-06-06 00:07:55 +0800484
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800485out_irqdesc_free:
486 irq_free_descs(irq_base, 32);
487out_gpiochip_remove:
abdoulaye berthe9f5132a2014-07-12 22:30:12 +0200488 gpiochip_remove(&port->bgc.gc);
Shawn Guo2ce420d2011-06-06 13:22:41 +0800489out_bgpio_remove:
490 bgpio_remove(&port->bgc);
Fabio Estevam8cd73e42013-07-08 17:14:39 -0300491out_bgio:
Shawn Guob78d8e52011-06-06 00:07:55 +0800492 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
493 return err;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200494}
Shawn Guob78d8e52011-06-06 00:07:55 +0800495
496static struct platform_driver mxc_gpio_driver = {
497 .driver = {
498 .name = "gpio-mxc",
Shawn Guo8937cb62011-07-07 00:37:43 +0800499 .of_match_table = mxc_gpio_dt_ids,
Shawn Guob78d8e52011-06-06 00:07:55 +0800500 },
501 .probe = mxc_gpio_probe,
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800502 .id_table = mxc_gpio_devtype,
Shawn Guob78d8e52011-06-06 00:07:55 +0800503};
504
505static int __init gpio_mxc_init(void)
506{
507 return platform_driver_register(&mxc_gpio_driver);
508}
509postcore_initcall(gpio_mxc_init);
510
511MODULE_AUTHOR("Freescale Semiconductor, "
512 "Daniel Mack <danielncaiaq.de>, "
513 "Juergen Beisert <kernel@pengutronix.de>");
514MODULE_DESCRIPTION("Freescale MXC GPIO");
515MODULE_LICENSE("GPL");