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Baruch Siach1e9c2852009-06-18 16:48:58 -07001/*
Grant Likelyc103de22011-06-04 18:38:28 -06002 * Copyright (C) 2008, 2009 Provigent Ltd.
Baruch Siach1e9c2852009-06-18 16:48:58 -07003 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
9 *
10 * Data sheet: ARM DDI 0190B, September 2000
11 */
12#include <linux/spinlock.h>
13#include <linux/errno.h>
14#include <linux/module.h>
Baruch Siach1e9c2852009-06-18 16:48:58 -070015#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000018#include <linux/irqchip/chained_irq.h>
Baruch Siach1e9c2852009-06-18 16:48:58 -070019#include <linux/bitops.h>
Baruch Siach1e9c2852009-06-18 16:48:58 -070020#include <linux/gpio.h>
21#include <linux/device.h>
22#include <linux/amba/bus.h>
23#include <linux/amba/pl061.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090024#include <linux/slab.h>
Haojian Zhuang39b70ee2013-02-17 19:42:51 +080025#include <linux/pinctrl/consumer.h>
Deepak Sikrie198a8de2011-11-18 15:20:12 +053026#include <linux/pm.h>
Baruch Siach1e9c2852009-06-18 16:48:58 -070027
28#define GPIODIR 0x400
29#define GPIOIS 0x404
30#define GPIOIBE 0x408
31#define GPIOIEV 0x40C
32#define GPIOIE 0x410
33#define GPIORIS 0x414
34#define GPIOMIS 0x418
35#define GPIOIC 0x41C
36
37#define PL061_GPIO_NR 8
38
Deepak Sikrie198a8de2011-11-18 15:20:12 +053039#ifdef CONFIG_PM
40struct pl061_context_save_regs {
41 u8 gpio_data;
42 u8 gpio_dir;
43 u8 gpio_is;
44 u8 gpio_ibe;
45 u8 gpio_iev;
46 u8 gpio_ie;
47};
48#endif
Baruch Siach1e9c2852009-06-18 16:48:58 -070049
Baruch Siach1e9c2852009-06-18 16:48:58 -070050struct pl061_gpio {
Baruch Siach835c1922012-11-22 11:46:14 +020051 spinlock_t lock;
Baruch Siach1e9c2852009-06-18 16:48:58 -070052
53 void __iomem *base;
Baruch Siach1e9c2852009-06-18 16:48:58 -070054 struct gpio_chip gc;
Yunlei He27f9fec2014-12-02 12:32:59 +080055 bool uses_pinctrl;
Deepak Sikrie198a8de2011-11-18 15:20:12 +053056
57#ifdef CONFIG_PM
58 struct pl061_context_save_regs csave_regs;
59#endif
Baruch Siach1e9c2852009-06-18 16:48:58 -070060};
61
Yunlei He27f9fec2014-12-02 12:32:59 +080062static int pl061_gpio_request(struct gpio_chip *gc, unsigned offset)
Haojian Zhuang39b70ee2013-02-17 19:42:51 +080063{
64 /*
65 * Map back to global GPIO space and request muxing, the direction
66 * parameter does not matter for this controller.
67 */
Yunlei He27f9fec2014-12-02 12:32:59 +080068 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
69 int gpio = gc->base + offset;
Haojian Zhuang39b70ee2013-02-17 19:42:51 +080070
Yunlei He27f9fec2014-12-02 12:32:59 +080071 if (chip->uses_pinctrl)
72 return pinctrl_request_gpio(gpio);
73 return 0;
Haojian Zhuang39b70ee2013-02-17 19:42:51 +080074}
75
Yunlei He27f9fec2014-12-02 12:32:59 +080076static void pl061_gpio_free(struct gpio_chip *gc, unsigned offset)
Axel Lin22ce4462013-03-15 20:52:07 +080077{
Yunlei He27f9fec2014-12-02 12:32:59 +080078 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
79 int gpio = gc->base + offset;
Axel Lin22ce4462013-03-15 20:52:07 +080080
Yunlei He27f9fec2014-12-02 12:32:59 +080081 if (chip->uses_pinctrl)
82 pinctrl_free_gpio(gpio);
Axel Lin22ce4462013-03-15 20:52:07 +080083}
84
Baruch Siach1e9c2852009-06-18 16:48:58 -070085static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
86{
87 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
88 unsigned long flags;
89 unsigned char gpiodir;
90
91 if (offset >= gc->ngpio)
92 return -EINVAL;
93
94 spin_lock_irqsave(&chip->lock, flags);
95 gpiodir = readb(chip->base + GPIODIR);
Javier Martinez Canillasbea41502014-04-27 02:00:50 +020096 gpiodir &= ~(BIT(offset));
Baruch Siach1e9c2852009-06-18 16:48:58 -070097 writeb(gpiodir, chip->base + GPIODIR);
98 spin_unlock_irqrestore(&chip->lock, flags);
99
100 return 0;
101}
102
103static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
104 int value)
105{
106 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
107 unsigned long flags;
108 unsigned char gpiodir;
109
110 if (offset >= gc->ngpio)
111 return -EINVAL;
112
113 spin_lock_irqsave(&chip->lock, flags);
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200114 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
Baruch Siach1e9c2852009-06-18 16:48:58 -0700115 gpiodir = readb(chip->base + GPIODIR);
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200116 gpiodir |= BIT(offset);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700117 writeb(gpiodir, chip->base + GPIODIR);
viresh kumar64b997c52010-04-21 09:42:05 +0100118
119 /*
120 * gpio value is set again, because pl061 doesn't allow to set value of
121 * a gpio pin before configuring it in OUT mode.
122 */
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200123 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
Baruch Siach1e9c2852009-06-18 16:48:58 -0700124 spin_unlock_irqrestore(&chip->lock, flags);
125
126 return 0;
127}
128
129static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
130{
131 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
132
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200133 return !!readb(chip->base + (BIT(offset + 2)));
Baruch Siach1e9c2852009-06-18 16:48:58 -0700134}
135
136static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
137{
138 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
139
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200140 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
Baruch Siach1e9c2852009-06-18 16:48:58 -0700141}
142
Lennert Buytenhekb2221862011-01-12 17:00:16 -0800143static int pl061_irq_type(struct irq_data *d, unsigned trigger)
Baruch Siach1e9c2852009-06-18 16:48:58 -0700144{
Linus Walleij8d5b24b2014-03-25 10:42:35 +0100145 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
146 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800147 int offset = irqd_to_hwirq(d);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700148 unsigned long flags;
149 u8 gpiois, gpioibe, gpioiev;
Linus Walleij438a2c92013-11-26 12:59:51 +0100150 u8 bit = BIT(offset);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700151
Axel Linc1cc9b92010-05-26 14:42:19 -0700152 if (offset < 0 || offset >= PL061_GPIO_NR)
Baruch Siach1e9c2852009-06-18 16:48:58 -0700153 return -EINVAL;
154
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800155 spin_lock_irqsave(&chip->lock, flags);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700156
157 gpioiev = readb(chip->base + GPIOIEV);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700158 gpiois = readb(chip->base + GPIOIS);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700159 gpioibe = readb(chip->base + GPIOIBE);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700160
Linus Walleij438a2c92013-11-26 12:59:51 +0100161 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
162 gpiois |= bit;
163 if (trigger & IRQ_TYPE_LEVEL_HIGH)
164 gpioiev |= bit;
165 else
166 gpioiev &= ~bit;
167 } else
168 gpiois &= ~bit;
169
170 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
171 /* Setting this makes GPIOEV be ignored */
172 gpioibe |= bit;
173 else {
174 gpioibe &= ~bit;
175 if (trigger & IRQ_TYPE_EDGE_RISING)
176 gpioiev |= bit;
177 else if (trigger & IRQ_TYPE_EDGE_FALLING)
178 gpioiev &= ~bit;
179 }
180
181 writeb(gpiois, chip->base + GPIOIS);
182 writeb(gpioibe, chip->base + GPIOIBE);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700183 writeb(gpioiev, chip->base + GPIOIEV);
184
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800185 spin_unlock_irqrestore(&chip->lock, flags);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700186
187 return 0;
188}
189
Baruch Siach1e9c2852009-06-18 16:48:58 -0700190static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
191{
Rob Herring2de0dbc2012-01-04 10:36:07 -0600192 unsigned long pending;
193 int offset;
Linus Walleij8d5b24b2014-03-25 10:42:35 +0100194 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
195 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
Rob Herringdece9042011-12-09 14:12:53 -0600196 struct irq_chip *irqchip = irq_desc_get_chip(desc);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700197
Rob Herringdece9042011-12-09 14:12:53 -0600198 chained_irq_enter(irqchip, desc);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700199
Rob Herring2de0dbc2012-01-04 10:36:07 -0600200 pending = readb(chip->base + GPIOMIS);
201 writeb(pending, chip->base + GPIOIC);
202 if (pending) {
Akinobu Mita984b3f52010-03-05 13:41:37 -0800203 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
Linus Walleij8d5b24b2014-03-25 10:42:35 +0100204 generic_handle_irq(irq_find_mapping(gc->irqdomain,
205 offset));
Baruch Siach1e9c2852009-06-18 16:48:58 -0700206 }
Rob Herring2de0dbc2012-01-04 10:36:07 -0600207
Rob Herringdece9042011-12-09 14:12:53 -0600208 chained_irq_exit(irqchip, desc);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700209}
210
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800211static void pl061_irq_mask(struct irq_data *d)
Rob Herring3ab52472011-10-21 08:05:53 -0500212{
Linus Walleij8d5b24b2014-03-25 10:42:35 +0100213 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
214 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200215 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800216 u8 gpioie;
Rob Herring3ab52472011-10-21 08:05:53 -0500217
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800218 spin_lock(&chip->lock);
219 gpioie = readb(chip->base + GPIOIE) & ~mask;
220 writeb(gpioie, chip->base + GPIOIE);
221 spin_unlock(&chip->lock);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700222}
223
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800224static void pl061_irq_unmask(struct irq_data *d)
225{
Linus Walleij8d5b24b2014-03-25 10:42:35 +0100226 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
227 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200228 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800229 u8 gpioie;
230
231 spin_lock(&chip->lock);
232 gpioie = readb(chip->base + GPIOIE) | mask;
233 writeb(gpioie, chip->base + GPIOIE);
234 spin_unlock(&chip->lock);
235}
236
237static struct irq_chip pl061_irqchip = {
Linus Walleij9ae7e9e2013-11-26 14:19:44 +0100238 .name = "pl061",
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800239 .irq_mask = pl061_irq_mask,
240 .irq_unmask = pl061_irq_unmask,
241 .irq_set_type = pl061_irq_type,
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800242};
243
Tobias Klauser8944df72012-10-05 11:45:28 +0200244static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
Baruch Siach1e9c2852009-06-18 16:48:58 -0700245{
Tobias Klauser8944df72012-10-05 11:45:28 +0200246 struct device *dev = &adev->dev;
Jingoo Hane56aee12013-07-30 17:08:05 +0900247 struct pl061_platform_data *pdata = dev_get_platdata(dev);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700248 struct pl061_gpio *chip;
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800249 int ret, irq, i, irq_base;
Baruch Siach1e9c2852009-06-18 16:48:58 -0700250
Tobias Klauser8944df72012-10-05 11:45:28 +0200251 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700252 if (chip == NULL)
253 return -ENOMEM;
254
Rob Herring76c05c82011-08-10 16:31:46 -0500255 if (pdata) {
256 chip->gc.base = pdata->gpio_base;
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800257 irq_base = pdata->irq_base;
Linus Walleij78087552013-11-22 10:11:49 +0100258 if (irq_base <= 0) {
259 dev_err(&adev->dev, "invalid IRQ base in pdata\n");
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800260 return -ENODEV;
Linus Walleij78087552013-11-22 10:11:49 +0100261 }
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800262 } else {
Rob Herring76c05c82011-08-10 16:31:46 -0500263 chip->gc.base = -1;
Haojian Zhuangf1f70472013-02-17 19:42:49 +0800264 irq_base = 0;
265 }
Rob Herring76c05c82011-08-10 16:31:46 -0500266
Jingoo Han09bafc32014-02-12 11:53:58 +0900267 chip->base = devm_ioremap_resource(dev, &adev->res);
268 if (IS_ERR(chip->base))
269 return PTR_ERR(chip->base);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700270
271 spin_lock_init(&chip->lock);
Yunlei He27f9fec2014-12-02 12:32:59 +0800272 if (of_property_read_bool(dev->of_node, "gpio-ranges"))
273 chip->uses_pinctrl = true;
Baruch Siach1e9c2852009-06-18 16:48:58 -0700274
Haojian Zhuang39b70ee2013-02-17 19:42:51 +0800275 chip->gc.request = pl061_gpio_request;
Axel Lin22ce4462013-03-15 20:52:07 +0800276 chip->gc.free = pl061_gpio_free;
Baruch Siach1e9c2852009-06-18 16:48:58 -0700277 chip->gc.direction_input = pl061_direction_input;
278 chip->gc.direction_output = pl061_direction_output;
279 chip->gc.get = pl061_get_value;
280 chip->gc.set = pl061_set_value;
Baruch Siach1e9c2852009-06-18 16:48:58 -0700281 chip->gc.ngpio = PL061_GPIO_NR;
Tobias Klauser8944df72012-10-05 11:45:28 +0200282 chip->gc.label = dev_name(dev);
283 chip->gc.dev = dev;
Baruch Siach1e9c2852009-06-18 16:48:58 -0700284 chip->gc.owner = THIS_MODULE;
285
Baruch Siach1e9c2852009-06-18 16:48:58 -0700286 ret = gpiochip_add(&chip->gc);
287 if (ret)
Tobias Klauser8944df72012-10-05 11:45:28 +0200288 return ret;
Baruch Siach1e9c2852009-06-18 16:48:58 -0700289
290 /*
291 * irq_chip support
292 */
Baruch Siach1e9c2852009-06-18 16:48:58 -0700293 writeb(0, chip->base + GPIOIE); /* disable irqs */
Tobias Klauser8944df72012-10-05 11:45:28 +0200294 irq = adev->irq[0];
Linus Walleij78087552013-11-22 10:11:49 +0100295 if (irq < 0) {
296 dev_err(&adev->dev, "invalid IRQ\n");
Tobias Klauser8944df72012-10-05 11:45:28 +0200297 return -ENODEV;
Linus Walleij78087552013-11-22 10:11:49 +0100298 }
Tobias Klauser8944df72012-10-05 11:45:28 +0200299
Linus Walleij8d5b24b2014-03-25 10:42:35 +0100300 ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
301 irq_base, handle_simple_irq,
302 IRQ_TYPE_NONE);
303 if (ret) {
304 dev_info(&adev->dev, "could not add irqchip\n");
305 return ret;
Linus Walleij78087552013-11-22 10:11:49 +0100306 }
Linus Walleij8d5b24b2014-03-25 10:42:35 +0100307 gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
308 irq, pl061_irq_handler);
Linus Walleij2ba31542013-11-27 08:47:02 +0100309
Baruch Siach1e9c2852009-06-18 16:48:58 -0700310 for (i = 0; i < PL061_GPIO_NR; i++) {
Rob Herring76c05c82011-08-10 16:31:46 -0500311 if (pdata) {
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200312 if (pdata->directions & (BIT(i)))
Rob Herring76c05c82011-08-10 16:31:46 -0500313 pl061_direction_output(&chip->gc, i,
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200314 pdata->values & (BIT(i)));
Rob Herring76c05c82011-08-10 16:31:46 -0500315 else
316 pl061_direction_input(&chip->gc, i);
317 }
Baruch Siach1e9c2852009-06-18 16:48:58 -0700318 }
319
Tobias Klauser8944df72012-10-05 11:45:28 +0200320 amba_set_drvdata(adev, chip);
Fabio Estevam76b36272014-02-26 08:12:37 -0300321 dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
322 &adev->res.start);
Deepak Sikrie198a8de2011-11-18 15:20:12 +0530323
Baruch Siach1e9c2852009-06-18 16:48:58 -0700324 return 0;
Baruch Siach1e9c2852009-06-18 16:48:58 -0700325}
326
Deepak Sikrie198a8de2011-11-18 15:20:12 +0530327#ifdef CONFIG_PM
328static int pl061_suspend(struct device *dev)
329{
330 struct pl061_gpio *chip = dev_get_drvdata(dev);
331 int offset;
332
333 chip->csave_regs.gpio_data = 0;
334 chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
335 chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
336 chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
337 chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
338 chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
339
340 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200341 if (chip->csave_regs.gpio_dir & (BIT(offset)))
Deepak Sikrie198a8de2011-11-18 15:20:12 +0530342 chip->csave_regs.gpio_data |=
343 pl061_get_value(&chip->gc, offset) << offset;
344 }
345
346 return 0;
347}
348
349static int pl061_resume(struct device *dev)
350{
351 struct pl061_gpio *chip = dev_get_drvdata(dev);
352 int offset;
353
354 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200355 if (chip->csave_regs.gpio_dir & (BIT(offset)))
Deepak Sikrie198a8de2011-11-18 15:20:12 +0530356 pl061_direction_output(&chip->gc, offset,
357 chip->csave_regs.gpio_data &
Javier Martinez Canillasbea41502014-04-27 02:00:50 +0200358 (BIT(offset)));
Deepak Sikrie198a8de2011-11-18 15:20:12 +0530359 else
360 pl061_direction_input(&chip->gc, offset);
361 }
362
363 writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
364 writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
365 writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
366 writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
367
368 return 0;
369}
370
Viresh Kumar6e33ace2012-01-11 15:25:20 +0530371static const struct dev_pm_ops pl061_dev_pm_ops = {
372 .suspend = pl061_suspend,
373 .resume = pl061_resume,
374 .freeze = pl061_suspend,
375 .restore = pl061_resume,
376};
Deepak Sikrie198a8de2011-11-18 15:20:12 +0530377#endif
378
Russell King2c39c9e2010-07-27 08:50:16 +0100379static struct amba_id pl061_ids[] = {
Baruch Siach1e9c2852009-06-18 16:48:58 -0700380 {
381 .id = 0x00041061,
382 .mask = 0x000fffff,
383 },
384 { 0, 0 },
385};
386
Dave Martin955b6782011-10-05 15:15:21 +0100387MODULE_DEVICE_TABLE(amba, pl061_ids);
388
Baruch Siach1e9c2852009-06-18 16:48:58 -0700389static struct amba_driver pl061_gpio_driver = {
390 .drv = {
391 .name = "pl061_gpio",
Deepak Sikrie198a8de2011-11-18 15:20:12 +0530392#ifdef CONFIG_PM
393 .pm = &pl061_dev_pm_ops,
394#endif
Baruch Siach1e9c2852009-06-18 16:48:58 -0700395 },
396 .id_table = pl061_ids,
397 .probe = pl061_probe,
398};
399
400static int __init pl061_gpio_init(void)
401{
402 return amba_driver_register(&pl061_gpio_driver);
403}
Haojian Zhuang5985d762013-01-18 15:31:13 +0800404module_init(pl061_gpio_init);
Baruch Siach1e9c2852009-06-18 16:48:58 -0700405
406MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
407MODULE_DESCRIPTION("PL061 GPIO driver");
408MODULE_LICENSE("GPL");