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gerrit-public.fairphone.software / kernel / msm-4.9 / 7629838ca33adf8d576d9e4a9d31df4f3b3bc258 / . / arch / arm / boot / dts / imx6q.dtsi
blob: 3290e61be3e1c185e697ee406a22b5b2808db5b0 [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 };
40
41 cpu@1 {
42 compatible = "arm,cortex-a9";
43 reg = <1>;
44 next-level-cache = <&L2>;
45 };
46
47 cpu@2 {
48 compatible = "arm,cortex-a9";
49 reg = <2>;
50 next-level-cache = <&L2>;
51 };
52
53 cpu@3 {
54 compatible = "arm,cortex-a9";
55 reg = <3>;
56 next-level-cache = <&L2>;
57 };
58 };
59
60 intc: interrupt-controller@00a01000 {
61 compatible = "arm,cortex-a9-gic";
62 #interrupt-cells = <3>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 interrupt-controller;
66 reg = <0x00a01000 0x1000>,
67 <0x00a00100 0x100>;
68 };
69
70 clocks {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 ckil {
75 compatible = "fsl,imx-ckil", "fixed-clock";
76 clock-frequency = <32768>;
77 };
78
79 ckih1 {
80 compatible = "fsl,imx-ckih1", "fixed-clock";
81 clock-frequency = <0>;
82 };
83
84 osc {
85 compatible = "fsl,imx-osc", "fixed-clock";
86 clock-frequency = <24000000>;
87 };
88 };
89
90 soc {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "simple-bus";
94 interrupt-parent = <&intc>;
95 ranges;
96
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]97 dma-apbh@00110000 {
98 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
99 reg = <0x00110000 0x2000>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]100 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]101 };
102
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]103 gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]104 compatible = "fsl,imx6q-gpmi-nand";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
108 reg-names = "gpmi-nand", "bch";
109 interrupts = <0 13 0x04>, <0 15 0x04>;
110 interrupt-names = "gpmi-dma", "bch";
111 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
112 <&clks 150>, <&clks 149>;
113 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
114 "gpmi_bch_apb", "per1_bch";
115 fsl,gpmi-dma-channel = <0>;
116 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]117 };
118
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]119 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]120 compatible = "arm,cortex-a9-twd-timer";
121 reg = <0x00a00600 0x20>;
122 interrupts = <1 13 0xf01>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]123 };
124
125 L2: l2-cache@00a02000 {
126 compatible = "arm,pl310-cache";
127 reg = <0x00a02000 0x1000>;
128 interrupts = <0 92 0x04>;
129 cache-unified;
130 cache-level = <2>;
131 };
132
133 aips-bus@02000000 { /* AIPS1 */
134 compatible = "fsl,aips-bus", "simple-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 reg = <0x02000000 0x100000>;
138 ranges;
139
140 spba-bus@02000000 {
141 compatible = "fsl,spba-bus", "simple-bus";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 reg = <0x02000000 0x40000>;
145 ranges;
146
147 spdif@02004000 {
148 reg = <0x02004000 0x4000>;
149 interrupts = <0 52 0x04>;
150 };
151
152 ecspi@02008000 { /* eCSPI1 */
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
156 reg = <0x02008000 0x4000>;
157 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]158 clocks = <&clks 112>, <&clks 112>;
159 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]160 status = "disabled";
161 };
162
163 ecspi@0200c000 { /* eCSPI2 */
164 #address-cells = <1>;
165 #size-cells = <0>;
166 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
167 reg = <0x0200c000 0x4000>;
168 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]169 clocks = <&clks 113>, <&clks 113>;
170 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]171 status = "disabled";
172 };
173
174 ecspi@02010000 { /* eCSPI3 */
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02010000 0x4000>;
179 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]180 clocks = <&clks 114>, <&clks 114>;
181 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]182 status = "disabled";
183 };
184
185 ecspi@02014000 { /* eCSPI4 */
186 #address-cells = <1>;
187 #size-cells = <0>;
188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
189 reg = <0x02014000 0x4000>;
190 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]191 clocks = <&clks 115>, <&clks 115>;
192 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]193 status = "disabled";
194 };
195
196 ecspi@02018000 { /* eCSPI5 */
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
200 reg = <0x02018000 0x4000>;
201 interrupts = <0 35 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]202 clocks = <&clks 116>, <&clks 116>;
203 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]204 status = "disabled";
205 };
206
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]207 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]208 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
209 reg = <0x02020000 0x4000>;
210 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]211 clocks = <&clks 160>, <&clks 161>;
212 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]213 status = "disabled";
214 };
215
216 esai@02024000 {
217 reg = <0x02024000 0x4000>;
218 interrupts = <0 51 0x04>;
219 };
220
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]221 ssi1: ssi@02028000 {
222 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]223 reg = <0x02028000 0x4000>;
224 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]225 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]226 fsl,fifo-depth = <15>;
227 fsl,ssi-dma-events = <38 37>;
228 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]229 };
230
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]231 ssi2: ssi@0202c000 {
232 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]233 reg = <0x0202c000 0x4000>;
234 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]235 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]236 fsl,fifo-depth = <15>;
237 fsl,ssi-dma-events = <42 41>;
238 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]239 };
240
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]241 ssi3: ssi@02030000 {
242 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]243 reg = <0x02030000 0x4000>;
244 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]245 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]246 fsl,fifo-depth = <15>;
247 fsl,ssi-dma-events = <46 45>;
248 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]249 };
250
251 asrc@02034000 {
252 reg = <0x02034000 0x4000>;
253 interrupts = <0 50 0x04>;
254 };
255
256 spba@0203c000 {
257 reg = <0x0203c000 0x4000>;
258 };
259 };
260
261 vpu@02040000 {
262 reg = <0x02040000 0x3c000>;
263 interrupts = <0 3 0x04 0 12 0x04>;
264 };
265
266 aipstz@0207c000 { /* AIPSTZ1 */
267 reg = <0x0207c000 0x4000>;
268 };
269
270 pwm@02080000 { /* PWM1 */
271 reg = <0x02080000 0x4000>;
272 interrupts = <0 83 0x04>;
273 };
274
275 pwm@02084000 { /* PWM2 */
276 reg = <0x02084000 0x4000>;
277 interrupts = <0 84 0x04>;
278 };
279
280 pwm@02088000 { /* PWM3 */
281 reg = <0x02088000 0x4000>;
282 interrupts = <0 85 0x04>;
283 };
284
285 pwm@0208c000 { /* PWM4 */
286 reg = <0x0208c000 0x4000>;
287 interrupts = <0 86 0x04>;
288 };
289
290 flexcan@02090000 { /* CAN1 */
291 reg = <0x02090000 0x4000>;
292 interrupts = <0 110 0x04>;
293 };
294
295 flexcan@02094000 { /* CAN2 */
296 reg = <0x02094000 0x4000>;
297 interrupts = <0 111 0x04>;
298 };
299
300 gpt@02098000 {
301 compatible = "fsl,imx6q-gpt";
302 reg = <0x02098000 0x4000>;
303 interrupts = <0 55 0x04>;
304 };
305
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]306 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]307 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]308 reg = <0x0209c000 0x4000>;
309 interrupts = <0 66 0x04 0 67 0x04>;
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]313 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]314 };
315
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]316 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]317 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]318 reg = <0x020a0000 0x4000>;
319 interrupts = <0 68 0x04 0 69 0x04>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]323 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]324 };
325
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]326 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]327 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]328 reg = <0x020a4000 0x4000>;
329 interrupts = <0 70 0x04 0 71 0x04>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]333 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]334 };
335
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]336 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]337 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]338 reg = <0x020a8000 0x4000>;
339 interrupts = <0 72 0x04 0 73 0x04>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]343 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]344 };
345
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]346 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]347 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]348 reg = <0x020ac000 0x4000>;
349 interrupts = <0 74 0x04 0 75 0x04>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]353 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]354 };
355
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]356 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]357 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]358 reg = <0x020b0000 0x4000>;
359 interrupts = <0 76 0x04 0 77 0x04>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]363 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]364 };
365
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]366 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]367 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]368 reg = <0x020b4000 0x4000>;
369 interrupts = <0 78 0x04 0 79 0x04>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]373 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]374 };
375
376 kpp@020b8000 {
377 reg = <0x020b8000 0x4000>;
378 interrupts = <0 82 0x04>;
379 };
380
381 wdog@020bc000 { /* WDOG1 */
382 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
383 reg = <0x020bc000 0x4000>;
384 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]385 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]386 };
387
388 wdog@020c0000 { /* WDOG2 */
389 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
390 reg = <0x020c0000 0x4000>;
391 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]392 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]393 status = "disabled";
394 };
395
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]396 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]397 compatible = "fsl,imx6q-ccm";
398 reg = <0x020c4000 0x4000>;
399 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]400 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]401 };
402
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]403 anatop: anatop@020c8000 {
404 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]405 reg = <0x020c8000 0x1000>;
406 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]407
408 regulator-1p1@110 {
409 compatible = "fsl,anatop-regulator";
410 regulator-name = "vdd1p1";
411 regulator-min-microvolt = <800000>;
412 regulator-max-microvolt = <1375000>;
413 regulator-always-on;
414 anatop-reg-offset = <0x110>;
415 anatop-vol-bit-shift = <8>;
416 anatop-vol-bit-width = <5>;
417 anatop-min-bit-val = <4>;
418 anatop-min-voltage = <800000>;
419 anatop-max-voltage = <1375000>;
420 };
421
422 regulator-3p0@120 {
423 compatible = "fsl,anatop-regulator";
424 regulator-name = "vdd3p0";
425 regulator-min-microvolt = <2800000>;
426 regulator-max-microvolt = <3150000>;
427 regulator-always-on;
428 anatop-reg-offset = <0x120>;
429 anatop-vol-bit-shift = <8>;
430 anatop-vol-bit-width = <5>;
431 anatop-min-bit-val = <0>;
432 anatop-min-voltage = <2625000>;
433 anatop-max-voltage = <3400000>;
434 };
435
436 regulator-2p5@130 {
437 compatible = "fsl,anatop-regulator";
438 regulator-name = "vdd2p5";
439 regulator-min-microvolt = <2000000>;
440 regulator-max-microvolt = <2750000>;
441 regulator-always-on;
442 anatop-reg-offset = <0x130>;
443 anatop-vol-bit-shift = <8>;
444 anatop-vol-bit-width = <5>;
445 anatop-min-bit-val = <0>;
446 anatop-min-voltage = <2000000>;
447 anatop-max-voltage = <2750000>;
448 };
449
450 regulator-vddcore@140 {
451 compatible = "fsl,anatop-regulator";
452 regulator-name = "cpu";
453 regulator-min-microvolt = <725000>;
454 regulator-max-microvolt = <1450000>;
455 regulator-always-on;
456 anatop-reg-offset = <0x140>;
457 anatop-vol-bit-shift = <0>;
458 anatop-vol-bit-width = <5>;
459 anatop-min-bit-val = <1>;
460 anatop-min-voltage = <725000>;
461 anatop-max-voltage = <1450000>;
462 };
463
464 regulator-vddpu@140 {
465 compatible = "fsl,anatop-regulator";
466 regulator-name = "vddpu";
467 regulator-min-microvolt = <725000>;
468 regulator-max-microvolt = <1450000>;
469 regulator-always-on;
470 anatop-reg-offset = <0x140>;
471 anatop-vol-bit-shift = <9>;
472 anatop-vol-bit-width = <5>;
473 anatop-min-bit-val = <1>;
474 anatop-min-voltage = <725000>;
475 anatop-max-voltage = <1450000>;
476 };
477
478 regulator-vddsoc@140 {
479 compatible = "fsl,anatop-regulator";
480 regulator-name = "vddsoc";
481 regulator-min-microvolt = <725000>;
482 regulator-max-microvolt = <1450000>;
483 regulator-always-on;
484 anatop-reg-offset = <0x140>;
485 anatop-vol-bit-shift = <18>;
486 anatop-vol-bit-width = <5>;
487 anatop-min-bit-val = <1>;
488 anatop-min-voltage = <725000>;
489 anatop-max-voltage = <1450000>;
490 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]491 };
492
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]493 usbphy1: usbphy@020c9000 {
494 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]495 reg = <0x020c9000 0x1000>;
496 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]497 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]498 };
499
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]500 usbphy2: usbphy@020ca000 {
501 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]502 reg = <0x020ca000 0x1000>;
503 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]504 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]505 };
506
507 snvs@020cc000 {
508 reg = <0x020cc000 0x4000>;
509 interrupts = <0 19 0x04 0 20 0x04>;
510 };
511
512 epit@020d0000 { /* EPIT1 */
513 reg = <0x020d0000 0x4000>;
514 interrupts = <0 56 0x04>;
515 };
516
517 epit@020d4000 { /* EPIT2 */
518 reg = <0x020d4000 0x4000>;
519 interrupts = <0 57 0x04>;
520 };
521
522 src@020d8000 {
523 compatible = "fsl,imx6q-src";
524 reg = <0x020d8000 0x4000>;
525 interrupts = <0 91 0x04 0 96 0x04>;
526 };
527
528 gpc@020dc000 {
529 compatible = "fsl,imx6q-gpc";
530 reg = <0x020dc000 0x4000>;
531 interrupts = <0 89 0x04 0 90 0x04>;
532 };
533
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]534 gpr: iomuxc-gpr@020e0000 {
535 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
536 reg = <0x020e0000 0x38>;
537 };
538
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]539 iomuxc@020e0000 {
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]540 compatible = "fsl,imx6q-iomuxc";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]541 reg = <0x020e0000 0x4000>;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]542
543 /* shared pinctrl settings */
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]544 audmux {
545 pinctrl_audmux_1: audmux-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]546 fsl,pins = <
547 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
548 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
549 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
550 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
551 >;
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]552 };
553 };
554
Shawn Guo52ccd492012-08-11 11:17:42 +0800[diff] [blame]555 ecspi1 {
556 pinctrl_ecspi1_1: ecspi1grp-1 {
557 fsl,pins = <
558 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
559 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
560 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
561 >;
562 };
563 };
564
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]565 enet {
566 pinctrl_enet_1: enetgrp-1 {
567 fsl,pins = <
568 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
569 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
570 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
571 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
572 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
573 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
574 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
575 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
576 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
577 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
578 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
579 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
580 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
581 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
582 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame^]583 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]584 >;
585 };
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]586
587 pinctrl_enet_2: enetgrp-2 {
588 fsl,pins = <
589 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
590 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
591 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
592 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
593 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
594 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
595 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
596 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
597 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
598 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
599 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
600 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
601 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
602 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
603 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
604 >;
605 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]606 };
607
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]608 gpmi-nand {
609 pinctrl_gpmi_nand_1: gpmi-nand-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]610 fsl,pins = <
611 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
612 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
613 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
614 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
615 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
616 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
617 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
618 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
619 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
620 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
621 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
622 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
623 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
624 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
625 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
626 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
627 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
628 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
629 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
630 >;
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]631 };
632 };
633
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]634 i2c1 {
635 pinctrl_i2c1_1: i2c1grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]636 fsl,pins = <
637 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
638 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
639 >;
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]640 };
641 };
642
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame]643 uart1 {
644 pinctrl_uart1_1: uart1grp-1 {
645 fsl,pins = <
646 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
647 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
648 >;
649 };
650 };
651
Shawn Guoe30ba892012-08-11 12:33:51 +0800[diff] [blame]652 uart2 {
653 pinctrl_uart2_1: uart2grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]654 fsl,pins = <
655 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
656 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
657 >;
Richard Zhaoc3001b22012-05-09 14:44:47 +0800[diff] [blame]658 };
659 };
660
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]661 uart4 {
662 pinctrl_uart4_1: uart4grp-1 {
663 fsl,pins = <
664 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
665 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
666 >;
667 };
668 };
669
Richard Zhao97a53092012-09-19 11:25:16 +0800[diff] [blame]670 usbotg {
671 pinctrl_usbotg_1: usbotggrp-1 {
672 fsl,pins = <
673 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
674 >;
675 };
676 };
677
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame]678 usdhc2 {
679 pinctrl_usdhc2_1: usdhc2grp-1 {
680 fsl,pins = <
681 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
682 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
683 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
684 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
685 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
686 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
687 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
688 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
689 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
690 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
691 >;
692 };
693 };
694
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]695 usdhc3 {
696 pinctrl_usdhc3_1: usdhc3grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]697 fsl,pins = <
698 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
699 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
700 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
701 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
702 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
703 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
704 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
705 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
706 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
707 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
708 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]709 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]710
711 pinctrl_usdhc3_2: usdhc3grp-2 {
712 fsl,pins = <
713 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
714 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
715 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
716 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
717 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
718 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
719 >;
720 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]721 };
722
723 usdhc4 {
724 pinctrl_usdhc4_1: usdhc4grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]725 fsl,pins = <
726 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
727 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
728 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
729 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
730 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
731 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
732 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
733 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
734 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
735 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
736 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]737 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]738
739 pinctrl_usdhc4_2: usdhc4grp-2 {
740 fsl,pins = <
741 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
742 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
743 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
744 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
745 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
746 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
747 >;
748 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]749 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]750 };
751
752 dcic@020e4000 { /* DCIC1 */
753 reg = <0x020e4000 0x4000>;
754 interrupts = <0 124 0x04>;
755 };
756
757 dcic@020e8000 { /* DCIC2 */
758 reg = <0x020e8000 0x4000>;
759 interrupts = <0 125 0x04>;
760 };
761
762 sdma@020ec000 {
763 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
764 reg = <0x020ec000 0x4000>;
765 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]766 clocks = <&clks 155>, <&clks 155>;
767 clock-names = "ipg", "ahb";
768 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]769 };
770 };
771
772 aips-bus@02100000 { /* AIPS2 */
773 compatible = "fsl,aips-bus", "simple-bus";
774 #address-cells = <1>;
775 #size-cells = <1>;
776 reg = <0x02100000 0x100000>;
777 ranges;
778
779 caam@02100000 {
780 reg = <0x02100000 0x40000>;
781 interrupts = <0 105 0x04 0 106 0x04>;
782 };
783
784 aipstz@0217c000 { /* AIPSTZ2 */
785 reg = <0x0217c000 0x4000>;
786 };
787
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]788 usb@02184000 { /* USB OTG */
789 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
790 reg = <0x02184000 0x200>;
791 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]792 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]793 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]794 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]795 status = "disabled";
796 };
797
798 usb@02184200 { /* USB1 */
799 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
800 reg = <0x02184200 0x200>;
801 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]802 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]803 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]804 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]805 status = "disabled";
806 };
807
808 usb@02184400 { /* USB2 */
809 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
810 reg = <0x02184400 0x200>;
811 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]812 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]813 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]814 status = "disabled";
815 };
816
817 usb@02184600 { /* USB3 */
818 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
819 reg = <0x02184600 0x200>;
820 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]821 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]822 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]823 status = "disabled";
824 };
825
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]826 usbmisc: usbmisc@02184800 {
827 #index-cells = <1>;
828 compatible = "fsl,imx6q-usbmisc";
829 reg = <0x02184800 0x200>;
830 clocks = <&clks 162>;
831 };
832
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]833 ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]834 compatible = "fsl,imx6q-fec";
835 reg = <0x02188000 0x4000>;
836 interrupts = <0 118 0x04 0 119 0x04>;
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame^]837 clocks = <&clks 117>, <&clks 117>, <&clks 177>;
838 clock-names = "ipg", "ahb", "ptp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]839 status = "disabled";
840 };
841
842 mlb@0218c000 {
843 reg = <0x0218c000 0x4000>;
844 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
845 };
846
847 usdhc@02190000 { /* uSDHC1 */
848 compatible = "fsl,imx6q-usdhc";
849 reg = <0x02190000 0x4000>;
850 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]851 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
852 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]853 status = "disabled";
854 };
855
856 usdhc@02194000 { /* uSDHC2 */
857 compatible = "fsl,imx6q-usdhc";
858 reg = <0x02194000 0x4000>;
859 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]860 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
861 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]862 status = "disabled";
863 };
864
865 usdhc@02198000 { /* uSDHC3 */
866 compatible = "fsl,imx6q-usdhc";
867 reg = <0x02198000 0x4000>;
868 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]869 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
870 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]871 status = "disabled";
872 };
873
874 usdhc@0219c000 { /* uSDHC4 */
875 compatible = "fsl,imx6q-usdhc";
876 reg = <0x0219c000 0x4000>;
877 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]878 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
879 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]880 status = "disabled";
881 };
882
883 i2c@021a0000 { /* I2C1 */
884 #address-cells = <1>;
885 #size-cells = <0>;
886 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
887 reg = <0x021a0000 0x4000>;
888 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]889 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]890 status = "disabled";
891 };
892
893 i2c@021a4000 { /* I2C2 */
894 #address-cells = <1>;
895 #size-cells = <0>;
896 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
897 reg = <0x021a4000 0x4000>;
898 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]899 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]900 status = "disabled";
901 };
902
903 i2c@021a8000 { /* I2C3 */
904 #address-cells = <1>;
905 #size-cells = <0>;
906 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
907 reg = <0x021a8000 0x4000>;
908 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]909 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]910 status = "disabled";
911 };
912
913 romcp@021ac000 {
914 reg = <0x021ac000 0x4000>;
915 };
916
917 mmdc@021b0000 { /* MMDC0 */
918 compatible = "fsl,imx6q-mmdc";
919 reg = <0x021b0000 0x4000>;
920 };
921
922 mmdc@021b4000 { /* MMDC1 */
923 reg = <0x021b4000 0x4000>;
924 };
925
926 weim@021b8000 {
927 reg = <0x021b8000 0x4000>;
928 interrupts = <0 14 0x04>;
929 };
930
931 ocotp@021bc000 {
932 reg = <0x021bc000 0x4000>;
933 };
934
935 ocotp@021c0000 {
936 reg = <0x021c0000 0x4000>;
937 interrupts = <0 21 0x04>;
938 };
939
940 tzasc@021d0000 { /* TZASC1 */
941 reg = <0x021d0000 0x4000>;
942 interrupts = <0 108 0x04>;
943 };
944
945 tzasc@021d4000 { /* TZASC2 */
946 reg = <0x021d4000 0x4000>;
947 interrupts = <0 109 0x04>;
948 };
949
950 audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]951 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]952 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]953 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]954 };
955
956 mipi@021dc000 { /* MIPI-CSI */
957 reg = <0x021dc000 0x4000>;
958 };
959
960 mipi@021e0000 { /* MIPI-DSI */
961 reg = <0x021e0000 0x4000>;
962 };
963
964 vdoa@021e4000 {
965 reg = <0x021e4000 0x4000>;
966 interrupts = <0 18 0x04>;
967 };
968
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]969 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]970 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
971 reg = <0x021e8000 0x4000>;
972 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]973 clocks = <&clks 160>, <&clks 161>;
974 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]975 status = "disabled";
976 };
977
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]978 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]979 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
980 reg = <0x021ec000 0x4000>;
981 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]982 clocks = <&clks 160>, <&clks 161>;
983 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]984 status = "disabled";
985 };
986
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]987 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]988 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
989 reg = <0x021f0000 0x4000>;
990 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]991 clocks = <&clks 160>, <&clks 161>;
992 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]993 status = "disabled";
994 };
995
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]996 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]997 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
998 reg = <0x021f4000 0x4000>;
999 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1000 clocks = <&clks 160>, <&clks 161>;
1001 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1002 status = "disabled";
1003 };
1004 };
1005 };
1006};