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Bard Liao07cf7cba2014-06-20 14:41:13 +08001/*
2 * rt286.c -- RT286 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
Bard Liao6c67cde2014-11-06 09:59:59 +080020#include <linux/dmi.h>
Bard Liao07cf7cba2014-06-20 14:41:13 +080021#include <linux/acpi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/jack.h>
30#include <linux/workqueue.h>
31#include <sound/rt286.h>
32#include <sound/hda_verbs.h>
33
34#include "rt286.h"
35
36#define RT286_VENDOR_ID 0x10ec0286
37
38struct rt286_priv {
39 struct regmap *regmap;
Bard Liao6879db72014-10-31 14:52:16 +080040 struct snd_soc_codec *codec;
Bard Liao07cf7cba2014-06-20 14:41:13 +080041 struct rt286_platform_data pdata;
42 struct i2c_client *i2c;
43 struct snd_soc_jack *jack;
44 struct delayed_work jack_detect_work;
45 int sys_clk;
Bard Liao6879db72014-10-31 14:52:16 +080046 int clk_id;
Bard Liao07cf7cba2014-06-20 14:41:13 +080047 struct reg_default *index_cache;
48};
49
50static struct reg_default rt286_index_def[] = {
51 { 0x01, 0xaaaa },
52 { 0x02, 0x8aaa },
53 { 0x03, 0x0002 },
54 { 0x04, 0xaf01 },
55 { 0x08, 0x000d },
56 { 0x09, 0xd810 },
Bard Liaob7a29762014-09-26 11:06:39 +080057 { 0x0a, 0x0120 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080058 { 0x0b, 0x0000 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080059 { 0x0d, 0x2800 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080060 { 0x0f, 0x0000 },
61 { 0x19, 0x0a17 },
62 { 0x20, 0x0020 },
63 { 0x33, 0x0208 },
64 { 0x49, 0x0004 },
65 { 0x4f, 0x50e9 },
Bard Liaob7a29762014-09-26 11:06:39 +080066 { 0x50, 0x2000 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080067 { 0x63, 0x2902 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080068 { 0x67, 0x1111 },
69 { 0x68, 0x1016 },
70 { 0x69, 0x273f },
Bard Liao07cf7cba2014-06-20 14:41:13 +080071};
72#define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
73
74static const struct reg_default rt286_reg[] = {
75 { 0x00170500, 0x00000400 },
76 { 0x00220000, 0x00000031 },
77 { 0x00239000, 0x0000007f },
78 { 0x0023a000, 0x0000007f },
79 { 0x00270500, 0x00000400 },
80 { 0x00370500, 0x00000400 },
81 { 0x00870500, 0x00000400 },
82 { 0x00920000, 0x00000031 },
83 { 0x00935000, 0x000000c3 },
84 { 0x00936000, 0x000000c3 },
85 { 0x00970500, 0x00000400 },
86 { 0x00b37000, 0x00000097 },
87 { 0x00b37200, 0x00000097 },
88 { 0x00b37300, 0x00000097 },
89 { 0x00c37000, 0x00000000 },
90 { 0x00c37100, 0x00000080 },
91 { 0x01270500, 0x00000400 },
92 { 0x01370500, 0x00000400 },
93 { 0x01371f00, 0x411111f0 },
94 { 0x01439000, 0x00000080 },
95 { 0x0143a000, 0x00000080 },
96 { 0x01470700, 0x00000000 },
97 { 0x01470500, 0x00000400 },
98 { 0x01470c00, 0x00000000 },
99 { 0x01470100, 0x00000000 },
100 { 0x01837000, 0x00000000 },
101 { 0x01870500, 0x00000400 },
102 { 0x02050000, 0x00000000 },
103 { 0x02139000, 0x00000080 },
104 { 0x0213a000, 0x00000080 },
105 { 0x02170100, 0x00000000 },
106 { 0x02170500, 0x00000400 },
107 { 0x02170700, 0x00000000 },
108 { 0x02270100, 0x00000000 },
109 { 0x02370100, 0x00000000 },
Bard Liao07cf7cba2014-06-20 14:41:13 +0800110 { 0x01870700, 0x00000020 },
111 { 0x00830000, 0x000000c3 },
112 { 0x00930000, 0x000000c3 },
113 { 0x01270700, 0x00000000 },
114};
115
116static bool rt286_volatile_register(struct device *dev, unsigned int reg)
117{
118 switch (reg) {
119 case 0 ... 0xff:
120 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
121 case RT286_GET_HP_SENSE:
122 case RT286_GET_MIC1_SENSE:
123 case RT286_PROC_COEF:
124 return true;
125 default:
126 return false;
127 }
128
129
130}
131
132static bool rt286_readable_register(struct device *dev, unsigned int reg)
133{
134 switch (reg) {
135 case 0 ... 0xff:
136 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
137 case RT286_GET_HP_SENSE:
138 case RT286_GET_MIC1_SENSE:
139 case RT286_SET_AUDIO_POWER:
140 case RT286_SET_HPO_POWER:
141 case RT286_SET_SPK_POWER:
142 case RT286_SET_DMIC1_POWER:
143 case RT286_SPK_MUX:
144 case RT286_HPO_MUX:
145 case RT286_ADC0_MUX:
146 case RT286_ADC1_MUX:
147 case RT286_SET_MIC1:
148 case RT286_SET_PIN_HPO:
149 case RT286_SET_PIN_SPK:
150 case RT286_SET_PIN_DMIC1:
151 case RT286_SPK_EAPD:
152 case RT286_SET_AMP_GAIN_HPO:
153 case RT286_SET_DMIC2_DEFAULT:
154 case RT286_DACL_GAIN:
155 case RT286_DACR_GAIN:
156 case RT286_ADCL_GAIN:
157 case RT286_ADCR_GAIN:
158 case RT286_MIC_GAIN:
159 case RT286_SPOL_GAIN:
160 case RT286_SPOR_GAIN:
161 case RT286_HPOL_GAIN:
162 case RT286_HPOR_GAIN:
163 case RT286_F_DAC_SWITCH:
164 case RT286_F_RECMIX_SWITCH:
165 case RT286_REC_MIC_SWITCH:
166 case RT286_REC_I2S_SWITCH:
167 case RT286_REC_LINE_SWITCH:
168 case RT286_REC_BEEP_SWITCH:
169 case RT286_DAC_FORMAT:
170 case RT286_ADC_FORMAT:
171 case RT286_COEF_INDEX:
172 case RT286_PROC_COEF:
173 case RT286_SET_AMP_GAIN_ADC_IN1:
174 case RT286_SET_AMP_GAIN_ADC_IN2:
175 case RT286_SET_POWER(RT286_DAC_OUT1):
176 case RT286_SET_POWER(RT286_DAC_OUT2):
177 case RT286_SET_POWER(RT286_ADC_IN1):
178 case RT286_SET_POWER(RT286_ADC_IN2):
179 case RT286_SET_POWER(RT286_DMIC2):
180 case RT286_SET_POWER(RT286_MIC1):
181 return true;
182 default:
183 return false;
184 }
185}
186
187static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
188{
189 struct i2c_client *client = context;
190 struct rt286_priv *rt286 = i2c_get_clientdata(client);
191 u8 data[4];
192 int ret, i;
193
Bard Liaof8c101b2014-11-06 10:00:00 +0800194 /* handle index registers */
Bard Liao07cf7cba2014-06-20 14:41:13 +0800195 if (reg <= 0xff) {
196 rt286_hw_write(client, RT286_COEF_INDEX, reg);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800197 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
198 if (reg == rt286->index_cache[i].reg) {
199 rt286->index_cache[i].def = value;
200 break;
201 }
202
203 }
Bard Liao66d627d2014-09-26 11:06:40 +0800204 reg = RT286_PROC_COEF;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800205 }
206
207 data[0] = (reg >> 24) & 0xff;
208 data[1] = (reg >> 16) & 0xff;
209 /*
210 * 4 bit VID: reg should be 0
211 * 12 bit VID: value should be 0
212 * So we use an OR operator to handle it rather than use if condition.
213 */
214 data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff);
215 data[3] = value & 0xff;
216
217 ret = i2c_master_send(client, data, 4);
218
219 if (ret == 4)
220 return 0;
221 else
222 pr_err("ret=%d\n", ret);
223 if (ret < 0)
224 return ret;
225 else
226 return -EIO;
227}
228
229static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value)
230{
231 struct i2c_client *client = context;
232 struct i2c_msg xfer[2];
233 int ret;
234 __be32 be_reg;
235 unsigned int index, vid, buf = 0x0;
236
Bard Liaof8c101b2014-11-06 10:00:00 +0800237 /* handle index registers */
Bard Liao07cf7cba2014-06-20 14:41:13 +0800238 if (reg <= 0xff) {
239 rt286_hw_write(client, RT286_COEF_INDEX, reg);
240 reg = RT286_PROC_COEF;
241 }
242
243 reg = reg | 0x80000;
244 vid = (reg >> 8) & 0xfff;
245
246 if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) {
247 index = (reg >> 8) & 0xf;
248 reg = (reg & ~0xf0f) | index;
249 }
250 be_reg = cpu_to_be32(reg);
251
252 /* Write register */
253 xfer[0].addr = client->addr;
254 xfer[0].flags = 0;
255 xfer[0].len = 4;
256 xfer[0].buf = (u8 *)&be_reg;
257
258 /* Read data */
259 xfer[1].addr = client->addr;
260 xfer[1].flags = I2C_M_RD;
261 xfer[1].len = 4;
262 xfer[1].buf = (u8 *)&buf;
263
264 ret = i2c_transfer(client->adapter, xfer, 2);
265 if (ret < 0)
266 return ret;
267 else if (ret != 2)
268 return -EIO;
269
270 *value = be32_to_cpu(buf);
271
272 return 0;
273}
274
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200275#ifdef CONFIG_PM
Bard Liao07cf7cba2014-06-20 14:41:13 +0800276static void rt286_index_sync(struct snd_soc_codec *codec)
277{
278 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
279 int i;
280
281 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
282 snd_soc_write(codec, rt286->index_cache[i].reg,
283 rt286->index_cache[i].def);
284 }
285}
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200286#endif
Bard Liao07cf7cba2014-06-20 14:41:13 +0800287
288static int rt286_support_power_controls[] = {
289 RT286_DAC_OUT1,
290 RT286_DAC_OUT2,
291 RT286_ADC_IN1,
292 RT286_ADC_IN2,
293 RT286_MIC1,
294 RT286_DMIC1,
295 RT286_DMIC2,
296 RT286_SPK_OUT,
297 RT286_HP_OUT,
298};
299#define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
300
Bard Liao90f601e2014-07-29 13:50:57 +0800301static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
Bard Liao07cf7cba2014-06-20 14:41:13 +0800302{
Bard Liao07cf7cba2014-06-20 14:41:13 +0800303 unsigned int val, buf;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800304
305 *hp = false;
306 *mic = false;
307
308 if (rt286->pdata.cbj_en) {
Bard Liao90f601e2014-07-29 13:50:57 +0800309 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800310 *hp = buf & 0x80000000;
311 if (*hp) {
312 /* power on HV,VERF */
Bard Liao90f601e2014-07-29 13:50:57 +0800313 regmap_update_bits(rt286->regmap,
Bard Liao6879db72014-10-31 14:52:16 +0800314 RT286_DC_GAIN, 0x200, 0x200);
315
316 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
317 "HV");
318 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
319 "VREF");
Bard Liao07cf7cba2014-06-20 14:41:13 +0800320 /* power LDO1 */
Bard Liao6879db72014-10-31 14:52:16 +0800321 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
322 "LDO1");
323 snd_soc_dapm_sync(&rt286->codec->dapm);
324
Bard Liao90f601e2014-07-29 13:50:57 +0800325 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
Bard Liao6879db72014-10-31 14:52:16 +0800326 msleep(50);
327
328 regmap_update_bits(rt286->regmap,
329 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
330 msleep(300);
Bard Liao90f601e2014-07-29 13:50:57 +0800331 regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800332
Bard Liao6879db72014-10-31 14:52:16 +0800333 if (0x0070 == (val & 0x0070)) {
334 *mic = true;
335 } else {
336 regmap_update_bits(rt286->regmap,
337 RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
338 msleep(300);
Bard Liao90f601e2014-07-29 13:50:57 +0800339 regmap_read(rt286->regmap,
340 RT286_CBJ_CTRL2, &val);
Bard Liao6879db72014-10-31 14:52:16 +0800341 if (0x0070 == (val & 0x0070))
342 *mic = true;
343 else
344 *mic = false;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800345 }
Bard Liao90f601e2014-07-29 13:50:57 +0800346 regmap_update_bits(rt286->regmap,
Bard Liao6879db72014-10-31 14:52:16 +0800347 RT286_DC_GAIN, 0x200, 0x0);
348
Bard Liao07cf7cba2014-06-20 14:41:13 +0800349 } else {
Bard Liao07cf7cba2014-06-20 14:41:13 +0800350 *mic = false;
Bard Liao6879db72014-10-31 14:52:16 +0800351 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800352 }
353 } else {
Bard Liao90f601e2014-07-29 13:50:57 +0800354 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800355 *hp = buf & 0x80000000;
Bard Liao90f601e2014-07-29 13:50:57 +0800356 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800357 *mic = buf & 0x80000000;
358 }
359
Bard Liao6879db72014-10-31 14:52:16 +0800360 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "HV");
361 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "VREF");
362 if (!*hp)
363 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "LDO1");
364 snd_soc_dapm_sync(&rt286->codec->dapm);
365
Bard Liao07cf7cba2014-06-20 14:41:13 +0800366 return 0;
367}
368
369static void rt286_jack_detect_work(struct work_struct *work)
370{
371 struct rt286_priv *rt286 =
372 container_of(work, struct rt286_priv, jack_detect_work.work);
373 int status = 0;
374 bool hp = false;
375 bool mic = false;
376
Bard Liao90f601e2014-07-29 13:50:57 +0800377 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800378
379 if (hp == true)
380 status |= SND_JACK_HEADPHONE;
381
382 if (mic == true)
383 status |= SND_JACK_MICROPHONE;
384
385 snd_soc_jack_report(rt286->jack, status,
386 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
387}
388
389int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
390{
391 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
392
393 rt286->jack = jack;
394
395 /* Send an initial empty report */
396 snd_soc_jack_report(rt286->jack, 0,
397 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
398
399 return 0;
400}
401EXPORT_SYMBOL_GPL(rt286_mic_detect);
402
Bard Liao6879db72014-10-31 14:52:16 +0800403static int is_mclk_mode(struct snd_soc_dapm_widget *source,
404 struct snd_soc_dapm_widget *sink)
405{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100406 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
407 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
Bard Liao6879db72014-10-31 14:52:16 +0800408
409 if (rt286->clk_id == RT286_SCLK_S_MCLK)
410 return 1;
411 else
412 return 0;
413}
414
Bard Liao07cf7cba2014-06-20 14:41:13 +0800415static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
416static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
417
418static const struct snd_kcontrol_new rt286_snd_controls[] = {
419 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
420 RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
421 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
422 RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
423 SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
424 0, 0x3, 0, mic_vol_tlv),
425 SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
426 RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
427};
428
429/* Digital Mixer */
430static const struct snd_kcontrol_new rt286_front_mix[] = {
431 SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
432 RT286_MUTE_SFT, 1, 1),
433 SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
434 RT286_MUTE_SFT, 1, 1),
435};
436
437/* Analog Input Mixer */
438static const struct snd_kcontrol_new rt286_rec_mix[] = {
439 SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
440 RT286_MUTE_SFT, 1, 1),
441 SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
442 RT286_MUTE_SFT, 1, 1),
443 SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
444 RT286_MUTE_SFT, 1, 1),
445 SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
446 RT286_MUTE_SFT, 1, 1),
447};
448
449static const struct snd_kcontrol_new spo_enable_control =
450 SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
451 RT286_SET_PIN_SFT, 1, 0);
452
453static const struct snd_kcontrol_new hpol_enable_control =
454 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
455 RT286_MUTE_SFT, 1, 1);
456
457static const struct snd_kcontrol_new hpor_enable_control =
458 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
459 RT286_MUTE_SFT, 1, 1);
460
461/* ADC0 source */
462static const char * const rt286_adc_src[] = {
463 "Mic", "RECMIX", "Dmic"
464};
465
466static const int rt286_adc_values[] = {
467 0, 4, 5,
468};
469
470static SOC_VALUE_ENUM_SINGLE_DECL(
471 rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
472 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
473
474static const struct snd_kcontrol_new rt286_adc0_mux =
475 SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
476
477static SOC_VALUE_ENUM_SINGLE_DECL(
478 rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
479 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
480
481static const struct snd_kcontrol_new rt286_adc1_mux =
482 SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
483
484static const char * const rt286_dac_src[] = {
485 "Front", "Surround"
486};
487/* HP-OUT source */
488static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
489 0, rt286_dac_src);
490
491static const struct snd_kcontrol_new rt286_hpo_mux =
492SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
493
494/* SPK-OUT source */
495static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
496 0, rt286_dac_src);
497
498static const struct snd_kcontrol_new rt286_spo_mux =
499SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
500
501static int rt286_spk_event(struct snd_soc_dapm_widget *w,
502 struct snd_kcontrol *kcontrol, int event)
503{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100504 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800505
506 switch (event) {
507 case SND_SOC_DAPM_POST_PMU:
508 snd_soc_write(codec,
509 RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
510 break;
511 case SND_SOC_DAPM_PRE_PMD:
512 snd_soc_write(codec,
513 RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
514 break;
515
516 default:
517 return 0;
518 }
519
520 return 0;
521}
522
523static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
524 struct snd_kcontrol *kcontrol, int event)
525{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100526 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800527
528 switch (event) {
529 case SND_SOC_DAPM_POST_PMU:
530 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
531 break;
532 case SND_SOC_DAPM_PRE_PMD:
533 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
534 break;
535 default:
536 return 0;
537 }
538
539 return 0;
540}
541
542static int rt286_adc_event(struct snd_soc_dapm_widget *w,
543 struct snd_kcontrol *kcontrol, int event)
544{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100545 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800546 unsigned int nid;
547
548 nid = (w->reg >> 20) & 0xff;
549
550 switch (event) {
551 case SND_SOC_DAPM_POST_PMU:
552 snd_soc_update_bits(codec,
553 VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
554 0x7080, 0x7000);
555 break;
556 case SND_SOC_DAPM_PRE_PMD:
557 snd_soc_update_bits(codec,
558 VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
559 0x7080, 0x7080);
560 break;
561 default:
562 return 0;
563 }
564
565 return 0;
566}
567
Bard Liao6879db72014-10-31 14:52:16 +0800568static int rt286_vref_event(struct snd_soc_dapm_widget *w,
569 struct snd_kcontrol *kcontrol, int event)
570{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100571 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Bard Liao6879db72014-10-31 14:52:16 +0800572
573 switch (event) {
574 case SND_SOC_DAPM_PRE_PMU:
575 snd_soc_update_bits(codec,
576 RT286_CBJ_CTRL1, 0x0400, 0x0000);
577 mdelay(50);
578 break;
579 default:
580 return 0;
581 }
582
583 return 0;
584}
585
586static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
587 struct snd_kcontrol *kcontrol, int event)
588{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100589 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Bard Liao6879db72014-10-31 14:52:16 +0800590
591 switch (event) {
592 case SND_SOC_DAPM_POST_PMU:
593 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
594 break;
595 case SND_SOC_DAPM_PRE_PMD:
596 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
597 break;
598 default:
599 return 0;
600 }
601
602 return 0;
603}
604
605static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
606 struct snd_kcontrol *kcontrol, int event)
607{
Lars-Peter Clausen76f17f12015-01-15 12:52:10 +0100608 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Bard Liao6879db72014-10-31 14:52:16 +0800609
610 switch (event) {
611 case SND_SOC_DAPM_PRE_PMU:
612 snd_soc_update_bits(codec,
613 RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
614 snd_soc_update_bits(codec,
615 RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
616 break;
617 case SND_SOC_DAPM_POST_PMD:
618 snd_soc_update_bits(codec,
619 RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
620 snd_soc_update_bits(codec,
621 RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
622 break;
623 default:
624 return 0;
625 }
626
627 return 0;
628}
629
Bard Liao07cf7cba2014-06-20 14:41:13 +0800630static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
Bard Liao6879db72014-10-31 14:52:16 +0800631 SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
632 12, 1, NULL, 0),
633 SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
634 0, 1, rt286_vref_event, SND_SOC_DAPM_PRE_PMU),
635 SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
636 2, 0, NULL, 0),
637 SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
638 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
639 SND_SOC_DAPM_POST_PMU),
640 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
641 5, 0, NULL, 0),
642 SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
643 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
644 SND_SOC_DAPM_POST_PMD),
645
Bard Liao07cf7cba2014-06-20 14:41:13 +0800646 /* Input Lines */
647 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
648 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
649 SND_SOC_DAPM_INPUT("MIC1"),
650 SND_SOC_DAPM_INPUT("LINE1"),
651 SND_SOC_DAPM_INPUT("Beep"),
652
653 /* DMIC */
654 SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
655 NULL, 0, rt286_set_dmic1_event,
656 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
657 SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
658 NULL, 0),
659 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
660 0, 0, NULL, 0),
661
662 /* REC Mixer */
663 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
664 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
665
666 /* ADCs */
667 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
668 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
669
670 /* ADC Mux */
671 SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
672 &rt286_adc0_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD |
673 SND_SOC_DAPM_POST_PMU),
674 SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
675 &rt286_adc1_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD |
676 SND_SOC_DAPM_POST_PMU),
677
678 /* Audio Interface */
679 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
680 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
681 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
682 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
683
684 /* Output Side */
685 /* DACs */
686 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
687 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
688
689 /* Output Mux */
690 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
691 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
692
693 SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
694 RT286_SET_PIN_SFT, 0, NULL, 0),
695
696 /* Output Mixer */
697 SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
698 rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
699 SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
700 NULL, 0),
701
702 /* Output Pga */
703 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
704 &spo_enable_control, rt286_spk_event,
705 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
706 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
707 &hpol_enable_control),
708 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
709 &hpor_enable_control),
710
711 /* Output Lines */
712 SND_SOC_DAPM_OUTPUT("SPOL"),
713 SND_SOC_DAPM_OUTPUT("SPOR"),
714 SND_SOC_DAPM_OUTPUT("HPO Pin"),
715 SND_SOC_DAPM_OUTPUT("SPDIF"),
716};
717
718static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
Bard Liao6879db72014-10-31 14:52:16 +0800719 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
720 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
721 {"Front", NULL, "MCLK MODE", is_mclk_mode},
722 {"Surround", NULL, "MCLK MODE", is_mclk_mode},
723
724 {"HP Power", NULL, "LDO1"},
725 {"HP Power", NULL, "LDO2"},
726
727 {"MIC1", NULL, "LDO1"},
728 {"MIC1", NULL, "LDO2"},
729 {"MIC1", NULL, "HV"},
730 {"MIC1", NULL, "VREF"},
731 {"MIC1", NULL, "MIC1 Input Buffer"},
732
733 {"SPO", NULL, "LDO1"},
734 {"SPO", NULL, "LDO2"},
735 {"SPO", NULL, "HV"},
736 {"SPO", NULL, "VREF"},
737
Bard Liao07cf7cba2014-06-20 14:41:13 +0800738 {"DMIC1", NULL, "DMIC1 Pin"},
739 {"DMIC2", NULL, "DMIC2 Pin"},
740 {"DMIC1", NULL, "DMIC Receiver"},
741 {"DMIC2", NULL, "DMIC Receiver"},
742
743 {"RECMIX", "Beep Switch", "Beep"},
744 {"RECMIX", "Line1 Switch", "LINE1"},
745 {"RECMIX", "Mic1 Switch", "MIC1"},
746
747 {"ADC 0 Mux", "Dmic", "DMIC1"},
748 {"ADC 0 Mux", "RECMIX", "RECMIX"},
749 {"ADC 0 Mux", "Mic", "MIC1"},
750 {"ADC 1 Mux", "Dmic", "DMIC2"},
751 {"ADC 1 Mux", "RECMIX", "RECMIX"},
752 {"ADC 1 Mux", "Mic", "MIC1"},
753
754 {"ADC 0", NULL, "ADC 0 Mux"},
755 {"ADC 1", NULL, "ADC 1 Mux"},
756
757 {"AIF1TX", NULL, "ADC 0"},
758 {"AIF2TX", NULL, "ADC 1"},
759
760 {"DAC 0", NULL, "AIF1RX"},
761 {"DAC 1", NULL, "AIF2RX"},
762
763 {"Front", "DAC Switch", "DAC 0"},
764 {"Front", "RECMIX Switch", "RECMIX"},
765
766 {"Surround", NULL, "DAC 1"},
767
768 {"SPK Mux", "Front", "Front"},
769 {"SPK Mux", "Surround", "Surround"},
770
771 {"HPO Mux", "Front", "Front"},
772 {"HPO Mux", "Surround", "Surround"},
773
774 {"SPO", "Switch", "SPK Mux"},
775 {"HPO L", "Switch", "HPO Mux"},
776 {"HPO R", "Switch", "HPO Mux"},
777 {"HPO L", NULL, "HP Power"},
778 {"HPO R", NULL, "HP Power"},
779
780 {"SPOL", NULL, "SPO"},
781 {"SPOR", NULL, "SPO"},
782 {"HPO Pin", NULL, "HPO L"},
783 {"HPO Pin", NULL, "HPO R"},
784};
785
786static int rt286_hw_params(struct snd_pcm_substream *substream,
787 struct snd_pcm_hw_params *params,
788 struct snd_soc_dai *dai)
789{
790 struct snd_soc_codec *codec = dai->codec;
791 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
792 unsigned int val = 0;
793 int d_len_code;
794
795 switch (params_rate(params)) {
796 /* bit 14 0:48K 1:44.1K */
797 case 44100:
798 val |= 0x4000;
799 break;
800 case 48000:
801 break;
802 default:
803 dev_err(codec->dev, "Unsupported sample rate %d\n",
804 params_rate(params));
805 return -EINVAL;
806 }
807 switch (rt286->sys_clk) {
808 case 12288000:
809 case 24576000:
810 if (params_rate(params) != 48000) {
811 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
812 params_rate(params), rt286->sys_clk);
813 return -EINVAL;
814 }
815 break;
816 case 11289600:
817 case 22579200:
818 if (params_rate(params) != 44100) {
819 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
820 params_rate(params), rt286->sys_clk);
821 return -EINVAL;
822 }
823 break;
824 }
825
826 if (params_channels(params) <= 16) {
827 /* bit 3:0 Number of Channel */
828 val |= (params_channels(params) - 1);
829 } else {
830 dev_err(codec->dev, "Unsupported channels %d\n",
831 params_channels(params));
832 return -EINVAL;
833 }
834
835 d_len_code = 0;
836 switch (params_width(params)) {
837 /* bit 6:4 Bits per Sample */
838 case 16:
839 d_len_code = 0;
840 val |= (0x1 << 4);
841 break;
842 case 32:
843 d_len_code = 2;
844 val |= (0x4 << 4);
845 break;
846 case 20:
847 d_len_code = 1;
848 val |= (0x2 << 4);
849 break;
850 case 24:
851 d_len_code = 2;
852 val |= (0x3 << 4);
853 break;
854 case 8:
855 d_len_code = 3;
856 break;
857 default:
858 return -EINVAL;
859 }
860
861 snd_soc_update_bits(codec,
862 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
863 dev_dbg(codec->dev, "format val = 0x%x\n", val);
864
865 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
866 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
867 else
868 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
869
870 return 0;
871}
872
873static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
874{
875 struct snd_soc_codec *codec = dai->codec;
876
877 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
878 case SND_SOC_DAIFMT_CBM_CFM:
879 snd_soc_update_bits(codec,
880 RT286_I2S_CTRL1, 0x800, 0x800);
881 break;
882 case SND_SOC_DAIFMT_CBS_CFS:
883 snd_soc_update_bits(codec,
884 RT286_I2S_CTRL1, 0x800, 0x0);
885 break;
886 default:
887 return -EINVAL;
888 }
889
890 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
891 case SND_SOC_DAIFMT_I2S:
892 snd_soc_update_bits(codec,
893 RT286_I2S_CTRL1, 0x300, 0x0);
894 break;
895 case SND_SOC_DAIFMT_LEFT_J:
896 snd_soc_update_bits(codec,
897 RT286_I2S_CTRL1, 0x300, 0x1 << 8);
898 break;
899 case SND_SOC_DAIFMT_DSP_A:
900 snd_soc_update_bits(codec,
901 RT286_I2S_CTRL1, 0x300, 0x2 << 8);
902 break;
903 case SND_SOC_DAIFMT_DSP_B:
904 snd_soc_update_bits(codec,
905 RT286_I2S_CTRL1, 0x300, 0x3 << 8);
906 break;
907 default:
908 return -EINVAL;
909 }
910 /* bit 15 Stream Type 0:PCM 1:Non-PCM */
911 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
912 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
913
914 return 0;
915}
916
917static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
918 int clk_id, unsigned int freq, int dir)
919{
920 struct snd_soc_codec *codec = dai->codec;
921 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
922
923 dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
924
925 if (RT286_SCLK_S_MCLK == clk_id) {
926 snd_soc_update_bits(codec,
927 RT286_I2S_CTRL2, 0x0100, 0x0);
928 snd_soc_update_bits(codec,
929 RT286_PLL_CTRL1, 0x20, 0x20);
930 } else {
931 snd_soc_update_bits(codec,
932 RT286_I2S_CTRL2, 0x0100, 0x0100);
933 snd_soc_update_bits(codec,
934 RT286_PLL_CTRL, 0x4, 0x4);
935 snd_soc_update_bits(codec,
936 RT286_PLL_CTRL1, 0x20, 0x0);
937 }
938
939 switch (freq) {
940 case 19200000:
941 if (RT286_SCLK_S_MCLK == clk_id) {
942 dev_err(codec->dev, "Should not use MCLK\n");
943 return -EINVAL;
944 }
945 snd_soc_update_bits(codec,
946 RT286_I2S_CTRL2, 0x40, 0x40);
947 break;
948 case 24000000:
949 if (RT286_SCLK_S_MCLK == clk_id) {
950 dev_err(codec->dev, "Should not use MCLK\n");
951 return -EINVAL;
952 }
953 snd_soc_update_bits(codec,
954 RT286_I2S_CTRL2, 0x40, 0x0);
955 break;
956 case 12288000:
957 case 11289600:
958 snd_soc_update_bits(codec,
959 RT286_I2S_CTRL2, 0x8, 0x0);
960 snd_soc_update_bits(codec,
961 RT286_CLK_DIV, 0xfc1e, 0x0004);
962 break;
963 case 24576000:
964 case 22579200:
965 snd_soc_update_bits(codec,
966 RT286_I2S_CTRL2, 0x8, 0x8);
967 snd_soc_update_bits(codec,
968 RT286_CLK_DIV, 0xfc1e, 0x5406);
969 break;
970 default:
971 dev_err(codec->dev, "Unsupported system clock\n");
972 return -EINVAL;
973 }
974
975 rt286->sys_clk = freq;
Bard Liao6879db72014-10-31 14:52:16 +0800976 rt286->clk_id = clk_id;
Bard Liao07cf7cba2014-06-20 14:41:13 +0800977
978 return 0;
979}
980
981static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
982{
983 struct snd_soc_codec *codec = dai->codec;
984
985 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
986 if (50 == ratio)
987 snd_soc_update_bits(codec,
988 RT286_I2S_CTRL1, 0x1000, 0x1000);
989 else
990 snd_soc_update_bits(codec,
991 RT286_I2S_CTRL1, 0x1000, 0x0);
992
993
994 return 0;
995}
996
997static int rt286_set_bias_level(struct snd_soc_codec *codec,
998 enum snd_soc_bias_level level)
999{
1000 switch (level) {
1001 case SND_SOC_BIAS_PREPARE:
Bard Liaobc6c4e42014-07-07 19:15:30 +08001002 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
Bard Liao07cf7cba2014-06-20 14:41:13 +08001003 snd_soc_write(codec,
1004 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
Bard Liaobc6c4e42014-07-07 19:15:30 +08001005 snd_soc_update_bits(codec,
1006 RT286_DC_GAIN, 0x200, 0x200);
1007 }
1008 break;
1009
1010 case SND_SOC_BIAS_ON:
1011 mdelay(10);
Bard Liao6879db72014-10-31 14:52:16 +08001012 snd_soc_update_bits(codec,
1013 RT286_CBJ_CTRL1, 0x0400, 0x0400);
1014 snd_soc_update_bits(codec,
1015 RT286_DC_GAIN, 0x200, 0x0);
1016
Bard Liao07cf7cba2014-06-20 14:41:13 +08001017 break;
1018
1019 case SND_SOC_BIAS_STANDBY:
1020 snd_soc_write(codec,
1021 RT286_SET_AUDIO_POWER, AC_PWRST_D3);
Bard Liaobc6c4e42014-07-07 19:15:30 +08001022 snd_soc_update_bits(codec,
Bard Liao6879db72014-10-31 14:52:16 +08001023 RT286_CBJ_CTRL1, 0x0400, 0x0000);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001024 break;
1025
1026 default:
1027 break;
1028 }
1029 codec->dapm.bias_level = level;
1030
1031 return 0;
1032}
1033
1034static irqreturn_t rt286_irq(int irq, void *data)
1035{
1036 struct rt286_priv *rt286 = data;
1037 bool hp = false;
1038 bool mic = false;
1039 int status = 0;
1040
Bard Liao90f601e2014-07-29 13:50:57 +08001041 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001042
1043 /* Clear IRQ */
Bard Liao90f601e2014-07-29 13:50:57 +08001044 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001045
1046 if (hp == true)
1047 status |= SND_JACK_HEADPHONE;
1048
1049 if (mic == true)
1050 status |= SND_JACK_MICROPHONE;
1051
1052 snd_soc_jack_report(rt286->jack, status,
1053 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
1054
1055 pm_wakeup_event(&rt286->i2c->dev, 300);
1056
1057 return IRQ_HANDLED;
1058}
1059
1060static int rt286_probe(struct snd_soc_codec *codec)
1061{
1062 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
Bard Liao07cf7cba2014-06-20 14:41:13 +08001063
Bard Liao6879db72014-10-31 14:52:16 +08001064 rt286->codec = codec;
Bard Liao07cf7cba2014-06-20 14:41:13 +08001065 codec->dapm.bias_level = SND_SOC_BIAS_OFF;
Bard Liao90f601e2014-07-29 13:50:57 +08001066
1067 if (rt286->i2c->irq) {
1068 regmap_update_bits(rt286->regmap,
1069 RT286_IRQ_CTRL, 0x2, 0x2);
1070
1071 INIT_DELAYED_WORK(&rt286->jack_detect_work,
1072 rt286_jack_detect_work);
1073 schedule_delayed_work(&rt286->jack_detect_work,
1074 msecs_to_jiffies(1250));
1075 }
Bard Liao07cf7cba2014-06-20 14:41:13 +08001076
Bard Liao07cf7cba2014-06-20 14:41:13 +08001077 return 0;
1078}
1079
1080static int rt286_remove(struct snd_soc_codec *codec)
1081{
1082 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1083
1084 cancel_delayed_work_sync(&rt286->jack_detect_work);
1085
1086 return 0;
1087}
1088
1089#ifdef CONFIG_PM
1090static int rt286_suspend(struct snd_soc_codec *codec)
1091{
1092 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1093
1094 regcache_cache_only(rt286->regmap, true);
1095 regcache_mark_dirty(rt286->regmap);
1096
1097 return 0;
1098}
1099
1100static int rt286_resume(struct snd_soc_codec *codec)
1101{
1102 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1103
1104 regcache_cache_only(rt286->regmap, false);
1105 rt286_index_sync(codec);
1106 regcache_sync(rt286->regmap);
1107
1108 return 0;
1109}
1110#else
1111#define rt286_suspend NULL
1112#define rt286_resume NULL
1113#endif
1114
1115#define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1116#define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1117 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1118
1119static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
1120 .hw_params = rt286_hw_params,
1121 .set_fmt = rt286_set_dai_fmt,
1122 .set_sysclk = rt286_set_dai_sysclk,
1123 .set_bclk_ratio = rt286_set_bclk_ratio,
1124};
1125
1126static struct snd_soc_dai_driver rt286_dai[] = {
1127 {
1128 .name = "rt286-aif1",
1129 .id = RT286_AIF1,
1130 .playback = {
1131 .stream_name = "AIF1 Playback",
1132 .channels_min = 1,
1133 .channels_max = 2,
1134 .rates = RT286_STEREO_RATES,
1135 .formats = RT286_FORMATS,
1136 },
1137 .capture = {
1138 .stream_name = "AIF1 Capture",
1139 .channels_min = 1,
1140 .channels_max = 2,
1141 .rates = RT286_STEREO_RATES,
1142 .formats = RT286_FORMATS,
1143 },
1144 .ops = &rt286_aif_dai_ops,
1145 .symmetric_rates = 1,
1146 },
1147 {
1148 .name = "rt286-aif2",
1149 .id = RT286_AIF2,
1150 .playback = {
1151 .stream_name = "AIF2 Playback",
1152 .channels_min = 1,
1153 .channels_max = 2,
1154 .rates = RT286_STEREO_RATES,
1155 .formats = RT286_FORMATS,
1156 },
1157 .capture = {
1158 .stream_name = "AIF2 Capture",
1159 .channels_min = 1,
1160 .channels_max = 2,
1161 .rates = RT286_STEREO_RATES,
1162 .formats = RT286_FORMATS,
1163 },
1164 .ops = &rt286_aif_dai_ops,
1165 .symmetric_rates = 1,
1166 },
1167
1168};
1169
1170static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1171 .probe = rt286_probe,
1172 .remove = rt286_remove,
1173 .suspend = rt286_suspend,
1174 .resume = rt286_resume,
1175 .set_bias_level = rt286_set_bias_level,
1176 .idle_bias_off = true,
1177 .controls = rt286_snd_controls,
1178 .num_controls = ARRAY_SIZE(rt286_snd_controls),
1179 .dapm_widgets = rt286_dapm_widgets,
1180 .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1181 .dapm_routes = rt286_dapm_routes,
1182 .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1183};
1184
1185static const struct regmap_config rt286_regmap = {
1186 .reg_bits = 32,
1187 .val_bits = 32,
1188 .max_register = 0x02370100,
1189 .volatile_reg = rt286_volatile_register,
1190 .readable_reg = rt286_readable_register,
1191 .reg_write = rt286_hw_write,
1192 .reg_read = rt286_hw_read,
1193 .cache_type = REGCACHE_RBTREE,
1194 .reg_defaults = rt286_reg,
1195 .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1196};
1197
1198static const struct i2c_device_id rt286_i2c_id[] = {
1199 {"rt286", 0},
1200 {}
1201};
1202MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1203
1204static const struct acpi_device_id rt286_acpi_match[] = {
1205 { "INT343A", 0 },
1206 {},
1207};
1208MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1209
Sudip Mukherjeea5a267c2014-11-18 17:42:54 +05301210static struct dmi_system_id force_combo_jack_table[] = {
Bard Liao6c67cde2014-11-06 09:59:59 +08001211 {
1212 .ident = "Intel Wilson Beach",
1213 .matches = {
1214 DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1215 }
1216 },
1217 { }
1218};
1219
Bard Liao07cf7cba2014-06-20 14:41:13 +08001220static int rt286_i2c_probe(struct i2c_client *i2c,
1221 const struct i2c_device_id *id)
1222{
1223 struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1224 struct rt286_priv *rt286;
Bard Liao61a414c2014-07-07 16:48:38 +08001225 int i, ret;
Bard Liao07cf7cba2014-06-20 14:41:13 +08001226
1227 rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1228 GFP_KERNEL);
1229 if (NULL == rt286)
1230 return -ENOMEM;
1231
1232 rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1233 if (IS_ERR(rt286->regmap)) {
1234 ret = PTR_ERR(rt286->regmap);
1235 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1236 ret);
1237 return ret;
1238 }
1239
Bard Liao4b21768a2014-07-07 16:48:37 +08001240 regmap_read(rt286->regmap,
1241 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret);
1242 if (ret != RT286_VENDOR_ID) {
1243 dev_err(&i2c->dev,
1244 "Device with ID register %x is not rt286\n", ret);
1245 return -ENODEV;
1246 }
1247
Bard Liao07cf7cba2014-06-20 14:41:13 +08001248 rt286->index_cache = rt286_index_def;
1249 rt286->i2c = i2c;
1250 i2c_set_clientdata(i2c, rt286);
1251
1252 if (pdata)
1253 rt286->pdata = *pdata;
1254
Bard Liao6c67cde2014-11-06 09:59:59 +08001255 if (dmi_check_system(force_combo_jack_table))
1256 rt286->pdata.cbj_en = true;
1257
Bard Liao61a414c2014-07-07 16:48:38 +08001258 regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1259
1260 for (i = 0; i < RT286_POWER_REG_LEN; i++)
1261 regmap_write(rt286->regmap,
1262 RT286_SET_POWER(rt286_support_power_controls[i]),
1263 AC_PWRST_D1);
1264
1265 if (!rt286->pdata.cbj_en) {
1266 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1267 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
Bard Liao61a414c2014-07-07 16:48:38 +08001268 regmap_update_bits(rt286->regmap,
1269 RT286_CBJ_CTRL1, 0xf000, 0xb000);
1270 } else {
1271 regmap_update_bits(rt286->regmap,
1272 RT286_CBJ_CTRL1, 0xf000, 0x5000);
1273 }
1274
1275 mdelay(10);
1276
1277 if (!rt286->pdata.gpio2_en)
1278 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1279 else
1280 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1281
1282 mdelay(10);
1283
Bard Liao6879db72014-10-31 14:52:16 +08001284 regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
Bard Liaof8c101b2014-11-06 10:00:00 +08001285 /* Power down LDO, VREF */
Bard Liao6879db72014-10-31 14:52:16 +08001286 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1287 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
Bard Liao61a414c2014-07-07 16:48:38 +08001288
Bard Liaof8c101b2014-11-06 10:00:00 +08001289 /* Set depop parameter */
Bard Liaobc6c4e42014-07-07 19:15:30 +08001290 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1291 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1292 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1293
Bard Liao61a414c2014-07-07 16:48:38 +08001294 if (rt286->i2c->irq) {
Bard Liao61a414c2014-07-07 16:48:38 +08001295 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1296 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1297 if (ret != 0) {
1298 dev_err(&i2c->dev,
1299 "Failed to reguest IRQ: %d\n", ret);
1300 return ret;
1301 }
1302 }
1303
Bard Liao07cf7cba2014-06-20 14:41:13 +08001304 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1305 rt286_dai, ARRAY_SIZE(rt286_dai));
1306
1307 return ret;
1308}
1309
1310static int rt286_i2c_remove(struct i2c_client *i2c)
1311{
1312 struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1313
1314 if (i2c->irq)
1315 free_irq(i2c->irq, rt286);
1316 snd_soc_unregister_codec(&i2c->dev);
1317
1318 return 0;
1319}
1320
1321
Bard Liao23c4fd52014-07-14 10:18:04 +08001322static struct i2c_driver rt286_i2c_driver = {
Bard Liao07cf7cba2014-06-20 14:41:13 +08001323 .driver = {
1324 .name = "rt286",
1325 .owner = THIS_MODULE,
1326 .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1327 },
1328 .probe = rt286_i2c_probe,
1329 .remove = rt286_i2c_remove,
1330 .id_table = rt286_i2c_id,
1331};
1332
1333module_i2c_driver(rt286_i2c_driver);
1334
1335MODULE_DESCRIPTION("ASoC RT286 driver");
1336MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1337MODULE_LICENSE("GPL");