Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/fs.h> |
| 19 | #include <linux/file.h> |
| 20 | #include <linux/sync.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/debugfs.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/dma-mapping.h> |
| 25 | #include <linux/dma-buf.h> |
| 26 | #include <linux/msm_ion.h> |
Alan Kwong | 315cd77 | 2016-08-03 22:29:42 -0400 | [diff] [blame] | 27 | #include <linux/clk/msm-clk.h> |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 28 | |
| 29 | #include "sde_rotator_core.h" |
| 30 | #include "sde_rotator_util.h" |
| 31 | #include "sde_rotator_smmu.h" |
| 32 | #include "sde_rotator_r3.h" |
| 33 | #include "sde_rotator_r3_internal.h" |
| 34 | #include "sde_rotator_r3_hwio.h" |
| 35 | #include "sde_rotator_r3_debug.h" |
| 36 | #include "sde_rotator_trace.h" |
Benjamin Chan | 53e3bce | 2016-08-31 14:43:29 -0400 | [diff] [blame] | 37 | #include "sde_rotator_debug.h" |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 38 | |
| 39 | /* XIN mapping */ |
| 40 | #define XIN_SSPP 0 |
| 41 | #define XIN_WRITEBACK 1 |
| 42 | |
| 43 | /* wait for at most 2 vsync for lowest refresh rate (24hz) */ |
| 44 | #define KOFF_TIMEOUT msecs_to_jiffies(42 * 32) |
| 45 | |
| 46 | /* Macro for constructing the REGDMA command */ |
| 47 | #define SDE_REGDMA_WRITE(p, off, data) \ |
| 48 | do { \ |
| 49 | *p++ = REGDMA_OP_REGWRITE | \ |
| 50 | ((off) & REGDMA_ADDR_OFFSET_MASK); \ |
| 51 | *p++ = (data); \ |
| 52 | } while (0) |
| 53 | |
| 54 | #define SDE_REGDMA_MODIFY(p, off, mask, data) \ |
| 55 | do { \ |
| 56 | *p++ = REGDMA_OP_REGMODIFY | \ |
| 57 | ((off) & REGDMA_ADDR_OFFSET_MASK); \ |
| 58 | *p++ = (mask); \ |
| 59 | *p++ = (data); \ |
| 60 | } while (0) |
| 61 | |
| 62 | #define SDE_REGDMA_BLKWRITE_INC(p, off, len) \ |
| 63 | do { \ |
| 64 | *p++ = REGDMA_OP_BLKWRITE_INC | \ |
| 65 | ((off) & REGDMA_ADDR_OFFSET_MASK); \ |
| 66 | *p++ = (len); \ |
| 67 | } while (0) |
| 68 | |
| 69 | #define SDE_REGDMA_BLKWRITE_DATA(p, data) \ |
| 70 | do { \ |
| 71 | *(p) = (data); \ |
| 72 | (p)++; \ |
| 73 | } while (0) |
| 74 | |
| 75 | /* Macro for directly accessing mapped registers */ |
| 76 | #define SDE_ROTREG_WRITE(base, off, data) \ |
| 77 | writel_relaxed(data, (base + (off))) |
| 78 | |
| 79 | #define SDE_ROTREG_READ(base, off) \ |
| 80 | readl_relaxed(base + (off)) |
| 81 | |
Alan Kwong | da16e44 | 2016-08-14 20:47:18 -0400 | [diff] [blame] | 82 | static u32 sde_hw_rotator_input_pixfmts[] = { |
| 83 | SDE_PIX_FMT_XRGB_8888, |
| 84 | SDE_PIX_FMT_ARGB_8888, |
| 85 | SDE_PIX_FMT_ABGR_8888, |
| 86 | SDE_PIX_FMT_RGBA_8888, |
| 87 | SDE_PIX_FMT_BGRA_8888, |
| 88 | SDE_PIX_FMT_RGBX_8888, |
| 89 | SDE_PIX_FMT_BGRX_8888, |
| 90 | SDE_PIX_FMT_XBGR_8888, |
| 91 | SDE_PIX_FMT_RGBA_5551, |
| 92 | SDE_PIX_FMT_ARGB_1555, |
| 93 | SDE_PIX_FMT_ABGR_1555, |
| 94 | SDE_PIX_FMT_BGRA_5551, |
| 95 | SDE_PIX_FMT_BGRX_5551, |
| 96 | SDE_PIX_FMT_RGBX_5551, |
| 97 | SDE_PIX_FMT_XBGR_1555, |
| 98 | SDE_PIX_FMT_XRGB_1555, |
| 99 | SDE_PIX_FMT_ARGB_4444, |
| 100 | SDE_PIX_FMT_RGBA_4444, |
| 101 | SDE_PIX_FMT_BGRA_4444, |
| 102 | SDE_PIX_FMT_ABGR_4444, |
| 103 | SDE_PIX_FMT_RGBX_4444, |
| 104 | SDE_PIX_FMT_XRGB_4444, |
| 105 | SDE_PIX_FMT_BGRX_4444, |
| 106 | SDE_PIX_FMT_XBGR_4444, |
| 107 | SDE_PIX_FMT_RGB_888, |
| 108 | SDE_PIX_FMT_BGR_888, |
| 109 | SDE_PIX_FMT_RGB_565, |
| 110 | SDE_PIX_FMT_BGR_565, |
| 111 | SDE_PIX_FMT_Y_CB_CR_H2V2, |
| 112 | SDE_PIX_FMT_Y_CR_CB_H2V2, |
| 113 | SDE_PIX_FMT_Y_CR_CB_GH2V2, |
| 114 | SDE_PIX_FMT_Y_CBCR_H2V2, |
| 115 | SDE_PIX_FMT_Y_CRCB_H2V2, |
| 116 | SDE_PIX_FMT_Y_CBCR_H1V2, |
| 117 | SDE_PIX_FMT_Y_CRCB_H1V2, |
| 118 | SDE_PIX_FMT_Y_CBCR_H2V1, |
| 119 | SDE_PIX_FMT_Y_CRCB_H2V1, |
| 120 | SDE_PIX_FMT_YCBYCR_H2V1, |
| 121 | SDE_PIX_FMT_Y_CBCR_H2V2_VENUS, |
| 122 | SDE_PIX_FMT_Y_CRCB_H2V2_VENUS, |
| 123 | SDE_PIX_FMT_RGBA_8888_UBWC, |
| 124 | SDE_PIX_FMT_RGBX_8888_UBWC, |
| 125 | SDE_PIX_FMT_RGB_565_UBWC, |
| 126 | SDE_PIX_FMT_Y_CBCR_H2V2_UBWC, |
| 127 | SDE_PIX_FMT_RGBA_1010102, |
| 128 | SDE_PIX_FMT_RGBX_1010102, |
| 129 | SDE_PIX_FMT_ARGB_2101010, |
| 130 | SDE_PIX_FMT_XRGB_2101010, |
| 131 | SDE_PIX_FMT_BGRA_1010102, |
| 132 | SDE_PIX_FMT_BGRX_1010102, |
| 133 | SDE_PIX_FMT_ABGR_2101010, |
| 134 | SDE_PIX_FMT_XBGR_2101010, |
| 135 | SDE_PIX_FMT_RGBA_1010102_UBWC, |
| 136 | SDE_PIX_FMT_RGBX_1010102_UBWC, |
| 137 | SDE_PIX_FMT_Y_CBCR_H2V2_P010, |
| 138 | SDE_PIX_FMT_Y_CBCR_H2V2_TP10, |
| 139 | SDE_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC, |
| 140 | }; |
| 141 | |
| 142 | static u32 sde_hw_rotator_output_pixfmts[] = { |
| 143 | SDE_PIX_FMT_XRGB_8888, |
| 144 | SDE_PIX_FMT_ARGB_8888, |
| 145 | SDE_PIX_FMT_ABGR_8888, |
| 146 | SDE_PIX_FMT_RGBA_8888, |
| 147 | SDE_PIX_FMT_BGRA_8888, |
| 148 | SDE_PIX_FMT_RGBX_8888, |
| 149 | SDE_PIX_FMT_BGRX_8888, |
| 150 | SDE_PIX_FMT_XBGR_8888, |
| 151 | SDE_PIX_FMT_RGBA_5551, |
| 152 | SDE_PIX_FMT_ARGB_1555, |
| 153 | SDE_PIX_FMT_ABGR_1555, |
| 154 | SDE_PIX_FMT_BGRA_5551, |
| 155 | SDE_PIX_FMT_BGRX_5551, |
| 156 | SDE_PIX_FMT_RGBX_5551, |
| 157 | SDE_PIX_FMT_XBGR_1555, |
| 158 | SDE_PIX_FMT_XRGB_1555, |
| 159 | SDE_PIX_FMT_ARGB_4444, |
| 160 | SDE_PIX_FMT_RGBA_4444, |
| 161 | SDE_PIX_FMT_BGRA_4444, |
| 162 | SDE_PIX_FMT_ABGR_4444, |
| 163 | SDE_PIX_FMT_RGBX_4444, |
| 164 | SDE_PIX_FMT_XRGB_4444, |
| 165 | SDE_PIX_FMT_BGRX_4444, |
| 166 | SDE_PIX_FMT_XBGR_4444, |
| 167 | SDE_PIX_FMT_RGB_888, |
| 168 | SDE_PIX_FMT_BGR_888, |
| 169 | SDE_PIX_FMT_RGB_565, |
| 170 | SDE_PIX_FMT_BGR_565, |
| 171 | /* SDE_PIX_FMT_Y_CB_CR_H2V2 */ |
| 172 | /* SDE_PIX_FMT_Y_CR_CB_H2V2 */ |
| 173 | /* SDE_PIX_FMT_Y_CR_CB_GH2V2 */ |
| 174 | SDE_PIX_FMT_Y_CBCR_H2V2, |
| 175 | SDE_PIX_FMT_Y_CRCB_H2V2, |
| 176 | SDE_PIX_FMT_Y_CBCR_H1V2, |
| 177 | SDE_PIX_FMT_Y_CRCB_H1V2, |
| 178 | SDE_PIX_FMT_Y_CBCR_H2V1, |
| 179 | SDE_PIX_FMT_Y_CRCB_H2V1, |
| 180 | /* SDE_PIX_FMT_YCBYCR_H2V1 */ |
| 181 | SDE_PIX_FMT_Y_CBCR_H2V2_VENUS, |
| 182 | SDE_PIX_FMT_Y_CRCB_H2V2_VENUS, |
| 183 | SDE_PIX_FMT_RGBA_8888_UBWC, |
| 184 | SDE_PIX_FMT_RGBX_8888_UBWC, |
| 185 | SDE_PIX_FMT_RGB_565_UBWC, |
| 186 | SDE_PIX_FMT_Y_CBCR_H2V2_UBWC, |
| 187 | SDE_PIX_FMT_RGBA_1010102, |
| 188 | SDE_PIX_FMT_RGBX_1010102, |
| 189 | /* SDE_PIX_FMT_ARGB_2101010 */ |
| 190 | /* SDE_PIX_FMT_XRGB_2101010 */ |
| 191 | SDE_PIX_FMT_BGRA_1010102, |
| 192 | SDE_PIX_FMT_BGRX_1010102, |
| 193 | /* SDE_PIX_FMT_ABGR_2101010 */ |
| 194 | /* SDE_PIX_FMT_XBGR_2101010 */ |
| 195 | SDE_PIX_FMT_RGBA_1010102_UBWC, |
| 196 | SDE_PIX_FMT_RGBX_1010102_UBWC, |
| 197 | SDE_PIX_FMT_Y_CBCR_H2V2_P010, |
| 198 | SDE_PIX_FMT_Y_CBCR_H2V2_TP10, |
| 199 | SDE_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC, |
| 200 | }; |
| 201 | |
Benjamin Chan | 53e3bce | 2016-08-31 14:43:29 -0400 | [diff] [blame] | 202 | static struct sde_rot_vbif_debug_bus nrt_vbif_dbg_bus_r3[] = { |
| 203 | {0x214, 0x21c, 16, 1, 0x10}, /* arb clients */ |
| 204 | {0x214, 0x21c, 0, 12, 0x13}, /* xin blocks - axi side */ |
| 205 | {0x21c, 0x214, 0, 12, 0xc}, /* xin blocks - clock side */ |
| 206 | }; |
| 207 | |
| 208 | static struct sde_rot_regdump sde_rot_r3_regdump[] = { |
| 209 | { "SDEROT_ROTTOP", SDE_ROT_ROTTOP_OFFSET, 0x100, SDE_ROT_REGDUMP_READ }, |
| 210 | { "SDEROT_SSPP", SDE_ROT_SSPP_OFFSET, 0x200, SDE_ROT_REGDUMP_READ }, |
| 211 | { "SDEROT_WB", SDE_ROT_WB_OFFSET, 0x300, SDE_ROT_REGDUMP_READ }, |
| 212 | { "SDEROT_REGDMA_CSR", SDE_ROT_REGDMA_OFFSET, 0x100, |
| 213 | SDE_ROT_REGDUMP_READ }, |
| 214 | /* |
| 215 | * Need to perform a SW reset to REGDMA in order to access the |
| 216 | * REGDMA RAM especially if REGDMA is waiting for Rotator IDLE. |
| 217 | * REGDMA RAM should be dump at last. |
| 218 | */ |
| 219 | { "SDEROT_REGDMA_RESET", ROTTOP_SW_RESET_OVERRIDE, 1, |
| 220 | SDE_ROT_REGDUMP_WRITE }, |
| 221 | { "SDEROT_REGDMA_RAM", SDE_ROT_REGDMA_RAM_OFFSET, 0x2000, |
| 222 | SDE_ROT_REGDUMP_READ }, |
| 223 | }; |
| 224 | |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 225 | /* Invalid software timestamp value for initialization */ |
| 226 | #define SDE_REGDMA_SWTS_INVALID (~0) |
| 227 | |
| 228 | /** |
| 229 | * sde_hw_rotator_elapsed_swts - Find difference of 2 software timestamps |
| 230 | * @ts_curr: current software timestamp |
| 231 | * @ts_prev: previous software timestamp |
| 232 | * @return: the amount ts_curr is ahead of ts_prev |
| 233 | */ |
| 234 | static int sde_hw_rotator_elapsed_swts(u32 ts_curr, u32 ts_prev) |
| 235 | { |
| 236 | u32 diff = (ts_curr - ts_prev) & SDE_REGDMA_SWTS_MASK; |
| 237 | |
| 238 | return sign_extend32(diff, (SDE_REGDMA_SWTS_SHIFT - 1)); |
| 239 | } |
| 240 | |
| 241 | /** |
| 242 | * sde_hw_rotator_pending_swts - Check if the given context is still pending |
| 243 | * @rot: Pointer to hw rotator |
| 244 | * @ctx: Pointer to rotator context |
| 245 | * @pswts: Pointer to returned reference software timestamp, optional |
| 246 | * @return: true if context has pending requests |
| 247 | */ |
| 248 | static int sde_hw_rotator_pending_swts(struct sde_hw_rotator *rot, |
| 249 | struct sde_hw_rotator_context *ctx, u32 *pswts) |
| 250 | { |
| 251 | u32 swts; |
| 252 | int ts_diff; |
| 253 | bool pending; |
| 254 | |
| 255 | if (ctx->last_regdma_timestamp == SDE_REGDMA_SWTS_INVALID) |
| 256 | swts = SDE_ROTREG_READ(rot->mdss_base, REGDMA_TIMESTAMP_REG); |
| 257 | else |
| 258 | swts = ctx->last_regdma_timestamp; |
| 259 | |
| 260 | if (ctx->q_id == ROT_QUEUE_LOW_PRIORITY) |
| 261 | swts >>= SDE_REGDMA_SWTS_SHIFT; |
| 262 | |
| 263 | swts &= SDE_REGDMA_SWTS_MASK; |
| 264 | |
| 265 | ts_diff = sde_hw_rotator_elapsed_swts(ctx->timestamp, swts); |
| 266 | |
| 267 | if (pswts) |
| 268 | *pswts = swts; |
| 269 | |
| 270 | pending = (ts_diff > 0) ? true : false; |
| 271 | |
| 272 | SDEROT_DBG("ts:0x%x, queue_id:%d, swts:0x%x, pending:%d\n", |
| 273 | ctx->timestamp, ctx->q_id, swts, pending); |
Benjamin Chan | 0f9e61d | 2016-09-16 16:01:09 -0400 | [diff] [blame] | 274 | SDEROT_EVTLOG(ctx->timestamp, swts, ctx->q_id, ts_diff); |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 275 | return pending; |
| 276 | } |
| 277 | |
| 278 | /** |
| 279 | * sde_hw_rotator_enable_irq - Enable hw rotator interrupt with ref. count |
| 280 | * Also, clear rotator/regdma irq status. |
| 281 | * @rot: Pointer to hw rotator |
| 282 | */ |
| 283 | static void sde_hw_rotator_enable_irq(struct sde_hw_rotator *rot) |
| 284 | { |
| 285 | SDEROT_DBG("irq_num:%d enabled:%d\n", rot->irq_num, |
| 286 | atomic_read(&rot->irq_enabled)); |
| 287 | |
| 288 | if (!atomic_read(&rot->irq_enabled)) { |
| 289 | if (rot->mode == ROT_REGDMA_OFF) |
| 290 | SDE_ROTREG_WRITE(rot->mdss_base, ROTTOP_INTR_CLEAR, |
| 291 | ROT_DONE_MASK); |
| 292 | else |
| 293 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 294 | REGDMA_CSR_REGDMA_INT_CLEAR, REGDMA_INT_MASK); |
| 295 | |
| 296 | enable_irq(rot->irq_num); |
| 297 | } |
| 298 | atomic_inc(&rot->irq_enabled); |
| 299 | } |
| 300 | |
| 301 | /** |
| 302 | * sde_hw_rotator_disable_irq - Disable hw rotator interrupt with ref. count |
| 303 | * Also, clear rotator/regdma irq enable masks. |
| 304 | * @rot: Pointer to hw rotator |
| 305 | */ |
| 306 | static void sde_hw_rotator_disable_irq(struct sde_hw_rotator *rot) |
| 307 | { |
| 308 | SDEROT_DBG("irq_num:%d enabled:%d\n", rot->irq_num, |
| 309 | atomic_read(&rot->irq_enabled)); |
| 310 | |
| 311 | if (!atomic_read(&rot->irq_enabled)) { |
| 312 | SDEROT_ERR("irq %d is already disabled\n", rot->irq_num); |
| 313 | return; |
| 314 | } |
| 315 | |
| 316 | if (!atomic_dec_return(&rot->irq_enabled)) { |
| 317 | if (rot->mode == ROT_REGDMA_OFF) |
| 318 | SDE_ROTREG_WRITE(rot->mdss_base, ROTTOP_INTR_EN, 0); |
| 319 | else |
| 320 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 321 | REGDMA_CSR_REGDMA_INT_EN, 0); |
| 322 | /* disable irq after last pending irq is handled, if any */ |
| 323 | synchronize_irq(rot->irq_num); |
| 324 | disable_irq_nosync(rot->irq_num); |
| 325 | } |
| 326 | } |
| 327 | |
| 328 | /** |
| 329 | * sde_hw_rotator_dump_status - Dump hw rotator status on error |
| 330 | * @rot: Pointer to hw rotator |
| 331 | */ |
| 332 | static void sde_hw_rotator_dump_status(struct sde_hw_rotator *rot) |
| 333 | { |
| 334 | SDEROT_ERR( |
| 335 | "op_mode = %x, int_en = %x, int_status = %x\n", |
| 336 | SDE_ROTREG_READ(rot->mdss_base, |
| 337 | REGDMA_CSR_REGDMA_OP_MODE), |
| 338 | SDE_ROTREG_READ(rot->mdss_base, |
| 339 | REGDMA_CSR_REGDMA_INT_EN), |
| 340 | SDE_ROTREG_READ(rot->mdss_base, |
| 341 | REGDMA_CSR_REGDMA_INT_STATUS)); |
| 342 | |
| 343 | SDEROT_ERR( |
| 344 | "ts = %x, q0_status = %x, q1_status = %x, block_status = %x\n", |
| 345 | SDE_ROTREG_READ(rot->mdss_base, |
| 346 | REGDMA_TIMESTAMP_REG), |
| 347 | SDE_ROTREG_READ(rot->mdss_base, |
| 348 | REGDMA_CSR_REGDMA_QUEUE_0_STATUS), |
| 349 | SDE_ROTREG_READ(rot->mdss_base, |
| 350 | REGDMA_CSR_REGDMA_QUEUE_1_STATUS), |
| 351 | SDE_ROTREG_READ(rot->mdss_base, |
| 352 | REGDMA_CSR_REGDMA_BLOCK_STATUS)); |
| 353 | |
| 354 | SDEROT_ERR( |
| 355 | "invalid_cmd_offset = %x, fsm_state = %x\n", |
| 356 | SDE_ROTREG_READ(rot->mdss_base, |
| 357 | REGDMA_CSR_REGDMA_INVALID_CMD_RAM_OFFSET), |
| 358 | SDE_ROTREG_READ(rot->mdss_base, |
| 359 | REGDMA_CSR_REGDMA_FSM_STATE)); |
| 360 | } |
| 361 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 362 | /** |
| 363 | * sde_hw_rotator_get_ctx(): Retrieve rotator context from rotator HW based |
| 364 | * on provided session_id. Each rotator has a different session_id. |
| 365 | */ |
| 366 | static struct sde_hw_rotator_context *sde_hw_rotator_get_ctx( |
| 367 | struct sde_hw_rotator *rot, u32 session_id, |
| 368 | enum sde_rot_queue_prio q_id) |
| 369 | { |
| 370 | int i; |
| 371 | struct sde_hw_rotator_context *ctx = NULL; |
| 372 | |
| 373 | for (i = 0; i < SDE_HW_ROT_REGDMA_TOTAL_CTX; i++) { |
| 374 | ctx = rot->rotCtx[q_id][i]; |
| 375 | |
| 376 | if (ctx && (ctx->session_id == session_id)) { |
| 377 | SDEROT_DBG( |
| 378 | "rotCtx sloti[%d][%d] ==> ctx:%p | session-id:%d\n", |
| 379 | q_id, i, ctx, ctx->session_id); |
| 380 | return ctx; |
| 381 | } |
| 382 | } |
| 383 | |
| 384 | return NULL; |
| 385 | } |
| 386 | |
| 387 | /* |
| 388 | * sde_hw_rotator_map_vaddr - map the debug buffer to kernel space |
| 389 | * @dbgbuf: Pointer to debug buffer |
| 390 | * @buf: Pointer to layer buffer structure |
| 391 | * @data: Pointer to h/w mapped buffer structure |
| 392 | */ |
| 393 | static void sde_hw_rotator_map_vaddr(struct sde_dbg_buf *dbgbuf, |
| 394 | struct sde_layer_buffer *buf, struct sde_mdp_data *data) |
| 395 | { |
| 396 | dbgbuf->dmabuf = data->p[0].srcp_dma_buf; |
| 397 | dbgbuf->buflen = data->p[0].srcp_dma_buf->size; |
| 398 | |
| 399 | dbgbuf->vaddr = NULL; |
| 400 | dbgbuf->width = buf->width; |
| 401 | dbgbuf->height = buf->height; |
| 402 | |
| 403 | if (dbgbuf->dmabuf && (dbgbuf->buflen > 0)) { |
| 404 | dma_buf_begin_cpu_access(dbgbuf->dmabuf, 0, dbgbuf->buflen, |
| 405 | DMA_FROM_DEVICE); |
| 406 | dbgbuf->vaddr = dma_buf_kmap(dbgbuf->dmabuf, 0); |
| 407 | SDEROT_DBG("vaddr mapping: 0x%p/%ld w:%d/h:%d\n", |
| 408 | dbgbuf->vaddr, dbgbuf->buflen, |
| 409 | dbgbuf->width, dbgbuf->height); |
| 410 | } |
| 411 | } |
| 412 | |
| 413 | /* |
| 414 | * sde_hw_rotator_unmap_vaddr - unmap the debug buffer from kernel space |
| 415 | * @dbgbuf: Pointer to debug buffer |
| 416 | */ |
| 417 | static void sde_hw_rotator_unmap_vaddr(struct sde_dbg_buf *dbgbuf) |
| 418 | { |
| 419 | if (dbgbuf->vaddr) { |
| 420 | dma_buf_kunmap(dbgbuf->dmabuf, 0, dbgbuf->vaddr); |
| 421 | dma_buf_end_cpu_access(dbgbuf->dmabuf, 0, dbgbuf->buflen, |
| 422 | DMA_FROM_DEVICE); |
| 423 | } |
| 424 | |
| 425 | dbgbuf->vaddr = NULL; |
| 426 | dbgbuf->dmabuf = NULL; |
| 427 | dbgbuf->buflen = 0; |
| 428 | dbgbuf->width = 0; |
| 429 | dbgbuf->height = 0; |
| 430 | } |
| 431 | |
| 432 | /* |
| 433 | * sde_hw_rotator_setup_timestamp_packet - setup timestamp writeback command |
| 434 | * @ctx: Pointer to rotator context |
| 435 | * @mask: Bit mask location of the timestamp |
| 436 | * @swts: Software timestamp |
| 437 | */ |
| 438 | static void sde_hw_rotator_setup_timestamp_packet( |
| 439 | struct sde_hw_rotator_context *ctx, u32 mask, u32 swts) |
| 440 | { |
| 441 | u32 *wrptr; |
| 442 | |
| 443 | wrptr = sde_hw_rotator_get_regdma_segment(ctx); |
| 444 | |
| 445 | /* |
| 446 | * Create a dummy packet write out to 1 location for timestamp |
| 447 | * generation. |
| 448 | */ |
| 449 | SDE_REGDMA_BLKWRITE_INC(wrptr, ROT_SSPP_SRC_SIZE, 6); |
| 450 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x00010001); |
| 451 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 452 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 453 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x00010001); |
| 454 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 455 | SDE_REGDMA_BLKWRITE_DATA(wrptr, ctx->ts_addr); |
| 456 | SDE_REGDMA_WRITE(wrptr, ROT_SSPP_SRC_YSTRIDE0, 4); |
| 457 | SDE_REGDMA_BLKWRITE_INC(wrptr, ROT_SSPP_SRC_FORMAT, 4); |
| 458 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x004037FF); |
| 459 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x03020100); |
| 460 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x80000000); |
| 461 | SDE_REGDMA_BLKWRITE_DATA(wrptr, ctx->timestamp); |
Benjamin Chan | 15c93d8 | 2016-08-29 10:04:22 -0400 | [diff] [blame] | 462 | /* |
| 463 | * Must clear secure buffer setting for SW timestamp because |
| 464 | * SW timstamp buffer allocation is always non-secure region. |
| 465 | */ |
| 466 | if (ctx->is_secure) { |
| 467 | SDE_REGDMA_WRITE(wrptr, ROT_SSPP_SRC_ADDR_SW_STATUS, 0); |
| 468 | SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_ADDR_SW_STATUS, 0); |
| 469 | } |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 470 | SDE_REGDMA_BLKWRITE_INC(wrptr, ROT_WB_DST_FORMAT, 4); |
| 471 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x000037FF); |
| 472 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 473 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0x03020100); |
| 474 | SDE_REGDMA_BLKWRITE_DATA(wrptr, ctx->ts_addr); |
| 475 | SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_YSTRIDE0, 4); |
| 476 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_SIZE, 0x00010001); |
| 477 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_IMG_SIZE, 0x00010001); |
| 478 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_XY, 0); |
| 479 | SDE_REGDMA_WRITE(wrptr, ROTTOP_DNSC, 0); |
| 480 | SDE_REGDMA_WRITE(wrptr, ROTTOP_OP_MODE, 1); |
| 481 | SDE_REGDMA_MODIFY(wrptr, REGDMA_TIMESTAMP_REG, mask, swts); |
| 482 | SDE_REGDMA_WRITE(wrptr, ROTTOP_START_CTRL, 1); |
| 483 | |
| 484 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 485 | } |
| 486 | |
| 487 | /* |
| 488 | * sde_hw_rotator_setup_fetchengine - setup fetch engine |
| 489 | * @ctx: Pointer to rotator context |
| 490 | * @queue_id: Priority queue identifier |
| 491 | * @cfg: Fetch configuration |
| 492 | * @danger_lut: real-time QoS LUT for danger setting (not used) |
| 493 | * @safe_lut: real-time QoS LUT for safe setting (not used) |
Benjamin Chan | fb6faa3 | 2016-08-16 17:21:01 -0400 | [diff] [blame] | 494 | * @dnsc_factor_w: downscale factor for width |
| 495 | * @dnsc_factor_h: downscale factor for height |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 496 | * @flags: Control flag |
| 497 | */ |
| 498 | static void sde_hw_rotator_setup_fetchengine(struct sde_hw_rotator_context *ctx, |
| 499 | enum sde_rot_queue_prio queue_id, |
| 500 | struct sde_hw_rot_sspp_cfg *cfg, u32 danger_lut, u32 safe_lut, |
Benjamin Chan | fb6faa3 | 2016-08-16 17:21:01 -0400 | [diff] [blame] | 501 | u32 dnsc_factor_w, u32 dnsc_factor_h, u32 flags) |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 502 | { |
| 503 | struct sde_hw_rotator *rot = ctx->rot; |
| 504 | struct sde_mdp_format_params *fmt; |
| 505 | struct sde_mdp_data *data; |
Benjamin Chan | fb6faa3 | 2016-08-16 17:21:01 -0400 | [diff] [blame] | 506 | struct sde_rot_data_type *mdata = sde_rot_get_mdata(); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 507 | u32 *wrptr; |
| 508 | u32 opmode = 0; |
| 509 | u32 chroma_samp = 0; |
| 510 | u32 src_format = 0; |
| 511 | u32 unpack = 0; |
| 512 | u32 width = cfg->img_width; |
| 513 | u32 height = cfg->img_height; |
| 514 | u32 fetch_blocksize = 0; |
| 515 | int i; |
| 516 | |
| 517 | if (ctx->rot->mode == ROT_REGDMA_ON) { |
| 518 | SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_CSR_REGDMA_INT_EN, |
| 519 | REGDMA_INT_MASK); |
| 520 | SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_CSR_REGDMA_OP_MODE, |
| 521 | REGDMA_EN); |
| 522 | } |
| 523 | |
| 524 | wrptr = sde_hw_rotator_get_regdma_segment(ctx); |
| 525 | |
| 526 | /* source image setup */ |
| 527 | if ((flags & SDE_ROT_FLAG_DEINTERLACE) |
| 528 | && !(flags & SDE_ROT_FLAG_SOURCE_ROTATED_90)) { |
| 529 | for (i = 0; i < cfg->src_plane.num_planes; i++) |
| 530 | cfg->src_plane.ystride[i] *= 2; |
| 531 | width *= 2; |
| 532 | height /= 2; |
| 533 | } |
| 534 | |
| 535 | /* |
| 536 | * REGDMA BLK write from SRC_SIZE to OP_MODE, total 15 registers |
| 537 | */ |
| 538 | SDE_REGDMA_BLKWRITE_INC(wrptr, ROT_SSPP_SRC_SIZE, 15); |
| 539 | |
| 540 | /* SRC_SIZE, SRC_IMG_SIZE, SRC_XY, OUT_SIZE, OUT_XY */ |
| 541 | SDE_REGDMA_BLKWRITE_DATA(wrptr, |
| 542 | cfg->src_rect->w | (cfg->src_rect->h << 16)); |
| 543 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); /* SRC_IMG_SIZE unused */ |
| 544 | SDE_REGDMA_BLKWRITE_DATA(wrptr, |
| 545 | cfg->src_rect->x | (cfg->src_rect->y << 16)); |
| 546 | SDE_REGDMA_BLKWRITE_DATA(wrptr, |
| 547 | cfg->src_rect->w | (cfg->src_rect->h << 16)); |
| 548 | SDE_REGDMA_BLKWRITE_DATA(wrptr, |
| 549 | cfg->src_rect->x | (cfg->src_rect->y << 16)); |
| 550 | |
| 551 | /* SRC_ADDR [0-3], SRC_YSTRIDE [0-1] */ |
| 552 | data = cfg->data; |
| 553 | for (i = 0; i < SDE_ROT_MAX_PLANES; i++) |
| 554 | SDE_REGDMA_BLKWRITE_DATA(wrptr, data->p[i].addr); |
| 555 | SDE_REGDMA_BLKWRITE_DATA(wrptr, cfg->src_plane.ystride[0] | |
| 556 | (cfg->src_plane.ystride[1] << 16)); |
| 557 | SDE_REGDMA_BLKWRITE_DATA(wrptr, cfg->src_plane.ystride[2] | |
| 558 | (cfg->src_plane.ystride[3] << 16)); |
| 559 | |
| 560 | /* UNUSED, write 0 */ |
| 561 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 562 | |
| 563 | /* setup source format */ |
| 564 | fmt = cfg->fmt; |
| 565 | |
| 566 | chroma_samp = fmt->chroma_sample; |
| 567 | if (flags & SDE_ROT_FLAG_SOURCE_ROTATED_90) { |
| 568 | if (chroma_samp == SDE_MDP_CHROMA_H2V1) |
| 569 | chroma_samp = SDE_MDP_CHROMA_H1V2; |
| 570 | else if (chroma_samp == SDE_MDP_CHROMA_H1V2) |
| 571 | chroma_samp = SDE_MDP_CHROMA_H2V1; |
| 572 | } |
| 573 | |
| 574 | src_format = (chroma_samp << 23) | |
| 575 | (fmt->fetch_planes << 19) | |
| 576 | (fmt->bits[C3_ALPHA] << 6) | |
| 577 | (fmt->bits[C2_R_Cr] << 4) | |
| 578 | (fmt->bits[C1_B_Cb] << 2) | |
| 579 | (fmt->bits[C0_G_Y] << 0); |
| 580 | |
| 581 | if (fmt->alpha_enable && |
| 582 | (fmt->fetch_planes == SDE_MDP_PLANE_INTERLEAVED)) |
| 583 | src_format |= BIT(8); /* SRCC3_EN */ |
| 584 | |
| 585 | src_format |= ((fmt->unpack_count - 1) << 12) | |
| 586 | (fmt->unpack_tight << 17) | |
| 587 | (fmt->unpack_align_msb << 18) | |
| 588 | ((fmt->bpp - 1) << 9) | |
| 589 | ((fmt->frame_format & 3) << 30); |
| 590 | |
| 591 | if (flags & SDE_ROT_FLAG_ROT_90) |
| 592 | src_format |= BIT(11); /* ROT90 */ |
| 593 | |
| 594 | if (sde_mdp_is_ubwc_format(fmt)) |
| 595 | opmode |= BIT(0); /* BWC_DEC_EN */ |
| 596 | |
| 597 | /* if this is YUV pixel format, enable CSC */ |
| 598 | if (sde_mdp_is_yuv_format(fmt)) |
| 599 | src_format |= BIT(15); /* SRC_COLOR_SPACE */ |
| 600 | |
| 601 | if (fmt->pixel_mode == SDE_MDP_PIXEL_10BIT) |
| 602 | src_format |= BIT(14); /* UNPACK_DX_FORMAT */ |
| 603 | |
| 604 | /* SRC_FORMAT */ |
| 605 | SDE_REGDMA_BLKWRITE_DATA(wrptr, src_format); |
| 606 | |
| 607 | /* setup source unpack pattern */ |
| 608 | unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) | |
| 609 | (fmt->element[1] << 8) | (fmt->element[0] << 0); |
| 610 | |
| 611 | /* SRC_UNPACK_PATTERN */ |
| 612 | SDE_REGDMA_BLKWRITE_DATA(wrptr, unpack); |
| 613 | |
| 614 | /* setup source op mode */ |
| 615 | if (flags & SDE_ROT_FLAG_FLIP_LR) |
| 616 | opmode |= BIT(13); /* FLIP_MODE L/R horizontal flip */ |
| 617 | if (flags & SDE_ROT_FLAG_FLIP_UD) |
| 618 | opmode |= BIT(14); /* FLIP_MODE U/D vertical flip */ |
| 619 | opmode |= BIT(31); /* MDSS_MDP_OP_PE_OVERRIDE */ |
| 620 | |
| 621 | /* SRC_OP_MODE */ |
| 622 | SDE_REGDMA_BLKWRITE_DATA(wrptr, opmode); |
| 623 | |
| 624 | /* setup source fetch config, TP10 uses different block size */ |
Benjamin Chan | fb6faa3 | 2016-08-16 17:21:01 -0400 | [diff] [blame] | 625 | if (test_bit(SDE_CAPS_R3_1P5_DOWNSCALE, mdata->sde_caps_map) && |
| 626 | (dnsc_factor_w == 1) && (dnsc_factor_h == 1)) { |
| 627 | if (sde_mdp_is_tp10_format(fmt)) |
| 628 | fetch_blocksize = SDE_ROT_SSPP_FETCH_BLOCKSIZE_144_EXT; |
| 629 | else |
| 630 | fetch_blocksize = SDE_ROT_SSPP_FETCH_BLOCKSIZE_192_EXT; |
| 631 | } else { |
| 632 | if (sde_mdp_is_tp10_format(fmt)) |
| 633 | fetch_blocksize = SDE_ROT_SSPP_FETCH_BLOCKSIZE_96; |
| 634 | else |
| 635 | fetch_blocksize = SDE_ROT_SSPP_FETCH_BLOCKSIZE_128; |
| 636 | } |
| 637 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 638 | SDE_REGDMA_WRITE(wrptr, ROT_SSPP_FETCH_CONFIG, |
| 639 | fetch_blocksize | |
| 640 | SDE_ROT_SSPP_FETCH_CONFIG_RESET_VALUE | |
| 641 | ((rot->highest_bank & 0x3) << 18)); |
| 642 | |
| 643 | /* setup source buffer plane security status */ |
| 644 | if (flags & SDE_ROT_FLAG_SECURE_OVERLAY_SESSION) { |
| 645 | SDE_REGDMA_WRITE(wrptr, ROT_SSPP_SRC_ADDR_SW_STATUS, 0xF); |
| 646 | ctx->is_secure = true; |
Benjamin Chan | 15c93d8 | 2016-08-29 10:04:22 -0400 | [diff] [blame] | 647 | } else { |
| 648 | SDE_REGDMA_WRITE(wrptr, ROT_SSPP_SRC_ADDR_SW_STATUS, 0); |
| 649 | ctx->is_secure = false; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 650 | } |
| 651 | |
| 652 | /* Update command queue write ptr */ |
| 653 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 654 | } |
| 655 | |
| 656 | /* |
| 657 | * sde_hw_rotator_setup_wbengine - setup writeback engine |
| 658 | * @ctx: Pointer to rotator context |
| 659 | * @queue_id: Priority queue identifier |
| 660 | * @cfg: Writeback configuration |
| 661 | * @flags: Control flag |
| 662 | */ |
| 663 | static void sde_hw_rotator_setup_wbengine(struct sde_hw_rotator_context *ctx, |
| 664 | enum sde_rot_queue_prio queue_id, |
| 665 | struct sde_hw_rot_wb_cfg *cfg, |
| 666 | u32 flags) |
| 667 | { |
| 668 | struct sde_mdp_format_params *fmt; |
| 669 | u32 *wrptr; |
| 670 | u32 pack = 0; |
| 671 | u32 dst_format = 0; |
| 672 | int i; |
| 673 | |
| 674 | wrptr = sde_hw_rotator_get_regdma_segment(ctx); |
| 675 | |
| 676 | fmt = cfg->fmt; |
| 677 | |
| 678 | /* setup WB DST format */ |
| 679 | dst_format |= (fmt->chroma_sample << 23) | |
| 680 | (fmt->fetch_planes << 19) | |
| 681 | (fmt->bits[C3_ALPHA] << 6) | |
| 682 | (fmt->bits[C2_R_Cr] << 4) | |
| 683 | (fmt->bits[C1_B_Cb] << 2) | |
| 684 | (fmt->bits[C0_G_Y] << 0); |
| 685 | |
| 686 | /* alpha control */ |
| 687 | if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) { |
| 688 | dst_format |= BIT(8); |
| 689 | if (!fmt->alpha_enable) { |
| 690 | dst_format |= BIT(14); |
| 691 | SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_ALPHA_X_VALUE, 0); |
| 692 | } |
| 693 | } |
| 694 | |
| 695 | dst_format |= ((fmt->unpack_count - 1) << 12) | |
| 696 | (fmt->unpack_tight << 17) | |
| 697 | (fmt->unpack_align_msb << 18) | |
| 698 | ((fmt->bpp - 1) << 9) | |
| 699 | ((fmt->frame_format & 3) << 30); |
| 700 | |
| 701 | if (sde_mdp_is_yuv_format(fmt)) |
| 702 | dst_format |= BIT(15); |
| 703 | |
| 704 | if (fmt->pixel_mode == SDE_MDP_PIXEL_10BIT) |
| 705 | dst_format |= BIT(21); /* PACK_DX_FORMAT */ |
| 706 | |
| 707 | /* |
| 708 | * REGDMA BLK write, from DST_FORMAT to DST_YSTRIDE 1, total 9 regs |
| 709 | */ |
| 710 | SDE_REGDMA_BLKWRITE_INC(wrptr, ROT_WB_DST_FORMAT, 9); |
| 711 | |
| 712 | /* DST_FORMAT */ |
| 713 | SDE_REGDMA_BLKWRITE_DATA(wrptr, dst_format); |
| 714 | |
| 715 | /* DST_OP_MODE */ |
| 716 | if (sde_mdp_is_ubwc_format(fmt)) |
| 717 | SDE_REGDMA_BLKWRITE_DATA(wrptr, BIT(0)); |
| 718 | else |
| 719 | SDE_REGDMA_BLKWRITE_DATA(wrptr, 0); |
| 720 | |
| 721 | /* DST_PACK_PATTERN */ |
| 722 | pack = (fmt->element[3] << 24) | (fmt->element[2] << 16) | |
| 723 | (fmt->element[1] << 8) | (fmt->element[0] << 0); |
| 724 | SDE_REGDMA_BLKWRITE_DATA(wrptr, pack); |
| 725 | |
| 726 | /* DST_ADDR [0-3], DST_YSTRIDE [0-1] */ |
| 727 | for (i = 0; i < SDE_ROT_MAX_PLANES; i++) |
| 728 | SDE_REGDMA_BLKWRITE_DATA(wrptr, cfg->data->p[i].addr); |
| 729 | SDE_REGDMA_BLKWRITE_DATA(wrptr, cfg->dst_plane.ystride[0] | |
| 730 | (cfg->dst_plane.ystride[1] << 16)); |
| 731 | SDE_REGDMA_BLKWRITE_DATA(wrptr, cfg->dst_plane.ystride[2] | |
| 732 | (cfg->dst_plane.ystride[3] << 16)); |
| 733 | |
| 734 | /* setup WB out image size and ROI */ |
| 735 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_IMG_SIZE, |
| 736 | cfg->img_width | (cfg->img_height << 16)); |
| 737 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_SIZE, |
| 738 | cfg->dst_rect->w | (cfg->dst_rect->h << 16)); |
| 739 | SDE_REGDMA_WRITE(wrptr, ROT_WB_OUT_XY, |
| 740 | cfg->dst_rect->x | (cfg->dst_rect->y << 16)); |
| 741 | |
Benjamin Chan | 15c93d8 | 2016-08-29 10:04:22 -0400 | [diff] [blame] | 742 | if (flags & SDE_ROT_FLAG_SECURE_OVERLAY_SESSION) |
| 743 | SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_ADDR_SW_STATUS, 0x1); |
| 744 | else |
| 745 | SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_ADDR_SW_STATUS, 0); |
| 746 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 747 | /* |
| 748 | * setup Downscale factor |
| 749 | */ |
| 750 | SDE_REGDMA_WRITE(wrptr, ROTTOP_DNSC, |
| 751 | cfg->v_downscale_factor | |
| 752 | (cfg->h_downscale_factor << 16)); |
| 753 | |
| 754 | /* write config setup for bank configration */ |
| 755 | SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_WRITE_CONFIG, |
| 756 | (ctx->rot->highest_bank & 0x3) << 8); |
| 757 | |
| 758 | if (flags & SDE_ROT_FLAG_ROT_90) |
| 759 | SDE_REGDMA_WRITE(wrptr, ROTTOP_OP_MODE, 0x3); |
| 760 | else |
| 761 | SDE_REGDMA_WRITE(wrptr, ROTTOP_OP_MODE, 0x1); |
| 762 | |
| 763 | /* Update command queue write ptr */ |
| 764 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 765 | } |
| 766 | |
| 767 | /* |
| 768 | * sde_hw_rotator_start_no_regdma - start non-regdma operation |
| 769 | * @ctx: Pointer to rotator context |
| 770 | * @queue_id: Priority queue identifier |
| 771 | */ |
| 772 | static u32 sde_hw_rotator_start_no_regdma(struct sde_hw_rotator_context *ctx, |
| 773 | enum sde_rot_queue_prio queue_id) |
| 774 | { |
| 775 | struct sde_hw_rotator *rot = ctx->rot; |
| 776 | u32 *wrptr; |
| 777 | u32 *rdptr; |
| 778 | u8 *addr; |
| 779 | u32 mask; |
| 780 | u32 blksize; |
| 781 | |
| 782 | rdptr = sde_hw_rotator_get_regdma_segment_base(ctx); |
| 783 | wrptr = sde_hw_rotator_get_regdma_segment(ctx); |
| 784 | |
| 785 | if (rot->irq_num >= 0) { |
| 786 | SDE_REGDMA_WRITE(wrptr, ROTTOP_INTR_EN, 1); |
| 787 | SDE_REGDMA_WRITE(wrptr, ROTTOP_INTR_CLEAR, 1); |
| 788 | reinit_completion(&ctx->rot_comp); |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 789 | sde_hw_rotator_enable_irq(rot); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 790 | } |
| 791 | |
| 792 | SDE_REGDMA_WRITE(wrptr, ROTTOP_START_CTRL, 1); |
| 793 | |
| 794 | /* Update command queue write ptr */ |
| 795 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 796 | |
| 797 | SDEROT_DBG("BEGIN %d\n", ctx->timestamp); |
| 798 | /* Write all command stream to Rotator blocks */ |
| 799 | /* Rotator will start right away after command stream finish writing */ |
| 800 | while (rdptr < wrptr) { |
| 801 | u32 op = REGDMA_OP_MASK & *rdptr; |
| 802 | |
| 803 | switch (op) { |
| 804 | case REGDMA_OP_NOP: |
| 805 | SDEROT_DBG("NOP\n"); |
| 806 | rdptr++; |
| 807 | break; |
| 808 | case REGDMA_OP_REGWRITE: |
| 809 | SDEROT_DBG("REGW %6.6x %8.8x\n", |
| 810 | rdptr[0] & REGDMA_ADDR_OFFSET_MASK, |
| 811 | rdptr[1]); |
| 812 | addr = rot->mdss_base + |
| 813 | (*rdptr++ & REGDMA_ADDR_OFFSET_MASK); |
| 814 | writel_relaxed(*rdptr++, addr); |
| 815 | break; |
| 816 | case REGDMA_OP_REGMODIFY: |
| 817 | SDEROT_DBG("REGM %6.6x %8.8x %8.8x\n", |
| 818 | rdptr[0] & REGDMA_ADDR_OFFSET_MASK, |
| 819 | rdptr[1], rdptr[2]); |
| 820 | addr = rot->mdss_base + |
| 821 | (*rdptr++ & REGDMA_ADDR_OFFSET_MASK); |
| 822 | mask = *rdptr++; |
| 823 | writel_relaxed((readl_relaxed(addr) & mask) | *rdptr++, |
| 824 | addr); |
| 825 | break; |
| 826 | case REGDMA_OP_BLKWRITE_SINGLE: |
| 827 | SDEROT_DBG("BLKWS %6.6x %6.6x\n", |
| 828 | rdptr[0] & REGDMA_ADDR_OFFSET_MASK, |
| 829 | rdptr[1]); |
| 830 | addr = rot->mdss_base + |
| 831 | (*rdptr++ & REGDMA_ADDR_OFFSET_MASK); |
| 832 | blksize = *rdptr++; |
| 833 | while (blksize--) { |
| 834 | SDEROT_DBG("DATA %8.8x\n", rdptr[0]); |
| 835 | writel_relaxed(*rdptr++, addr); |
| 836 | } |
| 837 | break; |
| 838 | case REGDMA_OP_BLKWRITE_INC: |
| 839 | SDEROT_DBG("BLKWI %6.6x %6.6x\n", |
| 840 | rdptr[0] & REGDMA_ADDR_OFFSET_MASK, |
| 841 | rdptr[1]); |
| 842 | addr = rot->mdss_base + |
| 843 | (*rdptr++ & REGDMA_ADDR_OFFSET_MASK); |
| 844 | blksize = *rdptr++; |
| 845 | while (blksize--) { |
| 846 | SDEROT_DBG("DATA %8.8x\n", rdptr[0]); |
| 847 | writel_relaxed(*rdptr++, addr); |
| 848 | addr += 4; |
| 849 | } |
| 850 | break; |
| 851 | default: |
| 852 | /* Other not supported OP mode |
| 853 | * Skip data for now for unregonized OP mode |
| 854 | */ |
| 855 | SDEROT_DBG("UNDEFINED\n"); |
| 856 | rdptr++; |
| 857 | break; |
| 858 | } |
| 859 | } |
| 860 | SDEROT_DBG("END %d\n", ctx->timestamp); |
| 861 | |
| 862 | return ctx->timestamp; |
| 863 | } |
| 864 | |
| 865 | /* |
| 866 | * sde_hw_rotator_start_regdma - start regdma operation |
| 867 | * @ctx: Pointer to rotator context |
| 868 | * @queue_id: Priority queue identifier |
| 869 | */ |
| 870 | static u32 sde_hw_rotator_start_regdma(struct sde_hw_rotator_context *ctx, |
| 871 | enum sde_rot_queue_prio queue_id) |
| 872 | { |
| 873 | struct sde_hw_rotator *rot = ctx->rot; |
| 874 | u32 *wrptr; |
| 875 | u32 regdmaSlot; |
| 876 | u32 offset; |
| 877 | long length; |
| 878 | long ts_length; |
| 879 | u32 enableInt; |
| 880 | u32 swts = 0; |
| 881 | u32 mask = 0; |
| 882 | |
| 883 | wrptr = sde_hw_rotator_get_regdma_segment(ctx); |
| 884 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 885 | /* |
| 886 | * Last ROT command must be ROT_START before REGDMA start |
| 887 | */ |
| 888 | SDE_REGDMA_WRITE(wrptr, ROTTOP_START_CTRL, 1); |
| 889 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 890 | |
| 891 | /* |
| 892 | * Start REGDMA with command offset and size |
| 893 | */ |
| 894 | regdmaSlot = sde_hw_rotator_get_regdma_ctxidx(ctx); |
| 895 | length = ((long)wrptr - (long)ctx->regdma_base) / 4; |
| 896 | offset = (u32)(ctx->regdma_base - (u32 *)(rot->mdss_base + |
| 897 | REGDMA_RAM_REGDMA_CMD_RAM)); |
| 898 | enableInt = ((ctx->timestamp & 1) + 1) << 30; |
| 899 | |
| 900 | SDEROT_DBG( |
| 901 | "regdma(%d)[%d] <== INT:0x%X|length:%ld|offset:0x%X, ts:%X\n", |
| 902 | queue_id, regdmaSlot, enableInt, length, offset, |
| 903 | ctx->timestamp); |
| 904 | |
| 905 | /* ensure the command packet is issued before the submit command */ |
| 906 | wmb(); |
| 907 | |
| 908 | /* REGDMA submission for current context */ |
| 909 | if (queue_id == ROT_QUEUE_HIGH_PRIORITY) { |
| 910 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 911 | REGDMA_CSR_REGDMA_QUEUE_0_SUBMIT, |
| 912 | (length << 14) | offset); |
| 913 | swts = ctx->timestamp; |
| 914 | mask = ~SDE_REGDMA_SWTS_MASK; |
| 915 | } else { |
| 916 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 917 | REGDMA_CSR_REGDMA_QUEUE_1_SUBMIT, |
| 918 | (length << 14) | offset); |
| 919 | swts = ctx->timestamp << SDE_REGDMA_SWTS_SHIFT; |
| 920 | mask = ~(SDE_REGDMA_SWTS_MASK << SDE_REGDMA_SWTS_SHIFT); |
| 921 | } |
| 922 | |
| 923 | /* Write timestamp after previous rotator job finished */ |
| 924 | sde_hw_rotator_setup_timestamp_packet(ctx, mask, swts); |
| 925 | offset += length; |
| 926 | ts_length = sde_hw_rotator_get_regdma_segment(ctx) - wrptr; |
| 927 | WARN_ON((length + ts_length) > SDE_HW_ROT_REGDMA_SEG_SIZE); |
| 928 | |
| 929 | /* ensure command packet is issue before the submit command */ |
| 930 | wmb(); |
| 931 | |
| 932 | if (queue_id == ROT_QUEUE_HIGH_PRIORITY) { |
| 933 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 934 | REGDMA_CSR_REGDMA_QUEUE_0_SUBMIT, |
| 935 | enableInt | (ts_length << 14) | offset); |
| 936 | } else { |
| 937 | SDE_ROTREG_WRITE(rot->mdss_base, |
| 938 | REGDMA_CSR_REGDMA_QUEUE_1_SUBMIT, |
| 939 | enableInt | (ts_length << 14) | offset); |
| 940 | } |
| 941 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 942 | /* Update command queue write ptr */ |
| 943 | sde_hw_rotator_put_regdma_segment(ctx, wrptr); |
| 944 | |
| 945 | return ctx->timestamp; |
| 946 | } |
| 947 | |
| 948 | /* |
| 949 | * sde_hw_rotator_wait_done_no_regdma - wait for non-regdma completion |
| 950 | * @ctx: Pointer to rotator context |
| 951 | * @queue_id: Priority queue identifier |
| 952 | * @flags: Option flag |
| 953 | */ |
| 954 | static u32 sde_hw_rotator_wait_done_no_regdma( |
| 955 | struct sde_hw_rotator_context *ctx, |
| 956 | enum sde_rot_queue_prio queue_id, u32 flag) |
| 957 | { |
| 958 | struct sde_hw_rotator *rot = ctx->rot; |
| 959 | int rc = 0; |
| 960 | u32 sts = 0; |
| 961 | u32 status; |
| 962 | unsigned long flags; |
| 963 | |
| 964 | if (rot->irq_num >= 0) { |
| 965 | SDEROT_DBG("Wait for Rotator completion\n"); |
| 966 | rc = wait_for_completion_timeout(&ctx->rot_comp, |
| 967 | KOFF_TIMEOUT); |
| 968 | |
| 969 | spin_lock_irqsave(&rot->rotisr_lock, flags); |
| 970 | status = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_STATUS); |
| 971 | if (rc == 0) { |
| 972 | /* |
| 973 | * Timeout, there might be error, |
| 974 | * or rotator still busy |
| 975 | */ |
| 976 | if (status & ROT_BUSY_BIT) |
| 977 | SDEROT_ERR( |
| 978 | "Timeout waiting for rotator done\n"); |
| 979 | else if (status & ROT_ERROR_BIT) |
| 980 | SDEROT_ERR( |
| 981 | "Rotator report error status\n"); |
| 982 | else |
| 983 | SDEROT_WARN( |
| 984 | "Timeout waiting, but rotator job is done!!\n"); |
| 985 | |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 986 | sde_hw_rotator_disable_irq(rot); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 987 | } |
| 988 | spin_unlock_irqrestore(&rot->rotisr_lock, flags); |
| 989 | } else { |
| 990 | int cnt = 200; |
| 991 | |
| 992 | do { |
| 993 | udelay(500); |
| 994 | status = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_STATUS); |
| 995 | cnt--; |
| 996 | } while ((cnt > 0) && (status & ROT_BUSY_BIT) |
| 997 | && ((status & ROT_ERROR_BIT) == 0)); |
| 998 | |
| 999 | if (status & ROT_ERROR_BIT) |
| 1000 | SDEROT_ERR("Rotator error\n"); |
| 1001 | else if (status & ROT_BUSY_BIT) |
| 1002 | SDEROT_ERR("Rotator busy\n"); |
| 1003 | |
| 1004 | SDE_ROTREG_WRITE(rot->mdss_base, ROTTOP_INTR_CLEAR, |
| 1005 | ROT_DONE_CLEAR); |
| 1006 | } |
| 1007 | |
| 1008 | sts = (status & ROT_ERROR_BIT) ? -ENODEV : 0; |
| 1009 | |
| 1010 | return sts; |
| 1011 | } |
| 1012 | |
| 1013 | /* |
| 1014 | * sde_hw_rotator_wait_done_regdma - wait for regdma completion |
| 1015 | * @ctx: Pointer to rotator context |
| 1016 | * @queue_id: Priority queue identifier |
| 1017 | * @flags: Option flag |
| 1018 | */ |
| 1019 | static u32 sde_hw_rotator_wait_done_regdma( |
| 1020 | struct sde_hw_rotator_context *ctx, |
| 1021 | enum sde_rot_queue_prio queue_id, u32 flag) |
| 1022 | { |
| 1023 | struct sde_hw_rotator *rot = ctx->rot; |
| 1024 | int rc = 0; |
| 1025 | u32 status; |
| 1026 | u32 last_isr; |
| 1027 | u32 last_ts; |
| 1028 | u32 int_id; |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1029 | u32 swts; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1030 | u32 sts = 0; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1031 | unsigned long flags; |
| 1032 | |
| 1033 | if (rot->irq_num >= 0) { |
| 1034 | SDEROT_DBG("Wait for REGDMA completion, ctx:%p, ts:%X\n", |
| 1035 | ctx, ctx->timestamp); |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1036 | rc = wait_event_timeout(ctx->regdma_waitq, |
| 1037 | !sde_hw_rotator_pending_swts(rot, ctx, &swts), |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1038 | KOFF_TIMEOUT); |
| 1039 | |
| 1040 | spin_lock_irqsave(&rot->rotisr_lock, flags); |
| 1041 | |
| 1042 | last_isr = ctx->last_regdma_isr_status; |
| 1043 | last_ts = ctx->last_regdma_timestamp; |
| 1044 | status = last_isr & REGDMA_INT_MASK; |
| 1045 | int_id = last_ts & 1; |
| 1046 | SDEROT_DBG("INT status:0x%X, INT id:%d, timestamp:0x%X\n", |
| 1047 | status, int_id, last_ts); |
| 1048 | |
| 1049 | if (rc == 0 || (status & REGDMA_INT_ERR_MASK)) { |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1050 | bool pending; |
| 1051 | |
| 1052 | pending = sde_hw_rotator_pending_swts(rot, ctx, &swts); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1053 | SDEROT_ERR( |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1054 | "Timeout wait for regdma interrupt status, ts:0x%X/0x%X pending:%d\n", |
| 1055 | ctx->timestamp, swts, pending); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1056 | |
| 1057 | if (status & REGDMA_WATCHDOG_INT) |
| 1058 | SDEROT_ERR("REGDMA watchdog interrupt\n"); |
| 1059 | else if (status & REGDMA_INVALID_DESCRIPTOR) |
| 1060 | SDEROT_ERR("REGDMA invalid descriptor\n"); |
| 1061 | else if (status & REGDMA_INCOMPLETE_CMD) |
| 1062 | SDEROT_ERR("REGDMA incomplete command\n"); |
| 1063 | else if (status & REGDMA_INVALID_CMD) |
| 1064 | SDEROT_ERR("REGDMA invalid command\n"); |
| 1065 | |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1066 | sde_hw_rotator_dump_status(rot); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1067 | status = ROT_ERROR_BIT; |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1068 | } else { |
| 1069 | if (rc == 1) |
| 1070 | SDEROT_WARN( |
| 1071 | "REGDMA done but no irq, ts:0x%X/0x%X\n", |
| 1072 | ctx->timestamp, swts); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1073 | status = 0; |
| 1074 | } |
| 1075 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1076 | spin_unlock_irqrestore(&rot->rotisr_lock, flags); |
| 1077 | } else { |
| 1078 | int cnt = 200; |
| 1079 | |
| 1080 | do { |
| 1081 | udelay(500); |
| 1082 | status = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_STATUS); |
| 1083 | cnt--; |
| 1084 | } while ((cnt > 0) && (status & ROT_BUSY_BIT) |
| 1085 | && ((status & ROT_ERROR_BIT) == 0)); |
| 1086 | |
| 1087 | if (status & ROT_ERROR_BIT) |
| 1088 | SDEROT_ERR("Rotator error\n"); |
| 1089 | else if (status & ROT_BUSY_BIT) |
| 1090 | SDEROT_ERR("Rotator busy\n"); |
| 1091 | |
| 1092 | SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_CSR_REGDMA_INT_CLEAR, |
| 1093 | 0xFFFF); |
| 1094 | } |
| 1095 | |
| 1096 | sts = (status & ROT_ERROR_BIT) ? -ENODEV : 0; |
| 1097 | |
Benjamin Chan | 4ec1f1d | 2016-09-15 22:49:49 -0400 | [diff] [blame] | 1098 | if (status & ROT_ERROR_BIT) |
| 1099 | SDEROT_EVTLOG_TOUT_HANDLER("rot", "vbif_dbg_bus", "panic"); |
| 1100 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1101 | return sts; |
| 1102 | } |
| 1103 | |
| 1104 | /* |
| 1105 | * setup_rotator_ops - setup callback functions for the low-level HAL |
| 1106 | * @ops: Pointer to low-level ops callback |
| 1107 | * @mode: Operation mode (non-regdma or regdma) |
| 1108 | */ |
| 1109 | static void setup_rotator_ops(struct sde_hw_rotator_ops *ops, |
| 1110 | enum sde_rotator_regdma_mode mode) |
| 1111 | { |
| 1112 | ops->setup_rotator_fetchengine = sde_hw_rotator_setup_fetchengine; |
| 1113 | ops->setup_rotator_wbengine = sde_hw_rotator_setup_wbengine; |
| 1114 | if (mode == ROT_REGDMA_ON) { |
| 1115 | ops->start_rotator = sde_hw_rotator_start_regdma; |
| 1116 | ops->wait_rotator_done = sde_hw_rotator_wait_done_regdma; |
| 1117 | } else { |
| 1118 | ops->start_rotator = sde_hw_rotator_start_no_regdma; |
| 1119 | ops->wait_rotator_done = sde_hw_rotator_wait_done_no_regdma; |
| 1120 | } |
| 1121 | } |
| 1122 | |
| 1123 | /* |
| 1124 | * sde_hw_rotator_swts_create - create software timestamp buffer |
| 1125 | * @rot: Pointer to rotator hw |
| 1126 | * |
| 1127 | * This buffer is used by regdma to keep track of last completed command. |
| 1128 | */ |
| 1129 | static int sde_hw_rotator_swts_create(struct sde_hw_rotator *rot) |
| 1130 | { |
| 1131 | int rc = 0; |
| 1132 | struct ion_handle *handle; |
| 1133 | struct sde_mdp_img_data *data; |
| 1134 | u32 bufsize = sizeof(int) * SDE_HW_ROT_REGDMA_TOTAL_CTX * 2; |
| 1135 | |
| 1136 | rot->iclient = msm_ion_client_create(rot->pdev->name); |
| 1137 | if (IS_ERR_OR_NULL(rot->iclient)) { |
| 1138 | SDEROT_ERR("msm_ion_client_create() return error (%p)\n", |
| 1139 | rot->iclient); |
| 1140 | return -EINVAL; |
| 1141 | } |
| 1142 | |
| 1143 | handle = ion_alloc(rot->iclient, bufsize, SZ_4K, |
| 1144 | ION_HEAP(ION_SYSTEM_HEAP_ID), 0); |
| 1145 | if (IS_ERR_OR_NULL(handle)) { |
| 1146 | SDEROT_ERR("ion memory allocation failed\n"); |
| 1147 | return -ENOMEM; |
| 1148 | } |
| 1149 | |
| 1150 | data = &rot->swts_buf; |
| 1151 | data->len = bufsize; |
| 1152 | data->srcp_dma_buf = ion_share_dma_buf(rot->iclient, handle); |
| 1153 | if (IS_ERR(data->srcp_dma_buf)) { |
| 1154 | SDEROT_ERR("ion_dma_buf setup failed\n"); |
| 1155 | rc = -ENOMEM; |
| 1156 | goto imap_err; |
| 1157 | } |
| 1158 | |
| 1159 | sde_smmu_ctrl(1); |
| 1160 | |
| 1161 | data->srcp_attachment = sde_smmu_dma_buf_attach(data->srcp_dma_buf, |
| 1162 | &rot->pdev->dev, SDE_IOMMU_DOMAIN_ROT_UNSECURE); |
| 1163 | if (IS_ERR_OR_NULL(data->srcp_attachment)) { |
| 1164 | SDEROT_ERR("sde_smmu_dma_buf_attach error\n"); |
| 1165 | rc = -ENOMEM; |
| 1166 | goto err_put; |
| 1167 | } |
| 1168 | |
| 1169 | data->srcp_table = dma_buf_map_attachment(data->srcp_attachment, |
| 1170 | DMA_BIDIRECTIONAL); |
| 1171 | if (IS_ERR_OR_NULL(data->srcp_table)) { |
| 1172 | SDEROT_ERR("dma_buf_map_attachment error\n"); |
| 1173 | rc = -ENOMEM; |
| 1174 | goto err_detach; |
| 1175 | } |
| 1176 | |
| 1177 | rc = sde_smmu_map_dma_buf(data->srcp_dma_buf, data->srcp_table, |
| 1178 | SDE_IOMMU_DOMAIN_ROT_UNSECURE, &data->addr, |
| 1179 | &data->len, DMA_BIDIRECTIONAL); |
| 1180 | if (IS_ERR_VALUE(rc)) { |
| 1181 | SDEROT_ERR("smmu_map_dma_buf failed: (%d)\n", rc); |
| 1182 | goto err_unmap; |
| 1183 | } |
| 1184 | |
| 1185 | dma_buf_begin_cpu_access(data->srcp_dma_buf, 0, data->len, |
| 1186 | DMA_FROM_DEVICE); |
| 1187 | rot->swts_buffer = dma_buf_kmap(data->srcp_dma_buf, 0); |
| 1188 | if (IS_ERR_OR_NULL(rot->swts_buffer)) { |
| 1189 | SDEROT_ERR("ion kernel memory mapping failed\n"); |
| 1190 | rc = IS_ERR(rot->swts_buffer); |
| 1191 | goto kmap_err; |
| 1192 | } |
| 1193 | |
| 1194 | data->mapped = true; |
| 1195 | SDEROT_DBG("swts buffer mapped: %pad/%lx va:%p\n", &data->addr, |
| 1196 | data->len, rot->swts_buffer); |
| 1197 | |
| 1198 | ion_free(rot->iclient, handle); |
| 1199 | |
| 1200 | sde_smmu_ctrl(0); |
| 1201 | |
| 1202 | return rc; |
| 1203 | kmap_err: |
| 1204 | sde_smmu_unmap_dma_buf(data->srcp_table, SDE_IOMMU_DOMAIN_ROT_UNSECURE, |
| 1205 | DMA_FROM_DEVICE, data->srcp_dma_buf); |
| 1206 | err_unmap: |
| 1207 | dma_buf_unmap_attachment(data->srcp_attachment, data->srcp_table, |
| 1208 | DMA_FROM_DEVICE); |
| 1209 | err_detach: |
| 1210 | dma_buf_detach(data->srcp_dma_buf, data->srcp_attachment); |
| 1211 | err_put: |
| 1212 | dma_buf_put(data->srcp_dma_buf); |
| 1213 | data->srcp_dma_buf = NULL; |
| 1214 | imap_err: |
| 1215 | ion_free(rot->iclient, handle); |
| 1216 | |
| 1217 | return rc; |
| 1218 | } |
| 1219 | |
| 1220 | /* |
| 1221 | * sde_hw_rotator_swtc_destroy - destroy software timestamp buffer |
| 1222 | * @rot: Pointer to rotator hw |
| 1223 | */ |
| 1224 | static void sde_hw_rotator_swtc_destroy(struct sde_hw_rotator *rot) |
| 1225 | { |
| 1226 | struct sde_mdp_img_data *data; |
| 1227 | |
| 1228 | data = &rot->swts_buf; |
| 1229 | |
| 1230 | dma_buf_end_cpu_access(data->srcp_dma_buf, 0, data->len, |
| 1231 | DMA_FROM_DEVICE); |
| 1232 | dma_buf_kunmap(data->srcp_dma_buf, 0, rot->swts_buffer); |
| 1233 | |
| 1234 | sde_smmu_unmap_dma_buf(data->srcp_table, SDE_IOMMU_DOMAIN_ROT_UNSECURE, |
| 1235 | DMA_FROM_DEVICE, data->srcp_dma_buf); |
| 1236 | dma_buf_unmap_attachment(data->srcp_attachment, data->srcp_table, |
| 1237 | DMA_FROM_DEVICE); |
| 1238 | dma_buf_detach(data->srcp_dma_buf, data->srcp_attachment); |
| 1239 | dma_buf_put(data->srcp_dma_buf); |
| 1240 | data->srcp_dma_buf = NULL; |
| 1241 | } |
| 1242 | |
| 1243 | /* |
Benjamin Chan | 0f9e61d | 2016-09-16 16:01:09 -0400 | [diff] [blame] | 1244 | * sde_hw_rotator_pre_pmevent - SDE rotator core will call this before a |
| 1245 | * PM event occurs |
| 1246 | * @mgr: Pointer to rotator manager |
| 1247 | * @pmon: Boolean indicate an on/off power event |
| 1248 | */ |
| 1249 | void sde_hw_rotator_pre_pmevent(struct sde_rot_mgr *mgr, bool pmon) |
| 1250 | { |
| 1251 | struct sde_hw_rotator *rot; |
| 1252 | u32 l_ts, h_ts, swts, hwts; |
| 1253 | u32 rotsts, regdmasts; |
| 1254 | |
| 1255 | /* |
| 1256 | * Check last HW timestamp with SW timestamp before power off event. |
| 1257 | * If there is a mismatch, that will be quite possible the rotator HW |
| 1258 | * is either hang or not finishing last submitted job. In that case, |
| 1259 | * it is best to do a timeout eventlog to capture some good events |
| 1260 | * log data for analysis. |
| 1261 | */ |
| 1262 | if (!pmon && mgr && mgr->hw_data) { |
| 1263 | rot = mgr->hw_data; |
| 1264 | h_ts = atomic_read(&rot->timestamp[ROT_QUEUE_HIGH_PRIORITY]); |
| 1265 | l_ts = atomic_read(&rot->timestamp[ROT_QUEUE_LOW_PRIORITY]); |
| 1266 | |
| 1267 | /* contruct the combined timstamp */ |
| 1268 | swts = (h_ts & SDE_REGDMA_SWTS_MASK) | |
| 1269 | ((l_ts & SDE_REGDMA_SWTS_MASK) << |
| 1270 | SDE_REGDMA_SWTS_SHIFT); |
| 1271 | |
| 1272 | /* Need to turn on clock to access rotator register */ |
| 1273 | sde_rotator_clk_ctrl(mgr, true); |
| 1274 | hwts = SDE_ROTREG_READ(rot->mdss_base, REGDMA_TIMESTAMP_REG); |
| 1275 | regdmasts = SDE_ROTREG_READ(rot->mdss_base, |
| 1276 | REGDMA_CSR_REGDMA_BLOCK_STATUS); |
| 1277 | rotsts = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_STATUS); |
| 1278 | |
| 1279 | SDEROT_DBG( |
| 1280 | "swts:0x%x, hwts:0x%x, regdma-sts:0x%x, rottop-sts:0x%x\n", |
| 1281 | swts, hwts, regdmasts, rotsts); |
| 1282 | SDEROT_EVTLOG(swts, hwts, regdmasts, rotsts); |
| 1283 | |
| 1284 | if ((swts != hwts) && ((regdmasts & REGDMA_BUSY) || |
| 1285 | (rotsts & ROT_STATUS_MASK))) { |
| 1286 | SDEROT_ERR( |
| 1287 | "Mismatch SWTS with HWTS: swts:0x%x, hwts:0x%x, regdma-sts:0x%x, rottop-sts:0x%x\n", |
| 1288 | swts, hwts, regdmasts, rotsts); |
| 1289 | SDEROT_EVTLOG_TOUT_HANDLER("rot", "vbif_dbg_bus", |
| 1290 | "panic"); |
| 1291 | } |
| 1292 | |
| 1293 | /* Turn off rotator clock after checking rotator registers */ |
| 1294 | sde_rotator_clk_ctrl(mgr, false); |
| 1295 | } |
| 1296 | } |
| 1297 | |
| 1298 | /* |
| 1299 | * sde_hw_rotator_post_pmevent - SDE rotator core will call this after a |
| 1300 | * PM event occurs |
| 1301 | * @mgr: Pointer to rotator manager |
| 1302 | * @pmon: Boolean indicate an on/off power event |
| 1303 | */ |
| 1304 | void sde_hw_rotator_post_pmevent(struct sde_rot_mgr *mgr, bool pmon) |
| 1305 | { |
| 1306 | struct sde_hw_rotator *rot; |
| 1307 | u32 l_ts, h_ts, swts; |
| 1308 | |
| 1309 | /* |
| 1310 | * After a power on event, the rotator HW is reset to default setting. |
| 1311 | * It is necessary to synchronize the SW timestamp with the HW. |
| 1312 | */ |
| 1313 | if (pmon && mgr && mgr->hw_data) { |
| 1314 | rot = mgr->hw_data; |
| 1315 | h_ts = atomic_read(&rot->timestamp[ROT_QUEUE_HIGH_PRIORITY]); |
| 1316 | l_ts = atomic_read(&rot->timestamp[ROT_QUEUE_LOW_PRIORITY]); |
| 1317 | |
| 1318 | /* contruct the combined timstamp */ |
| 1319 | swts = (h_ts & SDE_REGDMA_SWTS_MASK) | |
| 1320 | ((l_ts & SDE_REGDMA_SWTS_MASK) << |
| 1321 | SDE_REGDMA_SWTS_SHIFT); |
| 1322 | |
| 1323 | SDEROT_DBG("swts:0x%x, h_ts:0x%x, l_ts;0x%x\n", |
| 1324 | swts, h_ts, l_ts); |
| 1325 | SDEROT_EVTLOG(swts, h_ts, l_ts); |
| 1326 | rot->reset_hw_ts = true; |
| 1327 | rot->last_hw_ts = swts; |
| 1328 | } |
| 1329 | } |
| 1330 | |
| 1331 | /* |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1332 | * sde_hw_rotator_destroy - Destroy hw rotator and free allocated resources |
| 1333 | * @mgr: Pointer to rotator manager |
| 1334 | */ |
| 1335 | static void sde_hw_rotator_destroy(struct sde_rot_mgr *mgr) |
| 1336 | { |
| 1337 | struct sde_rot_data_type *mdata = sde_rot_get_mdata(); |
| 1338 | struct sde_hw_rotator *rot; |
| 1339 | |
| 1340 | if (!mgr || !mgr->pdev || !mgr->hw_data) { |
| 1341 | SDEROT_ERR("null parameters\n"); |
| 1342 | return; |
| 1343 | } |
| 1344 | |
| 1345 | rot = mgr->hw_data; |
| 1346 | if (rot->irq_num >= 0) |
| 1347 | devm_free_irq(&mgr->pdev->dev, rot->irq_num, mdata); |
| 1348 | |
| 1349 | if (rot->mode == ROT_REGDMA_ON) |
| 1350 | sde_hw_rotator_swtc_destroy(rot); |
| 1351 | |
| 1352 | devm_kfree(&mgr->pdev->dev, mgr->hw_data); |
| 1353 | mgr->hw_data = NULL; |
| 1354 | } |
| 1355 | |
| 1356 | /* |
| 1357 | * sde_hw_rotator_alloc_ext - allocate rotator resource from rotator hw |
| 1358 | * @mgr: Pointer to rotator manager |
| 1359 | * @pipe_id: pipe identifier (not used) |
| 1360 | * @wb_id: writeback identifier/priority queue identifier |
| 1361 | * |
| 1362 | * This function allocates a new hw rotator resource for the given priority. |
| 1363 | */ |
| 1364 | static struct sde_rot_hw_resource *sde_hw_rotator_alloc_ext( |
| 1365 | struct sde_rot_mgr *mgr, u32 pipe_id, u32 wb_id) |
| 1366 | { |
| 1367 | struct sde_hw_rotator_resource_info *resinfo; |
| 1368 | |
| 1369 | if (!mgr || !mgr->hw_data) { |
| 1370 | SDEROT_ERR("null parameters\n"); |
| 1371 | return NULL; |
| 1372 | } |
| 1373 | |
| 1374 | /* |
| 1375 | * Allocate rotator resource info. Each allocation is per |
| 1376 | * HW priority queue |
| 1377 | */ |
| 1378 | resinfo = devm_kzalloc(&mgr->pdev->dev, sizeof(*resinfo), GFP_KERNEL); |
| 1379 | if (!resinfo) { |
| 1380 | SDEROT_ERR("Failed allocation HW rotator resource info\n"); |
| 1381 | return NULL; |
| 1382 | } |
| 1383 | |
| 1384 | resinfo->rot = mgr->hw_data; |
| 1385 | resinfo->hw.wb_id = wb_id; |
| 1386 | atomic_set(&resinfo->hw.num_active, 0); |
| 1387 | init_waitqueue_head(&resinfo->hw.wait_queue); |
| 1388 | |
| 1389 | /* For non-regdma, only support one active session */ |
| 1390 | if (resinfo->rot->mode == ROT_REGDMA_OFF) |
| 1391 | resinfo->hw.max_active = 1; |
| 1392 | else { |
| 1393 | resinfo->hw.max_active = SDE_HW_ROT_REGDMA_TOTAL_CTX - 1; |
| 1394 | |
| 1395 | if (resinfo->rot->iclient == NULL) |
| 1396 | sde_hw_rotator_swts_create(resinfo->rot); |
| 1397 | } |
| 1398 | |
Alan Kwong | f987ea3 | 2016-07-06 12:11:44 -0400 | [diff] [blame] | 1399 | if (resinfo->rot->irq_num >= 0) |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1400 | sde_hw_rotator_enable_irq(resinfo->rot); |
Alan Kwong | f987ea3 | 2016-07-06 12:11:44 -0400 | [diff] [blame] | 1401 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1402 | SDEROT_DBG("New rotator resource:%p, priority:%d\n", |
| 1403 | resinfo, wb_id); |
| 1404 | |
| 1405 | return &resinfo->hw; |
| 1406 | } |
| 1407 | |
| 1408 | /* |
| 1409 | * sde_hw_rotator_free_ext - free the given rotator resource |
| 1410 | * @mgr: Pointer to rotator manager |
| 1411 | * @hw: Pointer to rotator resource |
| 1412 | */ |
| 1413 | static void sde_hw_rotator_free_ext(struct sde_rot_mgr *mgr, |
| 1414 | struct sde_rot_hw_resource *hw) |
| 1415 | { |
| 1416 | struct sde_hw_rotator_resource_info *resinfo; |
| 1417 | |
| 1418 | if (!mgr || !mgr->hw_data) |
| 1419 | return; |
| 1420 | |
| 1421 | resinfo = container_of(hw, struct sde_hw_rotator_resource_info, hw); |
| 1422 | |
| 1423 | SDEROT_DBG( |
| 1424 | "Free rotator resource:%p, priority:%d, active:%d, pending:%d\n", |
| 1425 | resinfo, hw->wb_id, atomic_read(&hw->num_active), |
| 1426 | hw->pending_count); |
| 1427 | |
Alan Kwong | f987ea3 | 2016-07-06 12:11:44 -0400 | [diff] [blame] | 1428 | if (resinfo->rot->irq_num >= 0) |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1429 | sde_hw_rotator_disable_irq(resinfo->rot); |
Alan Kwong | f987ea3 | 2016-07-06 12:11:44 -0400 | [diff] [blame] | 1430 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1431 | devm_kfree(&mgr->pdev->dev, resinfo); |
| 1432 | } |
| 1433 | |
| 1434 | /* |
| 1435 | * sde_hw_rotator_alloc_rotctx - allocate rotator context |
| 1436 | * @rot: Pointer to rotator hw |
| 1437 | * @hw: Pointer to rotator resource |
| 1438 | * @session_id: Session identifier of this context |
| 1439 | * |
| 1440 | * This function allocates a new rotator context for the given session id. |
| 1441 | */ |
| 1442 | static struct sde_hw_rotator_context *sde_hw_rotator_alloc_rotctx( |
| 1443 | struct sde_hw_rotator *rot, |
| 1444 | struct sde_rot_hw_resource *hw, |
| 1445 | u32 session_id) |
| 1446 | { |
| 1447 | struct sde_hw_rotator_context *ctx; |
| 1448 | |
| 1449 | /* Allocate rotator context */ |
| 1450 | ctx = devm_kzalloc(&rot->pdev->dev, sizeof(*ctx), GFP_KERNEL); |
| 1451 | if (!ctx) { |
| 1452 | SDEROT_ERR("Failed allocation HW rotator context\n"); |
| 1453 | return NULL; |
| 1454 | } |
| 1455 | |
| 1456 | ctx->rot = rot; |
| 1457 | ctx->q_id = hw->wb_id; |
| 1458 | ctx->session_id = session_id; |
| 1459 | ctx->hwres = hw; |
| 1460 | ctx->timestamp = atomic_add_return(1, &rot->timestamp[ctx->q_id]); |
| 1461 | ctx->timestamp &= SDE_REGDMA_SWTS_MASK; |
| 1462 | ctx->is_secure = false; |
| 1463 | |
| 1464 | ctx->regdma_base = rot->cmd_wr_ptr[ctx->q_id] |
| 1465 | [sde_hw_rotator_get_regdma_ctxidx(ctx)]; |
| 1466 | ctx->regdma_wrptr = ctx->regdma_base; |
| 1467 | ctx->ts_addr = (dma_addr_t)((u32 *)rot->swts_buf.addr + |
| 1468 | ctx->q_id * SDE_HW_ROT_REGDMA_TOTAL_CTX + |
| 1469 | sde_hw_rotator_get_regdma_ctxidx(ctx)); |
| 1470 | |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1471 | ctx->last_regdma_timestamp = SDE_REGDMA_SWTS_INVALID; |
| 1472 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1473 | init_completion(&ctx->rot_comp); |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1474 | init_waitqueue_head(&ctx->regdma_waitq); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1475 | |
| 1476 | /* Store rotator context for lookup purpose */ |
| 1477 | sde_hw_rotator_put_ctx(ctx); |
| 1478 | |
| 1479 | SDEROT_DBG( |
| 1480 | "New rot CTX:%p, ctxidx:%d, session-id:%d, prio:%d, timestamp:%X, active:%d\n", |
| 1481 | ctx, sde_hw_rotator_get_regdma_ctxidx(ctx), ctx->session_id, |
| 1482 | ctx->q_id, ctx->timestamp, |
| 1483 | atomic_read(&ctx->hwres->num_active)); |
| 1484 | |
| 1485 | return ctx; |
| 1486 | } |
| 1487 | |
| 1488 | /* |
| 1489 | * sde_hw_rotator_free_rotctx - free the given rotator context |
| 1490 | * @rot: Pointer to rotator hw |
| 1491 | * @ctx: Pointer to rotator context |
| 1492 | */ |
| 1493 | static void sde_hw_rotator_free_rotctx(struct sde_hw_rotator *rot, |
| 1494 | struct sde_hw_rotator_context *ctx) |
| 1495 | { |
| 1496 | if (!rot || !ctx) |
| 1497 | return; |
| 1498 | |
| 1499 | SDEROT_DBG( |
| 1500 | "Free rot CTX:%p, ctxidx:%d, session-id:%d, prio:%d, timestamp:%X, active:%d\n", |
| 1501 | ctx, sde_hw_rotator_get_regdma_ctxidx(ctx), ctx->session_id, |
| 1502 | ctx->q_id, ctx->timestamp, |
| 1503 | atomic_read(&ctx->hwres->num_active)); |
| 1504 | |
| 1505 | rot->rotCtx[ctx->q_id][sde_hw_rotator_get_regdma_ctxidx(ctx)] = NULL; |
| 1506 | |
| 1507 | devm_kfree(&rot->pdev->dev, ctx); |
| 1508 | } |
| 1509 | |
| 1510 | /* |
| 1511 | * sde_hw_rotator_config - configure hw for the given rotation entry |
| 1512 | * @hw: Pointer to rotator resource |
| 1513 | * @entry: Pointer to rotation entry |
| 1514 | * |
| 1515 | * This function setup the fetch/writeback/rotator blocks, as well as VBIF |
| 1516 | * based on the given rotation entry. |
| 1517 | */ |
| 1518 | static int sde_hw_rotator_config(struct sde_rot_hw_resource *hw, |
| 1519 | struct sde_rot_entry *entry) |
| 1520 | { |
| 1521 | struct sde_rot_data_type *mdata = sde_rot_get_mdata(); |
| 1522 | struct sde_hw_rotator *rot; |
| 1523 | struct sde_hw_rotator_resource_info *resinfo; |
| 1524 | struct sde_hw_rotator_context *ctx; |
| 1525 | struct sde_hw_rot_sspp_cfg sspp_cfg; |
| 1526 | struct sde_hw_rot_wb_cfg wb_cfg; |
| 1527 | u32 danger_lut = 0; /* applicable for realtime client only */ |
| 1528 | u32 safe_lut = 0; /* applicable for realtime client only */ |
| 1529 | u32 flags = 0; |
| 1530 | struct sde_rotation_item *item; |
| 1531 | |
| 1532 | if (!hw || !entry) { |
| 1533 | SDEROT_ERR("null hw resource/entry\n"); |
| 1534 | return -EINVAL; |
| 1535 | } |
| 1536 | |
| 1537 | resinfo = container_of(hw, struct sde_hw_rotator_resource_info, hw); |
| 1538 | rot = resinfo->rot; |
| 1539 | item = &entry->item; |
| 1540 | |
| 1541 | ctx = sde_hw_rotator_alloc_rotctx(rot, hw, item->session_id); |
| 1542 | if (!ctx) { |
| 1543 | SDEROT_ERR("Failed allocating rotator context!!\n"); |
| 1544 | return -EINVAL; |
| 1545 | } |
| 1546 | |
Benjamin Chan | 0f9e61d | 2016-09-16 16:01:09 -0400 | [diff] [blame] | 1547 | if (rot->reset_hw_ts) { |
| 1548 | SDEROT_EVTLOG(rot->last_hw_ts); |
| 1549 | SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_TIMESTAMP_REG, |
| 1550 | rot->last_hw_ts); |
| 1551 | /* ensure write is issued to the rotator HW */ |
| 1552 | wmb(); |
| 1553 | rot->reset_hw_ts = false; |
| 1554 | } |
| 1555 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1556 | flags = (item->flags & SDE_ROTATION_FLIP_LR) ? |
| 1557 | SDE_ROT_FLAG_FLIP_LR : 0; |
| 1558 | flags |= (item->flags & SDE_ROTATION_FLIP_UD) ? |
| 1559 | SDE_ROT_FLAG_FLIP_UD : 0; |
| 1560 | flags |= (item->flags & SDE_ROTATION_90) ? |
| 1561 | SDE_ROT_FLAG_ROT_90 : 0; |
| 1562 | flags |= (item->flags & SDE_ROTATION_DEINTERLACE) ? |
| 1563 | SDE_ROT_FLAG_DEINTERLACE : 0; |
| 1564 | flags |= (item->flags & SDE_ROTATION_SECURE) ? |
| 1565 | SDE_ROT_FLAG_SECURE_OVERLAY_SESSION : 0; |
| 1566 | |
| 1567 | sspp_cfg.img_width = item->input.width; |
| 1568 | sspp_cfg.img_height = item->input.height; |
| 1569 | sspp_cfg.fmt = sde_get_format_params(item->input.format); |
| 1570 | if (!sspp_cfg.fmt) { |
| 1571 | SDEROT_ERR("null format\n"); |
| 1572 | return -EINVAL; |
| 1573 | } |
| 1574 | sspp_cfg.src_rect = &item->src_rect; |
| 1575 | sspp_cfg.data = &entry->src_buf; |
| 1576 | sde_mdp_get_plane_sizes(sspp_cfg.fmt, item->input.width, |
| 1577 | item->input.height, &sspp_cfg.src_plane, |
| 1578 | 0, /* No bwc_mode */ |
| 1579 | (flags & SDE_ROT_FLAG_SOURCE_ROTATED_90) ? |
| 1580 | true : false); |
| 1581 | |
| 1582 | rot->ops.setup_rotator_fetchengine(ctx, ctx->q_id, |
Benjamin Chan | fb6faa3 | 2016-08-16 17:21:01 -0400 | [diff] [blame] | 1583 | &sspp_cfg, danger_lut, safe_lut, |
| 1584 | entry->dnsc_factor_w, entry->dnsc_factor_h, flags); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1585 | |
| 1586 | wb_cfg.img_width = item->output.width; |
| 1587 | wb_cfg.img_height = item->output.height; |
| 1588 | wb_cfg.fmt = sde_get_format_params(item->output.format); |
| 1589 | wb_cfg.dst_rect = &item->dst_rect; |
| 1590 | wb_cfg.data = &entry->dst_buf; |
| 1591 | sde_mdp_get_plane_sizes(wb_cfg.fmt, item->output.width, |
| 1592 | item->output.height, &wb_cfg.dst_plane, |
| 1593 | 0, /* No bwc_mode */ |
| 1594 | (flags & SDE_ROT_FLAG_ROT_90) ? true : false); |
| 1595 | |
| 1596 | wb_cfg.v_downscale_factor = entry->dnsc_factor_h; |
| 1597 | wb_cfg.h_downscale_factor = entry->dnsc_factor_w; |
| 1598 | |
| 1599 | rot->ops.setup_rotator_wbengine(ctx, ctx->q_id, &wb_cfg, flags); |
| 1600 | |
| 1601 | /* setup VA mapping for debugfs */ |
| 1602 | if (rot->dbgmem) { |
| 1603 | sde_hw_rotator_map_vaddr(&ctx->src_dbgbuf, |
| 1604 | &item->input, |
| 1605 | &entry->src_buf); |
| 1606 | |
| 1607 | sde_hw_rotator_map_vaddr(&ctx->dst_dbgbuf, |
| 1608 | &item->output, |
| 1609 | &entry->dst_buf); |
| 1610 | } |
| 1611 | |
Benjamin Chan | 0f9e61d | 2016-09-16 16:01:09 -0400 | [diff] [blame] | 1612 | SDEROT_EVTLOG(ctx->timestamp, flags, |
| 1613 | item->input.width, item->input.height, |
Benjamin Chan | 53e3bce | 2016-08-31 14:43:29 -0400 | [diff] [blame] | 1614 | item->output.width, item->output.height, |
| 1615 | entry->src_buf.p[0].addr, entry->dst_buf.p[0].addr); |
| 1616 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1617 | if (mdata->default_ot_rd_limit) { |
| 1618 | struct sde_mdp_set_ot_params ot_params; |
| 1619 | |
| 1620 | memset(&ot_params, 0, sizeof(struct sde_mdp_set_ot_params)); |
| 1621 | ot_params.xin_id = XIN_SSPP; |
| 1622 | ot_params.num = 0; /* not used */ |
Alan Kwong | effb5ee | 2016-03-12 19:47:45 -0500 | [diff] [blame] | 1623 | ot_params.width = entry->perf->config.input.width; |
| 1624 | ot_params.height = entry->perf->config.input.height; |
| 1625 | ot_params.fps = entry->perf->config.frame_rate; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1626 | ot_params.reg_off_vbif_lim_conf = MMSS_VBIF_RD_LIM_CONF; |
| 1627 | ot_params.reg_off_mdp_clk_ctrl = |
| 1628 | MMSS_VBIF_NRT_VBIF_CLK_FORCE_CTRL0; |
| 1629 | ot_params.bit_off_mdp_clk_ctrl = |
| 1630 | MMSS_VBIF_NRT_VBIF_CLK_FORCE_CTRL0_XIN0; |
Alan Kwong | effb5ee | 2016-03-12 19:47:45 -0500 | [diff] [blame] | 1631 | ot_params.fmt = entry->perf->config.input.format; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1632 | sde_mdp_set_ot_limit(&ot_params); |
| 1633 | } |
| 1634 | |
| 1635 | if (mdata->default_ot_wr_limit) { |
| 1636 | struct sde_mdp_set_ot_params ot_params; |
| 1637 | |
| 1638 | memset(&ot_params, 0, sizeof(struct sde_mdp_set_ot_params)); |
| 1639 | ot_params.xin_id = XIN_WRITEBACK; |
| 1640 | ot_params.num = 0; /* not used */ |
Alan Kwong | effb5ee | 2016-03-12 19:47:45 -0500 | [diff] [blame] | 1641 | ot_params.width = entry->perf->config.input.width; |
| 1642 | ot_params.height = entry->perf->config.input.height; |
| 1643 | ot_params.fps = entry->perf->config.frame_rate; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1644 | ot_params.reg_off_vbif_lim_conf = MMSS_VBIF_WR_LIM_CONF; |
| 1645 | ot_params.reg_off_mdp_clk_ctrl = |
| 1646 | MMSS_VBIF_NRT_VBIF_CLK_FORCE_CTRL0; |
| 1647 | ot_params.bit_off_mdp_clk_ctrl = |
| 1648 | MMSS_VBIF_NRT_VBIF_CLK_FORCE_CTRL0_XIN1; |
Alan Kwong | effb5ee | 2016-03-12 19:47:45 -0500 | [diff] [blame] | 1649 | ot_params.fmt = entry->perf->config.input.format; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1650 | sde_mdp_set_ot_limit(&ot_params); |
| 1651 | } |
| 1652 | |
| 1653 | if (test_bit(SDE_QOS_PER_PIPE_LUT, mdata->sde_qos_map)) { |
| 1654 | u32 qos_lut = 0; /* low priority for nrt read client */ |
| 1655 | |
| 1656 | trace_rot_perf_set_qos_luts(XIN_SSPP, sspp_cfg.fmt->format, |
| 1657 | qos_lut, sde_mdp_is_linear_format(sspp_cfg.fmt)); |
| 1658 | |
| 1659 | SDE_ROTREG_WRITE(rot->mdss_base, ROT_SSPP_CREQ_LUT, qos_lut); |
| 1660 | } |
| 1661 | |
| 1662 | if (mdata->npriority_lvl > 0) { |
| 1663 | u32 mask, reg_val, i, vbif_qos; |
| 1664 | |
| 1665 | for (i = 0; i < mdata->npriority_lvl; i++) { |
| 1666 | reg_val = SDE_VBIF_READ(mdata, |
| 1667 | MMSS_VBIF_NRT_VBIF_QOS_REMAP_00 + i*4); |
| 1668 | mask = 0x3 << (XIN_SSPP * 2); |
| 1669 | reg_val &= ~(mask); |
| 1670 | vbif_qos = mdata->vbif_nrt_qos[i]; |
| 1671 | reg_val |= vbif_qos << (XIN_SSPP * 2); |
| 1672 | /* ensure write is issued after the read operation */ |
| 1673 | mb(); |
| 1674 | SDE_VBIF_WRITE(mdata, |
| 1675 | MMSS_VBIF_NRT_VBIF_QOS_REMAP_00 + i*4, |
| 1676 | reg_val); |
| 1677 | } |
| 1678 | } |
| 1679 | |
| 1680 | /* Enable write gather for writeback to remove write gaps, which |
| 1681 | * may hang AXI/BIMC/SDE. |
| 1682 | */ |
| 1683 | SDE_VBIF_WRITE(mdata, MMSS_VBIF_NRT_VBIF_WRITE_GATHTER_EN, |
| 1684 | BIT(XIN_WRITEBACK)); |
| 1685 | |
| 1686 | return 0; |
| 1687 | } |
| 1688 | |
| 1689 | /* |
| 1690 | * sde_hw_rotator_kickoff - kickoff processing on the given entry |
| 1691 | * @hw: Pointer to rotator resource |
| 1692 | * @entry: Pointer to rotation entry |
| 1693 | */ |
| 1694 | static int sde_hw_rotator_kickoff(struct sde_rot_hw_resource *hw, |
| 1695 | struct sde_rot_entry *entry) |
| 1696 | { |
| 1697 | struct sde_hw_rotator *rot; |
| 1698 | struct sde_hw_rotator_resource_info *resinfo; |
| 1699 | struct sde_hw_rotator_context *ctx; |
| 1700 | int ret = 0; |
| 1701 | |
| 1702 | if (!hw || !entry) { |
| 1703 | SDEROT_ERR("null hw resource/entry\n"); |
| 1704 | return -EINVAL; |
| 1705 | } |
| 1706 | |
| 1707 | resinfo = container_of(hw, struct sde_hw_rotator_resource_info, hw); |
| 1708 | rot = resinfo->rot; |
| 1709 | |
| 1710 | /* Lookup rotator context from session-id */ |
| 1711 | ctx = sde_hw_rotator_get_ctx(rot, entry->item.session_id, hw->wb_id); |
| 1712 | if (!ctx) { |
| 1713 | SDEROT_ERR("Cannot locate rotator ctx from sesison id:%d\n", |
| 1714 | entry->item.session_id); |
Benjamin Chan | 62b94ed | 2016-08-18 23:55:21 -0400 | [diff] [blame] | 1715 | return -EINVAL; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1716 | } |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1717 | |
| 1718 | ret = sde_smmu_ctrl(1); |
| 1719 | if (IS_ERR_VALUE(ret)) { |
| 1720 | SDEROT_ERR("IOMMU attach failed\n"); |
| 1721 | return ret; |
| 1722 | } |
| 1723 | |
| 1724 | rot->ops.start_rotator(ctx, ctx->q_id); |
| 1725 | |
| 1726 | return 0; |
| 1727 | } |
| 1728 | |
| 1729 | /* |
| 1730 | * sde_hw_rotator_wait4done - wait for completion notification |
| 1731 | * @hw: Pointer to rotator resource |
| 1732 | * @entry: Pointer to rotation entry |
| 1733 | * |
| 1734 | * This function blocks until the given entry is complete, error |
| 1735 | * is detected, or timeout. |
| 1736 | */ |
| 1737 | static int sde_hw_rotator_wait4done(struct sde_rot_hw_resource *hw, |
| 1738 | struct sde_rot_entry *entry) |
| 1739 | { |
| 1740 | struct sde_hw_rotator *rot; |
| 1741 | struct sde_hw_rotator_resource_info *resinfo; |
| 1742 | struct sde_hw_rotator_context *ctx; |
| 1743 | int ret; |
| 1744 | |
| 1745 | if (!hw || !entry) { |
| 1746 | SDEROT_ERR("null hw resource/entry\n"); |
| 1747 | return -EINVAL; |
| 1748 | } |
| 1749 | |
| 1750 | resinfo = container_of(hw, struct sde_hw_rotator_resource_info, hw); |
| 1751 | rot = resinfo->rot; |
| 1752 | |
| 1753 | /* Lookup rotator context from session-id */ |
| 1754 | ctx = sde_hw_rotator_get_ctx(rot, entry->item.session_id, hw->wb_id); |
| 1755 | if (!ctx) { |
| 1756 | SDEROT_ERR("Cannot locate rotator ctx from sesison id:%d\n", |
| 1757 | entry->item.session_id); |
Benjamin Chan | 62b94ed | 2016-08-18 23:55:21 -0400 | [diff] [blame] | 1758 | return -EINVAL; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1759 | } |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1760 | |
| 1761 | ret = rot->ops.wait_rotator_done(ctx, ctx->q_id, 0); |
| 1762 | |
| 1763 | sde_smmu_ctrl(0); |
| 1764 | |
| 1765 | if (rot->dbgmem) { |
| 1766 | sde_hw_rotator_unmap_vaddr(&ctx->src_dbgbuf); |
| 1767 | sde_hw_rotator_unmap_vaddr(&ctx->dst_dbgbuf); |
| 1768 | } |
| 1769 | |
| 1770 | /* Current rotator context job is finished, time to free up*/ |
| 1771 | sde_hw_rotator_free_rotctx(rot, ctx); |
| 1772 | |
| 1773 | return ret; |
| 1774 | } |
| 1775 | |
| 1776 | /* |
| 1777 | * sde_rotator_hw_rev_init - setup feature and/or capability bitmask |
| 1778 | * @rot: Pointer to hw rotator |
| 1779 | * |
| 1780 | * This function initializes feature and/or capability bitmask based on |
| 1781 | * h/w version read from the device. |
| 1782 | */ |
| 1783 | static int sde_rotator_hw_rev_init(struct sde_hw_rotator *rot) |
| 1784 | { |
| 1785 | struct sde_rot_data_type *mdata = sde_rot_get_mdata(); |
| 1786 | u32 hw_version; |
| 1787 | |
| 1788 | if (!mdata) { |
| 1789 | SDEROT_ERR("null rotator data\n"); |
| 1790 | return -EINVAL; |
| 1791 | } |
| 1792 | |
| 1793 | hw_version = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_HW_VERSION); |
| 1794 | SDEROT_DBG("hw version %8.8x\n", hw_version); |
| 1795 | |
| 1796 | clear_bit(SDE_QOS_PER_PIPE_IB, mdata->sde_qos_map); |
| 1797 | set_bit(SDE_QOS_OVERHEAD_FACTOR, mdata->sde_qos_map); |
| 1798 | clear_bit(SDE_QOS_CDP, mdata->sde_qos_map); |
| 1799 | set_bit(SDE_QOS_OTLIM, mdata->sde_qos_map); |
| 1800 | set_bit(SDE_QOS_PER_PIPE_LUT, mdata->sde_qos_map); |
| 1801 | clear_bit(SDE_QOS_SIMPLIFIED_PREFILL, mdata->sde_qos_map); |
| 1802 | |
| 1803 | set_bit(SDE_CAPS_R3_WB, mdata->sde_caps_map); |
| 1804 | |
Benjamin Chan | fb6faa3 | 2016-08-16 17:21:01 -0400 | [diff] [blame] | 1805 | if (hw_version != SDE_ROT_TYPE_V1_0) { |
| 1806 | SDEROT_DBG("Supporting 1.5 downscale for SDE Rotator\n"); |
| 1807 | set_bit(SDE_CAPS_R3_1P5_DOWNSCALE, mdata->sde_caps_map); |
| 1808 | } |
| 1809 | |
Benjamin Chan | 53e3bce | 2016-08-31 14:43:29 -0400 | [diff] [blame] | 1810 | mdata->nrt_vbif_dbg_bus = nrt_vbif_dbg_bus_r3; |
| 1811 | mdata->nrt_vbif_dbg_bus_size = |
| 1812 | ARRAY_SIZE(nrt_vbif_dbg_bus_r3); |
| 1813 | |
| 1814 | mdata->regdump = sde_rot_r3_regdump; |
| 1815 | mdata->regdump_size = ARRAY_SIZE(sde_rot_r3_regdump); |
| 1816 | |
Benjamin Chan | 0f9e61d | 2016-09-16 16:01:09 -0400 | [diff] [blame] | 1817 | SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_TIMESTAMP_REG, 0); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1818 | return 0; |
| 1819 | } |
| 1820 | |
| 1821 | /* |
| 1822 | * sde_hw_rotator_rotirq_handler - non-regdma interrupt handler |
| 1823 | * @irq: Interrupt number |
| 1824 | * @ptr: Pointer to private handle provided during registration |
| 1825 | * |
| 1826 | * This function services rotator interrupt and wakes up waiting client |
| 1827 | * with pending rotation requests already submitted to h/w. |
| 1828 | */ |
| 1829 | static irqreturn_t sde_hw_rotator_rotirq_handler(int irq, void *ptr) |
| 1830 | { |
| 1831 | struct sde_hw_rotator *rot = ptr; |
| 1832 | struct sde_hw_rotator_context *ctx; |
| 1833 | irqreturn_t ret = IRQ_NONE; |
| 1834 | u32 isr; |
| 1835 | |
| 1836 | isr = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_INTR_STATUS); |
| 1837 | |
| 1838 | SDEROT_DBG("intr_status = %8.8x\n", isr); |
| 1839 | |
| 1840 | if (isr & ROT_DONE_MASK) { |
| 1841 | if (rot->irq_num >= 0) |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1842 | sde_hw_rotator_disable_irq(rot); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1843 | SDEROT_DBG("Notify rotator complete\n"); |
| 1844 | |
| 1845 | /* Normal rotator only 1 session, no need to lookup */ |
| 1846 | ctx = rot->rotCtx[0][0]; |
| 1847 | WARN_ON(ctx == NULL); |
| 1848 | complete_all(&ctx->rot_comp); |
| 1849 | |
| 1850 | spin_lock(&rot->rotisr_lock); |
| 1851 | SDE_ROTREG_WRITE(rot->mdss_base, ROTTOP_INTR_CLEAR, |
| 1852 | ROT_DONE_CLEAR); |
| 1853 | spin_unlock(&rot->rotisr_lock); |
| 1854 | ret = IRQ_HANDLED; |
| 1855 | } |
| 1856 | |
| 1857 | return ret; |
| 1858 | } |
| 1859 | |
| 1860 | /* |
| 1861 | * sde_hw_rotator_regdmairq_handler - regdma interrupt handler |
| 1862 | * @irq: Interrupt number |
| 1863 | * @ptr: Pointer to private handle provided during registration |
| 1864 | * |
| 1865 | * This function services rotator interrupt, decoding the source of |
| 1866 | * events (high/low priority queue), and wakes up all waiting clients |
| 1867 | * with pending rotation requests already submitted to h/w. |
| 1868 | */ |
| 1869 | static irqreturn_t sde_hw_rotator_regdmairq_handler(int irq, void *ptr) |
| 1870 | { |
| 1871 | struct sde_hw_rotator *rot = ptr; |
| 1872 | struct sde_hw_rotator_context *ctx; |
| 1873 | irqreturn_t ret = IRQ_NONE; |
| 1874 | u32 isr; |
| 1875 | u32 ts; |
| 1876 | u32 q_id; |
| 1877 | |
| 1878 | isr = SDE_ROTREG_READ(rot->mdss_base, REGDMA_CSR_REGDMA_INT_STATUS); |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1879 | /* acknowledge interrupt before reading latest timestamp */ |
| 1880 | SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_CSR_REGDMA_INT_CLEAR, isr); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1881 | ts = SDE_ROTREG_READ(rot->mdss_base, REGDMA_TIMESTAMP_REG); |
| 1882 | |
| 1883 | SDEROT_DBG("intr_status = %8.8x, sw_TS:%X\n", isr, ts); |
| 1884 | |
| 1885 | /* Any REGDMA status, including error and watchdog timer, should |
| 1886 | * trigger and wake up waiting thread |
| 1887 | */ |
| 1888 | if (isr & (REGDMA_INT_HIGH_MASK | REGDMA_INT_LOW_MASK)) { |
| 1889 | spin_lock(&rot->rotisr_lock); |
| 1890 | |
| 1891 | /* |
| 1892 | * Obtain rotator context based on timestamp from regdma |
| 1893 | * and low/high interrupt status |
| 1894 | */ |
| 1895 | if (isr & REGDMA_INT_HIGH_MASK) { |
| 1896 | q_id = ROT_QUEUE_HIGH_PRIORITY; |
| 1897 | ts = ts & SDE_REGDMA_SWTS_MASK; |
| 1898 | } else if (isr & REGDMA_INT_LOW_MASK) { |
| 1899 | q_id = ROT_QUEUE_LOW_PRIORITY; |
| 1900 | ts = (ts >> SDE_REGDMA_SWTS_SHIFT) & |
| 1901 | SDE_REGDMA_SWTS_MASK; |
Benjamin Chan | 62b94ed | 2016-08-18 23:55:21 -0400 | [diff] [blame] | 1902 | } else { |
| 1903 | SDEROT_ERR("unknown ISR status: isr=0x%X\n", isr); |
| 1904 | goto done_isr_handle; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1905 | } |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1906 | ctx = rot->rotCtx[q_id][ts & SDE_HW_ROT_REGDMA_SEG_MASK]; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1907 | |
| 1908 | /* |
| 1909 | * Wake up all waiting context from the current and previous |
| 1910 | * SW Timestamp. |
| 1911 | */ |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1912 | while (ctx && |
| 1913 | sde_hw_rotator_elapsed_swts(ctx->timestamp, ts) >= 0) { |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1914 | ctx->last_regdma_isr_status = isr; |
| 1915 | ctx->last_regdma_timestamp = ts; |
| 1916 | SDEROT_DBG( |
Alan Kwong | f987ea3 | 2016-07-06 12:11:44 -0400 | [diff] [blame] | 1917 | "regdma complete: ctx:%p, ts:%X\n", ctx, ts); |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1918 | wake_up_all(&ctx->regdma_waitq); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1919 | |
| 1920 | ts = (ts - 1) & SDE_REGDMA_SWTS_MASK; |
| 1921 | ctx = rot->rotCtx[q_id] |
| 1922 | [ts & SDE_HW_ROT_REGDMA_SEG_MASK]; |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1923 | }; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1924 | |
Benjamin Chan | 62b94ed | 2016-08-18 23:55:21 -0400 | [diff] [blame] | 1925 | done_isr_handle: |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1926 | spin_unlock(&rot->rotisr_lock); |
| 1927 | ret = IRQ_HANDLED; |
| 1928 | } else if (isr & REGDMA_INT_ERR_MASK) { |
| 1929 | /* |
| 1930 | * For REGDMA Err, we save the isr info and wake up |
| 1931 | * all waiting contexts |
| 1932 | */ |
| 1933 | int i, j; |
| 1934 | |
| 1935 | SDEROT_ERR( |
| 1936 | "regdma err isr:%X, wake up all waiting contexts\n", |
| 1937 | isr); |
| 1938 | |
| 1939 | spin_lock(&rot->rotisr_lock); |
| 1940 | |
| 1941 | for (i = 0; i < ROT_QUEUE_MAX; i++) { |
| 1942 | for (j = 0; j < SDE_HW_ROT_REGDMA_TOTAL_CTX; j++) { |
| 1943 | ctx = rot->rotCtx[i][j]; |
| 1944 | if (ctx && ctx->last_regdma_isr_status == 0) { |
| 1945 | ctx->last_regdma_isr_status = isr; |
| 1946 | ctx->last_regdma_timestamp = ts; |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 1947 | wake_up_all(&ctx->regdma_waitq); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1948 | SDEROT_DBG("Wakeup rotctx[%d][%d]:%p\n", |
| 1949 | i, j, ctx); |
| 1950 | } |
| 1951 | } |
| 1952 | } |
| 1953 | |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1954 | spin_unlock(&rot->rotisr_lock); |
| 1955 | ret = IRQ_HANDLED; |
| 1956 | } |
| 1957 | |
| 1958 | return ret; |
| 1959 | } |
| 1960 | |
| 1961 | /* |
| 1962 | * sde_hw_rotator_validate_entry - validate rotation entry |
| 1963 | * @mgr: Pointer to rotator manager |
| 1964 | * @entry: Pointer to rotation entry |
| 1965 | * |
| 1966 | * This function validates the given rotation entry and provides possible |
| 1967 | * fixup (future improvement) if available. This function returns 0 if |
| 1968 | * the entry is valid, and returns error code otherwise. |
| 1969 | */ |
| 1970 | static int sde_hw_rotator_validate_entry(struct sde_rot_mgr *mgr, |
| 1971 | struct sde_rot_entry *entry) |
| 1972 | { |
Benjamin Chan | fb6faa3 | 2016-08-16 17:21:01 -0400 | [diff] [blame] | 1973 | struct sde_rot_data_type *mdata = sde_rot_get_mdata(); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1974 | int ret = 0; |
| 1975 | u16 src_w, src_h, dst_w, dst_h; |
| 1976 | struct sde_rotation_item *item = &entry->item; |
| 1977 | struct sde_mdp_format_params *fmt; |
| 1978 | |
| 1979 | src_w = item->src_rect.w; |
| 1980 | src_h = item->src_rect.h; |
| 1981 | |
| 1982 | if (item->flags & SDE_ROTATION_90) { |
| 1983 | dst_w = item->dst_rect.h; |
| 1984 | dst_h = item->dst_rect.w; |
| 1985 | } else { |
| 1986 | dst_w = item->dst_rect.w; |
| 1987 | dst_h = item->dst_rect.h; |
| 1988 | } |
| 1989 | |
| 1990 | entry->dnsc_factor_w = 0; |
| 1991 | entry->dnsc_factor_h = 0; |
| 1992 | |
| 1993 | if ((src_w != dst_w) || (src_h != dst_h)) { |
| 1994 | if ((src_w % dst_w) || (src_h % dst_h)) { |
| 1995 | SDEROT_DBG("non integral scale not support\n"); |
| 1996 | ret = -EINVAL; |
Benjamin Chan | fb6faa3 | 2016-08-16 17:21:01 -0400 | [diff] [blame] | 1997 | goto dnsc_1p5_check; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 1998 | } |
| 1999 | entry->dnsc_factor_w = src_w / dst_w; |
| 2000 | if ((entry->dnsc_factor_w & (entry->dnsc_factor_w - 1)) || |
| 2001 | (entry->dnsc_factor_w > 64)) { |
| 2002 | SDEROT_DBG("non power-of-2 w_scale not support\n"); |
| 2003 | ret = -EINVAL; |
| 2004 | goto dnsc_err; |
| 2005 | } |
| 2006 | entry->dnsc_factor_h = src_h / dst_h; |
| 2007 | if ((entry->dnsc_factor_h & (entry->dnsc_factor_h - 1)) || |
| 2008 | (entry->dnsc_factor_h > 64)) { |
| 2009 | SDEROT_DBG("non power-of-2 h_scale not support\n"); |
| 2010 | ret = -EINVAL; |
| 2011 | goto dnsc_err; |
| 2012 | } |
| 2013 | } |
| 2014 | |
| 2015 | fmt = sde_get_format_params(item->output.format); |
| 2016 | /* Tiled format downscale support not applied to AYUV tiled */ |
| 2017 | if (sde_mdp_is_tilea5x_format(fmt) && (entry->dnsc_factor_h > 4)) { |
| 2018 | SDEROT_DBG("max downscale for tiled format is 4\n"); |
| 2019 | ret = -EINVAL; |
| 2020 | goto dnsc_err; |
| 2021 | } |
| 2022 | if (sde_mdp_is_ubwc_format(fmt) && (entry->dnsc_factor_h > 2)) { |
| 2023 | SDEROT_DBG("downscale with ubwc cannot be more than 2\n"); |
| 2024 | ret = -EINVAL; |
| 2025 | } |
Benjamin Chan | fb6faa3 | 2016-08-16 17:21:01 -0400 | [diff] [blame] | 2026 | goto dnsc_err; |
| 2027 | |
| 2028 | dnsc_1p5_check: |
| 2029 | /* Check for 1.5 downscale that only applies to V2 HW */ |
| 2030 | if (test_bit(SDE_CAPS_R3_1P5_DOWNSCALE, mdata->sde_caps_map)) { |
| 2031 | entry->dnsc_factor_w = src_w / dst_w; |
| 2032 | if ((entry->dnsc_factor_w != 1) || |
| 2033 | ((dst_w * 3) != (src_w * 2))) { |
| 2034 | SDEROT_DBG( |
| 2035 | "No supporting non 1.5 downscale width ratio, src_w:%d, dst_w:%d\n", |
| 2036 | src_w, dst_w); |
| 2037 | ret = -EINVAL; |
| 2038 | goto dnsc_err; |
| 2039 | } |
| 2040 | |
| 2041 | entry->dnsc_factor_h = src_h / dst_h; |
| 2042 | if ((entry->dnsc_factor_h != 1) || |
| 2043 | ((dst_h * 3) != (src_h * 2))) { |
| 2044 | SDEROT_DBG( |
| 2045 | "Not supporting non 1.5 downscale height ratio, src_h:%d, dst_h:%d\n", |
| 2046 | src_h, dst_h); |
| 2047 | ret = -EINVAL; |
| 2048 | goto dnsc_err; |
| 2049 | } |
| 2050 | ret = 0; |
| 2051 | } |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 2052 | |
| 2053 | dnsc_err: |
| 2054 | /* Downscaler does not support asymmetrical dnsc */ |
| 2055 | if (entry->dnsc_factor_w != entry->dnsc_factor_h) { |
| 2056 | SDEROT_DBG("asymmetric downscale not support\n"); |
| 2057 | ret = -EINVAL; |
| 2058 | } |
| 2059 | |
| 2060 | if (ret) { |
| 2061 | entry->dnsc_factor_w = 0; |
| 2062 | entry->dnsc_factor_h = 0; |
| 2063 | } |
| 2064 | return ret; |
| 2065 | } |
| 2066 | |
| 2067 | /* |
| 2068 | * sde_hw_rotator_show_caps - output capability info to sysfs 'caps' file |
| 2069 | * @mgr: Pointer to rotator manager |
| 2070 | * @attr: Pointer to device attribute interface |
| 2071 | * @buf: Pointer to output buffer |
| 2072 | * @len: Length of output buffer |
| 2073 | */ |
| 2074 | static ssize_t sde_hw_rotator_show_caps(struct sde_rot_mgr *mgr, |
| 2075 | struct device_attribute *attr, char *buf, ssize_t len) |
| 2076 | { |
| 2077 | struct sde_hw_rotator *hw_data; |
| 2078 | int cnt = 0; |
| 2079 | |
| 2080 | if (!mgr || !buf) |
| 2081 | return 0; |
| 2082 | |
| 2083 | hw_data = mgr->hw_data; |
| 2084 | |
| 2085 | #define SPRINT(fmt, ...) \ |
| 2086 | (cnt += scnprintf(buf + cnt, len - cnt, fmt, ##__VA_ARGS__)) |
| 2087 | |
| 2088 | /* insert capabilities here */ |
| 2089 | |
| 2090 | #undef SPRINT |
| 2091 | return cnt; |
| 2092 | } |
| 2093 | |
| 2094 | /* |
| 2095 | * sde_hw_rotator_show_state - output state info to sysfs 'state' file |
| 2096 | * @mgr: Pointer to rotator manager |
| 2097 | * @attr: Pointer to device attribute interface |
| 2098 | * @buf: Pointer to output buffer |
| 2099 | * @len: Length of output buffer |
| 2100 | */ |
| 2101 | static ssize_t sde_hw_rotator_show_state(struct sde_rot_mgr *mgr, |
| 2102 | struct device_attribute *attr, char *buf, ssize_t len) |
| 2103 | { |
| 2104 | struct sde_hw_rotator *rot; |
| 2105 | struct sde_hw_rotator_context *ctx; |
| 2106 | int cnt = 0; |
| 2107 | int num_active = 0; |
| 2108 | int i, j; |
| 2109 | |
| 2110 | if (!mgr || !buf) { |
| 2111 | SDEROT_ERR("null parameters\n"); |
| 2112 | return 0; |
| 2113 | } |
| 2114 | |
| 2115 | rot = mgr->hw_data; |
| 2116 | |
| 2117 | #define SPRINT(fmt, ...) \ |
| 2118 | (cnt += scnprintf(buf + cnt, len - cnt, fmt, ##__VA_ARGS__)) |
| 2119 | |
| 2120 | if (rot) { |
| 2121 | SPRINT("rot_mode=%d\n", rot->mode); |
| 2122 | SPRINT("irq_num=%d\n", rot->irq_num); |
| 2123 | |
| 2124 | if (rot->mode == ROT_REGDMA_OFF) { |
| 2125 | SPRINT("max_active=1\n"); |
| 2126 | SPRINT("num_active=%d\n", rot->rotCtx[0][0] ? 1 : 0); |
| 2127 | } else { |
| 2128 | for (i = 0; i < ROT_QUEUE_MAX; i++) { |
| 2129 | for (j = 0; j < SDE_HW_ROT_REGDMA_TOTAL_CTX; |
| 2130 | j++) { |
| 2131 | ctx = rot->rotCtx[i][j]; |
| 2132 | |
| 2133 | if (ctx) { |
| 2134 | SPRINT( |
| 2135 | "rotCtx[%d][%d]:%p\n", |
| 2136 | i, j, ctx); |
| 2137 | ++num_active; |
| 2138 | } |
| 2139 | } |
| 2140 | } |
| 2141 | |
| 2142 | SPRINT("max_active=%d\n", SDE_HW_ROT_REGDMA_TOTAL_CTX); |
| 2143 | SPRINT("num_active=%d\n", num_active); |
| 2144 | } |
| 2145 | } |
| 2146 | |
| 2147 | #undef SPRINT |
| 2148 | return cnt; |
| 2149 | } |
| 2150 | |
| 2151 | /* |
Alan Kwong | da16e44 | 2016-08-14 20:47:18 -0400 | [diff] [blame] | 2152 | * sde_hw_rotator_get_pixfmt - get the indexed pixel format |
| 2153 | * @mgr: Pointer to rotator manager |
| 2154 | * @index: index of pixel format |
| 2155 | * @input: true for input port; false for output port |
| 2156 | */ |
| 2157 | static u32 sde_hw_rotator_get_pixfmt(struct sde_rot_mgr *mgr, |
| 2158 | int index, bool input) |
| 2159 | { |
| 2160 | if (input) { |
| 2161 | if (index < ARRAY_SIZE(sde_hw_rotator_input_pixfmts)) |
| 2162 | return sde_hw_rotator_input_pixfmts[index]; |
| 2163 | else |
| 2164 | return 0; |
| 2165 | } else { |
| 2166 | if (index < ARRAY_SIZE(sde_hw_rotator_output_pixfmts)) |
| 2167 | return sde_hw_rotator_output_pixfmts[index]; |
| 2168 | else |
| 2169 | return 0; |
| 2170 | } |
| 2171 | } |
| 2172 | |
| 2173 | /* |
| 2174 | * sde_hw_rotator_is_valid_pixfmt - verify if the given pixel format is valid |
| 2175 | * @mgr: Pointer to rotator manager |
| 2176 | * @pixfmt: pixel format to be verified |
| 2177 | * @input: true for input port; false for output port |
| 2178 | */ |
| 2179 | static int sde_hw_rotator_is_valid_pixfmt(struct sde_rot_mgr *mgr, u32 pixfmt, |
| 2180 | bool input) |
| 2181 | { |
| 2182 | int i; |
| 2183 | |
| 2184 | if (input) { |
| 2185 | for (i = 0; i < ARRAY_SIZE(sde_hw_rotator_input_pixfmts); i++) |
| 2186 | if (sde_hw_rotator_input_pixfmts[i] == pixfmt) |
| 2187 | return true; |
| 2188 | } else { |
| 2189 | for (i = 0; i < ARRAY_SIZE(sde_hw_rotator_output_pixfmts); i++) |
| 2190 | if (sde_hw_rotator_output_pixfmts[i] == pixfmt) |
| 2191 | return true; |
| 2192 | } |
| 2193 | |
| 2194 | return false; |
| 2195 | } |
| 2196 | |
| 2197 | /* |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 2198 | * sde_hw_rotator_parse_dt - parse r3 specific device tree settings |
| 2199 | * @hw_data: Pointer to rotator hw |
| 2200 | * @dev: Pointer to platform device |
| 2201 | */ |
| 2202 | static int sde_hw_rotator_parse_dt(struct sde_hw_rotator *hw_data, |
| 2203 | struct platform_device *dev) |
| 2204 | { |
| 2205 | int ret = 0; |
| 2206 | u32 data; |
| 2207 | |
| 2208 | if (!hw_data || !dev) |
| 2209 | return -EINVAL; |
| 2210 | |
| 2211 | ret = of_property_read_u32(dev->dev.of_node, "qcom,mdss-rot-mode", |
| 2212 | &data); |
| 2213 | if (ret) { |
| 2214 | SDEROT_DBG("default to regdma off\n"); |
| 2215 | ret = 0; |
| 2216 | hw_data->mode = ROT_REGDMA_OFF; |
| 2217 | } else if (data < ROT_REGDMA_MAX) { |
| 2218 | SDEROT_DBG("set to regdma mode %d\n", data); |
| 2219 | hw_data->mode = data; |
| 2220 | } else { |
| 2221 | SDEROT_ERR("regdma mode out of range. default to regdma off\n"); |
| 2222 | hw_data->mode = ROT_REGDMA_OFF; |
| 2223 | } |
| 2224 | |
| 2225 | ret = of_property_read_u32(dev->dev.of_node, |
| 2226 | "qcom,mdss-highest-bank-bit", &data); |
| 2227 | if (ret) { |
| 2228 | SDEROT_DBG("default to A5X bank\n"); |
| 2229 | ret = 0; |
| 2230 | hw_data->highest_bank = 2; |
| 2231 | } else { |
| 2232 | SDEROT_DBG("set highest bank bit to %d\n", data); |
| 2233 | hw_data->highest_bank = data; |
| 2234 | } |
| 2235 | |
| 2236 | return ret; |
| 2237 | } |
| 2238 | |
| 2239 | /* |
| 2240 | * sde_rotator_r3_init - initialize the r3 module |
| 2241 | * @mgr: Pointer to rotator manager |
| 2242 | * |
| 2243 | * This function setup r3 callback functions, parses r3 specific |
| 2244 | * device tree settings, installs r3 specific interrupt handler, |
| 2245 | * as well as initializes r3 internal data structure. |
| 2246 | */ |
| 2247 | int sde_rotator_r3_init(struct sde_rot_mgr *mgr) |
| 2248 | { |
| 2249 | struct sde_hw_rotator *rot; |
| 2250 | struct sde_rot_data_type *mdata = sde_rot_get_mdata(); |
| 2251 | int i; |
| 2252 | int ret; |
| 2253 | |
| 2254 | rot = devm_kzalloc(&mgr->pdev->dev, sizeof(*rot), GFP_KERNEL); |
| 2255 | if (!rot) |
| 2256 | return -ENOMEM; |
| 2257 | |
| 2258 | mgr->hw_data = rot; |
| 2259 | mgr->queue_count = ROT_QUEUE_MAX; |
| 2260 | |
| 2261 | rot->mdss_base = mdata->sde_io.base; |
| 2262 | rot->pdev = mgr->pdev; |
| 2263 | |
| 2264 | /* Assign ops */ |
| 2265 | mgr->ops_hw_destroy = sde_hw_rotator_destroy; |
| 2266 | mgr->ops_hw_alloc = sde_hw_rotator_alloc_ext; |
| 2267 | mgr->ops_hw_free = sde_hw_rotator_free_ext; |
| 2268 | mgr->ops_config_hw = sde_hw_rotator_config; |
| 2269 | mgr->ops_kickoff_entry = sde_hw_rotator_kickoff; |
| 2270 | mgr->ops_wait_for_entry = sde_hw_rotator_wait4done; |
| 2271 | mgr->ops_hw_validate_entry = sde_hw_rotator_validate_entry; |
| 2272 | mgr->ops_hw_show_caps = sde_hw_rotator_show_caps; |
| 2273 | mgr->ops_hw_show_state = sde_hw_rotator_show_state; |
| 2274 | mgr->ops_hw_create_debugfs = sde_rotator_r3_create_debugfs; |
Alan Kwong | da16e44 | 2016-08-14 20:47:18 -0400 | [diff] [blame] | 2275 | mgr->ops_hw_get_pixfmt = sde_hw_rotator_get_pixfmt; |
| 2276 | mgr->ops_hw_is_valid_pixfmt = sde_hw_rotator_is_valid_pixfmt; |
Benjamin Chan | 0f9e61d | 2016-09-16 16:01:09 -0400 | [diff] [blame] | 2277 | mgr->ops_hw_pre_pmevent = sde_hw_rotator_pre_pmevent; |
| 2278 | mgr->ops_hw_post_pmevent = sde_hw_rotator_post_pmevent; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 2279 | |
| 2280 | ret = sde_hw_rotator_parse_dt(mgr->hw_data, mgr->pdev); |
| 2281 | if (ret) |
| 2282 | goto error_parse_dt; |
| 2283 | |
| 2284 | rot->irq_num = platform_get_irq(mgr->pdev, 0); |
| 2285 | if (rot->irq_num < 0) { |
| 2286 | SDEROT_ERR("fail to get rotator irq\n"); |
| 2287 | } else { |
| 2288 | if (rot->mode == ROT_REGDMA_OFF) |
| 2289 | ret = devm_request_threaded_irq(&mgr->pdev->dev, |
| 2290 | rot->irq_num, |
| 2291 | sde_hw_rotator_rotirq_handler, |
| 2292 | NULL, 0, "sde_rotator_r3", rot); |
| 2293 | else |
| 2294 | ret = devm_request_threaded_irq(&mgr->pdev->dev, |
| 2295 | rot->irq_num, |
| 2296 | sde_hw_rotator_regdmairq_handler, |
| 2297 | NULL, 0, "sde_rotator_r3", rot); |
| 2298 | if (ret) { |
| 2299 | SDEROT_ERR("fail to request irq r:%d\n", ret); |
| 2300 | rot->irq_num = -1; |
| 2301 | } else { |
| 2302 | disable_irq(rot->irq_num); |
| 2303 | } |
| 2304 | } |
Alan Kwong | 818b7fc | 2016-07-24 22:07:41 -0400 | [diff] [blame] | 2305 | atomic_set(&rot->irq_enabled, 0); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 2306 | |
| 2307 | setup_rotator_ops(&rot->ops, rot->mode); |
| 2308 | |
| 2309 | spin_lock_init(&rot->rotctx_lock); |
| 2310 | spin_lock_init(&rot->rotisr_lock); |
| 2311 | |
| 2312 | /* REGDMA initialization */ |
| 2313 | if (rot->mode == ROT_REGDMA_OFF) { |
| 2314 | for (i = 0; i < SDE_HW_ROT_REGDMA_TOTAL_CTX; i++) |
| 2315 | rot->cmd_wr_ptr[0][i] = &rot->cmd_queue[ |
| 2316 | SDE_HW_ROT_REGDMA_SEG_SIZE * i]; |
| 2317 | } else { |
| 2318 | for (i = 0; i < SDE_HW_ROT_REGDMA_TOTAL_CTX; i++) |
| 2319 | rot->cmd_wr_ptr[ROT_QUEUE_HIGH_PRIORITY][i] = |
| 2320 | (u32 *)(rot->mdss_base + |
| 2321 | REGDMA_RAM_REGDMA_CMD_RAM + |
| 2322 | SDE_HW_ROT_REGDMA_SEG_SIZE * 4 * i); |
| 2323 | |
| 2324 | for (i = 0; i < SDE_HW_ROT_REGDMA_TOTAL_CTX; i++) |
| 2325 | rot->cmd_wr_ptr[ROT_QUEUE_LOW_PRIORITY][i] = |
| 2326 | (u32 *)(rot->mdss_base + |
| 2327 | REGDMA_RAM_REGDMA_CMD_RAM + |
| 2328 | SDE_HW_ROT_REGDMA_SEG_SIZE * 4 * |
| 2329 | (i + SDE_HW_ROT_REGDMA_TOTAL_CTX)); |
| 2330 | } |
| 2331 | |
| 2332 | atomic_set(&rot->timestamp[0], 0); |
| 2333 | atomic_set(&rot->timestamp[1], 0); |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 2334 | |
| 2335 | ret = sde_rotator_hw_rev_init(rot); |
| 2336 | if (ret) |
| 2337 | goto error_hw_rev_init; |
| 2338 | |
Alan Kwong | 315cd77 | 2016-08-03 22:29:42 -0400 | [diff] [blame] | 2339 | /* set rotator CBCR to shutoff memory/periphery on clock off.*/ |
Benjamin Chan | 77aed19 | 2016-10-17 17:49:41 -0400 | [diff] [blame^] | 2340 | clk_set_flags(mgr->rot_clk[SDE_ROTATOR_CLK_ROT_CORE].clk, |
Alan Kwong | 315cd77 | 2016-08-03 22:29:42 -0400 | [diff] [blame] | 2341 | CLKFLAG_NORETAIN_MEM); |
Benjamin Chan | 77aed19 | 2016-10-17 17:49:41 -0400 | [diff] [blame^] | 2342 | clk_set_flags(mgr->rot_clk[SDE_ROTATOR_CLK_ROT_CORE].clk, |
Alan Kwong | 315cd77 | 2016-08-03 22:29:42 -0400 | [diff] [blame] | 2343 | CLKFLAG_NORETAIN_PERIPH); |
| 2344 | |
Benjamin Chan | 53e3bce | 2016-08-31 14:43:29 -0400 | [diff] [blame] | 2345 | mdata->sde_rot_hw = rot; |
Alan Kwong | 9487de2 | 2016-01-16 22:06:36 -0500 | [diff] [blame] | 2346 | return 0; |
| 2347 | error_hw_rev_init: |
| 2348 | if (rot->irq_num >= 0) |
| 2349 | devm_free_irq(&mgr->pdev->dev, rot->irq_num, mdata); |
| 2350 | devm_kfree(&mgr->pdev->dev, mgr->hw_data); |
| 2351 | error_parse_dt: |
| 2352 | return ret; |
| 2353 | } |