blob: 958fb9160c2df2ff2444cbdc2067f307f4a8efed [file] [log] [blame]
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001/*
2 * QTI CE device driver.
3 *
4 * Copyright (c) 2010-2017, The Linux Foundation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/mman.h>
16#include <linux/types.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19#include <linux/kernel.h>
20#include <linux/dmapool.h>
21#include <linux/interrupt.h>
22#include <linux/spinlock.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/fs.h>
26#include <linux/miscdevice.h>
27#include <linux/uaccess.h>
28#include <linux/debugfs.h>
29#include <linux/scatterlist.h>
30#include <linux/crypto.h>
31#include <linux/platform_data/qcom_crypto_device.h>
32#include <linux/msm-bus.h>
33#include <linux/qcedev.h>
34
35#include <crypto/hash.h>
36#include "qcedevi.h"
37#include "qce.h"
38
39#include <linux/compat.h>
40#include "compat_qcedev.h"
41
42#define CACHE_LINE_SIZE 32
43#define CE_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE
44
45static uint8_t _std_init_vector_sha1_uint8[] = {
46 0x67, 0x45, 0x23, 0x01, 0xEF, 0xCD, 0xAB, 0x89,
47 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76,
48 0xC3, 0xD2, 0xE1, 0xF0
49};
50/* standard initialization vector for SHA-256, source: FIPS 180-2 */
51static uint8_t _std_init_vector_sha256_uint8[] = {
52 0x6A, 0x09, 0xE6, 0x67, 0xBB, 0x67, 0xAE, 0x85,
53 0x3C, 0x6E, 0xF3, 0x72, 0xA5, 0x4F, 0xF5, 0x3A,
54 0x51, 0x0E, 0x52, 0x7F, 0x9B, 0x05, 0x68, 0x8C,
55 0x1F, 0x83, 0xD9, 0xAB, 0x5B, 0xE0, 0xCD, 0x19
56};
57
58static DEFINE_MUTEX(send_cmd_lock);
59static DEFINE_MUTEX(qcedev_sent_bw_req);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +053060static DEFINE_MUTEX(hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -070061
AnilKumar Chimatae5e60512017-05-03 14:06:59 -070062static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
63{
64 unsigned int control_flag;
65 int ret = 0;
66
67 if (podev->ce_support.req_bw_before_clk) {
68 if (enable)
69 control_flag = QCE_BW_REQUEST_FIRST;
70 else
71 control_flag = QCE_CLK_DISABLE_FIRST;
72 } else {
73 if (enable)
74 control_flag = QCE_CLK_ENABLE_FIRST;
75 else
76 control_flag = QCE_BW_REQUEST_RESET_FIRST;
77 }
78
79 switch (control_flag) {
80 case QCE_CLK_ENABLE_FIRST:
81 ret = qce_enable_clk(podev->qce);
82 if (ret) {
83 pr_err("%s Unable enable clk\n", __func__);
84 return ret;
85 }
86 ret = msm_bus_scale_client_update_request(
87 podev->bus_scale_handle, 1);
88 if (ret) {
89 pr_err("%s Unable to set high bw\n", __func__);
90 ret = qce_disable_clk(podev->qce);
91 if (ret)
92 pr_err("%s Unable disable clk\n", __func__);
93 return ret;
94 }
95 break;
96 case QCE_BW_REQUEST_FIRST:
97 ret = msm_bus_scale_client_update_request(
98 podev->bus_scale_handle, 1);
99 if (ret) {
100 pr_err("%s Unable to set high bw\n", __func__);
101 return ret;
102 }
103 ret = qce_enable_clk(podev->qce);
104 if (ret) {
105 pr_err("%s Unable enable clk\n", __func__);
106 ret = msm_bus_scale_client_update_request(
107 podev->bus_scale_handle, 0);
108 if (ret)
109 pr_err("%s Unable to set low bw\n", __func__);
110 return ret;
111 }
112 break;
113 case QCE_CLK_DISABLE_FIRST:
114 ret = qce_disable_clk(podev->qce);
115 if (ret) {
116 pr_err("%s Unable to disable clk\n", __func__);
117 return ret;
118 }
119 ret = msm_bus_scale_client_update_request(
120 podev->bus_scale_handle, 0);
121 if (ret) {
122 pr_err("%s Unable to set low bw\n", __func__);
123 ret = qce_enable_clk(podev->qce);
124 if (ret)
125 pr_err("%s Unable enable clk\n", __func__);
126 return ret;
127 }
128 break;
129 case QCE_BW_REQUEST_RESET_FIRST:
130 ret = msm_bus_scale_client_update_request(
131 podev->bus_scale_handle, 0);
132 if (ret) {
133 pr_err("%s Unable to set low bw\n", __func__);
134 return ret;
135 }
136 ret = qce_disable_clk(podev->qce);
137 if (ret) {
138 pr_err("%s Unable to disable clk\n", __func__);
139 ret = msm_bus_scale_client_update_request(
140 podev->bus_scale_handle, 1);
141 if (ret)
142 pr_err("%s Unable to set high bw\n", __func__);
143 return ret;
144 }
145 break;
146 default:
147 return -ENOENT;
148 }
149
150 return 0;
151}
152
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700153static void qcedev_ce_high_bw_req(struct qcedev_control *podev,
154 bool high_bw_req)
155{
156 int ret = 0;
157
158 mutex_lock(&qcedev_sent_bw_req);
159 if (high_bw_req) {
160 if (podev->high_bw_req_count == 0) {
AnilKumar Chimatae5e60512017-05-03 14:06:59 -0700161 ret = qcedev_control_clocks(podev, true);
162 if (ret)
163 goto exit_unlock_mutex;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700164 }
165 podev->high_bw_req_count++;
166 } else {
167 if (podev->high_bw_req_count == 1) {
AnilKumar Chimatae5e60512017-05-03 14:06:59 -0700168 ret = qcedev_control_clocks(podev, false);
169 if (ret)
170 goto exit_unlock_mutex;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700171 }
172 podev->high_bw_req_count--;
173 }
AnilKumar Chimatae5e60512017-05-03 14:06:59 -0700174
175exit_unlock_mutex:
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700176 mutex_unlock(&qcedev_sent_bw_req);
177}
178
179#define QCEDEV_MAGIC 0x56434544 /* "qced" */
180
181static int qcedev_open(struct inode *inode, struct file *file);
182static int qcedev_release(struct inode *inode, struct file *file);
183static int start_cipher_req(struct qcedev_control *podev);
184static int start_sha_req(struct qcedev_control *podev);
185static inline long qcedev_ioctl(struct file *file,
186 unsigned int cmd, unsigned long arg);
187
188#ifdef CONFIG_COMPAT
189#include "compat_qcedev.c"
190#else
191#define compat_qcedev_ioctl NULL
192#endif
193
194static const struct file_operations qcedev_fops = {
195 .owner = THIS_MODULE,
196 .unlocked_ioctl = qcedev_ioctl,
197 .compat_ioctl = compat_qcedev_ioctl,
198 .open = qcedev_open,
199 .release = qcedev_release,
200};
201
202static struct qcedev_control qce_dev[] = {
203 {
204 .miscdevice = {
205 .minor = MISC_DYNAMIC_MINOR,
206 .name = "qce",
207 .fops = &qcedev_fops,
208 },
209 .magic = QCEDEV_MAGIC,
210 },
211};
212
213#define MAX_QCE_DEVICE ARRAY_SIZE(qce_dev)
214#define DEBUG_MAX_FNAME 16
215#define DEBUG_MAX_RW_BUF 1024
216
217struct qcedev_stat {
218 u32 qcedev_dec_success;
219 u32 qcedev_dec_fail;
220 u32 qcedev_enc_success;
221 u32 qcedev_enc_fail;
222 u32 qcedev_sha_success;
223 u32 qcedev_sha_fail;
224};
225
226static struct qcedev_stat _qcedev_stat;
227static struct dentry *_debug_dent;
228static char _debug_read_buf[DEBUG_MAX_RW_BUF];
229static int _debug_qcedev;
230
231static struct qcedev_control *qcedev_minor_to_control(unsigned int n)
232{
233 int i;
234
235 for (i = 0; i < MAX_QCE_DEVICE; i++) {
236 if (qce_dev[i].miscdevice.minor == n)
237 return &qce_dev[i];
238 }
239 return NULL;
240}
241
242static int qcedev_open(struct inode *inode, struct file *file)
243{
244 struct qcedev_handle *handle;
245 struct qcedev_control *podev;
246
247 podev = qcedev_minor_to_control(MINOR(inode->i_rdev));
248 if (podev == NULL) {
249 pr_err("%s: no such device %d\n", __func__,
250 MINOR(inode->i_rdev));
251 return -ENOENT;
252 }
253
254 handle = kzalloc(sizeof(struct qcedev_handle), GFP_KERNEL);
255 if (handle == NULL)
256 return -ENOMEM;
257
258 handle->cntl = podev;
259 file->private_data = handle;
260 if (podev->platform_support.bus_scale_table != NULL)
261 qcedev_ce_high_bw_req(podev, true);
262 return 0;
263}
264
265static int qcedev_release(struct inode *inode, struct file *file)
266{
267 struct qcedev_control *podev;
268 struct qcedev_handle *handle;
269
270 handle = file->private_data;
271 podev = handle->cntl;
272 if (podev != NULL && podev->magic != QCEDEV_MAGIC) {
mohamed sunfeerc6b8e6d2017-06-29 15:13:34 +0530273 pr_err("%s: invalid handle %pK\n",
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700274 __func__, podev);
275 }
276 kzfree(handle);
277 file->private_data = NULL;
278 if (podev != NULL && podev->platform_support.bus_scale_table != NULL)
279 qcedev_ce_high_bw_req(podev, false);
280 return 0;
281}
282
283static void req_done(unsigned long data)
284{
285 struct qcedev_control *podev = (struct qcedev_control *)data;
286 struct qcedev_async_req *areq;
287 unsigned long flags = 0;
288 struct qcedev_async_req *new_req = NULL;
289 int ret = 0;
290
291 spin_lock_irqsave(&podev->lock, flags);
292 areq = podev->active_command;
293 podev->active_command = NULL;
294
295again:
296 if (!list_empty(&podev->ready_commands)) {
297 new_req = container_of(podev->ready_commands.next,
298 struct qcedev_async_req, list);
299 list_del(&new_req->list);
300 podev->active_command = new_req;
301 new_req->err = 0;
302 if (new_req->op_type == QCEDEV_CRYPTO_OPER_CIPHER)
303 ret = start_cipher_req(podev);
304 else
305 ret = start_sha_req(podev);
306 }
307
308 spin_unlock_irqrestore(&podev->lock, flags);
309
310 if (areq)
311 complete(&areq->complete);
312
313 if (new_req && ret) {
314 complete(&new_req->complete);
315 spin_lock_irqsave(&podev->lock, flags);
316 podev->active_command = NULL;
317 areq = NULL;
318 ret = 0;
319 new_req = NULL;
320 goto again;
321 }
322}
323
324void qcedev_sha_req_cb(void *cookie, unsigned char *digest,
325 unsigned char *authdata, int ret)
326{
327 struct qcedev_sha_req *areq;
328 struct qcedev_control *pdev;
329 struct qcedev_handle *handle;
330
331 uint32_t *auth32 = (uint32_t *)authdata;
332
333 areq = (struct qcedev_sha_req *) cookie;
334 handle = (struct qcedev_handle *) areq->cookie;
335 pdev = handle->cntl;
336
337 if (digest)
338 memcpy(&handle->sha_ctxt.digest[0], digest, 32);
339
340 if (authdata) {
341 handle->sha_ctxt.auth_data[0] = auth32[0];
342 handle->sha_ctxt.auth_data[1] = auth32[1];
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700343 }
344
345 tasklet_schedule(&pdev->done_tasklet);
346};
347
348
349void qcedev_cipher_req_cb(void *cookie, unsigned char *icv,
350 unsigned char *iv, int ret)
351{
352 struct qcedev_cipher_req *areq;
353 struct qcedev_handle *handle;
354 struct qcedev_control *podev;
355 struct qcedev_async_req *qcedev_areq;
356
357 areq = (struct qcedev_cipher_req *) cookie;
358 handle = (struct qcedev_handle *) areq->cookie;
359 podev = handle->cntl;
360 qcedev_areq = podev->active_command;
361
362 if (iv)
363 memcpy(&qcedev_areq->cipher_op_req.iv[0], iv,
364 qcedev_areq->cipher_op_req.ivlen);
365 tasklet_schedule(&podev->done_tasklet);
366};
367
368static int start_cipher_req(struct qcedev_control *podev)
369{
370 struct qcedev_async_req *qcedev_areq;
371 struct qce_req creq;
372 int ret = 0;
373
374 /* start the command on the podev->active_command */
375 qcedev_areq = podev->active_command;
376 qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
377 if (qcedev_areq->cipher_op_req.use_pmem == QCEDEV_USE_PMEM) {
378 pr_err("%s: Use of PMEM is not supported\n", __func__);
379 goto unsupported;
380 }
381 creq.pmem = NULL;
382 switch (qcedev_areq->cipher_op_req.alg) {
383 case QCEDEV_ALG_DES:
384 creq.alg = CIPHER_ALG_DES;
385 break;
386 case QCEDEV_ALG_3DES:
387 creq.alg = CIPHER_ALG_3DES;
388 break;
389 case QCEDEV_ALG_AES:
390 creq.alg = CIPHER_ALG_AES;
391 break;
392 default:
393 return -EINVAL;
394 };
395
396 switch (qcedev_areq->cipher_op_req.mode) {
397 case QCEDEV_AES_MODE_CBC:
398 case QCEDEV_DES_MODE_CBC:
399 creq.mode = QCE_MODE_CBC;
400 break;
401 case QCEDEV_AES_MODE_ECB:
402 case QCEDEV_DES_MODE_ECB:
403 creq.mode = QCE_MODE_ECB;
404 break;
405 case QCEDEV_AES_MODE_CTR:
406 creq.mode = QCE_MODE_CTR;
407 break;
408 case QCEDEV_AES_MODE_XTS:
409 creq.mode = QCE_MODE_XTS;
410 break;
411 default:
412 return -EINVAL;
413 };
414
415 if ((creq.alg == CIPHER_ALG_AES) &&
416 (creq.mode == QCE_MODE_CTR)) {
417 creq.dir = QCE_ENCRYPT;
418 } else {
419 if (qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC)
420 creq.dir = QCE_ENCRYPT;
421 else
422 creq.dir = QCE_DECRYPT;
423 }
424
425 creq.iv = &qcedev_areq->cipher_op_req.iv[0];
426 creq.ivsize = qcedev_areq->cipher_op_req.ivlen;
427
428 creq.enckey = &qcedev_areq->cipher_op_req.enckey[0];
429 creq.encklen = qcedev_areq->cipher_op_req.encklen;
430
431 creq.cryptlen = qcedev_areq->cipher_op_req.data_len;
432
433 if (qcedev_areq->cipher_op_req.encklen == 0) {
434 if ((qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC_NO_KEY)
435 || (qcedev_areq->cipher_op_req.op ==
436 QCEDEV_OPER_DEC_NO_KEY))
437 creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
438 else {
439 int i;
440
441 for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
442 if (qcedev_areq->cipher_op_req.enckey[i] != 0)
443 break;
444 }
445
446 if ((podev->platform_support.hw_key_support == 1) &&
447 (i == QCEDEV_MAX_KEY_SIZE))
448 creq.op = QCE_REQ_ABLK_CIPHER;
449 else {
450 ret = -EINVAL;
451 goto unsupported;
452 }
453 }
454 } else {
455 creq.op = QCE_REQ_ABLK_CIPHER;
456 }
457
458 creq.qce_cb = qcedev_cipher_req_cb;
459 creq.areq = (void *)&qcedev_areq->cipher_req;
460 creq.flags = 0;
461 ret = qce_ablk_cipher_req(podev->qce, &creq);
462unsupported:
463 if (ret)
464 qcedev_areq->err = -ENXIO;
465 else
466 qcedev_areq->err = 0;
467 return ret;
468};
469
470static int start_sha_req(struct qcedev_control *podev)
471{
472 struct qcedev_async_req *qcedev_areq;
473 struct qce_sha_req sreq;
474 int ret = 0;
475 struct qcedev_handle *handle;
476
477 /* start the command on the podev->active_command */
478 qcedev_areq = podev->active_command;
479 handle = qcedev_areq->handle;
480
481 switch (qcedev_areq->sha_op_req.alg) {
482 case QCEDEV_ALG_SHA1:
483 sreq.alg = QCE_HASH_SHA1;
484 break;
485 case QCEDEV_ALG_SHA256:
486 sreq.alg = QCE_HASH_SHA256;
487 break;
488 case QCEDEV_ALG_SHA1_HMAC:
489 if (podev->ce_support.sha_hmac) {
490 sreq.alg = QCE_HASH_SHA1_HMAC;
491 sreq.authkey = &handle->sha_ctxt.authkey[0];
492 sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
493
494 } else {
495 sreq.alg = QCE_HASH_SHA1;
496 sreq.authkey = NULL;
497 }
498 break;
499 case QCEDEV_ALG_SHA256_HMAC:
500 if (podev->ce_support.sha_hmac) {
501 sreq.alg = QCE_HASH_SHA256_HMAC;
502 sreq.authkey = &handle->sha_ctxt.authkey[0];
503 sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
504 } else {
505 sreq.alg = QCE_HASH_SHA256;
506 sreq.authkey = NULL;
507 }
508 break;
509 case QCEDEV_ALG_AES_CMAC:
510 sreq.alg = QCE_HASH_AES_CMAC;
511 sreq.authkey = &handle->sha_ctxt.authkey[0];
512 sreq.authklen = qcedev_areq->sha_op_req.authklen;
513 break;
514 default:
515 pr_err("Algorithm %d not supported, exiting\n",
516 qcedev_areq->sha_op_req.alg);
517 return -EINVAL;
518 };
519
520 qcedev_areq->sha_req.cookie = handle;
521
522 sreq.qce_cb = qcedev_sha_req_cb;
523 if (qcedev_areq->sha_op_req.alg != QCEDEV_ALG_AES_CMAC) {
524 sreq.auth_data[0] = handle->sha_ctxt.auth_data[0];
525 sreq.auth_data[1] = handle->sha_ctxt.auth_data[1];
526 sreq.auth_data[2] = handle->sha_ctxt.auth_data[2];
527 sreq.auth_data[3] = handle->sha_ctxt.auth_data[3];
528 sreq.digest = &handle->sha_ctxt.digest[0];
529 sreq.first_blk = handle->sha_ctxt.first_blk;
530 sreq.last_blk = handle->sha_ctxt.last_blk;
531 }
532 sreq.size = qcedev_areq->sha_req.sreq.nbytes;
533 sreq.src = qcedev_areq->sha_req.sreq.src;
534 sreq.areq = (void *)&qcedev_areq->sha_req;
535 sreq.flags = 0;
536
537 ret = qce_process_sha_req(podev->qce, &sreq);
538
539 if (ret)
540 qcedev_areq->err = -ENXIO;
541 else
542 qcedev_areq->err = 0;
543 return ret;
544};
545
546static int submit_req(struct qcedev_async_req *qcedev_areq,
547 struct qcedev_handle *handle)
548{
549 struct qcedev_control *podev;
550 unsigned long flags = 0;
551 int ret = 0;
552 struct qcedev_stat *pstat;
553
554 qcedev_areq->err = 0;
555 podev = handle->cntl;
556
557 spin_lock_irqsave(&podev->lock, flags);
558
559 if (podev->active_command == NULL) {
560 podev->active_command = qcedev_areq;
561 if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER)
562 ret = start_cipher_req(podev);
563 else
564 ret = start_sha_req(podev);
565 } else {
566 list_add_tail(&qcedev_areq->list, &podev->ready_commands);
567 }
568
569 if (ret != 0)
570 podev->active_command = NULL;
571
572 spin_unlock_irqrestore(&podev->lock, flags);
573
574 if (ret == 0)
575 wait_for_completion(&qcedev_areq->complete);
576
577 if (ret)
578 qcedev_areq->err = -EIO;
579
580 pstat = &_qcedev_stat;
581 if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER) {
582 switch (qcedev_areq->cipher_op_req.op) {
583 case QCEDEV_OPER_DEC:
584 if (qcedev_areq->err)
585 pstat->qcedev_dec_fail++;
586 else
587 pstat->qcedev_dec_success++;
588 break;
589 case QCEDEV_OPER_ENC:
590 if (qcedev_areq->err)
591 pstat->qcedev_enc_fail++;
592 else
593 pstat->qcedev_enc_success++;
594 break;
595 default:
596 break;
597 };
598 } else {
599 if (qcedev_areq->err)
600 pstat->qcedev_sha_fail++;
601 else
602 pstat->qcedev_sha_success++;
603 }
604
605 return qcedev_areq->err;
606}
607
608static int qcedev_sha_init(struct qcedev_async_req *areq,
609 struct qcedev_handle *handle)
610{
611 struct qcedev_sha_ctxt *sha_ctxt = &handle->sha_ctxt;
612
613 memset(sha_ctxt, 0, sizeof(struct qcedev_sha_ctxt));
614 sha_ctxt->first_blk = 1;
615
616 if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
617 (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)) {
618 memcpy(&sha_ctxt->digest[0],
619 &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
620 sha_ctxt->diglen = SHA1_DIGEST_SIZE;
621 } else {
622 if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA256) ||
623 (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)) {
624 memcpy(&sha_ctxt->digest[0],
625 &_std_init_vector_sha256_uint8[0],
626 SHA256_DIGEST_SIZE);
627 sha_ctxt->diglen = SHA256_DIGEST_SIZE;
628 }
629 }
630 sha_ctxt->init_done = true;
631 return 0;
632}
633
634
635static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq,
636 struct qcedev_handle *handle,
637 struct scatterlist *sg_src)
638{
639 int err = 0;
640 int i = 0;
641 uint32_t total;
642
643 uint8_t *user_src = NULL;
644 uint8_t *k_src = NULL;
645 uint8_t *k_buf_src = NULL;
646 uint8_t *k_align_src = NULL;
647
648 uint32_t sha_pad_len = 0;
649 uint32_t trailing_buf_len = 0;
650 uint32_t t_buf = handle->sha_ctxt.trailing_buf_len;
651 uint32_t sha_block_size;
652
653 total = qcedev_areq->sha_op_req.data_len + t_buf;
654
655 if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1)
656 sha_block_size = SHA1_BLOCK_SIZE;
657 else
658 sha_block_size = SHA256_BLOCK_SIZE;
659
660 if (total <= sha_block_size) {
661 uint32_t len = qcedev_areq->sha_op_req.data_len;
662
663 i = 0;
664
665 k_src = &handle->sha_ctxt.trailing_buf[t_buf];
666
667 /* Copy data from user src(s) */
668 while (len > 0) {
669 user_src =
670 (void __user *)qcedev_areq->sha_op_req.data[i].vaddr;
671 if (user_src && copy_from_user(k_src,
672 (void __user *)user_src,
673 qcedev_areq->sha_op_req.data[i].len))
674 return -EFAULT;
675
676 len -= qcedev_areq->sha_op_req.data[i].len;
677 k_src += qcedev_areq->sha_op_req.data[i].len;
678 i++;
679 }
680 handle->sha_ctxt.trailing_buf_len = total;
681
682 return 0;
683 }
684
685
686 k_buf_src = kmalloc(total + CACHE_LINE_SIZE * 2,
687 GFP_KERNEL);
688 if (k_buf_src == NULL)
689 return -ENOMEM;
690
691 k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
692 CACHE_LINE_SIZE);
693 k_src = k_align_src;
694
695 /* check for trailing buffer from previous updates and append it */
696 if (t_buf > 0) {
697 memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
698 t_buf);
699 k_src += t_buf;
700 }
701
702 /* Copy data from user src(s) */
703 user_src = (void __user *)qcedev_areq->sha_op_req.data[0].vaddr;
704 if (user_src && copy_from_user(k_src,
705 (void __user *)user_src,
706 qcedev_areq->sha_op_req.data[0].len)) {
707 kzfree(k_buf_src);
708 return -EFAULT;
709 }
710 k_src += qcedev_areq->sha_op_req.data[0].len;
711 for (i = 1; i < qcedev_areq->sha_op_req.entries; i++) {
712 user_src = (void __user *)qcedev_areq->sha_op_req.data[i].vaddr;
713 if (user_src && copy_from_user(k_src,
714 (void __user *)user_src,
715 qcedev_areq->sha_op_req.data[i].len)) {
716 kzfree(k_buf_src);
717 return -EFAULT;
718 }
719 k_src += qcedev_areq->sha_op_req.data[i].len;
720 }
721
722 /* get new trailing buffer */
723 sha_pad_len = ALIGN(total, CE_SHA_BLOCK_SIZE) - total;
724 trailing_buf_len = CE_SHA_BLOCK_SIZE - sha_pad_len;
725
726 qcedev_areq->sha_req.sreq.src = sg_src;
727 sg_set_buf(qcedev_areq->sha_req.sreq.src, k_align_src,
728 total-trailing_buf_len);
729 sg_mark_end(qcedev_areq->sha_req.sreq.src);
730
731 qcedev_areq->sha_req.sreq.nbytes = total - trailing_buf_len;
732
733 /* update sha_ctxt trailing buf content to new trailing buf */
734 if (trailing_buf_len > 0) {
735 memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
736 memcpy(&handle->sha_ctxt.trailing_buf[0],
737 (k_src - trailing_buf_len),
738 trailing_buf_len);
739 }
740 handle->sha_ctxt.trailing_buf_len = trailing_buf_len;
741
742 err = submit_req(qcedev_areq, handle);
743
744 handle->sha_ctxt.last_blk = 0;
745 handle->sha_ctxt.first_blk = 0;
746
747 kzfree(k_buf_src);
748 return err;
749}
750
751static int qcedev_sha_update(struct qcedev_async_req *qcedev_areq,
752 struct qcedev_handle *handle,
753 struct scatterlist *sg_src)
754{
755 int err = 0;
756 int i = 0;
757 int j = 0;
758 int k = 0;
759 int num_entries = 0;
760 uint32_t total = 0;
761
762 if (handle->sha_ctxt.init_done == false) {
763 pr_err("%s Init was not called\n", __func__);
764 return -EINVAL;
765 }
766
767 if (qcedev_areq->sha_op_req.data_len > QCE_MAX_OPER_DATA) {
768
769 struct qcedev_sha_op_req *saved_req;
770 struct qcedev_sha_op_req req;
771 struct qcedev_sha_op_req *sreq = &qcedev_areq->sha_op_req;
772
773 /* save the original req structure */
774 saved_req =
775 kmalloc(sizeof(struct qcedev_sha_op_req), GFP_KERNEL);
776 if (saved_req == NULL) {
777 pr_err("%s:Can't Allocate mem:saved_req 0x%lx\n",
778 __func__, (uintptr_t)saved_req);
779 return -ENOMEM;
780 }
781 memcpy(&req, sreq, sizeof(struct qcedev_sha_op_req));
782 memcpy(saved_req, sreq, sizeof(struct qcedev_sha_op_req));
783
784 i = 0;
785 /* Address 32 KB at a time */
786 while ((i < req.entries) && (err == 0)) {
787 if (sreq->data[i].len > QCE_MAX_OPER_DATA) {
788 sreq->data[0].len = QCE_MAX_OPER_DATA;
789 if (i > 0) {
790 sreq->data[0].vaddr =
791 sreq->data[i].vaddr;
792 }
793
794 sreq->data_len = QCE_MAX_OPER_DATA;
795 sreq->entries = 1;
796
797 err = qcedev_sha_update_max_xfer(qcedev_areq,
798 handle, sg_src);
799
800 sreq->data[i].len = req.data[i].len -
801 QCE_MAX_OPER_DATA;
802 sreq->data[i].vaddr = req.data[i].vaddr +
803 QCE_MAX_OPER_DATA;
804 req.data[i].vaddr = sreq->data[i].vaddr;
805 req.data[i].len = sreq->data[i].len;
806 } else {
807 total = 0;
808 for (j = i; j < req.entries; j++) {
809 num_entries++;
810 if ((total + sreq->data[j].len) >=
811 QCE_MAX_OPER_DATA) {
812 sreq->data[j].len =
813 (QCE_MAX_OPER_DATA - total);
814 total = QCE_MAX_OPER_DATA;
815 break;
816 }
817 total += sreq->data[j].len;
818 }
819
820 sreq->data_len = total;
821 if (i > 0)
822 for (k = 0; k < num_entries; k++) {
823 sreq->data[k].len =
824 sreq->data[i+k].len;
825 sreq->data[k].vaddr =
826 sreq->data[i+k].vaddr;
827 }
828 sreq->entries = num_entries;
829
830 i = j;
831 err = qcedev_sha_update_max_xfer(qcedev_areq,
832 handle, sg_src);
833 num_entries = 0;
834
835 sreq->data[i].vaddr = req.data[i].vaddr +
836 sreq->data[i].len;
837 sreq->data[i].len = req.data[i].len -
838 sreq->data[i].len;
839 req.data[i].vaddr = sreq->data[i].vaddr;
840 req.data[i].len = sreq->data[i].len;
841
842 if (sreq->data[i].len == 0)
843 i++;
844 }
845 } /* end of while ((i < req.entries) && (err == 0)) */
846
847 /* Restore the original req structure */
848 for (i = 0; i < saved_req->entries; i++) {
849 sreq->data[i].len = saved_req->data[i].len;
850 sreq->data[i].vaddr = saved_req->data[i].vaddr;
851 }
852 sreq->entries = saved_req->entries;
853 sreq->data_len = saved_req->data_len;
854 kzfree(saved_req);
855 } else
856 err = qcedev_sha_update_max_xfer(qcedev_areq, handle, sg_src);
857
858 return err;
859}
860
861static int qcedev_sha_final(struct qcedev_async_req *qcedev_areq,
862 struct qcedev_handle *handle)
863{
864 int err = 0;
865 struct scatterlist sg_src;
866 uint32_t total;
867 uint8_t *k_buf_src = NULL;
868 uint8_t *k_align_src = NULL;
869
870 if (handle->sha_ctxt.init_done == false) {
871 pr_err("%s Init was not called\n", __func__);
872 return -EINVAL;
873 }
874
875 handle->sha_ctxt.last_blk = 1;
876
877 total = handle->sha_ctxt.trailing_buf_len;
878
879 if (total) {
880 k_buf_src = kmalloc(total + CACHE_LINE_SIZE * 2,
881 GFP_KERNEL);
882 if (k_buf_src == NULL)
883 return -ENOMEM;
884
885 k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
886 CACHE_LINE_SIZE);
887 memcpy(k_align_src, &handle->sha_ctxt.trailing_buf[0], total);
888 }
889 qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
890 sg_set_buf(qcedev_areq->sha_req.sreq.src, k_align_src, total);
891 sg_mark_end(qcedev_areq->sha_req.sreq.src);
892
893 qcedev_areq->sha_req.sreq.nbytes = total;
894
895 err = submit_req(qcedev_areq, handle);
896
897 handle->sha_ctxt.first_blk = 0;
898 handle->sha_ctxt.last_blk = 0;
899 handle->sha_ctxt.auth_data[0] = 0;
900 handle->sha_ctxt.auth_data[1] = 0;
901 handle->sha_ctxt.trailing_buf_len = 0;
902 handle->sha_ctxt.init_done = false;
903 memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
904
905 kzfree(k_buf_src);
Zhen Kong0acaefa2017-10-18 14:27:44 -0700906 qcedev_areq->sha_req.sreq.src = NULL;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700907 return err;
908}
909
910static int qcedev_hash_cmac(struct qcedev_async_req *qcedev_areq,
911 struct qcedev_handle *handle,
912 struct scatterlist *sg_src)
913{
914 int err = 0;
915 int i = 0;
916 uint32_t total;
917
918 uint8_t *user_src = NULL;
919 uint8_t *k_src = NULL;
920 uint8_t *k_buf_src = NULL;
921
922 total = qcedev_areq->sha_op_req.data_len;
923
924 if (copy_from_user(&handle->sha_ctxt.authkey[0],
925 (void __user *)qcedev_areq->sha_op_req.authkey,
926 qcedev_areq->sha_op_req.authklen))
927 return -EFAULT;
928
929
930 k_buf_src = kmalloc(total, GFP_KERNEL);
931 if (k_buf_src == NULL)
932 return -ENOMEM;
933
934 k_src = k_buf_src;
935
936 /* Copy data from user src(s) */
937 user_src = (void __user *)qcedev_areq->sha_op_req.data[0].vaddr;
938 for (i = 0; i < qcedev_areq->sha_op_req.entries; i++) {
939 user_src =
940 (void __user *)qcedev_areq->sha_op_req.data[i].vaddr;
941 if (user_src && copy_from_user(k_src, (void __user *)user_src,
942 qcedev_areq->sha_op_req.data[i].len)) {
943 kzfree(k_buf_src);
944 return -EFAULT;
945 }
946 k_src += qcedev_areq->sha_op_req.data[i].len;
947 }
948
949 qcedev_areq->sha_req.sreq.src = sg_src;
950 sg_set_buf(qcedev_areq->sha_req.sreq.src, k_buf_src, total);
951 sg_mark_end(qcedev_areq->sha_req.sreq.src);
952
953 qcedev_areq->sha_req.sreq.nbytes = total;
954 handle->sha_ctxt.diglen = qcedev_areq->sha_op_req.diglen;
955 err = submit_req(qcedev_areq, handle);
956
957 kzfree(k_buf_src);
958 return err;
959}
960
961static int qcedev_set_hmac_auth_key(struct qcedev_async_req *areq,
962 struct qcedev_handle *handle,
963 struct scatterlist *sg_src)
964{
965 int err = 0;
966
967 if (areq->sha_op_req.authklen <= QCEDEV_MAX_KEY_SIZE) {
968 qcedev_sha_init(areq, handle);
969 if (copy_from_user(&handle->sha_ctxt.authkey[0],
970 (void __user *)areq->sha_op_req.authkey,
971 areq->sha_op_req.authklen))
972 return -EFAULT;
973 } else {
974 struct qcedev_async_req authkey_areq;
975 uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE];
976
977 init_completion(&authkey_areq.complete);
978
979 authkey_areq.sha_op_req.entries = 1;
980 authkey_areq.sha_op_req.data[0].vaddr =
981 areq->sha_op_req.authkey;
982 authkey_areq.sha_op_req.data[0].len = areq->sha_op_req.authklen;
983 authkey_areq.sha_op_req.data_len = areq->sha_op_req.authklen;
984 authkey_areq.sha_op_req.diglen = 0;
985 authkey_areq.handle = handle;
986
987 memset(&authkey_areq.sha_op_req.digest[0], 0,
988 QCEDEV_MAX_SHA_DIGEST);
989 if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
990 authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA1;
991 if (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)
992 authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA256;
993
994 authkey_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
995
996 qcedev_sha_init(&authkey_areq, handle);
997 err = qcedev_sha_update(&authkey_areq, handle, sg_src);
998 if (!err)
999 err = qcedev_sha_final(&authkey_areq, handle);
1000 else
1001 return err;
1002 memcpy(&authkey[0], &handle->sha_ctxt.digest[0],
1003 handle->sha_ctxt.diglen);
1004 qcedev_sha_init(areq, handle);
1005
1006 memcpy(&handle->sha_ctxt.authkey[0], &authkey[0],
1007 handle->sha_ctxt.diglen);
1008 }
1009 return err;
1010}
1011
1012static int qcedev_hmac_get_ohash(struct qcedev_async_req *qcedev_areq,
1013 struct qcedev_handle *handle)
1014{
1015 int err = 0;
1016 struct scatterlist sg_src;
1017 uint8_t *k_src = NULL;
1018 uint32_t sha_block_size = 0;
1019 uint32_t sha_digest_size = 0;
1020
1021 if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
1022 sha_digest_size = SHA1_DIGEST_SIZE;
1023 sha_block_size = SHA1_BLOCK_SIZE;
1024 } else {
1025 if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
1026 sha_digest_size = SHA256_DIGEST_SIZE;
1027 sha_block_size = SHA256_BLOCK_SIZE;
1028 }
1029 }
1030 k_src = kmalloc(sha_block_size, GFP_KERNEL);
1031 if (k_src == NULL)
1032 return -ENOMEM;
1033
1034 /* check for trailing buffer from previous updates and append it */
1035 memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
1036 handle->sha_ctxt.trailing_buf_len);
1037
1038 qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
1039 sg_set_buf(qcedev_areq->sha_req.sreq.src, k_src, sha_block_size);
1040 sg_mark_end(qcedev_areq->sha_req.sreq.src);
1041
1042 qcedev_areq->sha_req.sreq.nbytes = sha_block_size;
1043 memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
1044 memcpy(&handle->sha_ctxt.trailing_buf[0], &handle->sha_ctxt.digest[0],
1045 sha_digest_size);
1046 handle->sha_ctxt.trailing_buf_len = sha_digest_size;
1047
1048 handle->sha_ctxt.first_blk = 1;
1049 handle->sha_ctxt.last_blk = 0;
1050 handle->sha_ctxt.auth_data[0] = 0;
1051 handle->sha_ctxt.auth_data[1] = 0;
1052
1053 if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
1054 memcpy(&handle->sha_ctxt.digest[0],
1055 &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
1056 handle->sha_ctxt.diglen = SHA1_DIGEST_SIZE;
1057 }
1058
1059 if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
1060 memcpy(&handle->sha_ctxt.digest[0],
1061 &_std_init_vector_sha256_uint8[0], SHA256_DIGEST_SIZE);
1062 handle->sha_ctxt.diglen = SHA256_DIGEST_SIZE;
1063 }
1064 err = submit_req(qcedev_areq, handle);
1065
1066 handle->sha_ctxt.last_blk = 0;
1067 handle->sha_ctxt.first_blk = 0;
1068
1069 kzfree(k_src);
Zhen Kong0acaefa2017-10-18 14:27:44 -07001070 qcedev_areq->sha_req.sreq.src = NULL;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001071 return err;
1072}
1073
1074static int qcedev_hmac_update_iokey(struct qcedev_async_req *areq,
1075 struct qcedev_handle *handle, bool ikey)
1076{
1077 int i;
1078 uint32_t constant;
1079 uint32_t sha_block_size;
1080
1081 if (ikey)
1082 constant = 0x36;
1083 else
1084 constant = 0x5c;
1085
1086 if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
1087 sha_block_size = SHA1_BLOCK_SIZE;
1088 else
1089 sha_block_size = SHA256_BLOCK_SIZE;
1090
1091 memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
1092 for (i = 0; i < sha_block_size; i++)
1093 handle->sha_ctxt.trailing_buf[i] =
1094 (handle->sha_ctxt.authkey[i] ^ constant);
1095
1096 handle->sha_ctxt.trailing_buf_len = sha_block_size;
1097 return 0;
1098}
1099
1100static int qcedev_hmac_init(struct qcedev_async_req *areq,
1101 struct qcedev_handle *handle,
1102 struct scatterlist *sg_src)
1103{
1104 int err;
1105 struct qcedev_control *podev = handle->cntl;
1106
1107 err = qcedev_set_hmac_auth_key(areq, handle, sg_src);
1108 if (err)
1109 return err;
1110 if (!podev->ce_support.sha_hmac)
1111 qcedev_hmac_update_iokey(areq, handle, true);
1112 return 0;
1113}
1114
1115static int qcedev_hmac_final(struct qcedev_async_req *areq,
1116 struct qcedev_handle *handle)
1117{
1118 int err;
1119 struct qcedev_control *podev = handle->cntl;
1120
1121 err = qcedev_sha_final(areq, handle);
1122 if (podev->ce_support.sha_hmac)
1123 return err;
1124
1125 qcedev_hmac_update_iokey(areq, handle, false);
1126 err = qcedev_hmac_get_ohash(areq, handle);
1127 if (err)
1128 return err;
1129 err = qcedev_sha_final(areq, handle);
1130
1131 return err;
1132}
1133
1134static int qcedev_hash_init(struct qcedev_async_req *areq,
1135 struct qcedev_handle *handle,
1136 struct scatterlist *sg_src)
1137{
1138 if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
1139 (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
1140 return qcedev_sha_init(areq, handle);
1141 else
1142 return qcedev_hmac_init(areq, handle, sg_src);
1143}
1144
1145static int qcedev_hash_update(struct qcedev_async_req *qcedev_areq,
1146 struct qcedev_handle *handle,
1147 struct scatterlist *sg_src)
1148{
1149 return qcedev_sha_update(qcedev_areq, handle, sg_src);
1150}
1151
1152static int qcedev_hash_final(struct qcedev_async_req *areq,
1153 struct qcedev_handle *handle)
1154{
1155 if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
1156 (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
1157 return qcedev_sha_final(areq, handle);
1158 else
1159 return qcedev_hmac_final(areq, handle);
1160}
1161
1162static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
1163 int *di, struct qcedev_handle *handle,
1164 uint8_t *k_align_src)
1165{
1166 int err = 0;
1167 int i = 0;
1168 int dst_i = *di;
1169 struct scatterlist sg_src;
1170 uint32_t byteoffset = 0;
1171 uint8_t *user_src = NULL;
1172 uint8_t *k_align_dst = k_align_src;
1173 struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
1174
1175
1176 if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
1177 byteoffset = areq->cipher_op_req.byteoffset;
1178
1179 user_src = (void __user *)areq->cipher_op_req.vbuf.src[0].vaddr;
1180 if (user_src && copy_from_user((k_align_src + byteoffset),
1181 (void __user *)user_src,
1182 areq->cipher_op_req.vbuf.src[0].len))
1183 return -EFAULT;
1184
1185 k_align_src += byteoffset + areq->cipher_op_req.vbuf.src[0].len;
1186
1187 for (i = 1; i < areq->cipher_op_req.entries; i++) {
1188 user_src =
1189 (void __user *)areq->cipher_op_req.vbuf.src[i].vaddr;
1190 if (user_src && copy_from_user(k_align_src,
1191 (void __user *)user_src,
1192 areq->cipher_op_req.vbuf.src[i].len)) {
1193 return -EFAULT;
1194 }
1195 k_align_src += areq->cipher_op_req.vbuf.src[i].len;
1196 }
1197
1198 /* restore src beginning */
1199 k_align_src = k_align_dst;
1200 areq->cipher_op_req.data_len += byteoffset;
1201
1202 areq->cipher_req.creq.src = (struct scatterlist *) &sg_src;
1203 areq->cipher_req.creq.dst = (struct scatterlist *) &sg_src;
1204
1205 /* In place encryption/decryption */
1206 sg_set_buf(areq->cipher_req.creq.src,
1207 k_align_dst,
1208 areq->cipher_op_req.data_len);
1209 sg_mark_end(areq->cipher_req.creq.src);
1210
1211 areq->cipher_req.creq.nbytes = areq->cipher_op_req.data_len;
1212 areq->cipher_req.creq.info = areq->cipher_op_req.iv;
1213 areq->cipher_op_req.entries = 1;
1214
1215 err = submit_req(areq, handle);
1216
1217 /* copy data to destination buffer*/
1218 creq->data_len -= byteoffset;
1219
1220 while (creq->data_len > 0) {
1221 if (creq->vbuf.dst[dst_i].len <= creq->data_len) {
1222 if (err == 0 && copy_to_user(
1223 (void __user *)creq->vbuf.dst[dst_i].vaddr,
1224 (k_align_dst + byteoffset),
Zhen Kong0acaefa2017-10-18 14:27:44 -07001225 creq->vbuf.dst[dst_i].len)) {
1226 err = -EFAULT;
1227 goto exit;
1228 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001229
1230 k_align_dst += creq->vbuf.dst[dst_i].len +
1231 byteoffset;
1232 creq->data_len -= creq->vbuf.dst[dst_i].len;
1233 dst_i++;
1234 } else {
1235 if (err == 0 && copy_to_user(
1236 (void __user *)creq->vbuf.dst[dst_i].vaddr,
1237 (k_align_dst + byteoffset),
Zhen Kong0acaefa2017-10-18 14:27:44 -07001238 creq->data_len)) {
1239 err = -EFAULT;
1240 goto exit;
1241 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001242
1243 k_align_dst += creq->data_len;
1244 creq->vbuf.dst[dst_i].len -= creq->data_len;
1245 creq->vbuf.dst[dst_i].vaddr += creq->data_len;
1246 creq->data_len = 0;
1247 }
1248 }
1249 *di = dst_i;
Zhen Kong0acaefa2017-10-18 14:27:44 -07001250exit:
1251 areq->cipher_req.creq.src = NULL;
1252 areq->cipher_req.creq.dst = NULL;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001253 return err;
1254};
1255
1256static int qcedev_vbuf_ablk_cipher(struct qcedev_async_req *areq,
1257 struct qcedev_handle *handle)
1258{
1259 int err = 0;
1260 int di = 0;
1261 int i = 0;
1262 int j = 0;
1263 int k = 0;
1264 uint32_t byteoffset = 0;
1265 int num_entries = 0;
1266 uint32_t total = 0;
1267 uint32_t len;
1268 uint8_t *k_buf_src = NULL;
1269 uint8_t *k_align_src = NULL;
1270 uint32_t max_data_xfer;
1271 struct qcedev_cipher_op_req *saved_req;
1272 struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
1273
1274 total = 0;
1275
1276 if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
1277 byteoffset = areq->cipher_op_req.byteoffset;
1278 k_buf_src = kmalloc(QCE_MAX_OPER_DATA + CACHE_LINE_SIZE * 2,
1279 GFP_KERNEL);
1280 if (k_buf_src == NULL)
1281 return -ENOMEM;
1282 k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
1283 CACHE_LINE_SIZE);
1284 max_data_xfer = QCE_MAX_OPER_DATA - byteoffset;
1285
1286 saved_req = kmalloc(sizeof(struct qcedev_cipher_op_req), GFP_KERNEL);
1287 if (saved_req == NULL) {
1288 kzfree(k_buf_src);
1289 return -ENOMEM;
1290
1291 }
1292 memcpy(saved_req, creq, sizeof(struct qcedev_cipher_op_req));
1293
1294 if (areq->cipher_op_req.data_len > max_data_xfer) {
1295 struct qcedev_cipher_op_req req;
1296
1297 /* save the original req structure */
1298 memcpy(&req, creq, sizeof(struct qcedev_cipher_op_req));
1299
1300 i = 0;
1301 /* Address 32 KB at a time */
1302 while ((i < req.entries) && (err == 0)) {
1303 if (creq->vbuf.src[i].len > max_data_xfer) {
1304 creq->vbuf.src[0].len = max_data_xfer;
1305 if (i > 0) {
1306 creq->vbuf.src[0].vaddr =
1307 creq->vbuf.src[i].vaddr;
1308 }
1309
1310 creq->data_len = max_data_xfer;
1311 creq->entries = 1;
1312
1313 err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
1314 &di, handle, k_align_src);
1315 if (err < 0) {
1316 kzfree(k_buf_src);
1317 kzfree(saved_req);
1318 return err;
1319 }
1320
1321 creq->vbuf.src[i].len = req.vbuf.src[i].len -
1322 max_data_xfer;
1323 creq->vbuf.src[i].vaddr =
1324 req.vbuf.src[i].vaddr +
1325 max_data_xfer;
1326 req.vbuf.src[i].vaddr =
1327 creq->vbuf.src[i].vaddr;
1328 req.vbuf.src[i].len = creq->vbuf.src[i].len;
1329
1330 } else {
1331 total = areq->cipher_op_req.byteoffset;
1332 for (j = i; j < req.entries; j++) {
1333 num_entries++;
1334 if ((total + creq->vbuf.src[j].len)
1335 >= max_data_xfer) {
1336 creq->vbuf.src[j].len =
1337 max_data_xfer - total;
1338 total = max_data_xfer;
1339 break;
1340 }
1341 total += creq->vbuf.src[j].len;
1342 }
1343
1344 creq->data_len = total;
1345 if (i > 0)
1346 for (k = 0; k < num_entries; k++) {
1347 creq->vbuf.src[k].len =
1348 creq->vbuf.src[i+k].len;
1349 creq->vbuf.src[k].vaddr =
1350 creq->vbuf.src[i+k].vaddr;
1351 }
1352 creq->entries = num_entries;
1353
1354 i = j;
1355 err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
1356 &di, handle, k_align_src);
1357 if (err < 0) {
1358 kzfree(k_buf_src);
1359 kzfree(saved_req);
1360 return err;
1361 }
1362
1363 num_entries = 0;
1364 areq->cipher_op_req.byteoffset = 0;
1365
1366 creq->vbuf.src[i].vaddr = req.vbuf.src[i].vaddr
1367 + creq->vbuf.src[i].len;
1368 creq->vbuf.src[i].len = req.vbuf.src[i].len -
1369 creq->vbuf.src[i].len;
1370
1371 req.vbuf.src[i].vaddr =
1372 creq->vbuf.src[i].vaddr;
1373 req.vbuf.src[i].len = creq->vbuf.src[i].len;
1374
1375 if (creq->vbuf.src[i].len == 0)
1376 i++;
1377 }
1378
1379 areq->cipher_op_req.byteoffset = 0;
1380 max_data_xfer = QCE_MAX_OPER_DATA;
1381 byteoffset = 0;
1382
1383 } /* end of while ((i < req.entries) && (err == 0)) */
1384 } else
1385 err = qcedev_vbuf_ablk_cipher_max_xfer(areq, &di, handle,
1386 k_align_src);
1387
1388 /* Restore the original req structure */
1389 for (i = 0; i < saved_req->entries; i++) {
1390 creq->vbuf.src[i].len = saved_req->vbuf.src[i].len;
1391 creq->vbuf.src[i].vaddr = saved_req->vbuf.src[i].vaddr;
1392 }
1393 for (len = 0, i = 0; len < saved_req->data_len; i++) {
1394 creq->vbuf.dst[i].len = saved_req->vbuf.dst[i].len;
1395 creq->vbuf.dst[i].vaddr = saved_req->vbuf.dst[i].vaddr;
1396 len += saved_req->vbuf.dst[i].len;
1397 }
1398 creq->entries = saved_req->entries;
1399 creq->data_len = saved_req->data_len;
1400 creq->byteoffset = saved_req->byteoffset;
1401
1402 kzfree(saved_req);
1403 kzfree(k_buf_src);
1404 return err;
1405
1406}
1407
1408static int qcedev_check_cipher_key(struct qcedev_cipher_op_req *req,
1409 struct qcedev_control *podev)
1410{
1411 /* if intending to use HW key make sure key fields are set
1412 * correctly and HW key is indeed supported in target
1413 */
1414 if (req->encklen == 0) {
1415 int i;
1416
1417 for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
1418 if (req->enckey[i]) {
1419 pr_err("%s: Invalid key: non-zero key input\n",
1420 __func__);
1421 goto error;
1422 }
1423 }
1424 if ((req->op != QCEDEV_OPER_ENC_NO_KEY) &&
1425 (req->op != QCEDEV_OPER_DEC_NO_KEY))
1426 if (!podev->platform_support.hw_key_support) {
1427 pr_err("%s: Invalid op %d\n", __func__,
1428 (uint32_t)req->op);
1429 goto error;
1430 }
1431 } else {
1432 if (req->encklen == QCEDEV_AES_KEY_192) {
1433 if (!podev->ce_support.aes_key_192) {
1434 pr_err("%s: AES-192 not supported\n", __func__);
1435 goto error;
1436 }
1437 } else {
1438 /* if not using HW key make sure key
1439 * length is valid
1440 */
1441 if (req->mode == QCEDEV_AES_MODE_XTS) {
1442 if ((req->encklen != QCEDEV_AES_KEY_128*2) &&
1443 (req->encklen != QCEDEV_AES_KEY_256*2)) {
1444 pr_err("%s: unsupported key size: %d\n",
1445 __func__, req->encklen);
1446 goto error;
1447 }
1448 } else {
1449 if ((req->encklen != QCEDEV_AES_KEY_128) &&
1450 (req->encklen != QCEDEV_AES_KEY_256)) {
1451 pr_err("%s: unsupported key size %d\n",
1452 __func__, req->encklen);
1453 goto error;
1454 }
1455 }
1456 }
1457 }
1458 return 0;
1459error:
1460 return -EINVAL;
1461}
1462
1463static int qcedev_check_cipher_params(struct qcedev_cipher_op_req *req,
1464 struct qcedev_control *podev)
1465{
1466 uint32_t total = 0;
1467 uint32_t i;
1468
1469 if (req->use_pmem) {
1470 pr_err("%s: Use of PMEM is not supported\n", __func__);
1471 goto error;
1472 }
1473 if ((req->entries == 0) || (req->data_len == 0) ||
1474 (req->entries > QCEDEV_MAX_BUFFERS)) {
1475 pr_err("%s: Invalid cipher length/entries\n", __func__);
1476 goto error;
1477 }
1478 if ((req->alg >= QCEDEV_ALG_LAST) ||
1479 (req->mode >= QCEDEV_AES_DES_MODE_LAST)) {
1480 pr_err("%s: Invalid algorithm %d\n", __func__,
1481 (uint32_t)req->alg);
1482 goto error;
1483 }
1484 if ((req->mode == QCEDEV_AES_MODE_XTS) &&
1485 (!podev->ce_support.aes_xts)) {
1486 pr_err("%s: XTS algorithm is not supported\n", __func__);
1487 goto error;
1488 }
1489 if (req->alg == QCEDEV_ALG_AES) {
1490 if (qcedev_check_cipher_key(req, podev))
1491 goto error;
1492
1493 }
1494 /* if using a byteoffset, make sure it is CTR mode using vbuf */
1495 if (req->byteoffset) {
1496 if (req->mode != QCEDEV_AES_MODE_CTR) {
1497 pr_err("%s: Operation on byte offset not supported\n",
1498 __func__);
1499 goto error;
1500 }
1501 if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
1502 pr_err("%s: Invalid byte offset\n", __func__);
1503 goto error;
1504 }
1505 total = req->byteoffset;
1506 for (i = 0; i < req->entries; i++) {
1507 if (total > U32_MAX - req->vbuf.src[i].len) {
1508 pr_err("%s:Integer overflow on total src len\n",
1509 __func__);
1510 goto error;
1511 }
1512 total += req->vbuf.src[i].len;
1513 }
1514 }
1515
1516 if (req->data_len < req->byteoffset) {
1517 pr_err("%s: req data length %u is less than byteoffset %u\n",
1518 __func__, req->data_len, req->byteoffset);
1519 goto error;
1520 }
1521
1522 /* Ensure IV size */
1523 if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
1524 pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
1525 goto error;
1526 }
1527
1528 /* Ensure Key size */
1529 if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
1530 pr_err("%s: Klen is not correct: %u\n", __func__, req->encklen);
1531 goto error;
1532 }
1533
1534 /* Ensure zer ivlen for ECB mode */
1535 if (req->ivlen > 0) {
1536 if ((req->mode == QCEDEV_AES_MODE_ECB) ||
1537 (req->mode == QCEDEV_DES_MODE_ECB)) {
1538 pr_err("%s: Expecting a zero length IV\n", __func__);
1539 goto error;
1540 }
1541 } else {
1542 if ((req->mode != QCEDEV_AES_MODE_ECB) &&
1543 (req->mode != QCEDEV_DES_MODE_ECB)) {
1544 pr_err("%s: Expecting a non-zero ength IV\n", __func__);
1545 goto error;
1546 }
1547 }
1548 /* Check for sum of all dst length is equal to data_len */
1549 for (i = 0, total = 0; i < req->entries; i++) {
1550 if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
1551 pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
1552 __func__, i, req->vbuf.dst[i].len);
1553 goto error;
1554 }
1555 if (req->vbuf.dst[i].len >= U32_MAX - total) {
1556 pr_err("%s: Integer overflow on total req dst vbuf length\n",
1557 __func__);
1558 goto error;
1559 }
1560 total += req->vbuf.dst[i].len;
1561 }
1562 if (total != req->data_len) {
1563 pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
1564 __func__, i, total, req->data_len);
1565 goto error;
1566 }
1567 /* Check for sum of all src length is equal to data_len */
1568 for (i = 0, total = 0; i < req->entries; i++) {
1569 if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
1570 pr_err("%s: NULL req src vbuf[%d] with length %d\n",
1571 __func__, i, req->vbuf.src[i].len);
1572 goto error;
1573 }
1574 if (req->vbuf.src[i].len > U32_MAX - total) {
1575 pr_err("%s: Integer overflow on total req src vbuf length\n",
1576 __func__);
1577 goto error;
1578 }
1579 total += req->vbuf.src[i].len;
1580 }
1581 if (total != req->data_len) {
1582 pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
1583 __func__, total, req->data_len);
1584 goto error;
1585 }
1586 return 0;
1587error:
1588 return -EINVAL;
1589
1590}
1591
1592static int qcedev_check_sha_params(struct qcedev_sha_op_req *req,
1593 struct qcedev_control *podev)
1594{
1595 uint32_t total = 0;
1596 uint32_t i;
1597
1598 if ((req->alg == QCEDEV_ALG_AES_CMAC) &&
1599 (!podev->ce_support.cmac)) {
1600 pr_err("%s: CMAC not supported\n", __func__);
1601 goto sha_error;
1602 }
1603 if ((!req->entries) || (req->entries > QCEDEV_MAX_BUFFERS)) {
1604 pr_err("%s: Invalid num entries (%d)\n",
1605 __func__, req->entries);
1606 goto sha_error;
1607 }
1608
1609 if (req->alg >= QCEDEV_ALG_SHA_ALG_LAST) {
1610 pr_err("%s: Invalid algorithm (%d)\n", __func__, req->alg);
1611 goto sha_error;
1612 }
1613 if ((req->alg == QCEDEV_ALG_SHA1_HMAC) ||
1614 (req->alg == QCEDEV_ALG_SHA1_HMAC)) {
1615 if (req->authkey == NULL) {
1616 pr_err("%s: Invalid authkey pointer\n", __func__);
1617 goto sha_error;
1618 }
1619 if (req->authklen <= 0) {
1620 pr_err("%s: Invalid authkey length (%d)\n",
1621 __func__, req->authklen);
1622 goto sha_error;
1623 }
1624 }
1625
1626 if (req->alg == QCEDEV_ALG_AES_CMAC) {
1627 if ((req->authklen != QCEDEV_AES_KEY_128) &&
1628 (req->authklen != QCEDEV_AES_KEY_256)) {
1629 pr_err("%s: unsupported key length\n", __func__);
1630 goto sha_error;
1631 }
1632 }
1633
1634 /* Check for sum of all src length is equal to data_len */
1635 for (i = 0, total = 0; i < req->entries; i++) {
1636 if (req->data[i].len > U32_MAX - total) {
1637 pr_err("%s: Integer overflow on total req buf length\n",
1638 __func__);
1639 goto sha_error;
1640 }
1641 total += req->data[i].len;
1642 }
1643
1644 if (total != req->data_len) {
1645 pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
1646 __func__, total, req->data_len);
1647 goto sha_error;
1648 }
1649 return 0;
1650sha_error:
1651 return -EINVAL;
1652}
1653
1654static inline long qcedev_ioctl(struct file *file,
1655 unsigned int cmd, unsigned long arg)
1656{
1657 int err = 0;
1658 struct qcedev_handle *handle;
1659 struct qcedev_control *podev;
1660 struct qcedev_async_req qcedev_areq;
1661 struct qcedev_stat *pstat;
1662
1663 handle = file->private_data;
1664 podev = handle->cntl;
1665 qcedev_areq.handle = handle;
1666 if (podev == NULL || podev->magic != QCEDEV_MAGIC) {
mohamed sunfeerc6b8e6d2017-06-29 15:13:34 +05301667 pr_err("%s: invalid handle %pK\n",
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001668 __func__, podev);
1669 return -ENOENT;
1670 }
1671
1672 /* Verify user arguments. */
1673 if (_IOC_TYPE(cmd) != QCEDEV_IOC_MAGIC)
1674 return -ENOTTY;
1675
1676 init_completion(&qcedev_areq.complete);
1677 pstat = &_qcedev_stat;
1678
1679 switch (cmd) {
1680 case QCEDEV_IOCTL_ENC_REQ:
1681 case QCEDEV_IOCTL_DEC_REQ:
1682 if (copy_from_user(&qcedev_areq.cipher_op_req,
1683 (void __user *)arg,
1684 sizeof(struct qcedev_cipher_op_req)))
1685 return -EFAULT;
1686 qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_CIPHER;
1687
1688 if (qcedev_check_cipher_params(&qcedev_areq.cipher_op_req,
1689 podev))
1690 return -EINVAL;
1691
1692 err = qcedev_vbuf_ablk_cipher(&qcedev_areq, handle);
1693 if (err)
1694 return err;
1695 if (copy_to_user((void __user *)arg,
1696 &qcedev_areq.cipher_op_req,
1697 sizeof(struct qcedev_cipher_op_req)))
1698 return -EFAULT;
1699 break;
1700
1701 case QCEDEV_IOCTL_SHA_INIT_REQ:
1702 {
1703 struct scatterlist sg_src;
1704
1705 if (copy_from_user(&qcedev_areq.sha_op_req,
1706 (void __user *)arg,
1707 sizeof(struct qcedev_sha_op_req)))
1708 return -EFAULT;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301709 mutex_lock(&hash_access_lock);
1710 if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
1711 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001712 return -EINVAL;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301713 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001714 qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
1715 err = qcedev_hash_init(&qcedev_areq, handle, &sg_src);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301716 if (err) {
1717 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001718 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301719 }
1720 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001721 if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
1722 sizeof(struct qcedev_sha_op_req)))
1723 return -EFAULT;
1724 }
1725 handle->sha_ctxt.init_done = true;
1726 break;
1727 case QCEDEV_IOCTL_GET_CMAC_REQ:
1728 if (!podev->ce_support.cmac)
1729 return -ENOTTY;
1730 case QCEDEV_IOCTL_SHA_UPDATE_REQ:
1731 {
1732 struct scatterlist sg_src;
1733
1734 if (copy_from_user(&qcedev_areq.sha_op_req,
1735 (void __user *)arg,
1736 sizeof(struct qcedev_sha_op_req)))
1737 return -EFAULT;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301738 mutex_lock(&hash_access_lock);
1739 if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
1740 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001741 return -EINVAL;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301742 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001743 qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
1744
1745 if (qcedev_areq.sha_op_req.alg == QCEDEV_ALG_AES_CMAC) {
1746 err = qcedev_hash_cmac(&qcedev_areq, handle, &sg_src);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301747 if (err) {
1748 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001749 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301750 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001751 } else {
1752 if (handle->sha_ctxt.init_done == false) {
1753 pr_err("%s Init was not called\n", __func__);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301754 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001755 return -EINVAL;
1756 }
1757 err = qcedev_hash_update(&qcedev_areq, handle, &sg_src);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301758 if (err) {
1759 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001760 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301761 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001762 }
1763
1764 if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
1765 pr_err("Invalid sha_ctxt.diglen %d\n",
1766 handle->sha_ctxt.diglen);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301767 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001768 return -EINVAL;
1769 }
1770 memcpy(&qcedev_areq.sha_op_req.digest[0],
1771 &handle->sha_ctxt.digest[0],
1772 handle->sha_ctxt.diglen);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301773 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001774 if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
1775 sizeof(struct qcedev_sha_op_req)))
1776 return -EFAULT;
1777 }
1778 break;
1779
1780 case QCEDEV_IOCTL_SHA_FINAL_REQ:
1781
1782 if (handle->sha_ctxt.init_done == false) {
1783 pr_err("%s Init was not called\n", __func__);
1784 return -EINVAL;
1785 }
1786 if (copy_from_user(&qcedev_areq.sha_op_req,
1787 (void __user *)arg,
1788 sizeof(struct qcedev_sha_op_req)))
1789 return -EFAULT;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301790 mutex_lock(&hash_access_lock);
1791 if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
1792 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001793 return -EINVAL;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301794 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001795 qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
1796 err = qcedev_hash_final(&qcedev_areq, handle);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301797 if (err) {
1798 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001799 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301800 }
Brahmaji K2ec40862017-05-15 16:02:15 +05301801 if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
1802 pr_err("Invalid sha_ctxt.diglen %d\n",
1803 handle->sha_ctxt.diglen);
1804 mutex_unlock(&hash_access_lock);
1805 return -EINVAL;
1806 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001807 qcedev_areq.sha_op_req.diglen = handle->sha_ctxt.diglen;
1808 memcpy(&qcedev_areq.sha_op_req.digest[0],
1809 &handle->sha_ctxt.digest[0],
1810 handle->sha_ctxt.diglen);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301811 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001812 if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
1813 sizeof(struct qcedev_sha_op_req)))
1814 return -EFAULT;
1815 handle->sha_ctxt.init_done = false;
1816 break;
1817
1818 case QCEDEV_IOCTL_GET_SHA_REQ:
1819 {
1820 struct scatterlist sg_src;
1821
1822 if (copy_from_user(&qcedev_areq.sha_op_req,
1823 (void __user *)arg,
1824 sizeof(struct qcedev_sha_op_req)))
1825 return -EFAULT;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301826 mutex_lock(&hash_access_lock);
1827 if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
1828 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001829 return -EINVAL;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301830 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001831 qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
1832 qcedev_hash_init(&qcedev_areq, handle, &sg_src);
1833 err = qcedev_hash_update(&qcedev_areq, handle, &sg_src);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301834 if (err) {
1835 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001836 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301837 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001838 err = qcedev_hash_final(&qcedev_areq, handle);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301839 if (err) {
1840 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001841 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301842 }
Brahmaji K2ec40862017-05-15 16:02:15 +05301843 if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
1844 pr_err("Invalid sha_ctxt.diglen %d\n",
1845 handle->sha_ctxt.diglen);
1846 mutex_unlock(&hash_access_lock);
1847 return -EINVAL;
1848 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001849 qcedev_areq.sha_op_req.diglen = handle->sha_ctxt.diglen;
1850 memcpy(&qcedev_areq.sha_op_req.digest[0],
1851 &handle->sha_ctxt.digest[0],
1852 handle->sha_ctxt.diglen);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301853 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001854 if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
1855 sizeof(struct qcedev_sha_op_req)))
1856 return -EFAULT;
1857 }
1858 break;
1859
1860 default:
1861 return -ENOTTY;
1862 }
1863
1864 return err;
1865}
1866
1867static int qcedev_probe(struct platform_device *pdev)
1868{
1869 void *handle = NULL;
1870 int rc = 0;
1871 struct qcedev_control *podev;
1872 struct msm_ce_hw_support *platform_support;
1873
1874 podev = &qce_dev[0];
1875
1876 podev->high_bw_req_count = 0;
1877 INIT_LIST_HEAD(&podev->ready_commands);
1878 podev->active_command = NULL;
1879
1880 spin_lock_init(&podev->lock);
1881
1882 tasklet_init(&podev->done_tasklet, req_done, (unsigned long)podev);
1883
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001884 podev->platform_support.bus_scale_table = (struct msm_bus_scale_pdata *)
1885 msm_bus_cl_get_pdata(pdev);
1886 if (!podev->platform_support.bus_scale_table) {
1887 pr_err("bus_scale_table is NULL\n");
1888 return -ENODATA;
1889 }
1890 podev->bus_scale_handle = msm_bus_scale_register_client(
1891 (struct msm_bus_scale_pdata *)
1892 podev->platform_support.bus_scale_table);
1893 if (!podev->bus_scale_handle) {
1894 pr_err("%s not able to get bus scale\n", __func__);
1895 return -ENOMEM;
1896 }
1897
1898 rc = msm_bus_scale_client_update_request(podev->bus_scale_handle, 1);
1899 if (rc) {
1900 pr_err("%s Unable to set to high bandwidth\n", __func__);
1901 goto exit_unregister_bus_scale;
1902 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001903 handle = qce_open(pdev, &rc);
1904 if (handle == NULL) {
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001905 rc = -ENODEV;
1906 goto exit_scale_busbandwidth;
1907 }
1908 rc = msm_bus_scale_client_update_request(podev->bus_scale_handle, 0);
1909 if (rc) {
1910 pr_err("%s Unable to set to low bandwidth\n", __func__);
1911 goto exit_qce_close;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001912 }
1913
1914 podev->qce = handle;
1915 podev->pdev = pdev;
1916 platform_set_drvdata(pdev, podev);
1917
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001918 qce_hw_support(podev->qce, &podev->ce_support);
1919 if (podev->ce_support.bam) {
1920 podev->platform_support.ce_shared = 0;
1921 podev->platform_support.shared_ce_resource = 0;
1922 podev->platform_support.hw_key_support =
1923 podev->ce_support.hw_key;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001924 podev->platform_support.sha_hmac = 1;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001925 } else {
1926 platform_support =
1927 (struct msm_ce_hw_support *)pdev->dev.platform_data;
1928 podev->platform_support.ce_shared = platform_support->ce_shared;
1929 podev->platform_support.shared_ce_resource =
1930 platform_support->shared_ce_resource;
1931 podev->platform_support.hw_key_support =
1932 platform_support->hw_key_support;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001933 podev->platform_support.sha_hmac = platform_support->sha_hmac;
1934 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001935
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001936 rc = misc_register(&podev->miscdevice);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001937 if (rc >= 0)
1938 return 0;
1939
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001940 misc_deregister(&podev->miscdevice);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001941
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001942exit_qce_close:
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001943 if (handle)
1944 qce_close(handle);
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001945exit_scale_busbandwidth:
1946 msm_bus_scale_client_update_request(podev->bus_scale_handle, 0);
1947exit_unregister_bus_scale:
1948 if (podev->platform_support.bus_scale_table != NULL)
1949 msm_bus_scale_unregister_client(podev->bus_scale_handle);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001950 platform_set_drvdata(pdev, NULL);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001951 podev->pdev = NULL;
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001952 podev->qce = NULL;
1953
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001954 return rc;
1955};
1956
1957static int qcedev_remove(struct platform_device *pdev)
1958{
1959 struct qcedev_control *podev;
1960
1961 podev = platform_get_drvdata(pdev);
1962 if (!podev)
1963 return 0;
1964 if (podev->qce)
1965 qce_close(podev->qce);
1966
1967 if (podev->platform_support.bus_scale_table != NULL)
1968 msm_bus_scale_unregister_client(podev->bus_scale_handle);
1969
1970 if (podev->miscdevice.minor != MISC_DYNAMIC_MINOR)
1971 misc_deregister(&podev->miscdevice);
1972 tasklet_kill(&podev->done_tasklet);
1973 return 0;
1974};
1975
1976static int qcedev_suspend(struct platform_device *pdev, pm_message_t state)
1977{
1978 struct qcedev_control *podev;
1979 int ret;
1980
1981 podev = platform_get_drvdata(pdev);
1982
1983 if (!podev || !podev->platform_support.bus_scale_table)
1984 return 0;
1985
1986 mutex_lock(&qcedev_sent_bw_req);
1987 if (podev->high_bw_req_count) {
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001988 ret = qcedev_control_clocks(podev, false);
1989 if (ret)
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001990 goto suspend_exit;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001991 }
1992
1993suspend_exit:
1994 mutex_unlock(&qcedev_sent_bw_req);
1995 return 0;
1996}
1997
1998static int qcedev_resume(struct platform_device *pdev)
1999{
2000 struct qcedev_control *podev;
2001 int ret;
2002
2003 podev = platform_get_drvdata(pdev);
2004
2005 if (!podev || !podev->platform_support.bus_scale_table)
2006 return 0;
2007
2008 mutex_lock(&qcedev_sent_bw_req);
2009 if (podev->high_bw_req_count) {
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07002010 ret = qcedev_control_clocks(podev, true);
2011 if (ret)
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07002012 goto resume_exit;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07002013 }
2014
2015resume_exit:
2016 mutex_unlock(&qcedev_sent_bw_req);
2017 return 0;
2018}
2019
2020static const struct of_device_id qcedev_match[] = {
2021 { .compatible = "qcom,qcedev",
2022 },
2023 {}
2024};
2025
2026static struct platform_driver qcedev_plat_driver = {
2027 .probe = qcedev_probe,
2028 .remove = qcedev_remove,
2029 .suspend = qcedev_suspend,
2030 .resume = qcedev_resume,
2031 .driver = {
2032 .name = "qce",
2033 .owner = THIS_MODULE,
2034 .of_match_table = qcedev_match,
2035 },
2036};
2037
2038static int _disp_stats(int id)
2039{
2040 struct qcedev_stat *pstat;
2041 int len = 0;
2042
2043 pstat = &_qcedev_stat;
2044 len = scnprintf(_debug_read_buf, DEBUG_MAX_RW_BUF - 1,
2045 "\nQTI QCE dev driver %d Statistics:\n",
2046 id + 1);
2047
2048 len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
2049 " Encryption operation success : %d\n",
2050 pstat->qcedev_enc_success);
2051 len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
2052 " Encryption operation fail : %d\n",
2053 pstat->qcedev_enc_fail);
2054 len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
2055 " Decryption operation success : %d\n",
2056 pstat->qcedev_dec_success);
2057
2058 len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
2059 " Encryption operation fail : %d\n",
2060 pstat->qcedev_dec_fail);
2061
2062 return len;
2063}
2064
2065static int _debug_stats_open(struct inode *inode, struct file *file)
2066{
2067 file->private_data = inode->i_private;
2068 return 0;
2069}
2070
2071static ssize_t _debug_stats_read(struct file *file, char __user *buf,
2072 size_t count, loff_t *ppos)
2073{
2074 ssize_t rc = -EINVAL;
2075 int qcedev = *((int *) file->private_data);
2076 int len;
2077
2078 len = _disp_stats(qcedev);
2079
2080 if (len <= count)
2081 rc = simple_read_from_buffer((void __user *) buf, len,
2082 ppos, (void *) _debug_read_buf, len);
2083 return rc;
2084}
2085
2086static ssize_t _debug_stats_write(struct file *file, const char __user *buf,
2087 size_t count, loff_t *ppos)
2088{
2089 memset((char *)&_qcedev_stat, 0, sizeof(struct qcedev_stat));
2090 return count;
2091};
2092
2093static const struct file_operations _debug_stats_ops = {
2094 .open = _debug_stats_open,
2095 .read = _debug_stats_read,
2096 .write = _debug_stats_write,
2097};
2098
2099static int _qcedev_debug_init(void)
2100{
2101 int rc;
2102 char name[DEBUG_MAX_FNAME];
2103 struct dentry *dent;
2104
2105 _debug_dent = debugfs_create_dir("qcedev", NULL);
2106 if (IS_ERR(_debug_dent)) {
2107 pr_err("qcedev debugfs_create_dir fail, error %ld\n",
2108 PTR_ERR(_debug_dent));
2109 return PTR_ERR(_debug_dent);
2110 }
2111
2112 snprintf(name, DEBUG_MAX_FNAME-1, "stats-%d", 1);
2113 _debug_qcedev = 0;
2114 dent = debugfs_create_file(name, 0644, _debug_dent,
2115 &_debug_qcedev, &_debug_stats_ops);
2116 if (dent == NULL) {
2117 pr_err("qcedev debugfs_create_file fail, error %ld\n",
2118 PTR_ERR(dent));
2119 rc = PTR_ERR(dent);
2120 goto err;
2121 }
2122 return 0;
2123err:
2124 debugfs_remove_recursive(_debug_dent);
2125 return rc;
2126}
2127
2128static int qcedev_init(void)
2129{
2130 int rc;
2131
2132 rc = _qcedev_debug_init();
2133 if (rc)
2134 return rc;
2135 return platform_driver_register(&qcedev_plat_driver);
2136}
2137
2138static void qcedev_exit(void)
2139{
2140 debugfs_remove_recursive(_debug_dent);
2141 platform_driver_unregister(&qcedev_plat_driver);
2142}
2143
2144MODULE_LICENSE("GPL v2");
2145MODULE_DESCRIPTION("QTI DEV Crypto driver");
2146
2147module_init(qcedev_init);
2148module_exit(qcedev_exit);