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Mike Turquetteb24764902012-03-15 23:11:19 -07001/*
2 * linux/include/linux/clk-provider.h
3 *
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef __LINUX_CLK_PROVIDER_H
12#define __LINUX_CLK_PROVIDER_H
13
Gerhard Sittigaa514ce2013-07-22 14:14:40 +020014#include <linux/io.h>
Maxime Ripard355bb162014-08-30 21:18:00 +020015#include <linux/of.h>
Stephen Boyd5cb05a12016-05-16 11:05:16 +053016#include <linux/mutex.h>
Mike Turquetteb24764902012-03-15 23:11:19 -070017
18#ifdef CONFIG_COMMON_CLK
19
Mike Turquetteb24764902012-03-15 23:11:19 -070020/*
21 * flags used across common struct clk. these flags should only affect the
22 * top-level framework. custom flags for dealing with hardware specifics
23 * belong in struct clk_foo
24 */
25#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
26#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
27#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
28#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
Stephen Boydb9610e72016-06-01 14:56:57 -070029 /* unused */
Rajendra Nayakf7d8caa2012-06-01 14:02:47 +053030#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
Ulf Hanssona093bde2012-08-31 14:21:28 +020031#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
James Hogan819c1de2013-07-29 12:25:01 +010032#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
Boris BREZILLON5279fc42013-12-21 10:34:47 +010033#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
Bartlomiej Zolnierkiewiczd8d91982015-04-03 18:43:44 +020034#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
Heiko Stuebner2eb8c712015-12-22 22:27:58 +010035#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
Lee Jones32b9b102016-02-11 13:19:09 -080036#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
Dong Aishenga4b35182016-06-30 17:31:13 +080037/* parents need enable during gate/ungate, set rate and re-parent */
38#define CLK_OPS_PARENT_ENABLE BIT(12)
Michael Turquettee9b8c592017-04-21 12:27:39 +053039#define CLK_ENABLE_HAND_OFF BIT(13) /* enable clock when registered. */
40 /*
41 * hand-off enable_count & prepare_count
42 * to first consumer that enables clk
43 */
Taniya Das8436bd72016-11-21 17:50:13 +053044#define CLK_IS_MEASURE BIT(14) /* measure clock */
Mike Turquetteb24764902012-03-15 23:11:19 -070045
Stephen Boyd61ae7652015-06-22 17:13:49 -070046struct clk;
Saravana Kannan0197b3e2012-04-25 22:58:56 -070047struct clk_hw;
Tomeu Vizoso035a61c2015-01-23 12:03:30 +010048struct clk_core;
Alex Elderc646cbf2014-03-21 06:43:56 -050049struct dentry;
Saravana Kannan0197b3e2012-04-25 22:58:56 -070050
Mike Turquetteb24764902012-03-15 23:11:19 -070051/**
Boris Brezillon0817b622015-07-07 20:48:08 +020052 * struct clk_rate_request - Structure encoding the clk constraints that
53 * a clock user might require.
54 *
55 * @rate: Requested clock rate. This field will be adjusted by
56 * clock drivers according to hardware capabilities.
57 * @min_rate: Minimum rate imposed by clk users.
Masahiro Yamada1971dfb2015-11-05 18:02:34 +090058 * @max_rate: Maximum rate imposed by clk users.
Boris Brezillon0817b622015-07-07 20:48:08 +020059 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
60 * requested constraints.
61 * @best_parent_hw: The most appropriate parent clock that fulfills the
62 * requested constraints.
63 *
64 */
65struct clk_rate_request {
66 unsigned long rate;
67 unsigned long min_rate;
68 unsigned long max_rate;
69 unsigned long best_parent_rate;
70 struct clk_hw *best_parent_hw;
71};
72
73/**
Mike Turquetteb24764902012-03-15 23:11:19 -070074 * struct clk_ops - Callback operations for hardware clocks; these are to
75 * be provided by the clock implementation, and will be called by drivers
76 * through the clk_* api.
77 *
78 * @prepare: Prepare the clock for enabling. This must not return until
Geert Uytterhoeven725b4182014-04-22 15:11:41 +020079 * the clock is fully prepared, and it's safe to call clk_enable.
80 * This callback is intended to allow clock implementations to
81 * do any initialisation that may sleep. Called with
82 * prepare_lock held.
Mike Turquetteb24764902012-03-15 23:11:19 -070083 *
84 * @unprepare: Release the clock from its prepared state. This will typically
Geert Uytterhoeven725b4182014-04-22 15:11:41 +020085 * undo any work done in the @prepare callback. Called with
86 * prepare_lock held.
Mike Turquetteb24764902012-03-15 23:11:19 -070087 *
Ulf Hansson3d6ee282013-03-12 20:26:02 +010088 * @is_prepared: Queries the hardware to determine if the clock is prepared.
89 * This function is allowed to sleep. Optional, if this op is not
90 * set then the prepare count will be used.
91 *
Ulf Hansson3cc82472013-03-12 20:26:04 +010092 * @unprepare_unused: Unprepare the clock atomically. Only called from
93 * clk_disable_unused for prepare clocks with special needs.
94 * Called with prepare mutex held. This function may sleep.
95 *
Mike Turquetteb24764902012-03-15 23:11:19 -070096 * @enable: Enable the clock atomically. This must not return until the
Geert Uytterhoeven725b4182014-04-22 15:11:41 +020097 * clock is generating a valid clock signal, usable by consumer
98 * devices. Called with enable_lock held. This function must not
99 * sleep.
Mike Turquetteb24764902012-03-15 23:11:19 -0700100 *
101 * @disable: Disable the clock atomically. Called with enable_lock held.
Geert Uytterhoeven725b4182014-04-22 15:11:41 +0200102 * This function must not sleep.
Mike Turquetteb24764902012-03-15 23:11:19 -0700103 *
Stephen Boyd119c7122012-10-03 23:38:53 -0700104 * @is_enabled: Queries the hardware to determine if the clock is enabled.
Geert Uytterhoeven725b4182014-04-22 15:11:41 +0200105 * This function must not sleep. Optional, if this op is not
106 * set then the enable count will be used.
Stephen Boyd119c7122012-10-03 23:38:53 -0700107 *
Mike Turquette7c045a52012-12-04 11:00:35 -0800108 * @disable_unused: Disable the clock atomically. Only called from
109 * clk_disable_unused for gate clocks with special needs.
110 * Called with enable_lock held. This function must not
111 * sleep.
112 *
Stephen Boyd7ce3e8c2012-10-03 23:38:54 -0700113 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
Geert Uytterhoeven725b4182014-04-22 15:11:41 +0200114 * parent rate is an input parameter. It is up to the caller to
115 * ensure that the prepare_mutex is held across this call.
116 * Returns the calculated rate. Optional, but recommended - if
117 * this op is not set then clock rate will be initialized to 0.
Mike Turquetteb24764902012-03-15 23:11:19 -0700118 *
119 * @round_rate: Given a target rate as input, returns the closest rate actually
Geert Uytterhoeven54e73012014-04-22 15:11:42 +0200120 * supported by the clock. The parent rate is an input/output
121 * parameter.
Mike Turquetteb24764902012-03-15 23:11:19 -0700122 *
James Hogan71472c02013-07-29 12:25:00 +0100123 * @determine_rate: Given a target rate as input, returns the closest rate
124 * actually supported by the clock, and optionally the parent clock
125 * that should be used to provide the clock rate.
126 *
Mike Turquetteb24764902012-03-15 23:11:19 -0700127 * @set_parent: Change the input source of this clock; for clocks with multiple
Geert Uytterhoeven54e73012014-04-22 15:11:42 +0200128 * possible parents specify a new parent by passing in the index
129 * as a u8 corresponding to the parent in either the .parent_names
130 * or .parents arrays. This function in affect translates an
131 * array index into the value programmed into the hardware.
132 * Returns 0 on success, -EERROR otherwise.
133 *
Mike Turquetteb24764902012-03-15 23:11:19 -0700134 * @get_parent: Queries the hardware to determine the parent of a clock. The
Geert Uytterhoeven725b4182014-04-22 15:11:41 +0200135 * return value is a u8 which specifies the index corresponding to
136 * the parent clock. This index can be applied to either the
137 * .parent_names or .parents arrays. In short, this function
138 * translates the parent value read from hardware into an array
139 * index. Currently only called when the clock is initialized by
140 * __clk_init. This callback is mandatory for clocks with
141 * multiple parents. It is optional (and unnecessary) for clocks
142 * with 0 or 1 parents.
Mike Turquetteb24764902012-03-15 23:11:19 -0700143 *
Shawn Guo1c0035d2012-04-12 20:50:18 +0800144 * @set_rate: Change the rate of this clock. The requested rate is specified
145 * by the second argument, which should typically be the return
146 * of .round_rate call. The third argument gives the parent rate
147 * which is likely helpful for most .set_rate implementation.
148 * Returns 0 on success, -EERROR otherwise.
Mike Turquetteb24764902012-03-15 23:11:19 -0700149 *
Stephen Boyd3fa22522014-01-15 10:47:22 -0800150 * @set_rate_and_parent: Change the rate and the parent of this clock. The
151 * requested rate is specified by the second argument, which
152 * should typically be the return of .round_rate call. The
153 * third argument gives the parent rate which is likely helpful
154 * for most .set_rate_and_parent implementation. The fourth
155 * argument gives the parent index. This callback is optional (and
156 * unnecessary) for clocks with 0 or 1 parents as well as
157 * for clocks that can tolerate switching the rate and the parent
158 * separately via calls to .set_parent and .set_rate.
159 * Returns 0 on success, -EERROR otherwise.
160 *
Geert Uytterhoeven54e73012014-04-22 15:11:42 +0200161 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
162 * is expressed in ppb (parts per billion). The parent accuracy is
163 * an input parameter.
164 * Returns the calculated accuracy. Optional - if this op is not
165 * set then clock accuracy will be initialized to parent accuracy
166 * or 0 (perfect clock) if clock has no parent.
167 *
Maxime Ripard9824cf72014-07-14 13:53:27 +0200168 * @get_phase: Queries the hardware to get the current phase of a clock.
169 * Returned values are 0-359 degrees on success, negative
170 * error codes on failure.
171 *
Mike Turquettee59c5372014-02-18 21:21:25 -0800172 * @set_phase: Shift the phase this clock signal in degrees specified
173 * by the second argument. Valid values for degrees are
174 * 0-359. Return 0 on success, otherwise -EERROR.
175 *
Geert Uytterhoeven54e73012014-04-22 15:11:42 +0200176 * @init: Perform platform-specific initialization magic.
177 * This is not not used by any of the basic clock types.
178 * Please consider other ways of solving initialization problems
179 * before using this callback, as its use is discouraged.
180 *
Alex Elderc646cbf2014-03-21 06:43:56 -0500181 * @debug_init: Set up type-specific debugfs entries for this clock. This
182 * is called once, after the debugfs directory entry for this
183 * clock has been created. The dentry pointer representing that
184 * directory is provided as an argument. Called with
185 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
186 *
Taniya Das63c20c72016-06-15 12:15:01 +0530187 * @set_flags: Set custom flags which deal with hardware specifics. Returns 0
188 * on success, -EERROR otherwise.
Stephen Boyd3fa22522014-01-15 10:47:22 -0800189 *
Taniya Das2dd25722016-11-14 11:26:02 +0530190 * @list_registers: Queries the hardware to get the current register contents.
191 * This callback is optional.
192 *
Taniya Das876112d2016-11-14 11:54:02 +0530193 * @list_rate: On success, return the nth supported frequency for a given
194 * clock that is below rate_max. Return -ENXIO in case there is
195 * no frequency table.
196 *
Mike Turquetteb24764902012-03-15 23:11:19 -0700197 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
198 * implementations to split any work between atomic (enable) and sleepable
199 * (prepare) contexts. If enabling a clock requires code that might sleep,
200 * this must be done in clk_prepare. Clock enable code that will never be
Stephen Boyd7ce3e8c2012-10-03 23:38:54 -0700201 * called in a sleepable context may be implemented in clk_enable.
Mike Turquetteb24764902012-03-15 23:11:19 -0700202 *
203 * Typically, drivers will call clk_prepare when a clock may be needed later
204 * (eg. when a device is opened), and clk_enable when the clock is actually
205 * required (eg. from an interrupt). Note that clk_prepare MUST have been
206 * called before clk_enable.
207 */
208struct clk_ops {
209 int (*prepare)(struct clk_hw *hw);
210 void (*unprepare)(struct clk_hw *hw);
Ulf Hansson3d6ee282013-03-12 20:26:02 +0100211 int (*is_prepared)(struct clk_hw *hw);
Ulf Hansson3cc82472013-03-12 20:26:04 +0100212 void (*unprepare_unused)(struct clk_hw *hw);
Mike Turquetteb24764902012-03-15 23:11:19 -0700213 int (*enable)(struct clk_hw *hw);
214 void (*disable)(struct clk_hw *hw);
215 int (*is_enabled)(struct clk_hw *hw);
Mike Turquette7c045a52012-12-04 11:00:35 -0800216 void (*disable_unused)(struct clk_hw *hw);
Mike Turquetteb24764902012-03-15 23:11:19 -0700217 unsigned long (*recalc_rate)(struct clk_hw *hw,
218 unsigned long parent_rate);
Geert Uytterhoeven54e73012014-04-22 15:11:42 +0200219 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
220 unsigned long *parent_rate);
Boris Brezillon0817b622015-07-07 20:48:08 +0200221 int (*determine_rate)(struct clk_hw *hw,
222 struct clk_rate_request *req);
Mike Turquetteb24764902012-03-15 23:11:19 -0700223 int (*set_parent)(struct clk_hw *hw, u8 index);
224 u8 (*get_parent)(struct clk_hw *hw);
Geert Uytterhoeven54e73012014-04-22 15:11:42 +0200225 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
226 unsigned long parent_rate);
Stephen Boyd3fa22522014-01-15 10:47:22 -0800227 int (*set_rate_and_parent)(struct clk_hw *hw,
228 unsigned long rate,
229 unsigned long parent_rate, u8 index);
Boris BREZILLON5279fc42013-12-21 10:34:47 +0100230 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
231 unsigned long parent_accuracy);
Maxime Ripard9824cf72014-07-14 13:53:27 +0200232 int (*get_phase)(struct clk_hw *hw);
Mike Turquettee59c5372014-02-18 21:21:25 -0800233 int (*set_phase)(struct clk_hw *hw, int degrees);
Mike Turquetteb24764902012-03-15 23:11:19 -0700234 void (*init)(struct clk_hw *hw);
Alex Elderc646cbf2014-03-21 06:43:56 -0500235 int (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
Taniya Das63c20c72016-06-15 12:15:01 +0530236 int (*set_flags)(struct clk_hw *hw, unsigned int flags);
Taniya Das2dd25722016-11-14 11:26:02 +0530237 void (*list_registers)(struct seq_file *f,
238 struct clk_hw *hw);
Taniya Das876112d2016-11-14 11:54:02 +0530239 long (*list_rate)(struct clk_hw *hw, unsigned int n,
240 unsigned long rate_max);
Mike Turquetteb24764902012-03-15 23:11:19 -0700241};
242
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700243/**
244 * struct clk_init_data - holds init data that's common to all clocks and is
245 * shared between the clock provider and the common clock framework.
246 *
247 * @name: clock name
248 * @ops: operations this clock supports
249 * @parent_names: array of string names for all possible parents
250 * @num_parents: number of possible parents
251 * @flags: framework-level hints and quirks
Stephen Boyd5cb05a12016-05-16 11:05:16 +0530252 * @vdd_class: voltage scaling requirement class
253 * @rate_max: maximum clock rate in Hz supported at each voltage level
254 * @num_rate_max: number of maximum voltage level supported
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700255 */
256struct clk_init_data {
257 const char *name;
258 const struct clk_ops *ops;
Sascha Hauer2893c372015-03-31 20:16:52 +0200259 const char * const *parent_names;
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700260 u8 num_parents;
261 unsigned long flags;
Stephen Boyd5cb05a12016-05-16 11:05:16 +0530262 struct clk_vdd_class *vdd_class;
263 unsigned long *rate_max;
264 int num_rate_max;
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700265};
266
Stephen Boyd5cb05a12016-05-16 11:05:16 +0530267struct regulator;
268
269/**
270 * struct clk_vdd_class - Voltage scaling class
271 * @class_name: name of the class
272 * @regulator: array of regulators
273 * @num_regulators: size of regulator array. Standard regulator APIs will be
274 used if this field > 0
275 * @set_vdd: function to call when applying a new voltage setting
276 * @vdd_uv: sorted 2D array of legal voltage settings. Indexed by level, then
277 regulator
278 * @level_votes: array of votes for each level
279 * @num_levels: specifies the size of level_votes array
Taniya Daseee50c82016-12-03 19:06:59 +0530280 * @skip_handoff: do not vote for the max possible voltage during init
281 * @use_max_uV: use INT_MAX for max_uV when calling regulator_set_voltage
Stephen Boyd5cb05a12016-05-16 11:05:16 +0530282 * @cur_level: the currently set voltage level
283 * @lock: lock to protect this struct
284 */
285struct clk_vdd_class {
286 const char *class_name;
287 struct regulator **regulator;
288 int num_regulators;
289 int (*set_vdd)(struct clk_vdd_class *v_class, int level);
290 int *vdd_uv;
291 int *level_votes;
292 int num_levels;
Taniya Daseee50c82016-12-03 19:06:59 +0530293 bool skip_handoff;
294 bool use_max_uV;
Stephen Boyd5cb05a12016-05-16 11:05:16 +0530295 unsigned long cur_level;
296 struct mutex lock;
297};
298
299#define DEFINE_VDD_CLASS(_name, _set_vdd, _num_levels) \
300 struct clk_vdd_class _name = { \
301 .class_name = #_name, \
302 .set_vdd = _set_vdd, \
303 .level_votes = (int [_num_levels]) {}, \
304 .num_levels = _num_levels, \
305 .cur_level = _num_levels, \
306 .lock = __MUTEX_INITIALIZER(_name.lock) \
307 }
308
309#define DEFINE_VDD_REGULATORS(_name, _num_levels, _num_regulators, _vdd_uv) \
310 struct clk_vdd_class _name = { \
311 .class_name = #_name, \
312 .vdd_uv = _vdd_uv, \
313 .regulator = (struct regulator * [_num_regulators]) {}, \
314 .num_regulators = _num_regulators, \
315 .level_votes = (int [_num_levels]) {}, \
316 .num_levels = _num_levels, \
317 .cur_level = _num_levels, \
318 .lock = __MUTEX_INITIALIZER(_name.lock) \
319 }
320
321#define DEFINE_VDD_REGS_INIT(_name, _num_regulators) \
322 struct clk_vdd_class _name = { \
323 .class_name = #_name, \
324 .regulator = (struct regulator * [_num_regulators]) {}, \
325 .num_regulators = _num_regulators, \
326 .lock = __MUTEX_INITIALIZER(_name.lock) \
327 }
328
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700329/**
330 * struct clk_hw - handle for traversing from a struct clk to its corresponding
331 * hardware-specific structure. struct clk_hw should be declared within struct
332 * clk_foo and then referenced by the struct clk instance that uses struct
333 * clk_foo's clk_ops
334 *
Tomeu Vizoso035a61c2015-01-23 12:03:30 +0100335 * @core: pointer to the struct clk_core instance that points back to this
336 * struct clk_hw instance
337 *
338 * @clk: pointer to the per-user struct clk instance that can be used to call
339 * into the clk API
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700340 *
341 * @init: pointer to struct clk_init_data that contains the init data shared
342 * with the common clock framework.
343 */
344struct clk_hw {
Tomeu Vizoso035a61c2015-01-23 12:03:30 +0100345 struct clk_core *core;
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700346 struct clk *clk;
Mark Browndc4cd942012-05-14 15:12:42 +0100347 const struct clk_init_data *init;
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700348};
349
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700350/*
351 * DOC: Basic clock implementations common to many platforms
352 *
353 * Each basic clock hardware type is comprised of a structure describing the
354 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
355 * unique flags for that hardware type, a registration function and an
356 * alternative macro for static initialization
357 */
358
359/**
360 * struct clk_fixed_rate - fixed-rate clock
361 * @hw: handle between common and hardware-specific interfaces
362 * @fixed_rate: constant frequency of clock
363 */
364struct clk_fixed_rate {
365 struct clk_hw hw;
366 unsigned long fixed_rate;
Boris BREZILLON0903ea62013-12-21 10:34:48 +0100367 unsigned long fixed_accuracy;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700368 u8 flags;
369};
370
Geliang Tang5fd9c052016-01-08 23:51:46 +0800371#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
372
Shawn Guobffad662012-03-27 15:23:23 +0800373extern const struct clk_ops clk_fixed_rate_ops;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700374struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
375 const char *parent_name, unsigned long flags,
376 unsigned long fixed_rate);
Stephen Boyd26ef56b2016-02-07 00:34:13 -0800377struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,
378 const char *parent_name, unsigned long flags,
379 unsigned long fixed_rate);
Boris BREZILLON0903ea62013-12-21 10:34:48 +0100380struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
381 const char *name, const char *parent_name, unsigned long flags,
382 unsigned long fixed_rate, unsigned long fixed_accuracy);
Masahiro Yamada0b225e42016-01-06 13:25:10 +0900383void clk_unregister_fixed_rate(struct clk *clk);
Stephen Boyd26ef56b2016-02-07 00:34:13 -0800384struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
385 const char *name, const char *parent_name, unsigned long flags,
386 unsigned long fixed_rate, unsigned long fixed_accuracy);
Masahiro Yamada52445632016-05-22 14:33:35 +0900387void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
Stephen Boyd26ef56b2016-02-07 00:34:13 -0800388
Grant Likely015ba402012-04-07 21:39:39 -0500389void of_fixed_clk_setup(struct device_node *np);
390
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700391/**
392 * struct clk_gate - gating clock
393 *
394 * @hw: handle between common and hardware-specific interfaces
395 * @reg: register controlling gate
396 * @bit_idx: single bit controlling gate
397 * @flags: hardware-specific flags
398 * @lock: register lock
399 *
400 * Clock which can gate its output. Implements .enable & .disable
401 *
402 * Flags:
Viresh Kumar1f73f312012-04-17 16:45:35 +0530403 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
Geert Uytterhoeven725b4182014-04-22 15:11:41 +0200404 * enable the clock. Setting this flag does the opposite: setting the bit
405 * disable the clock and clearing it enables the clock
Haojian Zhuang04577992013-06-08 22:47:19 +0800406 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
Geert Uytterhoeven725b4182014-04-22 15:11:41 +0200407 * of this register, and mask of gate bits are in higher 16-bit of this
408 * register. While setting the gate bits, higher 16-bit should also be
409 * updated to indicate changing gate bits.
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700410 */
411struct clk_gate {
412 struct clk_hw hw;
413 void __iomem *reg;
414 u8 bit_idx;
415 u8 flags;
416 spinlock_t *lock;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700417};
418
Geliang Tang5fd9c052016-01-08 23:51:46 +0800419#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
420
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700421#define CLK_GATE_SET_TO_DISABLE BIT(0)
Haojian Zhuang04577992013-06-08 22:47:19 +0800422#define CLK_GATE_HIWORD_MASK BIT(1)
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700423
Shawn Guobffad662012-03-27 15:23:23 +0800424extern const struct clk_ops clk_gate_ops;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700425struct clk *clk_register_gate(struct device *dev, const char *name,
426 const char *parent_name, unsigned long flags,
427 void __iomem *reg, u8 bit_idx,
428 u8 clk_gate_flags, spinlock_t *lock);
Stephen Boyde270d8c2016-02-06 23:54:45 -0800429struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
430 const char *parent_name, unsigned long flags,
431 void __iomem *reg, u8 bit_idx,
432 u8 clk_gate_flags, spinlock_t *lock);
Krzysztof Kozlowski4e3c0212015-01-05 10:52:40 +0100433void clk_unregister_gate(struct clk *clk);
Stephen Boyde270d8c2016-02-06 23:54:45 -0800434void clk_hw_unregister_gate(struct clk_hw *hw);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700435
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530436struct clk_div_table {
437 unsigned int val;
438 unsigned int div;
439};
440
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700441/**
442 * struct clk_divider - adjustable divider clock
443 *
444 * @hw: handle between common and hardware-specific interfaces
445 * @reg: register containing the divider
446 * @shift: shift to the divider bit field
447 * @width: width of the divider bit field
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530448 * @table: array of value/divider pairs, last entry should have div = 0
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700449 * @lock: register lock
450 *
451 * Clock with an adjustable divider affecting its output frequency. Implements
452 * .recalc_rate, .set_rate and .round_rate
453 *
454 * Flags:
455 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
Geert Uytterhoeven725b4182014-04-22 15:11:41 +0200456 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
457 * the raw value read from the register, with the value of zero considered
Soren Brinkmann056b20532013-04-02 15:36:56 -0700458 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700459 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
Geert Uytterhoeven725b4182014-04-22 15:11:41 +0200460 * the hardware register
Soren Brinkmann056b20532013-04-02 15:36:56 -0700461 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
462 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
463 * Some hardware implementations gracefully handle this case and allow a
464 * zero divisor by not modifying their input clock
465 * (divide by one / bypass).
Haojian Zhuangd57dfe72013-06-08 22:47:18 +0800466 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
Geert Uytterhoeven725b4182014-04-22 15:11:41 +0200467 * of this register, and mask of divider bits are in higher 16-bit of this
468 * register. While setting the divider bits, higher 16-bit should also be
469 * updated to indicate changing divider bits.
Maxime COQUELIN774b5142014-01-29 17:24:07 +0100470 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
471 * to the closest integer instead of the up one.
Heiko Stuebner79c6ab52014-05-23 18:32:15 +0530472 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
473 * not be changed by the clock framework.
Jim Quinlanafe76c8f2015-05-15 15:45:47 -0400474 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
475 * except when the value read from the register is zero, the divisor is
476 * 2^width of the field.
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700477 */
478struct clk_divider {
479 struct clk_hw hw;
480 void __iomem *reg;
481 u8 shift;
482 u8 width;
483 u8 flags;
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530484 const struct clk_div_table *table;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700485 spinlock_t *lock;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700486};
487
Geliang Tang5fd9c052016-01-08 23:51:46 +0800488#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
489
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700490#define CLK_DIVIDER_ONE_BASED BIT(0)
491#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
Soren Brinkmann056b20532013-04-02 15:36:56 -0700492#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
Haojian Zhuangd57dfe72013-06-08 22:47:18 +0800493#define CLK_DIVIDER_HIWORD_MASK BIT(3)
Maxime COQUELIN774b5142014-01-29 17:24:07 +0100494#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
Heiko Stuebner79c6ab52014-05-23 18:32:15 +0530495#define CLK_DIVIDER_READ_ONLY BIT(5)
Jim Quinlanafe76c8f2015-05-15 15:45:47 -0400496#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
Vicky Wallace9c866bb2017-05-05 12:21:28 -0700497#define CLK_DIVIDER_ROUND_KHZ BIT(7)
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700498
Shawn Guobffad662012-03-27 15:23:23 +0800499extern const struct clk_ops clk_divider_ops;
Heiko Stuebner50359812016-01-21 21:53:09 +0100500extern const struct clk_ops clk_divider_ro_ops;
Stephen Boydbca96902015-01-19 18:05:29 -0800501
502unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
503 unsigned int val, const struct clk_div_table *table,
504 unsigned long flags);
505long divider_round_rate(struct clk_hw *hw, unsigned long rate,
506 unsigned long *prate, const struct clk_div_table *table,
507 u8 width, unsigned long flags);
508int divider_get_val(unsigned long rate, unsigned long parent_rate,
509 const struct clk_div_table *table, u8 width,
510 unsigned long flags);
511
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700512struct clk *clk_register_divider(struct device *dev, const char *name,
513 const char *parent_name, unsigned long flags,
514 void __iomem *reg, u8 shift, u8 width,
515 u8 clk_divider_flags, spinlock_t *lock);
Stephen Boydeb7d2642016-02-06 23:26:37 -0800516struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
517 const char *parent_name, unsigned long flags,
518 void __iomem *reg, u8 shift, u8 width,
519 u8 clk_divider_flags, spinlock_t *lock);
Rajendra Nayak357c3f02012-06-29 19:06:32 +0530520struct clk *clk_register_divider_table(struct device *dev, const char *name,
521 const char *parent_name, unsigned long flags,
522 void __iomem *reg, u8 shift, u8 width,
523 u8 clk_divider_flags, const struct clk_div_table *table,
524 spinlock_t *lock);
Stephen Boydeb7d2642016-02-06 23:26:37 -0800525struct clk_hw *clk_hw_register_divider_table(struct device *dev,
526 const char *name, const char *parent_name, unsigned long flags,
527 void __iomem *reg, u8 shift, u8 width,
528 u8 clk_divider_flags, const struct clk_div_table *table,
529 spinlock_t *lock);
Krzysztof Kozlowski4e3c0212015-01-05 10:52:40 +0100530void clk_unregister_divider(struct clk *clk);
Stephen Boydeb7d2642016-02-06 23:26:37 -0800531void clk_hw_unregister_divider(struct clk_hw *hw);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700532
533/**
534 * struct clk_mux - multiplexer clock
535 *
536 * @hw: handle between common and hardware-specific interfaces
537 * @reg: register controlling multiplexer
538 * @shift: shift to multiplexer bit field
539 * @width: width of mutliplexer bit field
James Hogan3566d402013-03-25 14:35:07 +0000540 * @flags: hardware-specific flags
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700541 * @lock: register lock
542 *
543 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
544 * and .recalc_rate
545 *
546 * Flags:
547 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
Viresh Kumar1f73f312012-04-17 16:45:35 +0530548 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
Haojian Zhuangba492e92013-06-08 22:47:17 +0800549 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
Geert Uytterhoeven725b4182014-04-22 15:11:41 +0200550 * register, and mask of mux bits are in higher 16-bit of this register.
551 * While setting the mux bits, higher 16-bit should also be updated to
552 * indicate changing mux bits.
Stephen Boyd15a02c12015-01-19 18:05:28 -0800553 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
554 * frequency.
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700555 */
556struct clk_mux {
557 struct clk_hw hw;
558 void __iomem *reg;
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200559 u32 *table;
560 u32 mask;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700561 u8 shift;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700562 u8 flags;
563 spinlock_t *lock;
564};
565
Geliang Tang5fd9c052016-01-08 23:51:46 +0800566#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
567
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700568#define CLK_MUX_INDEX_ONE BIT(0)
569#define CLK_MUX_INDEX_BIT BIT(1)
Haojian Zhuangba492e92013-06-08 22:47:17 +0800570#define CLK_MUX_HIWORD_MASK BIT(2)
Stephen Boyd15a02c12015-01-19 18:05:28 -0800571#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
572#define CLK_MUX_ROUND_CLOSEST BIT(4)
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700573
Shawn Guobffad662012-03-27 15:23:23 +0800574extern const struct clk_ops clk_mux_ops;
Tomasz Figac57acd12013-07-23 01:49:18 +0200575extern const struct clk_ops clk_mux_ro_ops;
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200576
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700577struct clk *clk_register_mux(struct device *dev, const char *name,
Sascha Hauer2893c372015-03-31 20:16:52 +0200578 const char * const *parent_names, u8 num_parents,
579 unsigned long flags,
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700580 void __iomem *reg, u8 shift, u8 width,
581 u8 clk_mux_flags, spinlock_t *lock);
Stephen Boyd264b3172016-02-07 00:05:48 -0800582struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
583 const char * const *parent_names, u8 num_parents,
584 unsigned long flags,
585 void __iomem *reg, u8 shift, u8 width,
586 u8 clk_mux_flags, spinlock_t *lock);
Mike Turquetteb24764902012-03-15 23:11:19 -0700587
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200588struct clk *clk_register_mux_table(struct device *dev, const char *name,
Sascha Hauer2893c372015-03-31 20:16:52 +0200589 const char * const *parent_names, u8 num_parents,
590 unsigned long flags,
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200591 void __iomem *reg, u8 shift, u32 mask,
592 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
Stephen Boyd264b3172016-02-07 00:05:48 -0800593struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
594 const char * const *parent_names, u8 num_parents,
595 unsigned long flags,
596 void __iomem *reg, u8 shift, u32 mask,
597 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200598
Krzysztof Kozlowski4e3c0212015-01-05 10:52:40 +0100599void clk_unregister_mux(struct clk *clk);
Stephen Boyd264b3172016-02-07 00:05:48 -0800600void clk_hw_unregister_mux(struct clk_hw *hw);
Krzysztof Kozlowski4e3c0212015-01-05 10:52:40 +0100601
Gregory CLEMENT79b16642013-04-12 13:57:44 +0200602void of_fixed_factor_clk_setup(struct device_node *node);
603
Mike Turquetteb24764902012-03-15 23:11:19 -0700604/**
Sascha Hauerf0948f52012-05-03 15:36:14 +0530605 * struct clk_fixed_factor - fixed multiplier and divider clock
606 *
607 * @hw: handle between common and hardware-specific interfaces
608 * @mult: multiplier
609 * @div: divider
610 *
611 * Clock with a fixed multiplier and divider. The output frequency is the
612 * parent clock rate divided by div and multiplied by mult.
613 * Implements .recalc_rate, .set_rate and .round_rate
614 */
615
616struct clk_fixed_factor {
617 struct clk_hw hw;
618 unsigned int mult;
619 unsigned int div;
620};
621
Geliang Tang5fd9c052016-01-08 23:51:46 +0800622#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
623
Daniel Thompson3037e9e2015-06-10 21:04:54 +0100624extern const struct clk_ops clk_fixed_factor_ops;
Sascha Hauerf0948f52012-05-03 15:36:14 +0530625struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
626 const char *parent_name, unsigned long flags,
627 unsigned int mult, unsigned int div);
Masahiro Yamadacbf95912016-01-06 13:25:09 +0900628void clk_unregister_fixed_factor(struct clk *clk);
Stephen Boyd0759ac82016-02-07 00:11:06 -0800629struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
630 const char *name, const char *parent_name, unsigned long flags,
631 unsigned int mult, unsigned int div);
632void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
Sascha Hauerf0948f52012-05-03 15:36:14 +0530633
Heikki Krogeruse2d0e902014-05-15 16:40:25 +0300634/**
635 * struct clk_fractional_divider - adjustable fractional divider clock
636 *
637 * @hw: handle between common and hardware-specific interfaces
638 * @reg: register containing the divider
639 * @mshift: shift to the numerator bit field
640 * @mwidth: width of the numerator bit field
641 * @nshift: shift to the denominator bit field
642 * @nwidth: width of the denominator bit field
643 * @lock: register lock
644 *
645 * Clock with adjustable fractional divider affecting its output frequency.
646 */
Heikki Krogeruse2d0e902014-05-15 16:40:25 +0300647struct clk_fractional_divider {
648 struct clk_hw hw;
649 void __iomem *reg;
650 u8 mshift;
Andy Shevchenko934e2532015-09-22 18:54:09 +0300651 u8 mwidth;
Heikki Krogeruse2d0e902014-05-15 16:40:25 +0300652 u32 mmask;
653 u8 nshift;
Andy Shevchenko934e2532015-09-22 18:54:09 +0300654 u8 nwidth;
Heikki Krogeruse2d0e902014-05-15 16:40:25 +0300655 u32 nmask;
656 u8 flags;
657 spinlock_t *lock;
658};
659
Geliang Tang5fd9c052016-01-08 23:51:46 +0800660#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
661
Heikki Krogeruse2d0e902014-05-15 16:40:25 +0300662extern const struct clk_ops clk_fractional_divider_ops;
663struct clk *clk_register_fractional_divider(struct device *dev,
664 const char *name, const char *parent_name, unsigned long flags,
665 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
666 u8 clk_divider_flags, spinlock_t *lock);
Stephen Boyd39b44cf2016-02-07 00:15:09 -0800667struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
668 const char *name, const char *parent_name, unsigned long flags,
669 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
670 u8 clk_divider_flags, spinlock_t *lock);
671void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
Heikki Krogeruse2d0e902014-05-15 16:40:25 +0300672
Maxime Ripardf2e0a532015-05-19 22:19:33 +0200673/**
674 * struct clk_multiplier - adjustable multiplier clock
675 *
676 * @hw: handle between common and hardware-specific interfaces
677 * @reg: register containing the multiplier
678 * @shift: shift to the multiplier bit field
679 * @width: width of the multiplier bit field
680 * @lock: register lock
681 *
682 * Clock with an adjustable multiplier affecting its output frequency.
683 * Implements .recalc_rate, .set_rate and .round_rate
684 *
685 * Flags:
686 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
687 * from the register, with 0 being a valid value effectively
688 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
689 * set, then a null multiplier will be considered as a bypass,
690 * leaving the parent rate unmodified.
691 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
692 * rounded to the closest integer instead of the down one.
693 */
694struct clk_multiplier {
695 struct clk_hw hw;
696 void __iomem *reg;
697 u8 shift;
698 u8 width;
699 u8 flags;
700 spinlock_t *lock;
701};
702
Geliang Tang5fd9c052016-01-08 23:51:46 +0800703#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
704
Maxime Ripardf2e0a532015-05-19 22:19:33 +0200705#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
706#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
707
708extern const struct clk_ops clk_multiplier_ops;
709
Prashant Gaikwadece70092013-03-20 17:30:34 +0530710/***
711 * struct clk_composite - aggregate clock of mux, divider and gate clocks
712 *
713 * @hw: handle between common and hardware-specific interfaces
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700714 * @mux_hw: handle between composite and hardware-specific mux clock
715 * @rate_hw: handle between composite and hardware-specific rate clock
716 * @gate_hw: handle between composite and hardware-specific gate clock
Prashant Gaikwadece70092013-03-20 17:30:34 +0530717 * @mux_ops: clock ops for mux
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700718 * @rate_ops: clock ops for rate
Prashant Gaikwadece70092013-03-20 17:30:34 +0530719 * @gate_ops: clock ops for gate
720 */
721struct clk_composite {
722 struct clk_hw hw;
723 struct clk_ops ops;
724
725 struct clk_hw *mux_hw;
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700726 struct clk_hw *rate_hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530727 struct clk_hw *gate_hw;
728
729 const struct clk_ops *mux_ops;
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700730 const struct clk_ops *rate_ops;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530731 const struct clk_ops *gate_ops;
732};
733
Geliang Tang5fd9c052016-01-08 23:51:46 +0800734#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
735
Prashant Gaikwadece70092013-03-20 17:30:34 +0530736struct clk *clk_register_composite(struct device *dev, const char *name,
Sascha Hauer2893c372015-03-31 20:16:52 +0200737 const char * const *parent_names, int num_parents,
Prashant Gaikwadece70092013-03-20 17:30:34 +0530738 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700739 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
Prashant Gaikwadece70092013-03-20 17:30:34 +0530740 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
741 unsigned long flags);
Maxime Ripard92a39d92016-03-23 17:38:24 +0100742void clk_unregister_composite(struct clk *clk);
Stephen Boyd49cb3922016-02-07 00:20:31 -0800743struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
744 const char * const *parent_names, int num_parents,
745 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
746 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
747 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
748 unsigned long flags);
749void clk_hw_unregister_composite(struct clk_hw *hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530750
Jyri Sarhac873d142014-09-05 15:21:34 +0300751/***
752 * struct clk_gpio_gate - gpio gated clock
753 *
754 * @hw: handle between common and hardware-specific interfaces
755 * @gpiod: gpio descriptor
756 *
757 * Clock with a gpio control for enabling and disabling the parent clock.
758 * Implements .enable, .disable and .is_enabled
759 */
760
761struct clk_gpio {
762 struct clk_hw hw;
763 struct gpio_desc *gpiod;
764};
765
Geliang Tang5fd9c052016-01-08 23:51:46 +0800766#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
767
Jyri Sarhac873d142014-09-05 15:21:34 +0300768extern const struct clk_ops clk_gpio_gate_ops;
769struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
Martin Fuzzey820ad972015-03-18 14:53:17 +0100770 const char *parent_name, unsigned gpio, bool active_low,
Jyri Sarhac873d142014-09-05 15:21:34 +0300771 unsigned long flags);
Stephen Boydb1207432016-02-07 00:27:55 -0800772struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
773 const char *parent_name, unsigned gpio, bool active_low,
774 unsigned long flags);
775void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
Jyri Sarhac873d142014-09-05 15:21:34 +0300776
Sascha Hauerf0948f52012-05-03 15:36:14 +0530777/**
Sergej Sawazki80eeb1f2015-06-28 16:24:55 +0200778 * struct clk_gpio_mux - gpio controlled clock multiplexer
779 *
780 * @hw: see struct clk_gpio
781 * @gpiod: gpio descriptor to select the parent of this clock multiplexer
782 *
783 * Clock with a gpio control for selecting the parent clock.
784 * Implements .get_parent, .set_parent and .determine_rate
785 */
786
787extern const struct clk_ops clk_gpio_mux_ops;
788struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
Stephen Boyd37bff2c2015-07-24 09:31:29 -0700789 const char * const *parent_names, u8 num_parents, unsigned gpio,
Sergej Sawazki80eeb1f2015-06-28 16:24:55 +0200790 bool active_low, unsigned long flags);
Stephen Boydb1207432016-02-07 00:27:55 -0800791struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
792 const char * const *parent_names, u8 num_parents, unsigned gpio,
793 bool active_low, unsigned long flags);
794void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
Sergej Sawazki80eeb1f2015-06-28 16:24:55 +0200795
Sergej Sawazki80eeb1f2015-06-28 16:24:55 +0200796/**
Mike Turquetteb24764902012-03-15 23:11:19 -0700797 * clk_register - allocate a new clock, register it and return an opaque cookie
798 * @dev: device that is registering this clock
Mike Turquetteb24764902012-03-15 23:11:19 -0700799 * @hw: link to hardware-specific clock data
Mike Turquetteb24764902012-03-15 23:11:19 -0700800 *
801 * clk_register is the primary interface for populating the clock tree with new
802 * clock nodes. It returns a pointer to the newly allocated struct clk which
803 * cannot be dereferenced by driver code but may be used in conjuction with the
Mike Turquetted1302a32012-03-29 14:30:40 -0700804 * rest of the clock API. In the event of an error clk_register will return an
805 * error code; drivers must test for an error code after calling clk_register.
Mike Turquetteb24764902012-03-15 23:11:19 -0700806 */
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700807struct clk *clk_register(struct device *dev, struct clk_hw *hw);
Stephen Boyd46c87732012-09-24 13:38:04 -0700808struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
Mike Turquetteb24764902012-03-15 23:11:19 -0700809
Stephen Boyd41438042016-02-05 17:02:52 -0800810int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
811int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
812
Mark Brown1df5c932012-04-18 09:07:12 +0100813void clk_unregister(struct clk *clk);
Stephen Boyd46c87732012-09-24 13:38:04 -0700814void devm_clk_unregister(struct device *dev, struct clk *clk);
Mark Brown1df5c932012-04-18 09:07:12 +0100815
Stephen Boyd41438042016-02-05 17:02:52 -0800816void clk_hw_unregister(struct clk_hw *hw);
817void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
818
Mike Turquetteb24764902012-03-15 23:11:19 -0700819/* helper functions */
Geert Uytterhoevenb76281c2015-10-16 14:35:21 +0200820const char *__clk_get_name(const struct clk *clk);
Stephen Boyde7df6f62015-08-12 13:04:56 -0700821const char *clk_hw_get_name(const struct clk_hw *hw);
Mike Turquetteb24764902012-03-15 23:11:19 -0700822struct clk_hw *__clk_get_hw(struct clk *clk);
Stephen Boyde7df6f62015-08-12 13:04:56 -0700823unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
824struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
825struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
Stephen Boyd1a9c0692015-06-25 15:55:14 -0700826 unsigned int index);
Linus Torvalds93874682012-12-11 11:25:08 -0800827unsigned int __clk_get_enable_count(struct clk *clk);
Stephen Boyde7df6f62015-08-12 13:04:56 -0700828unsigned long clk_hw_get_rate(const struct clk_hw *hw);
Mike Turquetteb24764902012-03-15 23:11:19 -0700829unsigned long __clk_get_flags(struct clk *clk);
Stephen Boyde7df6f62015-08-12 13:04:56 -0700830unsigned long clk_hw_get_flags(const struct clk_hw *hw);
831bool clk_hw_is_prepared(const struct clk_hw *hw);
Joachim Eastwoodbe68bf82015-10-24 18:55:22 +0200832bool clk_hw_is_enabled(const struct clk_hw *hw);
Stephen Boyd2ac6b1f2012-10-03 23:38:55 -0700833bool __clk_is_enabled(struct clk *clk);
Mike Turquetteb24764902012-03-15 23:11:19 -0700834struct clk *__clk_lookup(const char *name);
Boris Brezillon0817b622015-07-07 20:48:08 +0200835int __clk_mux_determine_rate(struct clk_hw *hw,
836 struct clk_rate_request *req);
837int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
838int __clk_mux_determine_rate_closest(struct clk_hw *hw,
839 struct clk_rate_request *req);
Tomeu Vizoso42c86542015-03-11 11:34:25 +0100840void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
Stephen Boyd9783c0d2015-07-16 12:50:27 -0700841void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
842 unsigned long max_rate);
Mike Turquetteb24764902012-03-15 23:11:19 -0700843
Taniya Dasd9744c12016-08-19 10:08:28 +0530844unsigned long clk_aggregate_rate(struct clk_hw *hw,
845 const struct clk_core *parent);
846
Javier Martinez Canillas2e65d8b2015-02-12 14:58:29 +0100847static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
848{
849 dst->clk = src->clk;
850 dst->core = src->core;
851}
852
Mike Turquetteb24764902012-03-15 23:11:19 -0700853/*
854 * FIXME clock api without lock protection
855 */
Stephen Boyd1a9c0692015-06-25 15:55:14 -0700856unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
Mike Turquetteb24764902012-03-15 23:11:19 -0700857
Grant Likely766e6a42012-04-09 14:50:06 -0500858struct of_device_id;
859
860typedef void (*of_clk_init_cb_t)(struct device_node *);
861
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200862struct clk_onecell_data {
863 struct clk **clks;
864 unsigned int clk_num;
865};
866
Stephen Boyd0861e5b2016-02-05 17:38:26 -0800867struct clk_hw_onecell_data {
Masahiro Yamada5963f192016-09-23 21:29:36 +0900868 unsigned int num;
Stephen Boyd0861e5b2016-02-05 17:38:26 -0800869 struct clk_hw *hws[];
870};
871
Tero Kristo819b4862013-10-22 11:39:36 +0300872extern struct of_device_id __clk_of_table;
873
Rob Herring54196cc2014-05-08 16:09:24 -0500874#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200875
Ricardo Ribalda Delgadoc7296c52016-07-05 18:23:25 +0200876/*
877 * Use this macro when you have a driver that requires two initialization
878 * routines, one at of_clk_init(), and one at platform device probe
879 */
880#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
Shawn Guo339e1e52016-10-08 16:59:38 +0800881 static void __init name##_of_clk_init_driver(struct device_node *np) \
Ricardo Ribalda Delgadoc7296c52016-07-05 18:23:25 +0200882 { \
883 of_node_clear_flag(np, OF_POPULATED); \
884 fn(np); \
885 } \
886 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
887
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200888#ifdef CONFIG_OF
Grant Likely766e6a42012-04-09 14:50:06 -0500889int of_clk_add_provider(struct device_node *np,
890 struct clk *(*clk_src_get)(struct of_phandle_args *args,
891 void *data),
892 void *data);
Stephen Boyd0861e5b2016-02-05 17:38:26 -0800893int of_clk_add_hw_provider(struct device_node *np,
894 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
895 void *data),
896 void *data);
Grant Likely766e6a42012-04-09 14:50:06 -0500897void of_clk_del_provider(struct device_node *np);
898struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
899 void *data);
Stephen Boyd0861e5b2016-02-05 17:38:26 -0800900struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
901 void *data);
Shawn Guo494bfec2012-08-22 21:36:27 +0800902struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
Stephen Boyd0861e5b2016-02-05 17:38:26 -0800903struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
904 void *data);
Stephen Boyd929e7f32016-02-19 15:52:32 -0800905unsigned int of_clk_get_parent_count(struct device_node *np);
Dinh Nguyen2e61dfb2015-06-05 11:26:13 -0500906int of_clk_parent_fill(struct device_node *np, const char **parents,
907 unsigned int size);
Grant Likely766e6a42012-04-09 14:50:06 -0500908const char *of_clk_get_parent_name(struct device_node *np, int index);
Lee Jonesd56f8992016-02-11 13:19:11 -0800909int of_clk_detect_critical(struct device_node *np, int index,
910 unsigned long *flags);
Grant Likely766e6a42012-04-09 14:50:06 -0500911void of_clk_init(const struct of_device_id *matches);
912
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200913#else /* !CONFIG_OF */
Prashant Gaikwadf2f6c252013-01-04 12:30:52 +0530914
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200915static inline int of_clk_add_provider(struct device_node *np,
916 struct clk *(*clk_src_get)(struct of_phandle_args *args,
917 void *data),
918 void *data)
919{
920 return 0;
921}
Stephen Boyd0861e5b2016-02-05 17:38:26 -0800922static inline int of_clk_add_hw_provider(struct device_node *np,
923 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
924 void *data),
925 void *data)
926{
927 return 0;
928}
Geert Uytterhoeven20dd8822015-10-29 22:12:56 +0100929static inline void of_clk_del_provider(struct device_node *np) {}
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200930static inline struct clk *of_clk_src_simple_get(
931 struct of_phandle_args *clkspec, void *data)
932{
933 return ERR_PTR(-ENOENT);
934}
Stephen Boyd0861e5b2016-02-05 17:38:26 -0800935static inline struct clk_hw *
936of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
937{
938 return ERR_PTR(-ENOENT);
939}
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200940static inline struct clk *of_clk_src_onecell_get(
941 struct of_phandle_args *clkspec, void *data)
942{
943 return ERR_PTR(-ENOENT);
944}
Stephen Boyd0861e5b2016-02-05 17:38:26 -0800945static inline struct clk_hw *
946of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
947{
948 return ERR_PTR(-ENOENT);
949}
Rafał Miłeckid42c0472016-08-26 14:58:07 +0200950static inline unsigned int of_clk_get_parent_count(struct device_node *np)
Stephen Boyd679c51c2015-10-26 11:55:34 -0700951{
952 return 0;
953}
954static inline int of_clk_parent_fill(struct device_node *np,
955 const char **parents, unsigned int size)
956{
957 return 0;
958}
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200959static inline const char *of_clk_get_parent_name(struct device_node *np,
960 int index)
961{
962 return NULL;
963}
Lee Jonesd56f8992016-02-11 13:19:11 -0800964static inline int of_clk_detect_critical(struct device_node *np, int index,
965 unsigned long *flags)
966{
967 return 0;
968}
Geert Uytterhoeven20dd8822015-10-29 22:12:56 +0100969static inline void of_clk_init(const struct of_device_id *matches) {}
Sebastian Hesselbarth0b151de2013-05-01 02:58:28 +0200970#endif /* CONFIG_OF */
Gerhard Sittigaa514ce2013-07-22 14:14:40 +0200971
972/*
973 * wrap access to peripherals in accessor routines
974 * for improved portability across platforms
975 */
976
Gerhard Sittig6d8cdb62013-11-30 23:51:24 +0100977#if IS_ENABLED(CONFIG_PPC)
978
979static inline u32 clk_readl(u32 __iomem *reg)
980{
981 return ioread32be(reg);
982}
983
984static inline void clk_writel(u32 val, u32 __iomem *reg)
985{
986 iowrite32be(val, reg);
987}
988
989#else /* platform dependent I/O accessors */
990
Gerhard Sittigaa514ce2013-07-22 14:14:40 +0200991static inline u32 clk_readl(u32 __iomem *reg)
992{
993 return readl(reg);
994}
995
996static inline void clk_writel(u32 val, u32 __iomem *reg)
997{
998 writel(val, reg);
999}
1000
Gerhard Sittig6d8cdb62013-11-30 23:51:24 +01001001#endif /* platform dependent I/O accessors */
1002
Peter De Schrijverfb2b3c92014-06-26 18:00:53 +03001003#ifdef CONFIG_DEBUG_FS
Tomeu Vizoso61c7cdd2014-12-02 08:54:21 +01001004struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
Peter De Schrijverfb2b3c92014-06-26 18:00:53 +03001005 void *data, const struct file_operations *fops);
1006#endif
1007
Mike Turquetteb24764902012-03-15 23:11:19 -07001008#endif /* CONFIG_COMMON_CLK */
1009#endif /* CLK_PROVIDER_H */