Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 1 | |
| 2 | /* |
| 3 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | */ |
| 10 | |
Shawn Guo | 36dffd8 | 2013-04-07 10:49:34 +0800 | [diff] [blame] | 11 | #include "imx6qdl.dtsi" |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 12 | #include "imx6q-pinfunc.h" |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 13 | |
| 14 | / { |
| 15 | cpus { |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <0>; |
| 18 | |
| 19 | cpu@0 { |
| 20 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame^] | 21 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 22 | reg = <0>; |
| 23 | next-level-cache = <&L2>; |
| 24 | operating-points = < |
| 25 | /* kHz uV */ |
| 26 | 1200000 1275000 |
| 27 | 996000 1250000 |
| 28 | 792000 1150000 |
| 29 | 396000 950000 |
| 30 | >; |
| 31 | clock-latency = <61036>; /* two CLK32 periods */ |
| 32 | clocks = <&clks 104>, <&clks 6>, <&clks 16>, |
| 33 | <&clks 17>, <&clks 170>; |
| 34 | clock-names = "arm", "pll2_pfd2_396m", "step", |
| 35 | "pll1_sw", "pll1_sys"; |
| 36 | arm-supply = <®_arm>; |
| 37 | pu-supply = <®_pu>; |
| 38 | soc-supply = <®_soc>; |
| 39 | }; |
| 40 | |
| 41 | cpu@1 { |
| 42 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame^] | 43 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 44 | reg = <1>; |
| 45 | next-level-cache = <&L2>; |
| 46 | }; |
| 47 | |
| 48 | cpu@2 { |
| 49 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame^] | 50 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 51 | reg = <2>; |
| 52 | next-level-cache = <&L2>; |
| 53 | }; |
| 54 | |
| 55 | cpu@3 { |
| 56 | compatible = "arm,cortex-a9"; |
Lorenzo Pieralisi | 7925e89 | 2013-04-18 18:34:06 +0100 | [diff] [blame^] | 57 | device_type = "cpu"; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 58 | reg = <3>; |
| 59 | next-level-cache = <&L2>; |
| 60 | }; |
| 61 | }; |
| 62 | |
| 63 | soc { |
| 64 | aips-bus@02000000 { /* AIPS1 */ |
| 65 | spba-bus@02000000 { |
| 66 | ecspi5: ecspi@02018000 { |
| 67 | #address-cells = <1>; |
| 68 | #size-cells = <0>; |
| 69 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 70 | reg = <0x02018000 0x4000>; |
| 71 | interrupts = <0 35 0x04>; |
| 72 | clocks = <&clks 116>, <&clks 116>; |
| 73 | clock-names = "ipg", "per"; |
| 74 | status = "disabled"; |
| 75 | }; |
| 76 | }; |
| 77 | |
| 78 | iomuxc: iomuxc@020e0000 { |
| 79 | compatible = "fsl,imx6q-iomuxc"; |
| 80 | reg = <0x020e0000 0x4000>; |
| 81 | |
| 82 | /* shared pinctrl settings */ |
| 83 | audmux { |
| 84 | pinctrl_audmux_1: audmux-1 { |
| 85 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 86 | MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000 |
| 87 | MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000 |
| 88 | MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000 |
| 89 | MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 90 | >; |
| 91 | }; |
Sean Cross | 624dbac | 2013-03-07 06:00:10 +0000 | [diff] [blame] | 92 | |
| 93 | pinctrl_audmux_2: audmux-2 { |
| 94 | fsl,pins = < |
| 95 | MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 |
| 96 | MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 |
| 97 | MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 |
| 98 | MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 |
| 99 | >; |
| 100 | }; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 101 | }; |
| 102 | |
| 103 | ecspi1 { |
| 104 | pinctrl_ecspi1_1: ecspi1grp-1 { |
| 105 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 106 | MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1 |
| 107 | MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 |
| 108 | MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 109 | >; |
| 110 | }; |
| 111 | }; |
| 112 | |
Sean Cross | 4820a9a | 2013-03-07 06:00:08 +0000 | [diff] [blame] | 113 | ecspi3 { |
| 114 | pinctrl_ecspi3_1: ecspi3grp-1 { |
| 115 | fsl,pins = < |
| 116 | MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 |
| 117 | MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 |
| 118 | MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 |
| 119 | >; |
| 120 | }; |
| 121 | }; |
| 122 | |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 123 | enet { |
| 124 | pinctrl_enet_1: enetgrp-1 { |
| 125 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 126 | MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
| 127 | MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
| 128 | MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| 129 | MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| 130 | MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| 131 | MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| 132 | MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| 133 | MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| 134 | MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| 135 | MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| 136 | MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| 137 | MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| 138 | MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| 139 | MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| 140 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| 141 | MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 142 | >; |
| 143 | }; |
| 144 | |
| 145 | pinctrl_enet_2: enetgrp-2 { |
| 146 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 147 | MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 |
| 148 | MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0 |
| 149 | MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| 150 | MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| 151 | MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| 152 | MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| 153 | MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| 154 | MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| 155 | MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| 156 | MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| 157 | MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| 158 | MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| 159 | MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| 160 | MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| 161 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 162 | >; |
| 163 | }; |
| 164 | }; |
| 165 | |
| 166 | gpmi-nand { |
| 167 | pinctrl_gpmi_nand_1: gpmi-nand-1 { |
| 168 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 169 | MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1 |
| 170 | MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1 |
| 171 | MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 |
| 172 | MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000 |
| 173 | MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 |
| 174 | MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 |
| 175 | MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 |
| 176 | MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 |
| 177 | MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1 |
| 178 | MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1 |
| 179 | MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1 |
| 180 | MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1 |
| 181 | MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1 |
| 182 | MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1 |
| 183 | MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1 |
| 184 | MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1 |
| 185 | MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1 |
| 186 | MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1 |
| 187 | MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 188 | >; |
| 189 | }; |
| 190 | }; |
| 191 | |
| 192 | i2c1 { |
| 193 | pinctrl_i2c1_1: i2c1grp-1 { |
| 194 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 195 | MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 |
| 196 | MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 197 | >; |
| 198 | }; |
| 199 | }; |
| 200 | |
Sean Cross | d27f512a | 2013-03-07 06:00:09 +0000 | [diff] [blame] | 201 | i2c2 { |
| 202 | pinctrl_i2c2_1: i2c2grp-1 { |
| 203 | fsl,pins = < |
| 204 | MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 |
| 205 | MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 |
| 206 | >; |
| 207 | }; |
| 208 | }; |
| 209 | |
| 210 | i2c3 { |
| 211 | pinctrl_i2c3_1: i2c3grp-1 { |
| 212 | fsl,pins = < |
| 213 | MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 |
| 214 | MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 |
| 215 | >; |
| 216 | }; |
| 217 | }; |
| 218 | |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 219 | uart1 { |
| 220 | pinctrl_uart1_1: uart1grp-1 { |
| 221 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 222 | MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 |
| 223 | MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 224 | >; |
| 225 | }; |
| 226 | }; |
| 227 | |
| 228 | uart2 { |
| 229 | pinctrl_uart2_1: uart2grp-1 { |
| 230 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 231 | MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 |
| 232 | MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 233 | >; |
| 234 | }; |
| 235 | }; |
| 236 | |
| 237 | uart4 { |
| 238 | pinctrl_uart4_1: uart4grp-1 { |
| 239 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 240 | MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 |
| 241 | MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 242 | >; |
| 243 | }; |
| 244 | }; |
| 245 | |
| 246 | usbotg { |
| 247 | pinctrl_usbotg_1: usbotggrp-1 { |
| 248 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 249 | MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 250 | >; |
| 251 | }; |
Peter Chen | a10c22e | 2013-02-18 10:06:44 +0800 | [diff] [blame] | 252 | |
| 253 | pinctrl_usbotg_2: usbotggrp-2 { |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 254 | fsl,pins = < |
| 255 | MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 |
Peter Chen | a10c22e | 2013-02-18 10:06:44 +0800 | [diff] [blame] | 256 | >; |
| 257 | }; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 258 | }; |
| 259 | |
| 260 | usdhc2 { |
| 261 | pinctrl_usdhc2_1: usdhc2grp-1 { |
| 262 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 263 | MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 |
| 264 | MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 |
| 265 | MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 |
| 266 | MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 |
| 267 | MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 |
| 268 | MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 |
| 269 | MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059 |
| 270 | MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059 |
| 271 | MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059 |
| 272 | MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 273 | >; |
| 274 | }; |
| 275 | }; |
| 276 | |
| 277 | usdhc3 { |
| 278 | pinctrl_usdhc3_1: usdhc3grp-1 { |
| 279 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 280 | MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059 |
| 281 | MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059 |
| 282 | MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| 283 | MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| 284 | MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| 285 | MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| 286 | MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059 |
| 287 | MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059 |
| 288 | MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059 |
| 289 | MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 290 | >; |
| 291 | }; |
| 292 | |
| 293 | pinctrl_usdhc3_2: usdhc3grp-2 { |
| 294 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 295 | MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059 |
| 296 | MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059 |
| 297 | MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| 298 | MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| 299 | MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| 300 | MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 301 | >; |
| 302 | }; |
| 303 | }; |
| 304 | |
| 305 | usdhc4 { |
| 306 | pinctrl_usdhc4_1: usdhc4grp-1 { |
| 307 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 308 | MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059 |
| 309 | MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059 |
| 310 | MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059 |
| 311 | MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059 |
| 312 | MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059 |
| 313 | MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059 |
| 314 | MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059 |
| 315 | MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059 |
| 316 | MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059 |
| 317 | MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 318 | >; |
| 319 | }; |
| 320 | |
| 321 | pinctrl_usdhc4_2: usdhc4grp-2 { |
| 322 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 323 | MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059 |
| 324 | MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059 |
| 325 | MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059 |
| 326 | MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059 |
| 327 | MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059 |
| 328 | MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059 |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 329 | >; |
| 330 | }; |
| 331 | }; |
| 332 | }; |
| 333 | }; |
| 334 | |
| 335 | ipu2: ipu@02800000 { |
| 336 | #crtc-cells = <1>; |
| 337 | compatible = "fsl,imx6q-ipu"; |
| 338 | reg = <0x02800000 0x400000>; |
| 339 | interrupts = <0 8 0x4 0 7 0x4>; |
| 340 | clocks = <&clks 133>, <&clks 134>, <&clks 137>; |
| 341 | clock-names = "bus", "di0", "di1"; |
Philipp Zabel | 09ebf36 | 2013-03-28 17:35:20 +0100 | [diff] [blame] | 342 | resets = <&src 4>; |
Shawn Guo | 7c1da58 | 2013-02-04 23:09:16 +0800 | [diff] [blame] | 343 | }; |
| 344 | }; |
| 345 | }; |
Steffen Trumtrar | 41c0434 | 2013-03-28 16:23:35 +0100 | [diff] [blame] | 346 | |
| 347 | &ldb { |
| 348 | clocks = <&clks 33>, <&clks 34>, |
| 349 | <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>, |
| 350 | <&clks 135>, <&clks 136>; |
| 351 | clock-names = "di0_pll", "di1_pll", |
| 352 | "di0_sel", "di1_sel", "di2_sel", "di3_sel", |
| 353 | "di0", "di1"; |
| 354 | |
| 355 | lvds-channel@0 { |
| 356 | crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; |
| 357 | }; |
| 358 | |
| 359 | lvds-channel@1 { |
| 360 | crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; |
| 361 | }; |
| 362 | }; |