blob: fbf287307c4cc736c5032fdbf1ddbc3a77dec45d [file] [log] [blame]
Magnus Damma07e1032012-05-17 15:22:23 +09001/*
2 * Emma Mobile GPIO Support - GIO
3 *
4 * Copyright (C) 2012 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/irqdomain.h>
28#include <linux/bitops.h>
29#include <linux/err.h>
30#include <linux/gpio.h>
31#include <linux/slab.h>
32#include <linux/module.h>
Magnus Damm640efa02013-07-03 13:14:32 +090033#include <linux/pinctrl/consumer.h>
Magnus Damma07e1032012-05-17 15:22:23 +090034#include <linux/platform_data/gpio-em.h>
35
36struct em_gio_priv {
37 void __iomem *base0;
38 void __iomem *base1;
Magnus Damma07e1032012-05-17 15:22:23 +090039 spinlock_t sense_lock;
40 struct platform_device *pdev;
41 struct gpio_chip gpio_chip;
42 struct irq_chip irq_chip;
43 struct irq_domain *irq_domain;
44};
45
46#define GIO_E1 0x00
47#define GIO_E0 0x04
48#define GIO_EM 0x04
49#define GIO_OL 0x08
50#define GIO_OH 0x0c
51#define GIO_I 0x10
52#define GIO_IIA 0x14
53#define GIO_IEN 0x18
54#define GIO_IDS 0x1c
55#define GIO_IIM 0x1c
56#define GIO_RAW 0x20
57#define GIO_MST 0x24
58#define GIO_IIR 0x28
59
60#define GIO_IDT0 0x40
61#define GIO_IDT1 0x44
62#define GIO_IDT2 0x48
63#define GIO_IDT3 0x4c
64#define GIO_RAWBL 0x50
65#define GIO_RAWBH 0x54
66#define GIO_IRBL 0x58
67#define GIO_IRBH 0x5c
68
69#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
70
71static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
72{
73 if (offs < GIO_IDT0)
74 return ioread32(p->base0 + offs);
75 else
76 return ioread32(p->base1 + (offs - GIO_IDT0));
77}
78
79static inline void em_gio_write(struct em_gio_priv *p, int offs,
80 unsigned long value)
81{
82 if (offs < GIO_IDT0)
83 iowrite32(value, p->base0 + offs);
84 else
85 iowrite32(value, p->base1 + (offs - GIO_IDT0));
86}
87
Magnus Damma07e1032012-05-17 15:22:23 +090088static void em_gio_irq_disable(struct irq_data *d)
89{
Axel Lina9f77c92012-09-04 21:58:33 +080090 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
Magnus Damma07e1032012-05-17 15:22:23 +090091
92 em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
93}
94
95static void em_gio_irq_enable(struct irq_data *d)
96{
Axel Lina9f77c92012-09-04 21:58:33 +080097 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
Magnus Damma07e1032012-05-17 15:22:23 +090098
99 em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
100}
101
Linus Walleij57ef0422014-03-14 18:16:20 +0100102static int em_gio_irq_reqres(struct irq_data *d)
Linus Walleij0dc61622013-11-20 10:16:54 +0100103{
104 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
105
Alexandre Courbote3a2e872014-10-23 17:27:07 +0900106 if (gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) {
Linus Walleij0dc61622013-11-20 10:16:54 +0100107 dev_err(p->gpio_chip.dev,
108 "unable to lock HW IRQ %lu for IRQ\n",
109 irqd_to_hwirq(d));
Linus Walleij57ef0422014-03-14 18:16:20 +0100110 return -EINVAL;
111 }
Linus Walleij0dc61622013-11-20 10:16:54 +0100112 return 0;
113}
114
Linus Walleij57ef0422014-03-14 18:16:20 +0100115static void em_gio_irq_relres(struct irq_data *d)
Linus Walleij0dc61622013-11-20 10:16:54 +0100116{
117 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
118
Alexandre Courbote3a2e872014-10-23 17:27:07 +0900119 gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
Linus Walleij0dc61622013-11-20 10:16:54 +0100120}
121
122
Magnus Damma07e1032012-05-17 15:22:23 +0900123#define GIO_ASYNC(x) (x + 8)
124
125static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
126 [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
127 [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
128 [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
129 [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
130 [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
131};
132
133static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
134{
135 unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
Axel Lina9f77c92012-09-04 21:58:33 +0800136 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
Magnus Damma07e1032012-05-17 15:22:23 +0900137 unsigned int reg, offset, shift;
138 unsigned long flags;
139 unsigned long tmp;
140
141 if (!value)
142 return -EINVAL;
143
144 offset = irqd_to_hwirq(d);
145
146 pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
147
148 /* 8 x 4 bit fields in 4 IDT registers */
149 reg = GIO_IDT(offset >> 3);
150 shift = (offset & 0x07) << 4;
151
152 spin_lock_irqsave(&p->sense_lock, flags);
153
154 /* disable the interrupt in IIA */
155 tmp = em_gio_read(p, GIO_IIA);
156 tmp &= ~BIT(offset);
157 em_gio_write(p, GIO_IIA, tmp);
158
159 /* change the sense setting in IDT */
160 tmp = em_gio_read(p, reg);
161 tmp &= ~(0xf << shift);
162 tmp |= value << shift;
163 em_gio_write(p, reg, tmp);
164
165 /* clear pending interrupts */
166 em_gio_write(p, GIO_IIR, BIT(offset));
167
168 /* enable the interrupt in IIA */
169 tmp = em_gio_read(p, GIO_IIA);
170 tmp |= BIT(offset);
171 em_gio_write(p, GIO_IIA, tmp);
172
173 spin_unlock_irqrestore(&p->sense_lock, flags);
174
175 return 0;
176}
177
178static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
179{
180 struct em_gio_priv *p = dev_id;
181 unsigned long pending;
182 unsigned int offset, irqs_handled = 0;
183
184 while ((pending = em_gio_read(p, GIO_MST))) {
185 offset = __ffs(pending);
186 em_gio_write(p, GIO_IIR, BIT(offset));
187 generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
188 irqs_handled++;
189 }
190
191 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
192}
193
194static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
195{
196 return container_of(chip, struct em_gio_priv, gpio_chip);
197}
198
199static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
200{
201 em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
202 return 0;
203}
204
205static int em_gio_get(struct gpio_chip *chip, unsigned offset)
206{
207 return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
208}
209
210static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
211 unsigned shift, int value)
212{
213 /* upper 16 bits contains mask and lower 16 actual value */
214 em_gio_write(gpio_to_priv(chip), reg,
Javier Martinez Canillas5f077642014-04-27 02:00:47 +0200215 (BIT(shift + 16)) | (value << shift));
Magnus Damma07e1032012-05-17 15:22:23 +0900216}
217
218static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
219{
220 /* output is split into two registers */
221 if (offset < 16)
222 __em_gio_set(chip, GIO_OL, offset, value);
223 else
224 __em_gio_set(chip, GIO_OH, offset - 16, value);
225}
226
227static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
228 int value)
229{
230 /* write GPIO value to output before selecting output mode of pin */
231 em_gio_set(chip, offset, value);
232 em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
233 return 0;
234}
235
236static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
237{
Linus Walleij73855002012-10-16 20:15:02 +0200238 return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
Magnus Damma07e1032012-05-17 15:22:23 +0900239}
240
Magnus Damm640efa02013-07-03 13:14:32 +0900241static int em_gio_request(struct gpio_chip *chip, unsigned offset)
242{
243 return pinctrl_request_gpio(chip->base + offset);
244}
245
246static void em_gio_free(struct gpio_chip *chip, unsigned offset)
247{
248 pinctrl_free_gpio(chip->base + offset);
249
250 /* Set the GPIO as an input to ensure that the next GPIO request won't
251 * drive the GPIO pin as an output.
252 */
253 em_gio_direction_input(chip, offset);
254}
255
Linus Walleij2d61e3e2013-10-11 19:21:34 +0200256static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
257 irq_hw_number_t hwirq)
Magnus Damma07e1032012-05-17 15:22:23 +0900258{
259 struct em_gio_priv *p = h->host_data;
260
Linus Walleij2d61e3e2013-10-11 19:21:34 +0200261 pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
Magnus Damma07e1032012-05-17 15:22:23 +0900262
Linus Walleij2d61e3e2013-10-11 19:21:34 +0200263 irq_set_chip_data(irq, h->host_data);
264 irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
265 set_irq_flags(irq, IRQF_VALID); /* kill me now */
Magnus Damma07e1032012-05-17 15:22:23 +0900266 return 0;
267}
268
Krzysztof Kozlowski0b354dc2015-04-27 21:54:07 +0900269static const struct irq_domain_ops em_gio_irq_domain_ops = {
Magnus Damma07e1032012-05-17 15:22:23 +0900270 .map = em_gio_irq_domain_map,
Magnus Damm753c5982013-02-26 22:26:23 +0900271 .xlate = irq_domain_xlate_twocell,
Magnus Damma07e1032012-05-17 15:22:23 +0900272};
273
Bill Pemberton38363092012-11-19 13:22:34 -0500274static int em_gio_probe(struct platform_device *pdev)
Magnus Damma07e1032012-05-17 15:22:23 +0900275{
Magnus Damm753c5982013-02-26 22:26:23 +0900276 struct gpio_em_config pdata_dt;
Jingoo Hane56aee12013-07-30 17:08:05 +0900277 struct gpio_em_config *pdata = dev_get_platdata(&pdev->dev);
Magnus Damma07e1032012-05-17 15:22:23 +0900278 struct em_gio_priv *p;
279 struct resource *io[2], *irq[2];
280 struct gpio_chip *gpio_chip;
281 struct irq_chip *irq_chip;
282 const char *name = dev_name(&pdev->dev);
283 int ret;
284
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900285 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
Magnus Damma07e1032012-05-17 15:22:23 +0900286 if (!p) {
Magnus Damma07e1032012-05-17 15:22:23 +0900287 ret = -ENOMEM;
288 goto err0;
289 }
290
291 p->pdev = pdev;
292 platform_set_drvdata(pdev, p);
293 spin_lock_init(&p->sense_lock);
294
295 io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
296 io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
297 irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
298 irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
299
Magnus Damm753c5982013-02-26 22:26:23 +0900300 if (!io[0] || !io[1] || !irq[0] || !irq[1]) {
301 dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
Magnus Damma07e1032012-05-17 15:22:23 +0900302 ret = -EINVAL;
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900303 goto err0;
Magnus Damma07e1032012-05-17 15:22:23 +0900304 }
305
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900306 p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
307 resource_size(io[0]));
Magnus Damma07e1032012-05-17 15:22:23 +0900308 if (!p->base0) {
309 dev_err(&pdev->dev, "failed to remap low I/O memory\n");
310 ret = -ENXIO;
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900311 goto err0;
Magnus Damma07e1032012-05-17 15:22:23 +0900312 }
313
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900314 p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
315 resource_size(io[1]));
Magnus Damma07e1032012-05-17 15:22:23 +0900316 if (!p->base1) {
317 dev_err(&pdev->dev, "failed to remap high I/O memory\n");
318 ret = -ENXIO;
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900319 goto err0;
Magnus Damma07e1032012-05-17 15:22:23 +0900320 }
321
Magnus Damm753c5982013-02-26 22:26:23 +0900322 if (!pdata) {
323 memset(&pdata_dt, 0, sizeof(pdata_dt));
324 pdata = &pdata_dt;
325
326 if (of_property_read_u32(pdev->dev.of_node, "ngpios",
327 &pdata->number_of_pins)) {
328 dev_err(&pdev->dev, "Missing ngpios OF property\n");
329 ret = -EINVAL;
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900330 goto err0;
Magnus Damm753c5982013-02-26 22:26:23 +0900331 }
332
Geert Uytterhoevenfcb8bd42014-11-17 15:30:32 +0100333 pdata->gpio_base = -1;
Magnus Damm753c5982013-02-26 22:26:23 +0900334 }
335
Magnus Damma07e1032012-05-17 15:22:23 +0900336 gpio_chip = &p->gpio_chip;
Ian Moltonb5927852013-09-02 16:44:55 +0100337 gpio_chip->of_node = pdev->dev.of_node;
Magnus Damma07e1032012-05-17 15:22:23 +0900338 gpio_chip->direction_input = em_gio_direction_input;
339 gpio_chip->get = em_gio_get;
340 gpio_chip->direction_output = em_gio_direction_output;
341 gpio_chip->set = em_gio_set;
342 gpio_chip->to_irq = em_gio_to_irq;
Magnus Damm640efa02013-07-03 13:14:32 +0900343 gpio_chip->request = em_gio_request;
344 gpio_chip->free = em_gio_free;
Magnus Damma07e1032012-05-17 15:22:23 +0900345 gpio_chip->label = name;
Magnus Damm969bf7a2013-11-20 09:23:26 +0900346 gpio_chip->dev = &pdev->dev;
Magnus Damma07e1032012-05-17 15:22:23 +0900347 gpio_chip->owner = THIS_MODULE;
348 gpio_chip->base = pdata->gpio_base;
349 gpio_chip->ngpio = pdata->number_of_pins;
350
351 irq_chip = &p->irq_chip;
352 irq_chip->name = name;
353 irq_chip->irq_mask = em_gio_irq_disable;
354 irq_chip->irq_unmask = em_gio_irq_enable;
Magnus Damma07e1032012-05-17 15:22:23 +0900355 irq_chip->irq_set_type = em_gio_irq_set_type;
Linus Walleij57ef0422014-03-14 18:16:20 +0100356 irq_chip->irq_request_resources = em_gio_irq_reqres;
357 irq_chip->irq_release_resources = em_gio_irq_relres;
Magnus Damm03621b62013-11-20 09:23:44 +0900358 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
Magnus Damma07e1032012-05-17 15:22:23 +0900359
Magnus Dammc7886b12013-02-13 00:56:13 +0900360 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
Linus Walleij73855002012-10-16 20:15:02 +0200361 pdata->number_of_pins,
Magnus Dammc7886b12013-02-13 00:56:13 +0900362 pdata->irq_base,
Linus Walleij73855002012-10-16 20:15:02 +0200363 &em_gio_irq_domain_ops, p);
Axel Lin16310812012-10-31 17:03:33 +0800364 if (!p->irq_domain) {
365 ret = -ENXIO;
Magnus Damma07e1032012-05-17 15:22:23 +0900366 dev_err(&pdev->dev, "cannot initialize irq domain\n");
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900367 goto err0;
Magnus Damma07e1032012-05-17 15:22:23 +0900368 }
369
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900370 if (devm_request_irq(&pdev->dev, irq[0]->start,
371 em_gio_irq_handler, 0, name, p)) {
Magnus Damma07e1032012-05-17 15:22:23 +0900372 dev_err(&pdev->dev, "failed to request low IRQ\n");
373 ret = -ENOENT;
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900374 goto err1;
Magnus Damma07e1032012-05-17 15:22:23 +0900375 }
376
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900377 if (devm_request_irq(&pdev->dev, irq[1]->start,
378 em_gio_irq_handler, 0, name, p)) {
Magnus Damma07e1032012-05-17 15:22:23 +0900379 dev_err(&pdev->dev, "failed to request high IRQ\n");
380 ret = -ENOENT;
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900381 goto err1;
Magnus Damma07e1032012-05-17 15:22:23 +0900382 }
383
384 ret = gpiochip_add(gpio_chip);
385 if (ret) {
386 dev_err(&pdev->dev, "failed to add GPIO controller\n");
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900387 goto err1;
Magnus Damma07e1032012-05-17 15:22:23 +0900388 }
Magnus Damm640efa02013-07-03 13:14:32 +0900389
390 if (pdata->pctl_name) {
391 ret = gpiochip_add_pin_range(gpio_chip, pdata->pctl_name, 0,
392 gpio_chip->base, gpio_chip->ngpio);
393 if (ret < 0)
394 dev_warn(&pdev->dev, "failed to add pin range\n");
395 }
Magnus Damma07e1032012-05-17 15:22:23 +0900396 return 0;
397
Magnus Damma07e1032012-05-17 15:22:23 +0900398err1:
Magnus Damm1cfe6f82013-03-13 20:06:30 +0900399 irq_domain_remove(p->irq_domain);
Magnus Damma07e1032012-05-17 15:22:23 +0900400err0:
401 return ret;
402}
403
Bill Pemberton206210c2012-11-19 13:25:50 -0500404static int em_gio_remove(struct platform_device *pdev)
Magnus Damma07e1032012-05-17 15:22:23 +0900405{
406 struct em_gio_priv *p = platform_get_drvdata(pdev);
Magnus Damma07e1032012-05-17 15:22:23 +0900407
abdoulaye berthe9f5132a2014-07-12 22:30:12 +0200408 gpiochip_remove(&p->gpio_chip);
Magnus Damma07e1032012-05-17 15:22:23 +0900409
Axel Lin16310812012-10-31 17:03:33 +0800410 irq_domain_remove(p->irq_domain);
Magnus Damma07e1032012-05-17 15:22:23 +0900411 return 0;
412}
413
Magnus Damm753c5982013-02-26 22:26:23 +0900414static const struct of_device_id em_gio_dt_ids[] = {
415 { .compatible = "renesas,em-gio", },
416 {},
417};
418MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
419
Magnus Damma07e1032012-05-17 15:22:23 +0900420static struct platform_driver em_gio_device_driver = {
421 .probe = em_gio_probe,
Bill Pemberton8283c4f2012-11-19 13:20:08 -0500422 .remove = em_gio_remove,
Magnus Damma07e1032012-05-17 15:22:23 +0900423 .driver = {
424 .name = "em_gio",
Magnus Damm753c5982013-02-26 22:26:23 +0900425 .of_match_table = em_gio_dt_ids,
Magnus Damma07e1032012-05-17 15:22:23 +0900426 }
427};
428
Magnus Damm753c5982013-02-26 22:26:23 +0900429static int __init em_gio_init(void)
430{
431 return platform_driver_register(&em_gio_device_driver);
432}
433postcore_initcall(em_gio_init);
434
435static void __exit em_gio_exit(void)
436{
437 platform_driver_unregister(&em_gio_device_driver);
438}
439module_exit(em_gio_exit);
Magnus Damma07e1032012-05-17 15:22:23 +0900440
441MODULE_AUTHOR("Magnus Damm");
442MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
443MODULE_LICENSE("GPL v2");