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Chris Leechc13c8262006-05-23 17:18:44 -07001#
2# DMA engine configuration
3#
4
Shannon Nelson2ed6dc32007-10-16 01:27:42 -07005menuconfig DMADEVICES
Haavard Skinnemoen6d4f5872007-11-28 16:21:43 -08006 bool "DMA Engine support"
Dan Williams04ce9ab2009-06-03 14:22:28 -07007 depends on HAS_DMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -07008 help
Haavard Skinnemoen6d4f5872007-11-28 16:21:43 -08009 DMA engines can do asynchronous data transfers without
10 involving the host CPU. Currently, this framework can be
11 used to offload memory copies in the network stack and
Dan Williams9c402f42008-06-27 01:21:11 -070012 RAID operations in the MD driver. This menu only presents
13 DMA Device drivers supported by the configured arch, it may
14 be empty in some cases.
Chris Leechc13c8262006-05-23 17:18:44 -070015
Linus Walleij6c664a82010-02-09 22:34:54 +010016config DMADEVICES_DEBUG
17 bool "DMA Engine debugging"
18 depends on DMADEVICES != n
19 help
20 This is an option for use by developers; most people should
21 say N here. This enables DMA engine core and driver debugging.
22
23config DMADEVICES_VDEBUG
24 bool "DMA Engine verbose debugging"
25 depends on DMADEVICES_DEBUG != n
26 help
27 This is an option for use by developers; most people should
28 say N here. This enables deeper (more verbose) debugging of
29 the DMA engine core and drivers.
30
31
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070032if DMADEVICES
Chris Leechdb217332006-06-17 21:24:58 -070033
Chris Leech0bbd5f42006-05-23 17:35:34 -070034comment "DMA Devices"
35
Vinod Koulb3c567e2010-07-21 13:28:10 +053036config INTEL_MID_DMAC
37 tristate "Intel MID DMA support for Peripheral DMA controllers"
38 depends on PCI && X86
39 select DMA_ENGINE
40 default n
41 help
42 Enable support for the Intel(R) MID DMA engine present
43 in Intel MID chipsets.
44
45 Say Y here if you have such a chipset.
46
47 If unsure, say N.
48
Dan Williams5fc6d892010-10-07 16:44:50 -070049config ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williams138f4c32009-09-08 17:42:51 -070050 bool
51
Linus Walleije8689e62010-09-28 15:57:37 +020052config AMBA_PL08X
53 bool "ARM PrimeCell PL080 or PL081 support"
54 depends on ARM_AMBA && EXPERIMENTAL
55 select DMA_ENGINE
56 help
57 Platform has a PL08x DMAC device
58 which can provide DMA engine support
59
Chris Leech0bbd5f42006-05-23 17:35:34 -070060config INTEL_IOATDMA
61 tristate "Intel I/OAT DMA support"
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070062 depends on PCI && X86
63 select DMA_ENGINE
64 select DCA
Dan Williams7b3cc2b2009-11-19 17:10:37 -070065 select ASYNC_TX_DISABLE_PQ_VAL_DMA
66 select ASYNC_TX_DISABLE_XOR_VAL_DMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070067 help
68 Enable support for the Intel(R) I/OAT DMA engine present
69 in recent Intel Xeon chipsets.
70
71 Say Y here if you have such a chipset.
72
73 If unsure, say N.
Dan Williamsc2110922007-01-02 13:52:26 -070074
75config INTEL_IOP_ADMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070076 tristate "Intel IOP ADMA support"
77 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070078 select DMA_ENGINE
Dan Williams5fc6d892010-10-07 16:44:50 -070079 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070080 help
81 Enable support for the Intel(R) IOP Series RAID engines.
Dan Williamsc2110922007-01-02 13:52:26 -070082
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070083config DW_DMAC
84 tristate "Synopsys DesignWare AHB DMA support"
Viresh Kumarf44ad7e2011-03-03 15:47:14 +053085 depends on HAVE_CLK
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070086 select DMA_ENGINE
87 default y if CPU_AT32AP7000
88 help
89 Support the Synopsys DesignWare AHB DMA controller. This
90 can be integrated in chips such as the Atmel AT32ap7000.
91
Nicolas Ferredc78baa2009-07-03 19:24:33 +020092config AT_HDMAC
93 tristate "Atmel AHB DMA support"
Nicolas Ferref898fed2012-03-15 11:31:58 +010094 depends on ARCH_AT91
Nicolas Ferredc78baa2009-07-03 19:24:33 +020095 select DMA_ENGINE
96 help
Nicolas Ferref898fed2012-03-15 11:31:58 +010097 Support the Atmel AHB DMA controller.
Nicolas Ferredc78baa2009-07-03 19:24:33 +020098
Zhang Wei173acc72008-03-01 07:42:48 -070099config FSL_DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -0700100 tristate "Freescale Elo and Elo Plus DMA support"
101 depends on FSL_SOC
Zhang Wei173acc72008-03-01 07:42:48 -0700102 select DMA_ENGINE
Dan Williams5fc6d892010-10-07 16:44:50 -0700103 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
Zhang Wei173acc72008-03-01 07:42:48 -0700104 ---help---
Timur Tabi77cd62e2008-09-26 17:00:11 -0700105 Enable support for the Freescale Elo and Elo Plus DMA controllers.
106 The Elo is the DMA controller on some 82xx and 83xx parts, and the
107 Elo Plus is the DMA controller on 85xx and 86xx parts.
Zhang Wei173acc72008-03-01 07:42:48 -0700108
Piotr Ziecik0fb6f732010-02-05 03:42:52 +0000109config MPC512X_DMA
110 tristate "Freescale MPC512x built-in DMA engine support"
Ilya Yanokba2eea22010-10-27 01:52:57 +0200111 depends on PPC_MPC512x || PPC_MPC831x
Piotr Ziecik0fb6f732010-02-05 03:42:52 +0000112 select DMA_ENGINE
113 ---help---
114 Enable support for the Freescale MPC512x built-in DMA engine.
115
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700116config MV_XOR
117 bool "Marvell XOR engine support"
118 depends on PLAT_ORION
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700119 select DMA_ENGINE
Dan Williams5fc6d892010-10-07 16:44:50 -0700120 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700121 ---help---
122 Enable support for the Marvell XOR engine.
123
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700124config MX3_IPU
125 bool "MX3x Image Processing Unit support"
Sascha Hauer8e2d41f2011-08-24 08:41:09 +0200126 depends on ARCH_MXC
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -0700127 select DMA_ENGINE
128 default y
129 help
130 If you plan to use the Image Processing unit in the i.MX3x, say
131 Y here. If unsure, select Y.
132
133config MX3_IPU_IRQS
134 int "Number of dynamically mapped interrupts for IPU"
135 depends on MX3_IPU
136 range 2 137
137 default 4
138 help
139 Out of 137 interrupt sources on i.MX31 IPU only very few are used.
140 To avoid bloating the irq_desc[] array we allocate a sufficient
141 number of IRQ slots and map them dynamically to specific sources.
142
Atsushi Nemotoea76f0b2009-04-23 00:40:30 +0900143config TXX9_DMAC
144 tristate "Toshiba TXx9 SoC DMA support"
145 depends on MACH_TX49XX || MACH_TX39XX
146 select DMA_ENGINE
147 help
148 Support the TXx9 SoC internal DMA controller. This can be
149 integrated in chips such as the Toshiba TX4927/38/39.
150
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000151config SH_DMAE
152 tristate "Renesas SuperH DMAC support"
Magnus Damm927a7c92010-03-19 04:47:19 +0000153 depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
Nobuhiro Iwamatsud8902ad2009-09-07 03:26:23 +0000154 depends on !SH_DMA_API
155 select DMA_ENGINE
156 help
157 Enable support for the Renesas SuperH DMA controllers.
158
Linus Walleij61f135b2009-11-19 19:49:17 +0100159config COH901318
160 bool "ST-Ericsson COH901318 DMA support"
161 select DMA_ENGINE
162 depends on ARCH_U300
163 help
164 Enable support for ST-Ericsson COH 901 318 DMA.
165
Linus Walleij8d318a52010-03-30 15:33:42 +0200166config STE_DMA40
167 bool "ST-Ericsson DMA40 support"
168 depends on ARCH_U8500
169 select DMA_ENGINE
170 help
171 Support for ST-Ericsson DMA40 controller
172
Anatolij Gustschin12458ea2009-12-11 21:24:44 -0700173config AMCC_PPC440SPE_ADMA
174 tristate "AMCC PPC440SPe ADMA support"
175 depends on 440SPe || 440SP
176 select DMA_ENGINE
177 select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
Dan Williams5fc6d892010-10-07 16:44:50 -0700178 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
Anatolij Gustschin12458ea2009-12-11 21:24:44 -0700179 help
180 Enable support for the AMCC PPC440SPe RAID engines.
181
Richard Röjforsde5d4452010-03-25 19:44:21 +0100182config TIMB_DMA
183 tristate "Timberdale FPGA DMA support"
184 depends on MFD_TIMBERDALE || HAS_IOMEM
185 select DMA_ENGINE
186 help
187 Enable support for the Timberdale FPGA DMA engine.
188
Rongjun Yingca21a142011-10-27 19:22:39 -0700189config SIRF_DMA
190 tristate "CSR SiRFprimaII DMA support"
191 depends on ARCH_PRIMA2
192 select DMA_ENGINE
193 help
194 Enable support for the CSR SiRFprimaII DMA engine.
195
Anatolij Gustschin12458ea2009-12-11 21:24:44 -0700196config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
197 bool
198
Jassi Brarb3040e42010-05-23 20:28:19 -0700199config PL330_DMA
200 tristate "DMA API Driver for PL330"
201 select DMA_ENGINE
Boojin Kim1b9bb712011-09-02 09:44:30 +0900202 depends on ARM_AMBA
Jassi Brarb3040e42010-05-23 20:28:19 -0700203 help
204 Select if your platform has one or more PL330 DMACs.
205 You need to provide platform specific settings via
206 platform_data for a dma-pl330 device.
207
Yong Wang0c42bd02010-07-30 16:23:03 +0800208config PCH_DMA
Tomoya MORINAGAca7fe2d2011-11-17 16:14:23 +0900209 tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
Yong Wang0c42bd02010-07-30 16:23:03 +0800210 depends on PCI && X86
211 select DMA_ENGINE
212 help
Tomoya MORINAGA2cdf2452011-01-05 17:43:52 +0900213 Enable support for Intel EG20T PCH DMA engine.
214
Tomoya MORINAGAe79e72b2011-11-17 16:14:22 +0900215 This driver also can be used for LAPIS Semiconductor IOH(Input/
Tomoya MORINAGAca7fe2d2011-11-17 16:14:23 +0900216 Output Hub), ML7213, ML7223 and ML7831.
217 ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
218 for MP(Media Phone) use and ML7831 IOH is for general purpose use.
219 ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
220 ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
Yong Wang0c42bd02010-07-30 16:23:03 +0800221
Sascha Hauer1ec1e822010-09-30 13:56:34 +0000222config IMX_SDMA
223 tristate "i.MX SDMA support"
Sascha Hauer8e2d41f2011-08-24 08:41:09 +0200224 depends on ARCH_MXC
Sascha Hauer1ec1e822010-09-30 13:56:34 +0000225 select DMA_ENGINE
226 help
227 Support the i.MX SDMA engine. This engine is integrated into
Sascha Hauer8e2d41f2011-08-24 08:41:09 +0200228 Freescale i.MX25/31/35/51/53 chips.
Sascha Hauer1ec1e822010-09-30 13:56:34 +0000229
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200230config IMX_DMA
231 tristate "i.MX DMA support"
Vinod Koul5b2e02e2012-03-27 13:53:00 +0530232 depends on ARCH_MXC
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200233 select DMA_ENGINE
234 help
235 Support the i.MX DMA engine. This engine is integrated into
236 Freescale i.MX1/21/27 chips.
237
Shawn Guoa580b8c2011-02-27 00:47:42 +0800238config MXS_DMA
239 bool "MXS DMA support"
240 depends on SOC_IMX23 || SOC_IMX28
Dong Aishengf5b7efc2012-05-04 20:12:15 +0800241 select STMP_DEVICE
Shawn Guoa580b8c2011-02-27 00:47:42 +0800242 select DMA_ENGINE
243 help
244 Support the MXS DMA engine. This engine including APBH-DMA
245 and APBX-DMA is integrated into Freescale i.MX23/28 chips.
246
Mika Westerberg760ee1c2011-05-29 13:10:02 +0300247config EP93XX_DMA
248 bool "Cirrus Logic EP93xx DMA support"
249 depends on ARCH_EP93XX
250 select DMA_ENGINE
251 help
252 Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
253
Russell King6365bea2012-01-09 21:44:07 +0000254config DMA_SA11X0
255 tristate "SA-11x0 DMA support"
256 depends on ARCH_SA1100
257 select DMA_ENGINE
Russell King50437bf2012-04-13 12:07:23 +0100258 select DMA_VIRTUAL_CHANNELS
Russell King6365bea2012-01-09 21:44:07 +0000259 help
260 Support the DMA engine found on Intel StrongARM SA-1100 and
261 SA-1110 SoCs. This DMA engine can only be used with on-chip
262 devices.
263
Russell King7bedaa52012-04-13 12:10:24 +0100264config DMA_OMAP
265 tristate "OMAP DMA support"
266 depends on ARCH_OMAP
267 select DMA_ENGINE
268 select DMA_VIRTUAL_CHANNELS
269
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700270config DMA_ENGINE
271 bool
272
Russell King50437bf2012-04-13 12:07:23 +0100273config DMA_VIRTUAL_CHANNELS
274 tristate
275
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700276comment "DMA Clients"
277 depends on DMA_ENGINE
278
279config NET_DMA
280 bool "Network: TCP receive copy offload"
281 depends on DMA_ENGINE && NET
Dan Williams9c402f42008-06-27 01:21:11 -0700282 default (INTEL_IOATDMA || FSL_DMA)
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700283 help
284 This enables the use of DMA engines in the network stack to
285 offload receive copy-to-user operations, freeing CPU cycles.
Dan Williams9c402f42008-06-27 01:21:11 -0700286
287 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
288 say N.
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700289
Dan Williams729b5d12009-03-25 09:13:25 -0700290config ASYNC_TX_DMA
291 bool "Async_tx: Offload support for the async_tx api"
Dan Williams9a8de632009-09-08 15:06:10 -0700292 depends on DMA_ENGINE
Dan Williams729b5d12009-03-25 09:13:25 -0700293 help
294 This allows the async_tx api to take advantage of offload engines for
295 memcpy, memset, xor, and raid6 p+q operations. If your platform has
296 a dma engine that can perform raid operations and you have enabled
297 MD_RAID456 say Y.
298
299 If unsure, say N.
300
Haavard Skinnemoen4a776f02008-07-08 11:58:45 -0700301config DMATEST
302 tristate "DMA Test client"
303 depends on DMA_ENGINE
304 help
305 Simple DMA test client. Say N unless you're debugging a
306 DMA Device driver.
307
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700308endif