Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. |
| 3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 18 | #include <linux/acpi.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 19 | #include <linux/cpu.h> |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 20 | #include <linux/cpu_pm.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 21 | #include <linux/delay.h> |
| 22 | #include <linux/interrupt.h> |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 23 | #include <linux/irqdomain.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 24 | #include <linux/of.h> |
| 25 | #include <linux/of_address.h> |
| 26 | #include <linux/of_irq.h> |
| 27 | #include <linux/percpu.h> |
| 28 | #include <linux/slab.h> |
| 29 | |
Joel Porquet | 41a83e0 | 2015-07-07 17:11:46 -0400 | [diff] [blame] | 30 | #include <linux/irqchip.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 31 | #include <linux/irqchip/arm-gic-v3.h> |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 32 | #include <linux/irqchip/irq-partition-percpu.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 33 | |
| 34 | #include <asm/cputype.h> |
| 35 | #include <asm/exception.h> |
| 36 | #include <asm/smp_plat.h> |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 37 | #include <asm/virt.h> |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 38 | |
| 39 | #include "irq-gic-common.h" |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 40 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 41 | struct redist_region { |
| 42 | void __iomem *redist_base; |
| 43 | phys_addr_t phys_base; |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 44 | bool single_redist; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 45 | }; |
| 46 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 47 | struct gic_chip_data { |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 48 | struct fwnode_handle *fwnode; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 49 | void __iomem *dist_base; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 50 | struct redist_region *redist_regions; |
| 51 | struct rdists rdists; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 52 | struct irq_domain *domain; |
| 53 | u64 redist_stride; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 54 | u32 nr_redist_regions; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 55 | unsigned int irq_nr; |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 56 | struct partition_desc *ppi_descs[16]; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 57 | }; |
| 58 | |
| 59 | static struct gic_chip_data gic_data __read_mostly; |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 60 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 61 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 62 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
| 63 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 64 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
| 65 | |
| 66 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ |
| 67 | #define DEFAULT_PMR_VALUE 0xf0 |
| 68 | |
| 69 | static inline unsigned int gic_irq(struct irq_data *d) |
| 70 | { |
| 71 | return d->hwirq; |
| 72 | } |
| 73 | |
| 74 | static inline int gic_irq_in_rdist(struct irq_data *d) |
| 75 | { |
| 76 | return gic_irq(d) < 32; |
| 77 | } |
| 78 | |
| 79 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
| 80 | { |
| 81 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ |
| 82 | return gic_data_rdist_sgi_base(); |
| 83 | |
| 84 | if (d->hwirq <= 1023) /* SPI -> dist_base */ |
| 85 | return gic_data.dist_base; |
| 86 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 87 | return NULL; |
| 88 | } |
| 89 | |
| 90 | static void gic_do_wait_for_rwp(void __iomem *base) |
| 91 | { |
| 92 | u32 count = 1000000; /* 1s! */ |
| 93 | |
| 94 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { |
| 95 | count--; |
| 96 | if (!count) { |
| 97 | pr_err_ratelimited("RWP timeout, gone fishing\n"); |
| 98 | return; |
| 99 | } |
| 100 | cpu_relax(); |
| 101 | udelay(1); |
| 102 | }; |
| 103 | } |
| 104 | |
| 105 | /* Wait for completion of a distributor change */ |
| 106 | static void gic_dist_wait_for_rwp(void) |
| 107 | { |
| 108 | gic_do_wait_for_rwp(gic_data.dist_base); |
| 109 | } |
| 110 | |
| 111 | /* Wait for completion of a redistributor change */ |
| 112 | static void gic_redist_wait_for_rwp(void) |
| 113 | { |
| 114 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); |
| 115 | } |
| 116 | |
Jean-Philippe Brucker | 7936e91 | 2015-10-01 13:47:14 +0100 | [diff] [blame] | 117 | #ifdef CONFIG_ARM64 |
Robert Richter | 8ac2a17 | 2015-09-21 22:58:39 +0200 | [diff] [blame] | 118 | static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 119 | |
| 120 | static u64 __maybe_unused gic_read_iar(void) |
| 121 | { |
Robert Richter | 8ac2a17 | 2015-09-21 22:58:39 +0200 | [diff] [blame] | 122 | if (static_branch_unlikely(&is_cavium_thunderx)) |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 123 | return gic_read_iar_cavium_thunderx(); |
| 124 | else |
| 125 | return gic_read_iar_common(); |
| 126 | } |
Jean-Philippe Brucker | 7936e91 | 2015-10-01 13:47:14 +0100 | [diff] [blame] | 127 | #endif |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 128 | |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 129 | static void gic_enable_redist(bool enable) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 130 | { |
| 131 | void __iomem *rbase; |
| 132 | u32 count = 1000000; /* 1s! */ |
| 133 | u32 val; |
| 134 | |
| 135 | rbase = gic_data_rdist_rd_base(); |
| 136 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 137 | val = readl_relaxed(rbase + GICR_WAKER); |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 138 | if (enable) |
| 139 | /* Wake up this CPU redistributor */ |
| 140 | val &= ~GICR_WAKER_ProcessorSleep; |
| 141 | else |
| 142 | val |= GICR_WAKER_ProcessorSleep; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 143 | writel_relaxed(val, rbase + GICR_WAKER); |
| 144 | |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 145 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
| 146 | val = readl_relaxed(rbase + GICR_WAKER); |
| 147 | if (!(val & GICR_WAKER_ProcessorSleep)) |
| 148 | return; /* No PM support in this redistributor */ |
| 149 | } |
| 150 | |
| 151 | while (count--) { |
| 152 | val = readl_relaxed(rbase + GICR_WAKER); |
| 153 | if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) |
| 154 | break; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 155 | cpu_relax(); |
| 156 | udelay(1); |
| 157 | }; |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 158 | if (!count) |
| 159 | pr_err_ratelimited("redistributor failed to %s...\n", |
| 160 | enable ? "wakeup" : "sleep"); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | /* |
| 164 | * Routines to disable, enable, EOI and route interrupts |
| 165 | */ |
Marc Zyngier | b594c6e | 2015-03-18 11:01:24 +0000 | [diff] [blame] | 166 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
| 167 | { |
| 168 | u32 mask = 1 << (gic_irq(d) % 32); |
| 169 | void __iomem *base; |
| 170 | |
| 171 | if (gic_irq_in_rdist(d)) |
| 172 | base = gic_data_rdist_sgi_base(); |
| 173 | else |
| 174 | base = gic_data.dist_base; |
| 175 | |
| 176 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); |
| 177 | } |
| 178 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 179 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
| 180 | { |
| 181 | u32 mask = 1 << (gic_irq(d) % 32); |
| 182 | void (*rwp_wait)(void); |
| 183 | void __iomem *base; |
| 184 | |
| 185 | if (gic_irq_in_rdist(d)) { |
| 186 | base = gic_data_rdist_sgi_base(); |
| 187 | rwp_wait = gic_redist_wait_for_rwp; |
| 188 | } else { |
| 189 | base = gic_data.dist_base; |
| 190 | rwp_wait = gic_dist_wait_for_rwp; |
| 191 | } |
| 192 | |
| 193 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); |
| 194 | rwp_wait(); |
| 195 | } |
| 196 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 197 | static void gic_mask_irq(struct irq_data *d) |
| 198 | { |
| 199 | gic_poke_irq(d, GICD_ICENABLER); |
| 200 | } |
| 201 | |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 202 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
| 203 | { |
| 204 | gic_mask_irq(d); |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 205 | /* |
| 206 | * When masking a forwarded interrupt, make sure it is |
| 207 | * deactivated as well. |
| 208 | * |
| 209 | * This ensures that an interrupt that is getting |
| 210 | * disabled/masked will not get "stuck", because there is |
| 211 | * noone to deactivate it (guest is being terminated). |
| 212 | */ |
Thomas Gleixner | 4df7f54 | 2015-09-15 13:19:16 +0200 | [diff] [blame] | 213 | if (irqd_is_forwarded_to_vcpu(d)) |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 214 | gic_poke_irq(d, GICD_ICACTIVER); |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 215 | } |
| 216 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 217 | static void gic_unmask_irq(struct irq_data *d) |
| 218 | { |
| 219 | gic_poke_irq(d, GICD_ISENABLER); |
| 220 | } |
| 221 | |
Marc Zyngier | b594c6e | 2015-03-18 11:01:24 +0000 | [diff] [blame] | 222 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
| 223 | enum irqchip_irq_state which, bool val) |
| 224 | { |
| 225 | u32 reg; |
| 226 | |
| 227 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ |
| 228 | return -EINVAL; |
| 229 | |
| 230 | switch (which) { |
| 231 | case IRQCHIP_STATE_PENDING: |
| 232 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; |
| 233 | break; |
| 234 | |
| 235 | case IRQCHIP_STATE_ACTIVE: |
| 236 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; |
| 237 | break; |
| 238 | |
| 239 | case IRQCHIP_STATE_MASKED: |
| 240 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; |
| 241 | break; |
| 242 | |
| 243 | default: |
| 244 | return -EINVAL; |
| 245 | } |
| 246 | |
| 247 | gic_poke_irq(d, reg); |
| 248 | return 0; |
| 249 | } |
| 250 | |
| 251 | static int gic_irq_get_irqchip_state(struct irq_data *d, |
| 252 | enum irqchip_irq_state which, bool *val) |
| 253 | { |
| 254 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ |
| 255 | return -EINVAL; |
| 256 | |
| 257 | switch (which) { |
| 258 | case IRQCHIP_STATE_PENDING: |
| 259 | *val = gic_peek_irq(d, GICD_ISPENDR); |
| 260 | break; |
| 261 | |
| 262 | case IRQCHIP_STATE_ACTIVE: |
| 263 | *val = gic_peek_irq(d, GICD_ISACTIVER); |
| 264 | break; |
| 265 | |
| 266 | case IRQCHIP_STATE_MASKED: |
| 267 | *val = !gic_peek_irq(d, GICD_ISENABLER); |
| 268 | break; |
| 269 | |
| 270 | default: |
| 271 | return -EINVAL; |
| 272 | } |
| 273 | |
| 274 | return 0; |
| 275 | } |
| 276 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 277 | static void gic_eoi_irq(struct irq_data *d) |
| 278 | { |
| 279 | gic_write_eoir(gic_irq(d)); |
| 280 | } |
| 281 | |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 282 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
| 283 | { |
| 284 | /* |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 285 | * No need to deactivate an LPI, or an interrupt that |
| 286 | * is is getting forwarded to a vcpu. |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 287 | */ |
Thomas Gleixner | 4df7f54 | 2015-09-15 13:19:16 +0200 | [diff] [blame] | 288 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 289 | return; |
| 290 | gic_write_dir(gic_irq(d)); |
| 291 | } |
| 292 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 293 | static int gic_set_type(struct irq_data *d, unsigned int type) |
| 294 | { |
| 295 | unsigned int irq = gic_irq(d); |
| 296 | void (*rwp_wait)(void); |
| 297 | void __iomem *base; |
| 298 | |
| 299 | /* Interrupt configuration for SGIs can't be changed */ |
| 300 | if (irq < 16) |
| 301 | return -EINVAL; |
| 302 | |
Liviu Dudau | fb7e7de | 2015-01-20 16:52:59 +0000 | [diff] [blame] | 303 | /* SPIs have restrictions on the supported types */ |
| 304 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && |
| 305 | type != IRQ_TYPE_EDGE_RISING) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 306 | return -EINVAL; |
| 307 | |
| 308 | if (gic_irq_in_rdist(d)) { |
| 309 | base = gic_data_rdist_sgi_base(); |
| 310 | rwp_wait = gic_redist_wait_for_rwp; |
| 311 | } else { |
| 312 | base = gic_data.dist_base; |
| 313 | rwp_wait = gic_dist_wait_for_rwp; |
| 314 | } |
| 315 | |
Liviu Dudau | fb7e7de | 2015-01-20 16:52:59 +0000 | [diff] [blame] | 316 | return gic_configure_irq(irq, type, base, rwp_wait); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 317 | } |
| 318 | |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 319 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
| 320 | { |
Thomas Gleixner | 4df7f54 | 2015-09-15 13:19:16 +0200 | [diff] [blame] | 321 | if (vcpu) |
| 322 | irqd_set_forwarded_to_vcpu(d); |
| 323 | else |
| 324 | irqd_clr_forwarded_to_vcpu(d); |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 325 | return 0; |
| 326 | } |
| 327 | |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 328 | static u64 gic_mpidr_to_affinity(unsigned long mpidr) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 329 | { |
| 330 | u64 aff; |
| 331 | |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 332 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 333 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
| 334 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | |
| 335 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); |
| 336 | |
| 337 | return aff; |
| 338 | } |
| 339 | |
| 340 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
| 341 | { |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 342 | u32 irqnr; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 343 | |
| 344 | do { |
| 345 | irqnr = gic_read_iar(); |
| 346 | |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 347 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
Marc Zyngier | ebc6de0 | 2014-08-26 11:03:33 +0100 | [diff] [blame] | 348 | int err; |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 349 | |
| 350 | if (static_key_true(&supports_deactivate)) |
| 351 | gic_write_eoir(irqnr); |
| 352 | |
Marc Zyngier | ebc6de0 | 2014-08-26 11:03:33 +0100 | [diff] [blame] | 353 | err = handle_domain_irq(gic_data.domain, irqnr, regs); |
| 354 | if (err) { |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 355 | WARN_ONCE(true, "Unexpected interrupt received!\n"); |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 356 | if (static_key_true(&supports_deactivate)) { |
| 357 | if (irqnr < 8192) |
| 358 | gic_write_dir(irqnr); |
| 359 | } else { |
| 360 | gic_write_eoir(irqnr); |
| 361 | } |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 362 | } |
Marc Zyngier | ebc6de0 | 2014-08-26 11:03:33 +0100 | [diff] [blame] | 363 | continue; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 364 | } |
| 365 | if (irqnr < 16) { |
| 366 | gic_write_eoir(irqnr); |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 367 | if (static_key_true(&supports_deactivate)) |
| 368 | gic_write_dir(irqnr); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 369 | #ifdef CONFIG_SMP |
Will Deacon | f86c4fb | 2016-04-26 12:00:00 +0100 | [diff] [blame] | 370 | /* |
| 371 | * Unlike GICv2, we don't need an smp_rmb() here. |
| 372 | * The control dependency from gic_read_iar to |
| 373 | * the ISB in gic_write_eoir is enough to ensure |
| 374 | * that any shared data read by handle_IPI will |
| 375 | * be read after the ACK. |
| 376 | */ |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 377 | handle_IPI(irqnr, regs); |
| 378 | #else |
| 379 | WARN_ONCE(true, "Unexpected SGI received!\n"); |
| 380 | #endif |
| 381 | continue; |
| 382 | } |
| 383 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); |
| 384 | } |
| 385 | |
| 386 | static void __init gic_dist_init(void) |
| 387 | { |
| 388 | unsigned int i; |
| 389 | u64 affinity; |
| 390 | void __iomem *base = gic_data.dist_base; |
| 391 | |
| 392 | /* Disable the distributor */ |
| 393 | writel_relaxed(0, base + GICD_CTLR); |
| 394 | gic_dist_wait_for_rwp(); |
| 395 | |
Marc Zyngier | 7c9b973 | 2016-05-06 19:41:56 +0100 | [diff] [blame^] | 396 | /* |
| 397 | * Configure SPIs as non-secure Group-1. This will only matter |
| 398 | * if the GIC only has a single security state. This will not |
| 399 | * do the right thing if the kernel is running in secure mode, |
| 400 | * but that's not the intended use case anyway. |
| 401 | */ |
| 402 | for (i = 32; i < gic_data.irq_nr; i += 32) |
| 403 | writel_relaxed(~0, base + GICD_IGROUPR + i / 8); |
| 404 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 405 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); |
| 406 | |
| 407 | /* Enable distributor with ARE, Group1 */ |
| 408 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, |
| 409 | base + GICD_CTLR); |
| 410 | |
| 411 | /* |
| 412 | * Set all global interrupts to the boot CPU only. ARE must be |
| 413 | * enabled. |
| 414 | */ |
| 415 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); |
| 416 | for (i = 32; i < gic_data.irq_nr; i++) |
Jean-Philippe Brucker | 72c9712 | 2015-10-01 13:47:16 +0100 | [diff] [blame] | 417 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 418 | } |
| 419 | |
| 420 | static int gic_populate_rdist(void) |
| 421 | { |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 422 | unsigned long mpidr = cpu_logical_map(smp_processor_id()); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 423 | u64 typer; |
| 424 | u32 aff; |
| 425 | int i; |
| 426 | |
| 427 | /* |
| 428 | * Convert affinity to a 32bit value that can be matched to |
| 429 | * GICR_TYPER bits [63:32]. |
| 430 | */ |
| 431 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | |
| 432 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
| 433 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | |
| 434 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); |
| 435 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 436 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
| 437 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 438 | u32 reg; |
| 439 | |
| 440 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; |
| 441 | if (reg != GIC_PIDR2_ARCH_GICv3 && |
| 442 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ |
| 443 | pr_warn("No redistributor present @%p\n", ptr); |
| 444 | break; |
| 445 | } |
| 446 | |
| 447 | do { |
Jean-Philippe Brucker | 72c9712 | 2015-10-01 13:47:16 +0100 | [diff] [blame] | 448 | typer = gic_read_typer(ptr + GICR_TYPER); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 449 | if ((typer >> 32) == aff) { |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 450 | u64 offset = ptr - gic_data.redist_regions[i].redist_base; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 451 | gic_data_rdist_rd_base() = ptr; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 452 | gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 453 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", |
| 454 | smp_processor_id(), mpidr, i, |
| 455 | &gic_data_rdist()->phys_base); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 456 | return 0; |
| 457 | } |
| 458 | |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 459 | if (gic_data.redist_regions[i].single_redist) |
| 460 | break; |
| 461 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 462 | if (gic_data.redist_stride) { |
| 463 | ptr += gic_data.redist_stride; |
| 464 | } else { |
| 465 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ |
| 466 | if (typer & GICR_TYPER_VLPIS) |
| 467 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ |
| 468 | } |
| 469 | } while (!(typer & GICR_TYPER_LAST)); |
| 470 | } |
| 471 | |
| 472 | /* We couldn't even deal with ourselves... */ |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 473 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
| 474 | smp_processor_id(), mpidr); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 475 | return -ENODEV; |
| 476 | } |
| 477 | |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 478 | static void gic_cpu_sys_reg_init(void) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 479 | { |
Marc Zyngier | 7cabd00 | 2015-09-30 11:48:01 +0100 | [diff] [blame] | 480 | /* |
| 481 | * Need to check that the SRE bit has actually been set. If |
| 482 | * not, it means that SRE is disabled at EL2. We're going to |
| 483 | * die painfully, and there is nothing we can do about it. |
| 484 | * |
| 485 | * Kindly inform the luser. |
| 486 | */ |
| 487 | if (!gic_enable_sre()) |
| 488 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 489 | |
| 490 | /* Set priority mask register */ |
| 491 | gic_write_pmr(DEFAULT_PMR_VALUE); |
| 492 | |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 493 | if (static_key_true(&supports_deactivate)) { |
| 494 | /* EOI drops priority only (mode 1) */ |
| 495 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); |
| 496 | } else { |
| 497 | /* EOI deactivates interrupt too (mode 0) */ |
| 498 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); |
| 499 | } |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 500 | |
| 501 | /* ... and let's hit the road... */ |
| 502 | gic_write_grpen1(1); |
| 503 | } |
| 504 | |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 505 | static int gic_dist_supports_lpis(void) |
| 506 | { |
| 507 | return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); |
| 508 | } |
| 509 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 510 | static void gic_cpu_init(void) |
| 511 | { |
| 512 | void __iomem *rbase; |
| 513 | |
| 514 | /* Register ourselves with the rest of the world */ |
| 515 | if (gic_populate_rdist()) |
| 516 | return; |
| 517 | |
Sudeep Holla | a2c2251 | 2014-08-26 16:03:34 +0100 | [diff] [blame] | 518 | gic_enable_redist(true); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 519 | |
| 520 | rbase = gic_data_rdist_sgi_base(); |
| 521 | |
Marc Zyngier | 7c9b973 | 2016-05-06 19:41:56 +0100 | [diff] [blame^] | 522 | /* Configure SGIs/PPIs as non-secure Group-1 */ |
| 523 | writel_relaxed(~0, rbase + GICR_IGROUPR0); |
| 524 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 525 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); |
| 526 | |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 527 | /* Give LPIs a spin */ |
| 528 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) |
| 529 | its_cpu_init(); |
| 530 | |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 531 | /* initialise system registers */ |
| 532 | gic_cpu_sys_reg_init(); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 533 | } |
| 534 | |
| 535 | #ifdef CONFIG_SMP |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 536 | static int gic_secondary_init(struct notifier_block *nfb, |
| 537 | unsigned long action, void *hcpu) |
| 538 | { |
| 539 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
| 540 | gic_cpu_init(); |
| 541 | return NOTIFY_OK; |
| 542 | } |
| 543 | |
| 544 | /* |
| 545 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high |
| 546 | * priority because the GIC needs to be up before the ARM generic timers. |
| 547 | */ |
| 548 | static struct notifier_block gic_cpu_notifier = { |
| 549 | .notifier_call = gic_secondary_init, |
| 550 | .priority = 100, |
| 551 | }; |
| 552 | |
| 553 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 554 | unsigned long cluster_id) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 555 | { |
| 556 | int cpu = *base_cpu; |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 557 | unsigned long mpidr = cpu_logical_map(cpu); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 558 | u16 tlist = 0; |
| 559 | |
| 560 | while (cpu < nr_cpu_ids) { |
| 561 | /* |
| 562 | * If we ever get a cluster of more than 16 CPUs, just |
| 563 | * scream and skip that CPU. |
| 564 | */ |
| 565 | if (WARN_ON((mpidr & 0xff) >= 16)) |
| 566 | goto out; |
| 567 | |
| 568 | tlist |= 1 << (mpidr & 0xf); |
| 569 | |
| 570 | cpu = cpumask_next(cpu, mask); |
Vladimir Murzin | 614be38 | 2015-03-06 16:37:45 +0000 | [diff] [blame] | 571 | if (cpu >= nr_cpu_ids) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 572 | goto out; |
| 573 | |
| 574 | mpidr = cpu_logical_map(cpu); |
| 575 | |
| 576 | if (cluster_id != (mpidr & ~0xffUL)) { |
| 577 | cpu--; |
| 578 | goto out; |
| 579 | } |
| 580 | } |
| 581 | out: |
| 582 | *base_cpu = cpu; |
| 583 | return tlist; |
| 584 | } |
| 585 | |
Andre Przywara | 7e58027 | 2014-11-12 13:46:06 +0000 | [diff] [blame] | 586 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
| 587 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ |
| 588 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) |
| 589 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 590 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
| 591 | { |
| 592 | u64 val; |
| 593 | |
Andre Przywara | 7e58027 | 2014-11-12 13:46:06 +0000 | [diff] [blame] | 594 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
| 595 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | |
| 596 | irq << ICC_SGI1R_SGI_ID_SHIFT | |
| 597 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | |
| 598 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 599 | |
| 600 | pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); |
| 601 | gic_write_sgi1r(val); |
| 602 | } |
| 603 | |
| 604 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
| 605 | { |
| 606 | int cpu; |
| 607 | |
| 608 | if (WARN_ON(irq >= 16)) |
| 609 | return; |
| 610 | |
| 611 | /* |
| 612 | * Ensure that stores to Normal memory are visible to the |
| 613 | * other CPUs before issuing the IPI. |
| 614 | */ |
| 615 | smp_wmb(); |
| 616 | |
Rusty Russell | f9b531f | 2015-03-05 10:49:16 +1030 | [diff] [blame] | 617 | for_each_cpu(cpu, mask) { |
Jean-Philippe Brucker | f6c86a4 | 2015-10-01 13:47:15 +0100 | [diff] [blame] | 618 | unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 619 | u16 tlist; |
| 620 | |
| 621 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); |
| 622 | gic_send_sgi(cluster_id, tlist, irq); |
| 623 | } |
| 624 | |
| 625 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ |
| 626 | isb(); |
| 627 | } |
| 628 | |
| 629 | static void gic_smp_init(void) |
| 630 | { |
| 631 | set_smp_cross_call(gic_raise_softirq); |
| 632 | register_cpu_notifier(&gic_cpu_notifier); |
| 633 | } |
| 634 | |
| 635 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
| 636 | bool force) |
| 637 | { |
| 638 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); |
| 639 | void __iomem *reg; |
| 640 | int enabled; |
| 641 | u64 val; |
| 642 | |
| 643 | if (gic_irq_in_rdist(d)) |
| 644 | return -EINVAL; |
| 645 | |
| 646 | /* If interrupt was enabled, disable it first */ |
| 647 | enabled = gic_peek_irq(d, GICD_ISENABLER); |
| 648 | if (enabled) |
| 649 | gic_mask_irq(d); |
| 650 | |
| 651 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); |
| 652 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); |
| 653 | |
Jean-Philippe Brucker | 72c9712 | 2015-10-01 13:47:16 +0100 | [diff] [blame] | 654 | gic_write_irouter(val, reg); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 655 | |
| 656 | /* |
| 657 | * If the interrupt was enabled, enabled it again. Otherwise, |
| 658 | * just wait for the distributor to have digested our changes. |
| 659 | */ |
| 660 | if (enabled) |
| 661 | gic_unmask_irq(d); |
| 662 | else |
| 663 | gic_dist_wait_for_rwp(); |
| 664 | |
Antoine Tenart | 0fc6fa2 | 2016-02-19 16:22:43 +0100 | [diff] [blame] | 665 | return IRQ_SET_MASK_OK_DONE; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 666 | } |
| 667 | #else |
| 668 | #define gic_set_affinity NULL |
| 669 | #define gic_smp_init() do { } while(0) |
| 670 | #endif |
| 671 | |
Sudeep Holla | 3708d52 | 2014-08-26 16:03:35 +0100 | [diff] [blame] | 672 | #ifdef CONFIG_CPU_PM |
| 673 | static int gic_cpu_pm_notifier(struct notifier_block *self, |
| 674 | unsigned long cmd, void *v) |
| 675 | { |
| 676 | if (cmd == CPU_PM_EXIT) { |
| 677 | gic_enable_redist(true); |
| 678 | gic_cpu_sys_reg_init(); |
| 679 | } else if (cmd == CPU_PM_ENTER) { |
| 680 | gic_write_grpen1(0); |
| 681 | gic_enable_redist(false); |
| 682 | } |
| 683 | return NOTIFY_OK; |
| 684 | } |
| 685 | |
| 686 | static struct notifier_block gic_cpu_pm_notifier_block = { |
| 687 | .notifier_call = gic_cpu_pm_notifier, |
| 688 | }; |
| 689 | |
| 690 | static void gic_cpu_pm_init(void) |
| 691 | { |
| 692 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); |
| 693 | } |
| 694 | |
| 695 | #else |
| 696 | static inline void gic_cpu_pm_init(void) { } |
| 697 | #endif /* CONFIG_CPU_PM */ |
| 698 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 699 | static struct irq_chip gic_chip = { |
| 700 | .name = "GICv3", |
| 701 | .irq_mask = gic_mask_irq, |
| 702 | .irq_unmask = gic_unmask_irq, |
| 703 | .irq_eoi = gic_eoi_irq, |
| 704 | .irq_set_type = gic_set_type, |
| 705 | .irq_set_affinity = gic_set_affinity, |
Marc Zyngier | b594c6e | 2015-03-18 11:01:24 +0000 | [diff] [blame] | 706 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
| 707 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, |
Sudeep Holla | 55963c9 | 2015-06-05 11:59:57 +0100 | [diff] [blame] | 708 | .flags = IRQCHIP_SET_TYPE_MASKED, |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 709 | }; |
| 710 | |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 711 | static struct irq_chip gic_eoimode1_chip = { |
| 712 | .name = "GICv3", |
| 713 | .irq_mask = gic_eoimode1_mask_irq, |
| 714 | .irq_unmask = gic_unmask_irq, |
| 715 | .irq_eoi = gic_eoimode1_eoi_irq, |
| 716 | .irq_set_type = gic_set_type, |
| 717 | .irq_set_affinity = gic_set_affinity, |
| 718 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
| 719 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, |
Marc Zyngier | 530bf35 | 2015-08-26 17:00:43 +0100 | [diff] [blame] | 720 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 721 | .flags = IRQCHIP_SET_TYPE_MASKED, |
| 722 | }; |
| 723 | |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 724 | #define GIC_ID_NR (1U << gic_data.rdists.id_bits) |
| 725 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 726 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
| 727 | irq_hw_number_t hw) |
| 728 | { |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 729 | struct irq_chip *chip = &gic_chip; |
| 730 | |
| 731 | if (static_key_true(&supports_deactivate)) |
| 732 | chip = &gic_eoimode1_chip; |
| 733 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 734 | /* SGIs are private to the core kernel */ |
| 735 | if (hw < 16) |
| 736 | return -EPERM; |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 737 | /* Nothing here */ |
| 738 | if (hw >= gic_data.irq_nr && hw < 8192) |
| 739 | return -EPERM; |
| 740 | /* Off limits */ |
| 741 | if (hw >= GIC_ID_NR) |
| 742 | return -EPERM; |
| 743 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 744 | /* PPIs */ |
| 745 | if (hw < 32) { |
| 746 | irq_set_percpu_devid(irq); |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 747 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 748 | handle_percpu_devid_irq, NULL, NULL); |
Rob Herring | d17cab4 | 2015-08-29 18:01:22 -0500 | [diff] [blame] | 749 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 750 | } |
| 751 | /* SPIs */ |
| 752 | if (hw >= 32 && hw < gic_data.irq_nr) { |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 753 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 754 | handle_fasteoi_irq, NULL, NULL); |
Rob Herring | d17cab4 | 2015-08-29 18:01:22 -0500 | [diff] [blame] | 755 | irq_set_probe(irq); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 756 | } |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 757 | /* LPIs */ |
| 758 | if (hw >= 8192 && hw < GIC_ID_NR) { |
| 759 | if (!gic_dist_supports_lpis()) |
| 760 | return -EPERM; |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 761 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 762 | handle_fasteoi_irq, NULL, NULL); |
Marc Zyngier | da33f31 | 2014-11-24 14:35:18 +0000 | [diff] [blame] | 763 | } |
| 764 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 765 | return 0; |
| 766 | } |
| 767 | |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 768 | static int gic_irq_domain_translate(struct irq_domain *d, |
| 769 | struct irq_fwspec *fwspec, |
| 770 | unsigned long *hwirq, |
| 771 | unsigned int *type) |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 772 | { |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 773 | if (is_of_node(fwspec->fwnode)) { |
| 774 | if (fwspec->param_count < 3) |
| 775 | return -EINVAL; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 776 | |
Marc Zyngier | db8c70e | 2015-10-14 12:27:16 +0100 | [diff] [blame] | 777 | switch (fwspec->param[0]) { |
| 778 | case 0: /* SPI */ |
| 779 | *hwirq = fwspec->param[1] + 32; |
| 780 | break; |
| 781 | case 1: /* PPI */ |
| 782 | *hwirq = fwspec->param[1] + 16; |
| 783 | break; |
| 784 | case GIC_IRQ_TYPE_LPI: /* LPI */ |
| 785 | *hwirq = fwspec->param[1]; |
| 786 | break; |
| 787 | default: |
| 788 | return -EINVAL; |
| 789 | } |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 790 | |
| 791 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; |
| 792 | return 0; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 793 | } |
| 794 | |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 795 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
| 796 | if(fwspec->param_count != 2) |
| 797 | return -EINVAL; |
| 798 | |
| 799 | *hwirq = fwspec->param[0]; |
| 800 | *type = fwspec->param[1]; |
| 801 | return 0; |
| 802 | } |
| 803 | |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 804 | return -EINVAL; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 805 | } |
| 806 | |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 807 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
| 808 | unsigned int nr_irqs, void *arg) |
| 809 | { |
| 810 | int i, ret; |
| 811 | irq_hw_number_t hwirq; |
| 812 | unsigned int type = IRQ_TYPE_NONE; |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 813 | struct irq_fwspec *fwspec = arg; |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 814 | |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 815 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 816 | if (ret) |
| 817 | return ret; |
| 818 | |
| 819 | for (i = 0; i < nr_irqs; i++) |
| 820 | gic_irq_domain_map(domain, virq + i, hwirq + i); |
| 821 | |
| 822 | return 0; |
| 823 | } |
| 824 | |
| 825 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
| 826 | unsigned int nr_irqs) |
| 827 | { |
| 828 | int i; |
| 829 | |
| 830 | for (i = 0; i < nr_irqs; i++) { |
| 831 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); |
| 832 | irq_set_handler(virq + i, NULL); |
| 833 | irq_domain_reset_irq_data(d); |
| 834 | } |
| 835 | } |
| 836 | |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 837 | static int gic_irq_domain_select(struct irq_domain *d, |
| 838 | struct irq_fwspec *fwspec, |
| 839 | enum irq_domain_bus_token bus_token) |
| 840 | { |
| 841 | /* Not for us */ |
| 842 | if (fwspec->fwnode != d->fwnode) |
| 843 | return 0; |
| 844 | |
| 845 | /* If this is not DT, then we have a single domain */ |
| 846 | if (!is_of_node(fwspec->fwnode)) |
| 847 | return 1; |
| 848 | |
| 849 | /* |
| 850 | * If this is a PPI and we have a 4th (non-null) parameter, |
| 851 | * then we need to match the partition domain. |
| 852 | */ |
| 853 | if (fwspec->param_count >= 4 && |
| 854 | fwspec->param[0] == 1 && fwspec->param[3] != 0) |
| 855 | return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); |
| 856 | |
| 857 | return d == gic_data.domain; |
| 858 | } |
| 859 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 860 | static const struct irq_domain_ops gic_irq_domain_ops = { |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 861 | .translate = gic_irq_domain_translate, |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 862 | .alloc = gic_irq_domain_alloc, |
| 863 | .free = gic_irq_domain_free, |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 864 | .select = gic_irq_domain_select, |
| 865 | }; |
| 866 | |
| 867 | static int partition_domain_translate(struct irq_domain *d, |
| 868 | struct irq_fwspec *fwspec, |
| 869 | unsigned long *hwirq, |
| 870 | unsigned int *type) |
| 871 | { |
| 872 | struct device_node *np; |
| 873 | int ret; |
| 874 | |
| 875 | np = of_find_node_by_phandle(fwspec->param[3]); |
| 876 | if (WARN_ON(!np)) |
| 877 | return -EINVAL; |
| 878 | |
| 879 | ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], |
| 880 | of_node_to_fwnode(np)); |
| 881 | if (ret < 0) |
| 882 | return ret; |
| 883 | |
| 884 | *hwirq = ret; |
| 885 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; |
| 886 | |
| 887 | return 0; |
| 888 | } |
| 889 | |
| 890 | static const struct irq_domain_ops partition_domain_ops = { |
| 891 | .translate = partition_domain_translate, |
| 892 | .select = gic_irq_domain_select, |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 893 | }; |
| 894 | |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 895 | static void gicv3_enable_quirks(void) |
| 896 | { |
Jean-Philippe Brucker | 7936e91 | 2015-10-01 13:47:14 +0100 | [diff] [blame] | 897 | #ifdef CONFIG_ARM64 |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 898 | if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
Robert Richter | 8ac2a17 | 2015-09-21 22:58:39 +0200 | [diff] [blame] | 899 | static_branch_enable(&is_cavium_thunderx); |
Jean-Philippe Brucker | 7936e91 | 2015-10-01 13:47:14 +0100 | [diff] [blame] | 900 | #endif |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 901 | } |
| 902 | |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 903 | static int __init gic_init_bases(void __iomem *dist_base, |
| 904 | struct redist_region *rdist_regs, |
| 905 | u32 nr_redist_regions, |
| 906 | u64 redist_stride, |
| 907 | struct fwnode_handle *handle) |
| 908 | { |
| 909 | struct device_node *node; |
| 910 | u32 typer; |
| 911 | int gic_irqs; |
| 912 | int err; |
| 913 | |
| 914 | if (!is_hyp_mode_available()) |
| 915 | static_key_slow_dec(&supports_deactivate); |
| 916 | |
| 917 | if (static_key_true(&supports_deactivate)) |
| 918 | pr_info("GIC: Using split EOI/Deactivate mode\n"); |
| 919 | |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 920 | gic_data.fwnode = handle; |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 921 | gic_data.dist_base = dist_base; |
| 922 | gic_data.redist_regions = rdist_regs; |
| 923 | gic_data.nr_redist_regions = nr_redist_regions; |
| 924 | gic_data.redist_stride = redist_stride; |
| 925 | |
| 926 | gicv3_enable_quirks(); |
| 927 | |
| 928 | /* |
| 929 | * Find out how many interrupts are supported. |
| 930 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) |
| 931 | */ |
| 932 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
| 933 | gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); |
| 934 | gic_irqs = GICD_TYPER_IRQS(typer); |
| 935 | if (gic_irqs > 1020) |
| 936 | gic_irqs = 1020; |
| 937 | gic_data.irq_nr = gic_irqs; |
| 938 | |
| 939 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
| 940 | &gic_data); |
| 941 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
| 942 | |
| 943 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
| 944 | err = -ENOMEM; |
| 945 | goto out_free; |
| 946 | } |
| 947 | |
| 948 | set_handle_irq(gic_handle_irq); |
| 949 | |
| 950 | node = to_of_node(handle); |
| 951 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && |
| 952 | node) /* Temp hack to prevent ITS init for ACPI */ |
| 953 | its_init(node, &gic_data.rdists, gic_data.domain); |
| 954 | |
| 955 | gic_smp_init(); |
| 956 | gic_dist_init(); |
| 957 | gic_cpu_init(); |
| 958 | gic_cpu_pm_init(); |
| 959 | |
| 960 | return 0; |
| 961 | |
| 962 | out_free: |
| 963 | if (gic_data.domain) |
| 964 | irq_domain_remove(gic_data.domain); |
| 965 | free_percpu(gic_data.rdists.rdist); |
| 966 | return err; |
| 967 | } |
| 968 | |
| 969 | static int __init gic_validate_dist_version(void __iomem *dist_base) |
| 970 | { |
| 971 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
| 972 | |
| 973 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) |
| 974 | return -ENODEV; |
| 975 | |
| 976 | return 0; |
| 977 | } |
| 978 | |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 979 | static int get_cpu_number(struct device_node *dn) |
| 980 | { |
| 981 | const __be32 *cell; |
| 982 | u64 hwid; |
| 983 | int i; |
| 984 | |
| 985 | cell = of_get_property(dn, "reg", NULL); |
| 986 | if (!cell) |
| 987 | return -1; |
| 988 | |
| 989 | hwid = of_read_number(cell, of_n_addr_cells(dn)); |
| 990 | |
| 991 | /* |
| 992 | * Non affinity bits must be set to 0 in the DT |
| 993 | */ |
| 994 | if (hwid & ~MPIDR_HWID_BITMASK) |
| 995 | return -1; |
| 996 | |
| 997 | for (i = 0; i < num_possible_cpus(); i++) |
| 998 | if (cpu_logical_map(i) == hwid) |
| 999 | return i; |
| 1000 | |
| 1001 | return -1; |
| 1002 | } |
| 1003 | |
| 1004 | /* Create all possible partitions at boot time */ |
| 1005 | static void gic_populate_ppi_partitions(struct device_node *gic_node) |
| 1006 | { |
| 1007 | struct device_node *parts_node, *child_part; |
| 1008 | int part_idx = 0, i; |
| 1009 | int nr_parts; |
| 1010 | struct partition_affinity *parts; |
| 1011 | |
| 1012 | parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); |
| 1013 | if (!parts_node) |
| 1014 | return; |
| 1015 | |
| 1016 | nr_parts = of_get_child_count(parts_node); |
| 1017 | |
| 1018 | if (!nr_parts) |
| 1019 | return; |
| 1020 | |
| 1021 | parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); |
| 1022 | if (WARN_ON(!parts)) |
| 1023 | return; |
| 1024 | |
| 1025 | for_each_child_of_node(parts_node, child_part) { |
| 1026 | struct partition_affinity *part; |
| 1027 | int n; |
| 1028 | |
| 1029 | part = &parts[part_idx]; |
| 1030 | |
| 1031 | part->partition_id = of_node_to_fwnode(child_part); |
| 1032 | |
| 1033 | pr_info("GIC: PPI partition %s[%d] { ", |
| 1034 | child_part->name, part_idx); |
| 1035 | |
| 1036 | n = of_property_count_elems_of_size(child_part, "affinity", |
| 1037 | sizeof(u32)); |
| 1038 | WARN_ON(n <= 0); |
| 1039 | |
| 1040 | for (i = 0; i < n; i++) { |
| 1041 | int err, cpu; |
| 1042 | u32 cpu_phandle; |
| 1043 | struct device_node *cpu_node; |
| 1044 | |
| 1045 | err = of_property_read_u32_index(child_part, "affinity", |
| 1046 | i, &cpu_phandle); |
| 1047 | if (WARN_ON(err)) |
| 1048 | continue; |
| 1049 | |
| 1050 | cpu_node = of_find_node_by_phandle(cpu_phandle); |
| 1051 | if (WARN_ON(!cpu_node)) |
| 1052 | continue; |
| 1053 | |
| 1054 | cpu = get_cpu_number(cpu_node); |
| 1055 | if (WARN_ON(cpu == -1)) |
| 1056 | continue; |
| 1057 | |
| 1058 | pr_cont("%s[%d] ", cpu_node->full_name, cpu); |
| 1059 | |
| 1060 | cpumask_set_cpu(cpu, &part->mask); |
| 1061 | } |
| 1062 | |
| 1063 | pr_cont("}\n"); |
| 1064 | part_idx++; |
| 1065 | } |
| 1066 | |
| 1067 | for (i = 0; i < 16; i++) { |
| 1068 | unsigned int irq; |
| 1069 | struct partition_desc *desc; |
| 1070 | struct irq_fwspec ppi_fwspec = { |
| 1071 | .fwnode = gic_data.fwnode, |
| 1072 | .param_count = 3, |
| 1073 | .param = { |
| 1074 | [0] = 1, |
| 1075 | [1] = i, |
| 1076 | [2] = IRQ_TYPE_NONE, |
| 1077 | }, |
| 1078 | }; |
| 1079 | |
| 1080 | irq = irq_create_fwspec_mapping(&ppi_fwspec); |
| 1081 | if (WARN_ON(!irq)) |
| 1082 | continue; |
| 1083 | desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, |
| 1084 | irq, &partition_domain_ops); |
| 1085 | if (WARN_ON(!desc)) |
| 1086 | continue; |
| 1087 | |
| 1088 | gic_data.ppi_descs[i] = desc; |
| 1089 | } |
| 1090 | } |
| 1091 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1092 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
| 1093 | { |
| 1094 | void __iomem *dist_base; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1095 | struct redist_region *rdist_regs; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1096 | u64 redist_stride; |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1097 | u32 nr_redist_regions; |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 1098 | int err, i; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1099 | |
| 1100 | dist_base = of_iomap(node, 0); |
| 1101 | if (!dist_base) { |
| 1102 | pr_err("%s: unable to map gic dist registers\n", |
| 1103 | node->full_name); |
| 1104 | return -ENXIO; |
| 1105 | } |
| 1106 | |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 1107 | err = gic_validate_dist_version(dist_base); |
| 1108 | if (err) { |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1109 | pr_err("%s: no distributor detected, giving up\n", |
| 1110 | node->full_name); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1111 | goto out_unmap_dist; |
| 1112 | } |
| 1113 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1114 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) |
| 1115 | nr_redist_regions = 1; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1116 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1117 | rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); |
| 1118 | if (!rdist_regs) { |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1119 | err = -ENOMEM; |
| 1120 | goto out_unmap_dist; |
| 1121 | } |
| 1122 | |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1123 | for (i = 0; i < nr_redist_regions; i++) { |
| 1124 | struct resource res; |
| 1125 | int ret; |
| 1126 | |
| 1127 | ret = of_address_to_resource(node, 1 + i, &res); |
| 1128 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); |
| 1129 | if (ret || !rdist_regs[i].redist_base) { |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1130 | pr_err("%s: couldn't map region %d\n", |
| 1131 | node->full_name, i); |
| 1132 | err = -ENODEV; |
| 1133 | goto out_unmap_rdist; |
| 1134 | } |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1135 | rdist_regs[i].phys_base = res.start; |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1136 | } |
| 1137 | |
| 1138 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) |
| 1139 | redist_stride = 0; |
| 1140 | |
Tomasz Nowicki | db57d74 | 2016-01-19 14:11:14 +0100 | [diff] [blame] | 1141 | err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, |
| 1142 | redist_stride, &node->fwnode); |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 1143 | if (err) |
| 1144 | goto out_unmap_rdist; |
| 1145 | |
| 1146 | gic_populate_ppi_partitions(node); |
| 1147 | return 0; |
Marc Zyngier | 0b6a3da | 2015-08-26 17:00:42 +0100 | [diff] [blame] | 1148 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1149 | out_unmap_rdist: |
Marc Zyngier | f5c1434 | 2014-11-24 14:35:10 +0000 | [diff] [blame] | 1150 | for (i = 0; i < nr_redist_regions; i++) |
| 1151 | if (rdist_regs[i].redist_base) |
| 1152 | iounmap(rdist_regs[i].redist_base); |
| 1153 | kfree(rdist_regs); |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 1154 | out_unmap_dist: |
| 1155 | iounmap(dist_base); |
| 1156 | return err; |
| 1157 | } |
| 1158 | |
| 1159 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1160 | |
| 1161 | #ifdef CONFIG_ACPI |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1162 | static void __iomem *dist_base; |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1163 | static struct redist_region *redist_regs __initdata; |
| 1164 | static u32 nr_redist_regions __initdata; |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1165 | static bool single_redist; |
| 1166 | |
| 1167 | static void __init |
| 1168 | gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) |
| 1169 | { |
| 1170 | static int count = 0; |
| 1171 | |
| 1172 | redist_regs[count].phys_base = phys_base; |
| 1173 | redist_regs[count].redist_base = redist_base; |
| 1174 | redist_regs[count].single_redist = single_redist; |
| 1175 | count++; |
| 1176 | } |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1177 | |
| 1178 | static int __init |
| 1179 | gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, |
| 1180 | const unsigned long end) |
| 1181 | { |
| 1182 | struct acpi_madt_generic_redistributor *redist = |
| 1183 | (struct acpi_madt_generic_redistributor *)header; |
| 1184 | void __iomem *redist_base; |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1185 | |
| 1186 | redist_base = ioremap(redist->base_address, redist->length); |
| 1187 | if (!redist_base) { |
| 1188 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); |
| 1189 | return -ENOMEM; |
| 1190 | } |
| 1191 | |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1192 | gic_acpi_register_redist(redist->base_address, redist_base); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1193 | return 0; |
| 1194 | } |
| 1195 | |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1196 | static int __init |
| 1197 | gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, |
| 1198 | const unsigned long end) |
| 1199 | { |
| 1200 | struct acpi_madt_generic_interrupt *gicc = |
| 1201 | (struct acpi_madt_generic_interrupt *)header; |
| 1202 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
| 1203 | u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; |
| 1204 | void __iomem *redist_base; |
| 1205 | |
| 1206 | redist_base = ioremap(gicc->gicr_base_address, size); |
| 1207 | if (!redist_base) |
| 1208 | return -ENOMEM; |
| 1209 | |
| 1210 | gic_acpi_register_redist(gicc->gicr_base_address, redist_base); |
| 1211 | return 0; |
| 1212 | } |
| 1213 | |
| 1214 | static int __init gic_acpi_collect_gicr_base(void) |
| 1215 | { |
| 1216 | acpi_tbl_entry_handler redist_parser; |
| 1217 | enum acpi_madt_type type; |
| 1218 | |
| 1219 | if (single_redist) { |
| 1220 | type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; |
| 1221 | redist_parser = gic_acpi_parse_madt_gicc; |
| 1222 | } else { |
| 1223 | type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; |
| 1224 | redist_parser = gic_acpi_parse_madt_redist; |
| 1225 | } |
| 1226 | |
| 1227 | /* Collect redistributor base addresses in GICR entries */ |
| 1228 | if (acpi_table_parse_madt(type, redist_parser, 0) > 0) |
| 1229 | return 0; |
| 1230 | |
| 1231 | pr_info("No valid GICR entries exist\n"); |
| 1232 | return -ENODEV; |
| 1233 | } |
| 1234 | |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1235 | static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, |
| 1236 | const unsigned long end) |
| 1237 | { |
| 1238 | /* Subtable presence means that redist exists, that's it */ |
| 1239 | return 0; |
| 1240 | } |
| 1241 | |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1242 | static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, |
| 1243 | const unsigned long end) |
| 1244 | { |
| 1245 | struct acpi_madt_generic_interrupt *gicc = |
| 1246 | (struct acpi_madt_generic_interrupt *)header; |
| 1247 | |
| 1248 | /* |
| 1249 | * If GICC is enabled and has valid gicr base address, then it means |
| 1250 | * GICR base is presented via GICC |
| 1251 | */ |
| 1252 | if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) |
| 1253 | return 0; |
| 1254 | |
| 1255 | return -ENODEV; |
| 1256 | } |
| 1257 | |
| 1258 | static int __init gic_acpi_count_gicr_regions(void) |
| 1259 | { |
| 1260 | int count; |
| 1261 | |
| 1262 | /* |
| 1263 | * Count how many redistributor regions we have. It is not allowed |
| 1264 | * to mix redistributor description, GICR and GICC subtables have to be |
| 1265 | * mutually exclusive. |
| 1266 | */ |
| 1267 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, |
| 1268 | gic_acpi_match_gicr, 0); |
| 1269 | if (count > 0) { |
| 1270 | single_redist = false; |
| 1271 | return count; |
| 1272 | } |
| 1273 | |
| 1274 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, |
| 1275 | gic_acpi_match_gicc, 0); |
| 1276 | if (count > 0) |
| 1277 | single_redist = true; |
| 1278 | |
| 1279 | return count; |
| 1280 | } |
| 1281 | |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1282 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, |
| 1283 | struct acpi_probe_entry *ape) |
| 1284 | { |
| 1285 | struct acpi_madt_generic_distributor *dist; |
| 1286 | int count; |
| 1287 | |
| 1288 | dist = (struct acpi_madt_generic_distributor *)header; |
| 1289 | if (dist->version != ape->driver_data) |
| 1290 | return false; |
| 1291 | |
| 1292 | /* We need to do that exercise anyway, the sooner the better */ |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1293 | count = gic_acpi_count_gicr_regions(); |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1294 | if (count <= 0) |
| 1295 | return false; |
| 1296 | |
| 1297 | nr_redist_regions = count; |
| 1298 | return true; |
| 1299 | } |
| 1300 | |
| 1301 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) |
| 1302 | |
| 1303 | static int __init |
| 1304 | gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) |
| 1305 | { |
| 1306 | struct acpi_madt_generic_distributor *dist; |
| 1307 | struct fwnode_handle *domain_handle; |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1308 | int i, err; |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1309 | |
| 1310 | /* Get distributor base address */ |
| 1311 | dist = (struct acpi_madt_generic_distributor *)header; |
| 1312 | dist_base = ioremap(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE); |
| 1313 | if (!dist_base) { |
| 1314 | pr_err("Unable to map GICD registers\n"); |
| 1315 | return -ENOMEM; |
| 1316 | } |
| 1317 | |
| 1318 | err = gic_validate_dist_version(dist_base); |
| 1319 | if (err) { |
| 1320 | pr_err("No distributor detected at @%p, giving up", dist_base); |
| 1321 | goto out_dist_unmap; |
| 1322 | } |
| 1323 | |
| 1324 | redist_regs = kzalloc(sizeof(*redist_regs) * nr_redist_regions, |
| 1325 | GFP_KERNEL); |
| 1326 | if (!redist_regs) { |
| 1327 | err = -ENOMEM; |
| 1328 | goto out_dist_unmap; |
| 1329 | } |
| 1330 | |
Tomasz Nowicki | b70fb7a | 2016-01-19 14:11:16 +0100 | [diff] [blame] | 1331 | err = gic_acpi_collect_gicr_base(); |
| 1332 | if (err) |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1333 | goto out_redist_unmap; |
Tomasz Nowicki | ffa7d61 | 2016-01-19 14:11:15 +0100 | [diff] [blame] | 1334 | |
| 1335 | domain_handle = irq_domain_alloc_fwnode(dist_base); |
| 1336 | if (!domain_handle) { |
| 1337 | err = -ENOMEM; |
| 1338 | goto out_redist_unmap; |
| 1339 | } |
| 1340 | |
| 1341 | err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0, |
| 1342 | domain_handle); |
| 1343 | if (err) |
| 1344 | goto out_fwhandle_free; |
| 1345 | |
| 1346 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); |
| 1347 | return 0; |
| 1348 | |
| 1349 | out_fwhandle_free: |
| 1350 | irq_domain_free_fwnode(domain_handle); |
| 1351 | out_redist_unmap: |
| 1352 | for (i = 0; i < nr_redist_regions; i++) |
| 1353 | if (redist_regs[i].redist_base) |
| 1354 | iounmap(redist_regs[i].redist_base); |
| 1355 | kfree(redist_regs); |
| 1356 | out_dist_unmap: |
| 1357 | iounmap(dist_base); |
| 1358 | return err; |
| 1359 | } |
| 1360 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
| 1361 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, |
| 1362 | gic_acpi_init); |
| 1363 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
| 1364 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, |
| 1365 | gic_acpi_init); |
| 1366 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
| 1367 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, |
| 1368 | gic_acpi_init); |
| 1369 | #endif |