Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1 | /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module |
| 2 | * |
| 3 | * This driver supports the memory controllers found on the Intel |
| 4 | * processor family Sandy Bridge. |
| 5 | * |
| 6 | * This file may be distributed under the terms of the |
| 7 | * GNU General Public License version 2 only. |
| 8 | * |
| 9 | * Copyright (c) 2011 by: |
Mauro Carvalho Chehab | 37e59f8 | 2014-02-07 08:03:07 -0200 | [diff] [blame] | 10 | * Mauro Carvalho Chehab |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/pci.h> |
| 16 | #include <linux/pci_ids.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/edac.h> |
| 20 | #include <linux/mmzone.h> |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 21 | #include <linux/smp.h> |
| 22 | #include <linux/bitmap.h> |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 23 | #include <linux/math64.h> |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 24 | #include <asm/processor.h> |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 25 | #include <asm/mce.h> |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 26 | |
| 27 | #include "edac_core.h" |
| 28 | |
| 29 | /* Static vars */ |
| 30 | static LIST_HEAD(sbridge_edac_list); |
| 31 | static DEFINE_MUTEX(sbridge_edac_lock); |
| 32 | static int probed; |
| 33 | |
| 34 | /* |
| 35 | * Alter this version for the module when modifications are made |
| 36 | */ |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 37 | #define SBRIDGE_REVISION " Ver: 1.1.1 " |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 38 | #define EDAC_MOD_STR "sbridge_edac" |
| 39 | |
| 40 | /* |
| 41 | * Debug macros |
| 42 | */ |
| 43 | #define sbridge_printk(level, fmt, arg...) \ |
| 44 | edac_printk(level, "sbridge", fmt, ##arg) |
| 45 | |
| 46 | #define sbridge_mc_printk(mci, level, fmt, arg...) \ |
| 47 | edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) |
| 48 | |
| 49 | /* |
| 50 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> |
| 51 | */ |
| 52 | #define GET_BITFIELD(v, lo, hi) \ |
Chen, Gong | 10ef6b0 | 2013-10-18 14:29:07 -0700 | [diff] [blame] | 53 | (((v) & GENMASK_ULL(hi, lo)) >> (lo)) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 54 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 55 | /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 56 | static const u32 sbridge_dram_rule[] = { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 57 | 0x80, 0x88, 0x90, 0x98, 0xa0, |
| 58 | 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, |
| 59 | }; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 60 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 61 | static const u32 ibridge_dram_rule[] = { |
| 62 | 0x60, 0x68, 0x70, 0x78, 0x80, |
| 63 | 0x88, 0x90, 0x98, 0xa0, 0xa8, |
| 64 | 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, |
| 65 | 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, |
| 66 | }; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 67 | |
| 68 | #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff) |
| 69 | #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3) |
| 70 | #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1) |
| 71 | #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 72 | #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 73 | |
| 74 | static char *get_dram_attr(u32 reg) |
| 75 | { |
| 76 | switch(DRAM_ATTR(reg)) { |
| 77 | case 0: |
| 78 | return "DRAM"; |
| 79 | case 1: |
| 80 | return "MMCFG"; |
| 81 | case 2: |
| 82 | return "NXM"; |
| 83 | default: |
| 84 | return "unknown"; |
| 85 | } |
| 86 | } |
| 87 | |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 88 | static const u32 sbridge_interleave_list[] = { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 89 | 0x84, 0x8c, 0x94, 0x9c, 0xa4, |
| 90 | 0xac, 0xb4, 0xbc, 0xc4, 0xcc, |
| 91 | }; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 92 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 93 | static const u32 ibridge_interleave_list[] = { |
| 94 | 0x64, 0x6c, 0x74, 0x7c, 0x84, |
| 95 | 0x8c, 0x94, 0x9c, 0xa4, 0xac, |
| 96 | 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, |
| 97 | 0xdc, 0xe4, 0xec, 0xf4, 0xfc, |
| 98 | }; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 99 | |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 100 | struct interleave_pkg { |
| 101 | unsigned char start; |
| 102 | unsigned char end; |
| 103 | }; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 104 | |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 105 | static const struct interleave_pkg sbridge_interleave_pkg[] = { |
| 106 | { 0, 2 }, |
| 107 | { 3, 5 }, |
| 108 | { 8, 10 }, |
| 109 | { 11, 13 }, |
| 110 | { 16, 18 }, |
| 111 | { 19, 21 }, |
| 112 | { 24, 26 }, |
| 113 | { 27, 29 }, |
| 114 | }; |
| 115 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 116 | static const struct interleave_pkg ibridge_interleave_pkg[] = { |
| 117 | { 0, 3 }, |
| 118 | { 4, 7 }, |
| 119 | { 8, 11 }, |
| 120 | { 12, 15 }, |
| 121 | { 16, 19 }, |
| 122 | { 20, 23 }, |
| 123 | { 24, 27 }, |
| 124 | { 28, 31 }, |
| 125 | }; |
| 126 | |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 127 | static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, |
| 128 | int interleave) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 129 | { |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 130 | return GET_BITFIELD(reg, table[interleave].start, |
| 131 | table[interleave].end); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | /* Devices 12 Function 7 */ |
| 135 | |
| 136 | #define TOLM 0x80 |
| 137 | #define TOHM 0x84 |
Tony Luck | f7cf2a2 | 2014-10-29 10:36:50 -0700 | [diff] [blame] | 138 | #define HASWELL_TOLM 0xd0 |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 139 | #define HASWELL_TOHM_0 0xd4 |
| 140 | #define HASWELL_TOHM_1 0xd8 |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 141 | |
| 142 | #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) |
| 143 | #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) |
| 144 | |
| 145 | /* Device 13 Function 6 */ |
| 146 | |
| 147 | #define SAD_TARGET 0xf0 |
| 148 | |
| 149 | #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) |
| 150 | |
| 151 | #define SAD_CONTROL 0xf4 |
| 152 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 153 | /* Device 14 function 0 */ |
| 154 | |
| 155 | static const u32 tad_dram_rule[] = { |
| 156 | 0x40, 0x44, 0x48, 0x4c, |
| 157 | 0x50, 0x54, 0x58, 0x5c, |
| 158 | 0x60, 0x64, 0x68, 0x6c, |
| 159 | }; |
| 160 | #define MAX_TAD ARRAY_SIZE(tad_dram_rule) |
| 161 | |
| 162 | #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) |
| 163 | #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) |
| 164 | #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) |
| 165 | #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) |
| 166 | #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) |
| 167 | #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) |
| 168 | #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) |
| 169 | |
| 170 | /* Device 15, function 0 */ |
| 171 | |
| 172 | #define MCMTR 0x7c |
| 173 | |
| 174 | #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) |
| 175 | #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) |
| 176 | #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) |
| 177 | |
| 178 | /* Device 15, function 1 */ |
| 179 | |
| 180 | #define RASENABLES 0xac |
| 181 | #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) |
| 182 | |
| 183 | /* Device 15, functions 2-5 */ |
| 184 | |
| 185 | static const int mtr_regs[] = { |
| 186 | 0x80, 0x84, 0x88, |
| 187 | }; |
| 188 | |
| 189 | #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) |
| 190 | #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) |
| 191 | #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) |
| 192 | #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) |
| 193 | #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) |
| 194 | |
| 195 | static const u32 tad_ch_nilv_offset[] = { |
| 196 | 0x90, 0x94, 0x98, 0x9c, |
| 197 | 0xa0, 0xa4, 0xa8, 0xac, |
| 198 | 0xb0, 0xb4, 0xb8, 0xbc, |
| 199 | }; |
| 200 | #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) |
| 201 | #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) |
| 202 | |
| 203 | static const u32 rir_way_limit[] = { |
| 204 | 0x108, 0x10c, 0x110, 0x114, 0x118, |
| 205 | }; |
| 206 | #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) |
| 207 | |
| 208 | #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) |
| 209 | #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 210 | |
| 211 | #define MAX_RIR_WAY 8 |
| 212 | |
| 213 | static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { |
| 214 | { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, |
| 215 | { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, |
| 216 | { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, |
| 217 | { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, |
| 218 | { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, |
| 219 | }; |
| 220 | |
| 221 | #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) |
| 222 | #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) |
| 223 | |
| 224 | /* Device 16, functions 2-7 */ |
| 225 | |
| 226 | /* |
| 227 | * FIXME: Implement the error count reads directly |
| 228 | */ |
| 229 | |
| 230 | static const u32 correrrcnt[] = { |
| 231 | 0x104, 0x108, 0x10c, 0x110, |
| 232 | }; |
| 233 | |
| 234 | #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) |
| 235 | #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) |
| 236 | #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) |
| 237 | #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) |
| 238 | |
| 239 | static const u32 correrrthrsld[] = { |
| 240 | 0x11c, 0x120, 0x124, 0x128, |
| 241 | }; |
| 242 | |
| 243 | #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) |
| 244 | #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) |
| 245 | |
| 246 | |
| 247 | /* Device 17, function 0 */ |
| 248 | |
Aristeu Rozanski | ef1e8d0 | 2013-10-30 13:26:56 -0300 | [diff] [blame] | 249 | #define SB_RANK_CFG_A 0x0328 |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 250 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 251 | #define IB_RANK_CFG_A 0x0320 |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 252 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 253 | /* |
| 254 | * sbridge structs |
| 255 | */ |
| 256 | |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 257 | #define NUM_CHANNELS 8 /* 2MC per socket, four chan per MC */ |
Seth Jennings | 351fc4a | 2014-09-05 14:28:47 -0500 | [diff] [blame] | 258 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ |
| 259 | #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */ |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 260 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 261 | enum type { |
| 262 | SANDY_BRIDGE, |
| 263 | IVY_BRIDGE, |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 264 | HASWELL, |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 265 | BROADWELL, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 266 | }; |
| 267 | |
Aristeu Rozanski | fb79a50 | 2013-10-30 13:26:57 -0300 | [diff] [blame] | 268 | struct sbridge_pvt; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 269 | struct sbridge_info { |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 270 | enum type type; |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 271 | u32 mcmtr; |
| 272 | u32 rankcfgr; |
| 273 | u64 (*get_tolm)(struct sbridge_pvt *pvt); |
| 274 | u64 (*get_tohm)(struct sbridge_pvt *pvt); |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 275 | u64 (*rir_limit)(u32 reg); |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 276 | const u32 *dram_rule; |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 277 | const u32 *interleave_list; |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 278 | const struct interleave_pkg *interleave_pkg; |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 279 | u8 max_sad; |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 280 | u8 max_interleave; |
Aristeu Rozanski | f14d689 | 2014-06-02 15:15:23 -0300 | [diff] [blame] | 281 | u8 (*get_node_id)(struct sbridge_pvt *pvt); |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 282 | enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 283 | struct pci_dev *pci_vtd; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 284 | }; |
| 285 | |
| 286 | struct sbridge_channel { |
| 287 | u32 ranks; |
| 288 | u32 dimms; |
| 289 | }; |
| 290 | |
| 291 | struct pci_id_descr { |
Mauro Carvalho Chehab | c41afdc | 2014-06-26 15:35:14 -0300 | [diff] [blame] | 292 | int dev_id; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 293 | int optional; |
| 294 | }; |
| 295 | |
| 296 | struct pci_id_table { |
| 297 | const struct pci_id_descr *descr; |
| 298 | int n_devs; |
| 299 | }; |
| 300 | |
| 301 | struct sbridge_dev { |
| 302 | struct list_head list; |
| 303 | u8 bus, mc; |
| 304 | u8 node_id, source_id; |
| 305 | struct pci_dev **pdev; |
| 306 | int n_devs; |
| 307 | struct mem_ctl_info *mci; |
| 308 | }; |
| 309 | |
| 310 | struct sbridge_pvt { |
| 311 | struct pci_dev *pci_ta, *pci_ddrio, *pci_ras; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 312 | struct pci_dev *pci_sad0, *pci_sad1; |
| 313 | struct pci_dev *pci_ha0, *pci_ha1; |
| 314 | struct pci_dev *pci_br0, *pci_br1; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 315 | struct pci_dev *pci_ha1_ta; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 316 | struct pci_dev *pci_tad[NUM_CHANNELS]; |
| 317 | |
| 318 | struct sbridge_dev *sbridge_dev; |
| 319 | |
| 320 | struct sbridge_info info; |
| 321 | struct sbridge_channel channel[NUM_CHANNELS]; |
| 322 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 323 | /* Memory type detection */ |
| 324 | bool is_mirrored, is_lockstep, is_close_pg; |
| 325 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 326 | /* Fifo double buffers */ |
| 327 | struct mce mce_entry[MCE_LOG_LEN]; |
| 328 | struct mce mce_outentry[MCE_LOG_LEN]; |
| 329 | |
| 330 | /* Fifo in/out counters */ |
| 331 | unsigned mce_in, mce_out; |
| 332 | |
| 333 | /* Count indicator to show errors not got */ |
| 334 | unsigned mce_overrun; |
| 335 | |
| 336 | /* Memory description */ |
| 337 | u64 tolm, tohm; |
| 338 | }; |
| 339 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 340 | #define PCI_DESCR(device_id, opt) \ |
| 341 | .dev_id = (device_id), \ |
Luck, Tony | de4772c | 2013-03-28 09:59:15 -0700 | [diff] [blame] | 342 | .optional = opt |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 343 | |
| 344 | static const struct pci_id_descr pci_dev_descr_sbridge[] = { |
| 345 | /* Processor Home Agent */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 346 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) }, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 347 | |
| 348 | /* Memory controller */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 349 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) }, |
| 350 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) }, |
| 351 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) }, |
| 352 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) }, |
| 353 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) }, |
| 354 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) }, |
| 355 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) }, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 356 | |
| 357 | /* System Address Decoder */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 358 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) }, |
| 359 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) }, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 360 | |
| 361 | /* Broadcast Registers */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 362 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) }, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 363 | }; |
| 364 | |
| 365 | #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } |
| 366 | static const struct pci_id_table pci_dev_descr_sbridge_table[] = { |
| 367 | PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge), |
| 368 | {0,} /* 0 terminated list. */ |
| 369 | }; |
| 370 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 371 | /* This changes depending if 1HA or 2HA: |
| 372 | * 1HA: |
| 373 | * 0x0eb8 (17.0) is DDRIO0 |
| 374 | * 2HA: |
| 375 | * 0x0ebc (17.4) is DDRIO0 |
| 376 | */ |
| 377 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8 |
| 378 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc |
| 379 | |
| 380 | /* pci ids */ |
| 381 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0 |
| 382 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8 |
| 383 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71 |
| 384 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa |
| 385 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab |
| 386 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac |
| 387 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead |
| 388 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8 |
| 389 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9 |
| 390 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca |
| 391 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60 |
| 392 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68 |
| 393 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79 |
| 394 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a |
| 395 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 396 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c |
| 397 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 398 | |
| 399 | static const struct pci_id_descr pci_dev_descr_ibridge[] = { |
| 400 | /* Processor Home Agent */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 401 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 402 | |
| 403 | /* Memory controller */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 404 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) }, |
| 405 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) }, |
| 406 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) }, |
| 407 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) }, |
| 408 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) }, |
| 409 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 410 | |
| 411 | /* System Address Decoder */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 412 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 413 | |
| 414 | /* Broadcast Registers */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 415 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) }, |
| 416 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 417 | |
| 418 | /* Optional, mode 2HA */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 419 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 420 | #if 0 |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 421 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) }, |
| 422 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 423 | #endif |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 424 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) }, |
| 425 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) }, |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 426 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1) }, |
| 427 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 428 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 429 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) }, |
| 430 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 431 | }; |
| 432 | |
| 433 | static const struct pci_id_table pci_dev_descr_ibridge_table[] = { |
| 434 | PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge), |
| 435 | {0,} /* 0 terminated list. */ |
| 436 | }; |
| 437 | |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 438 | /* Haswell support */ |
| 439 | /* EN processor: |
| 440 | * - 1 IMC |
| 441 | * - 3 DDR3 channels, 2 DPC per channel |
| 442 | * EP processor: |
| 443 | * - 1 or 2 IMC |
| 444 | * - 4 DDR4 channels, 3 DPC per channel |
| 445 | * EP 4S processor: |
| 446 | * - 2 IMC |
| 447 | * - 4 DDR4 channels, 3 DPC per channel |
| 448 | * EX processor: |
| 449 | * - 2 IMC |
| 450 | * - each IMC interfaces with a SMI 2 channel |
| 451 | * - each SMI channel interfaces with a scalable memory buffer |
| 452 | * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC |
| 453 | */ |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 454 | #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */ |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 455 | #define HASWELL_HASYSDEFEATURE2 0x84 |
| 456 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28 |
| 457 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0 |
| 458 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60 |
| 459 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8 |
| 460 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71 |
| 461 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68 |
| 462 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79 |
| 463 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc |
| 464 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd |
| 465 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa |
| 466 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab |
| 467 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac |
| 468 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad |
| 469 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a |
| 470 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b |
| 471 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c |
| 472 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d |
| 473 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd |
| 474 | static const struct pci_id_descr pci_dev_descr_haswell[] = { |
| 475 | /* first item must be the HA */ |
| 476 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) }, |
| 477 | |
| 478 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) }, |
| 479 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) }, |
| 480 | |
| 481 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) }, |
| 482 | |
| 483 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) }, |
| 484 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) }, |
| 485 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) }, |
| 486 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) }, |
| 487 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) }, |
| 488 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) }, |
| 489 | |
| 490 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) }, |
| 491 | |
| 492 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) }, |
| 493 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) }, |
| 494 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) }, |
| 495 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) }, |
| 496 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) }, |
| 497 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) }, |
| 498 | }; |
| 499 | |
| 500 | static const struct pci_id_table pci_dev_descr_haswell_table[] = { |
| 501 | PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell), |
| 502 | {0,} /* 0 terminated list. */ |
| 503 | }; |
| 504 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 505 | /* |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 506 | * Broadwell support |
| 507 | * |
| 508 | * DE processor: |
| 509 | * - 1 IMC |
| 510 | * - 2 DDR3 channels, 2 DPC per channel |
| 511 | */ |
| 512 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28 |
| 513 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0 |
| 514 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8 |
| 515 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71 |
| 516 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc |
| 517 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd |
| 518 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa |
| 519 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab |
| 520 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac |
| 521 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad |
| 522 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf |
| 523 | |
| 524 | static const struct pci_id_descr pci_dev_descr_broadwell[] = { |
| 525 | /* first item must be the HA */ |
| 526 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) }, |
| 527 | |
| 528 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) }, |
| 529 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) }, |
| 530 | |
| 531 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) }, |
| 532 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) }, |
| 533 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) }, |
| 534 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) }, |
| 535 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 0) }, |
| 536 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 0) }, |
| 537 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) }, |
| 538 | }; |
| 539 | |
| 540 | static const struct pci_id_table pci_dev_descr_broadwell_table[] = { |
| 541 | PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell), |
| 542 | {0,} /* 0 terminated list. */ |
| 543 | }; |
| 544 | |
| 545 | /* |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 546 | * pci_device_id table for which devices we are looking for |
| 547 | */ |
Jingoo Han | ba935f4 | 2013-12-06 10:23:08 +0100 | [diff] [blame] | 548 | static const struct pci_device_id sbridge_pci_tbl[] = { |
Andy Lutomirski | d0585cd | 2014-08-14 14:45:41 -0700 | [diff] [blame] | 549 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)}, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 550 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)}, |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 551 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)}, |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 552 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)}, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 553 | {0,} /* 0 terminated list. */ |
| 554 | }; |
| 555 | |
| 556 | |
| 557 | /**************************************************************************** |
David Mackey | 15ed103 | 2012-04-17 11:30:52 -0700 | [diff] [blame] | 558 | Ancillary status routines |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 559 | ****************************************************************************/ |
| 560 | |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 561 | static inline int numrank(enum type type, u32 mtr) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 562 | { |
| 563 | int ranks = (1 << RANK_CNT_BITS(mtr)); |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 564 | int max = 4; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 565 | |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 566 | if (type == HASWELL) |
| 567 | max = 8; |
| 568 | |
| 569 | if (ranks > max) { |
| 570 | edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n", |
| 571 | ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 572 | return -EINVAL; |
| 573 | } |
| 574 | |
| 575 | return ranks; |
| 576 | } |
| 577 | |
| 578 | static inline int numrow(u32 mtr) |
| 579 | { |
| 580 | int rows = (RANK_WIDTH_BITS(mtr) + 12); |
| 581 | |
| 582 | if (rows < 13 || rows > 18) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 583 | edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", |
| 584 | rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 585 | return -EINVAL; |
| 586 | } |
| 587 | |
| 588 | return 1 << rows; |
| 589 | } |
| 590 | |
| 591 | static inline int numcol(u32 mtr) |
| 592 | { |
| 593 | int cols = (COL_WIDTH_BITS(mtr) + 10); |
| 594 | |
| 595 | if (cols > 12) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 596 | edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", |
| 597 | cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 598 | return -EINVAL; |
| 599 | } |
| 600 | |
| 601 | return 1 << cols; |
| 602 | } |
| 603 | |
| 604 | static struct sbridge_dev *get_sbridge_dev(u8 bus) |
| 605 | { |
| 606 | struct sbridge_dev *sbridge_dev; |
| 607 | |
| 608 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { |
| 609 | if (sbridge_dev->bus == bus) |
| 610 | return sbridge_dev; |
| 611 | } |
| 612 | |
| 613 | return NULL; |
| 614 | } |
| 615 | |
| 616 | static struct sbridge_dev *alloc_sbridge_dev(u8 bus, |
| 617 | const struct pci_id_table *table) |
| 618 | { |
| 619 | struct sbridge_dev *sbridge_dev; |
| 620 | |
| 621 | sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL); |
| 622 | if (!sbridge_dev) |
| 623 | return NULL; |
| 624 | |
| 625 | sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs, |
| 626 | GFP_KERNEL); |
| 627 | if (!sbridge_dev->pdev) { |
| 628 | kfree(sbridge_dev); |
| 629 | return NULL; |
| 630 | } |
| 631 | |
| 632 | sbridge_dev->bus = bus; |
| 633 | sbridge_dev->n_devs = table->n_devs; |
| 634 | list_add_tail(&sbridge_dev->list, &sbridge_edac_list); |
| 635 | |
| 636 | return sbridge_dev; |
| 637 | } |
| 638 | |
| 639 | static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) |
| 640 | { |
| 641 | list_del(&sbridge_dev->list); |
| 642 | kfree(sbridge_dev->pdev); |
| 643 | kfree(sbridge_dev); |
| 644 | } |
| 645 | |
Aristeu Rozanski | fb79a50 | 2013-10-30 13:26:57 -0300 | [diff] [blame] | 646 | static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) |
| 647 | { |
| 648 | u32 reg; |
| 649 | |
| 650 | /* Address range is 32:28 */ |
| 651 | pci_read_config_dword(pvt->pci_sad1, TOLM, ®); |
| 652 | return GET_TOLM(reg); |
| 653 | } |
| 654 | |
Aristeu Rozanski | 8fd6a43 | 2013-10-30 13:26:59 -0300 | [diff] [blame] | 655 | static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) |
| 656 | { |
| 657 | u32 reg; |
| 658 | |
| 659 | pci_read_config_dword(pvt->pci_sad1, TOHM, ®); |
| 660 | return GET_TOHM(reg); |
| 661 | } |
| 662 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 663 | static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) |
| 664 | { |
| 665 | u32 reg; |
| 666 | |
| 667 | pci_read_config_dword(pvt->pci_br1, TOLM, ®); |
| 668 | |
| 669 | return GET_TOLM(reg); |
| 670 | } |
| 671 | |
| 672 | static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) |
| 673 | { |
| 674 | u32 reg; |
| 675 | |
| 676 | pci_read_config_dword(pvt->pci_br1, TOHM, ®); |
| 677 | |
| 678 | return GET_TOHM(reg); |
| 679 | } |
| 680 | |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 681 | static u64 rir_limit(u32 reg) |
| 682 | { |
| 683 | return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; |
| 684 | } |
| 685 | |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 686 | static enum mem_type get_memory_type(struct sbridge_pvt *pvt) |
| 687 | { |
| 688 | u32 reg; |
| 689 | enum mem_type mtype; |
| 690 | |
| 691 | if (pvt->pci_ddrio) { |
| 692 | pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, |
| 693 | ®); |
| 694 | if (GET_BITFIELD(reg, 11, 11)) |
| 695 | /* FIXME: Can also be LRDIMM */ |
| 696 | mtype = MEM_RDDR3; |
| 697 | else |
| 698 | mtype = MEM_DDR3; |
| 699 | } else |
| 700 | mtype = MEM_UNKNOWN; |
| 701 | |
| 702 | return mtype; |
| 703 | } |
| 704 | |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 705 | static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) |
| 706 | { |
| 707 | u32 reg; |
| 708 | bool registered = false; |
| 709 | enum mem_type mtype = MEM_UNKNOWN; |
| 710 | |
| 711 | if (!pvt->pci_ddrio) |
| 712 | goto out; |
| 713 | |
| 714 | pci_read_config_dword(pvt->pci_ddrio, |
| 715 | HASWELL_DDRCRCLKCONTROLS, ®); |
| 716 | /* Is_Rdimm */ |
| 717 | if (GET_BITFIELD(reg, 16, 16)) |
| 718 | registered = true; |
| 719 | |
| 720 | pci_read_config_dword(pvt->pci_ta, MCMTR, ®); |
| 721 | if (GET_BITFIELD(reg, 14, 14)) { |
| 722 | if (registered) |
| 723 | mtype = MEM_RDDR4; |
| 724 | else |
| 725 | mtype = MEM_DDR4; |
| 726 | } else { |
| 727 | if (registered) |
| 728 | mtype = MEM_RDDR3; |
| 729 | else |
| 730 | mtype = MEM_DDR3; |
| 731 | } |
| 732 | |
| 733 | out: |
| 734 | return mtype; |
| 735 | } |
| 736 | |
Aristeu Rozanski | f14d689 | 2014-06-02 15:15:23 -0300 | [diff] [blame] | 737 | static u8 get_node_id(struct sbridge_pvt *pvt) |
| 738 | { |
| 739 | u32 reg; |
| 740 | pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); |
| 741 | return GET_BITFIELD(reg, 0, 2); |
| 742 | } |
| 743 | |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 744 | static u8 haswell_get_node_id(struct sbridge_pvt *pvt) |
| 745 | { |
| 746 | u32 reg; |
| 747 | |
| 748 | pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); |
| 749 | return GET_BITFIELD(reg, 0, 3); |
| 750 | } |
| 751 | |
| 752 | static u64 haswell_get_tolm(struct sbridge_pvt *pvt) |
| 753 | { |
| 754 | u32 reg; |
| 755 | |
Tony Luck | f7cf2a2 | 2014-10-29 10:36:50 -0700 | [diff] [blame] | 756 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); |
| 757 | return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 758 | } |
| 759 | |
| 760 | static u64 haswell_get_tohm(struct sbridge_pvt *pvt) |
| 761 | { |
| 762 | u64 rc; |
| 763 | u32 reg; |
| 764 | |
| 765 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); |
| 766 | rc = GET_BITFIELD(reg, 26, 31); |
| 767 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); |
| 768 | rc = ((reg << 6) | rc) << 26; |
| 769 | |
| 770 | return rc | 0x1ffffff; |
| 771 | } |
| 772 | |
| 773 | static u64 haswell_rir_limit(u32 reg) |
| 774 | { |
| 775 | return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; |
| 776 | } |
| 777 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 778 | static inline u8 sad_pkg_socket(u8 pkg) |
| 779 | { |
| 780 | /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ |
Aristeu Rozanski | 2ff3a30 | 2014-06-02 15:15:27 -0300 | [diff] [blame] | 781 | return ((pkg >> 3) << 2) | (pkg & 0x3); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 782 | } |
| 783 | |
| 784 | static inline u8 sad_pkg_ha(u8 pkg) |
| 785 | { |
| 786 | return (pkg >> 2) & 0x1; |
| 787 | } |
| 788 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 789 | /**************************************************************************** |
| 790 | Memory check routines |
| 791 | ****************************************************************************/ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 792 | static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 793 | { |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 794 | struct pci_dev *pdev = NULL; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 795 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 796 | do { |
| 797 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev); |
| 798 | if (pdev && pdev->bus->number == bus) |
| 799 | break; |
| 800 | } while (pdev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 801 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 802 | return pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 803 | } |
| 804 | |
| 805 | /** |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 806 | * check_if_ecc_is_active() - Checks if ECC is active |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 807 | * @bus: Device bus |
| 808 | * @type: Memory controller type |
| 809 | * returns: 0 in case ECC is active, -ENODEV if it can't be determined or |
| 810 | * disabled |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 811 | */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 812 | static int check_if_ecc_is_active(const u8 bus, enum type type) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 813 | { |
| 814 | struct pci_dev *pdev = NULL; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 815 | u32 mcmtr, id; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 816 | |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 817 | switch (type) { |
| 818 | case IVY_BRIDGE: |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 819 | id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA; |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 820 | break; |
| 821 | case HASWELL: |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 822 | id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA; |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 823 | break; |
| 824 | case SANDY_BRIDGE: |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 825 | id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA; |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 826 | break; |
| 827 | case BROADWELL: |
| 828 | id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA; |
| 829 | break; |
| 830 | default: |
| 831 | return -ENODEV; |
| 832 | } |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 833 | |
| 834 | pdev = get_pdev_same_bus(bus, id); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 835 | if (!pdev) { |
| 836 | sbridge_printk(KERN_ERR, "Couldn't find PCI device " |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 837 | "%04x:%04x! on bus %02d\n", |
| 838 | PCI_VENDOR_ID_INTEL, id, bus); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 839 | return -ENODEV; |
| 840 | } |
| 841 | |
| 842 | pci_read_config_dword(pdev, MCMTR, &mcmtr); |
| 843 | if (!IS_ECC_ENABLED(mcmtr)) { |
| 844 | sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n"); |
| 845 | return -ENODEV; |
| 846 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 847 | return 0; |
| 848 | } |
| 849 | |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 850 | static int get_dimm_config(struct mem_ctl_info *mci) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 851 | { |
| 852 | struct sbridge_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 853 | struct dimm_info *dimm; |
Mauro Carvalho Chehab | deb09dd | 2012-09-20 12:09:30 -0300 | [diff] [blame] | 854 | unsigned i, j, banks, ranks, rows, cols, npages; |
| 855 | u64 size; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 856 | u32 reg; |
| 857 | enum edac_type mode; |
Mark A. Grondona | c6e13b5 | 2011-10-18 11:02:58 -0200 | [diff] [blame] | 858 | enum mem_type mtype; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 859 | |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 860 | if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 861 | pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); |
| 862 | else |
| 863 | pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); |
| 864 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 865 | pvt->sbridge_dev->source_id = SOURCE_ID(reg); |
| 866 | |
Aristeu Rozanski | f14d689 | 2014-06-02 15:15:23 -0300 | [diff] [blame] | 867 | pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 868 | edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", |
| 869 | pvt->sbridge_dev->mc, |
| 870 | pvt->sbridge_dev->node_id, |
| 871 | pvt->sbridge_dev->source_id); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 872 | |
| 873 | pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); |
| 874 | if (IS_MIRROR_ENABLED(reg)) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 875 | edac_dbg(0, "Memory mirror is enabled\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 876 | pvt->is_mirrored = true; |
| 877 | } else { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 878 | edac_dbg(0, "Memory mirror is disabled\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 879 | pvt->is_mirrored = false; |
| 880 | } |
| 881 | |
| 882 | pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); |
| 883 | if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 884 | edac_dbg(0, "Lockstep is enabled\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 885 | mode = EDAC_S8ECD8ED; |
| 886 | pvt->is_lockstep = true; |
| 887 | } else { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 888 | edac_dbg(0, "Lockstep is disabled\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 889 | mode = EDAC_S4ECD4ED; |
| 890 | pvt->is_lockstep = false; |
| 891 | } |
| 892 | if (IS_CLOSE_PG(pvt->info.mcmtr)) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 893 | edac_dbg(0, "address map is on closed page mode\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 894 | pvt->is_close_pg = true; |
| 895 | } else { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 896 | edac_dbg(0, "address map is on open page mode\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 897 | pvt->is_close_pg = false; |
| 898 | } |
| 899 | |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 900 | mtype = pvt->info.get_memory_type(pvt); |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 901 | if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4) |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 902 | edac_dbg(0, "Memory is registered\n"); |
| 903 | else if (mtype == MEM_UNKNOWN) |
Luck, Tony | de4772c | 2013-03-28 09:59:15 -0700 | [diff] [blame] | 904 | edac_dbg(0, "Cannot determine memory type\n"); |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 905 | else |
| 906 | edac_dbg(0, "Memory is unregistered\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 907 | |
Tony Luck | fec53af | 2014-12-02 09:41:58 -0800 | [diff] [blame] | 908 | if (mtype == MEM_DDR4 || mtype == MEM_RDDR4) |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 909 | banks = 16; |
| 910 | else |
| 911 | banks = 8; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 912 | |
| 913 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 914 | u32 mtr; |
| 915 | |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 916 | if (!pvt->pci_tad[i]) |
| 917 | continue; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 918 | for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) { |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 919 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
| 920 | i, j, 0); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 921 | pci_read_config_dword(pvt->pci_tad[i], |
| 922 | mtr_regs[j], &mtr); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 923 | edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 924 | if (IS_DIMM_PRESENT(mtr)) { |
| 925 | pvt->channel[i].dimms++; |
| 926 | |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 927 | ranks = numrank(pvt->info.type, mtr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 928 | rows = numrow(mtr); |
| 929 | cols = numcol(mtr); |
| 930 | |
Mauro Carvalho Chehab | deb09dd | 2012-09-20 12:09:30 -0300 | [diff] [blame] | 931 | size = ((u64)rows * cols * banks * ranks) >> (20 - 3); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 932 | npages = MiB_TO_PAGES(size); |
| 933 | |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 934 | edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", |
| 935 | pvt->sbridge_dev->mc, i/4, i%4, j, |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 936 | size, npages, |
| 937 | banks, ranks, rows, cols); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 938 | |
Mauro Carvalho Chehab | a895bf8 | 2012-01-28 09:09:38 -0300 | [diff] [blame] | 939 | dimm->nr_pages = npages; |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 940 | dimm->grain = 32; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 941 | switch (banks) { |
| 942 | case 16: |
| 943 | dimm->dtype = DEV_X16; |
| 944 | break; |
| 945 | case 8: |
| 946 | dimm->dtype = DEV_X8; |
| 947 | break; |
| 948 | case 4: |
| 949 | dimm->dtype = DEV_X4; |
| 950 | break; |
| 951 | } |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 952 | dimm->mtype = mtype; |
| 953 | dimm->edac_mode = mode; |
| 954 | snprintf(dimm->label, sizeof(dimm->label), |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 955 | "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u", |
| 956 | pvt->sbridge_dev->source_id, i/4, i%4, j); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 957 | } |
| 958 | } |
| 959 | } |
| 960 | |
| 961 | return 0; |
| 962 | } |
| 963 | |
| 964 | static void get_memory_layout(const struct mem_ctl_info *mci) |
| 965 | { |
| 966 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 967 | int i, j, k, n_sads, n_tads, sad_interl; |
| 968 | u32 reg; |
| 969 | u64 limit, prv = 0; |
| 970 | u64 tmp_mb; |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 971 | u32 gb, mb; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 972 | u32 rir_way; |
| 973 | |
| 974 | /* |
| 975 | * Step 1) Get TOLM/TOHM ranges |
| 976 | */ |
| 977 | |
Aristeu Rozanski | fb79a50 | 2013-10-30 13:26:57 -0300 | [diff] [blame] | 978 | pvt->tolm = pvt->info.get_tolm(pvt); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 979 | tmp_mb = (1 + pvt->tolm) >> 20; |
| 980 | |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 981 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
| 982 | edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", |
| 983 | gb, (mb*1000)/1024, (u64)pvt->tolm); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 984 | |
| 985 | /* Address range is already 45:25 */ |
Aristeu Rozanski | 8fd6a43 | 2013-10-30 13:26:59 -0300 | [diff] [blame] | 986 | pvt->tohm = pvt->info.get_tohm(pvt); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 987 | tmp_mb = (1 + pvt->tohm) >> 20; |
| 988 | |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 989 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
| 990 | edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", |
| 991 | gb, (mb*1000)/1024, (u64)pvt->tohm); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 992 | |
| 993 | /* |
| 994 | * Step 2) Get SAD range and SAD Interleave list |
| 995 | * TAD registers contain the interleave wayness. However, it |
| 996 | * seems simpler to just discover it indirectly, with the |
| 997 | * algorithm bellow. |
| 998 | */ |
| 999 | prv = 0; |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 1000 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1001 | /* SAD_LIMIT Address range is 45:26 */ |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 1002 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1003 | ®); |
| 1004 | limit = SAD_LIMIT(reg); |
| 1005 | |
| 1006 | if (!DRAM_RULE_ENABLE(reg)) |
| 1007 | continue; |
| 1008 | |
| 1009 | if (limit <= prv) |
| 1010 | break; |
| 1011 | |
| 1012 | tmp_mb = (limit + 1) >> 20; |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1013 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1014 | edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", |
| 1015 | n_sads, |
| 1016 | get_dram_attr(reg), |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1017 | gb, (mb*1000)/1024, |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1018 | ((u64)tmp_mb) << 20L, |
| 1019 | INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]", |
| 1020 | reg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1021 | prv = limit; |
| 1022 | |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 1023 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1024 | ®); |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 1025 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1026 | for (j = 0; j < 8; j++) { |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 1027 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); |
| 1028 | if (j > 0 && sad_interl == pkg) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1029 | break; |
| 1030 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1031 | edac_dbg(0, "SAD#%d, interleave #%d: %d\n", |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 1032 | n_sads, j, pkg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1033 | } |
| 1034 | } |
| 1035 | |
| 1036 | /* |
| 1037 | * Step 3) Get TAD range |
| 1038 | */ |
| 1039 | prv = 0; |
| 1040 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { |
| 1041 | pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], |
| 1042 | ®); |
| 1043 | limit = TAD_LIMIT(reg); |
| 1044 | if (limit <= prv) |
| 1045 | break; |
| 1046 | tmp_mb = (limit + 1) >> 20; |
| 1047 | |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1048 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1049 | edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1050 | n_tads, gb, (mb*1000)/1024, |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1051 | ((u64)tmp_mb) << 20L, |
| 1052 | (u32)TAD_SOCK(reg), |
| 1053 | (u32)TAD_CH(reg), |
| 1054 | (u32)TAD_TGT0(reg), |
| 1055 | (u32)TAD_TGT1(reg), |
| 1056 | (u32)TAD_TGT2(reg), |
| 1057 | (u32)TAD_TGT3(reg), |
| 1058 | reg); |
Hui Wang | 7fae0db | 2012-02-06 04:11:01 -0300 | [diff] [blame] | 1059 | prv = limit; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1060 | } |
| 1061 | |
| 1062 | /* |
| 1063 | * Step 4) Get TAD offsets, per each channel |
| 1064 | */ |
| 1065 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 1066 | if (!pvt->channel[i].dimms) |
| 1067 | continue; |
| 1068 | for (j = 0; j < n_tads; j++) { |
| 1069 | pci_read_config_dword(pvt->pci_tad[i], |
| 1070 | tad_ch_nilv_offset[j], |
| 1071 | ®); |
| 1072 | tmp_mb = TAD_OFFSET(reg) >> 20; |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1073 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1074 | edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", |
| 1075 | i, j, |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1076 | gb, (mb*1000)/1024, |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1077 | ((u64)tmp_mb) << 20L, |
| 1078 | reg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1079 | } |
| 1080 | } |
| 1081 | |
| 1082 | /* |
| 1083 | * Step 6) Get RIR Wayness/Limit, per each channel |
| 1084 | */ |
| 1085 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 1086 | if (!pvt->channel[i].dimms) |
| 1087 | continue; |
| 1088 | for (j = 0; j < MAX_RIR_RANGES; j++) { |
| 1089 | pci_read_config_dword(pvt->pci_tad[i], |
| 1090 | rir_way_limit[j], |
| 1091 | ®); |
| 1092 | |
| 1093 | if (!IS_RIR_VALID(reg)) |
| 1094 | continue; |
| 1095 | |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 1096 | tmp_mb = pvt->info.rir_limit(reg) >> 20; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1097 | rir_way = 1 << RIR_WAY(reg); |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1098 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1099 | edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", |
| 1100 | i, j, |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1101 | gb, (mb*1000)/1024, |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1102 | ((u64)tmp_mb) << 20L, |
| 1103 | rir_way, |
| 1104 | reg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1105 | |
| 1106 | for (k = 0; k < rir_way; k++) { |
| 1107 | pci_read_config_dword(pvt->pci_tad[i], |
| 1108 | rir_offset[j][k], |
| 1109 | ®); |
| 1110 | tmp_mb = RIR_OFFSET(reg) << 6; |
| 1111 | |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1112 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1113 | edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", |
| 1114 | i, j, k, |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1115 | gb, (mb*1000)/1024, |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1116 | ((u64)tmp_mb) << 20L, |
| 1117 | (u32)RIR_RNK_TGT(reg), |
| 1118 | reg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1119 | } |
| 1120 | } |
| 1121 | } |
| 1122 | } |
| 1123 | |
Rashika Kheria | 8112c0c | 2013-12-14 19:32:09 +0530 | [diff] [blame] | 1124 | static struct mem_ctl_info *get_mci_for_node_id(u8 node_id) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1125 | { |
| 1126 | struct sbridge_dev *sbridge_dev; |
| 1127 | |
| 1128 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { |
| 1129 | if (sbridge_dev->node_id == node_id) |
| 1130 | return sbridge_dev->mci; |
| 1131 | } |
| 1132 | return NULL; |
| 1133 | } |
| 1134 | |
| 1135 | static int get_memory_error_data(struct mem_ctl_info *mci, |
| 1136 | u64 addr, |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1137 | u8 *socket, u8 *ha, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1138 | long *channel_mask, |
| 1139 | u8 *rank, |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 1140 | char **area_type, char *msg) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1141 | { |
| 1142 | struct mem_ctl_info *new_mci; |
| 1143 | struct sbridge_pvt *pvt = mci->pvt_info; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1144 | struct pci_dev *pci_ha; |
Mauro Carvalho Chehab | c41afdc | 2014-06-26 15:35:14 -0300 | [diff] [blame] | 1145 | int n_rir, n_sads, n_tads, sad_way, sck_xch; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1146 | int sad_interl, idx, base_ch; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1147 | int interleave_mode, shiftup = 0; |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 1148 | unsigned sad_interleave[pvt->info.max_interleave]; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1149 | u32 reg, dram_rule; |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1150 | u8 ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1151 | u32 tad_offset; |
| 1152 | u32 rir_way; |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1153 | u32 mb, gb; |
Aristeu Rozanski | bd4b968 | 2013-11-21 09:08:03 -0500 | [diff] [blame] | 1154 | u64 ch_addr, offset, limit = 0, prv = 0; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1155 | |
| 1156 | |
| 1157 | /* |
| 1158 | * Step 0) Check if the address is at special memory ranges |
| 1159 | * The check bellow is probably enough to fill all cases where |
| 1160 | * the error is not inside a memory, except for the legacy |
| 1161 | * range (e. g. VGA addresses). It is unlikely, however, that the |
| 1162 | * memory controller would generate an error on that range. |
| 1163 | */ |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 1164 | if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1165 | sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1166 | return -EINVAL; |
| 1167 | } |
| 1168 | if (addr >= (u64)pvt->tohm) { |
| 1169 | sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1170 | return -EINVAL; |
| 1171 | } |
| 1172 | |
| 1173 | /* |
| 1174 | * Step 1) Get socket |
| 1175 | */ |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 1176 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
| 1177 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1178 | ®); |
| 1179 | |
| 1180 | if (!DRAM_RULE_ENABLE(reg)) |
| 1181 | continue; |
| 1182 | |
| 1183 | limit = SAD_LIMIT(reg); |
| 1184 | if (limit <= prv) { |
| 1185 | sprintf(msg, "Can't discover the memory socket"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1186 | return -EINVAL; |
| 1187 | } |
| 1188 | if (addr <= limit) |
| 1189 | break; |
| 1190 | prv = limit; |
| 1191 | } |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 1192 | if (n_sads == pvt->info.max_sad) { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1193 | sprintf(msg, "Can't discover the memory socket"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1194 | return -EINVAL; |
| 1195 | } |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1196 | dram_rule = reg; |
| 1197 | *area_type = get_dram_attr(dram_rule); |
| 1198 | interleave_mode = INTERLEAVE_MODE(dram_rule); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1199 | |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 1200 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1201 | ®); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1202 | |
| 1203 | if (pvt->info.type == SANDY_BRIDGE) { |
| 1204 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); |
| 1205 | for (sad_way = 0; sad_way < 8; sad_way++) { |
| 1206 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); |
| 1207 | if (sad_way > 0 && sad_interl == pkg) |
| 1208 | break; |
| 1209 | sad_interleave[sad_way] = pkg; |
| 1210 | edac_dbg(0, "SAD interleave #%d: %d\n", |
| 1211 | sad_way, sad_interleave[sad_way]); |
| 1212 | } |
| 1213 | edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", |
| 1214 | pvt->sbridge_dev->mc, |
| 1215 | n_sads, |
| 1216 | addr, |
| 1217 | limit, |
| 1218 | sad_way + 7, |
| 1219 | !interleave_mode ? "" : "XOR[18:16]"); |
| 1220 | if (interleave_mode) |
| 1221 | idx = ((addr >> 6) ^ (addr >> 16)) & 7; |
| 1222 | else |
| 1223 | idx = (addr >> 6) & 7; |
| 1224 | switch (sad_way) { |
| 1225 | case 1: |
| 1226 | idx = 0; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1227 | break; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1228 | case 2: |
| 1229 | idx = idx & 1; |
| 1230 | break; |
| 1231 | case 4: |
| 1232 | idx = idx & 3; |
| 1233 | break; |
| 1234 | case 8: |
| 1235 | break; |
| 1236 | default: |
| 1237 | sprintf(msg, "Can't discover socket interleave"); |
| 1238 | return -EINVAL; |
| 1239 | } |
| 1240 | *socket = sad_interleave[idx]; |
| 1241 | edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", |
| 1242 | idx, sad_way, *socket); |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 1243 | } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1244 | int bits, a7mode = A7MODE(dram_rule); |
| 1245 | |
| 1246 | if (a7mode) { |
| 1247 | /* A7 mode swaps P9 with P6 */ |
| 1248 | bits = GET_BITFIELD(addr, 7, 8) << 1; |
| 1249 | bits |= GET_BITFIELD(addr, 9, 9); |
| 1250 | } else |
Tony Luck | bb89e71 | 2015-05-18 17:39:06 -0300 | [diff] [blame] | 1251 | bits = GET_BITFIELD(addr, 6, 8); |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1252 | |
Tony Luck | bb89e71 | 2015-05-18 17:39:06 -0300 | [diff] [blame] | 1253 | if (interleave_mode == 0) { |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1254 | /* interleave mode will XOR {8,7,6} with {18,17,16} */ |
| 1255 | idx = GET_BITFIELD(addr, 16, 18); |
| 1256 | idx ^= bits; |
| 1257 | } else |
| 1258 | idx = bits; |
| 1259 | |
| 1260 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); |
| 1261 | *socket = sad_pkg_socket(pkg); |
| 1262 | sad_ha = sad_pkg_ha(pkg); |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1263 | if (sad_ha) |
| 1264 | ch_add = 4; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1265 | |
| 1266 | if (a7mode) { |
| 1267 | /* MCChanShiftUpEnable */ |
| 1268 | pci_read_config_dword(pvt->pci_ha0, |
| 1269 | HASWELL_HASYSDEFEATURE2, ®); |
| 1270 | shiftup = GET_BITFIELD(reg, 22, 22); |
| 1271 | } |
| 1272 | |
| 1273 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", |
| 1274 | idx, *socket, sad_ha, shiftup); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1275 | } else { |
| 1276 | /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1277 | idx = (addr >> 6) & 7; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1278 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); |
| 1279 | *socket = sad_pkg_socket(pkg); |
| 1280 | sad_ha = sad_pkg_ha(pkg); |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1281 | if (sad_ha) |
| 1282 | ch_add = 4; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1283 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", |
| 1284 | idx, *socket, sad_ha); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1285 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1286 | |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1287 | *ha = sad_ha; |
| 1288 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1289 | /* |
| 1290 | * Move to the proper node structure, in order to access the |
| 1291 | * right PCI registers |
| 1292 | */ |
| 1293 | new_mci = get_mci_for_node_id(*socket); |
| 1294 | if (!new_mci) { |
| 1295 | sprintf(msg, "Struct for socket #%u wasn't initialized", |
| 1296 | *socket); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1297 | return -EINVAL; |
| 1298 | } |
| 1299 | mci = new_mci; |
| 1300 | pvt = mci->pvt_info; |
| 1301 | |
| 1302 | /* |
| 1303 | * Step 2) Get memory channel |
| 1304 | */ |
| 1305 | prv = 0; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1306 | if (pvt->info.type == SANDY_BRIDGE) |
| 1307 | pci_ha = pvt->pci_ha0; |
| 1308 | else { |
| 1309 | if (sad_ha) |
| 1310 | pci_ha = pvt->pci_ha1; |
| 1311 | else |
| 1312 | pci_ha = pvt->pci_ha0; |
| 1313 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1314 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1315 | pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1316 | limit = TAD_LIMIT(reg); |
| 1317 | if (limit <= prv) { |
| 1318 | sprintf(msg, "Can't discover the memory channel"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1319 | return -EINVAL; |
| 1320 | } |
| 1321 | if (addr <= limit) |
| 1322 | break; |
| 1323 | prv = limit; |
| 1324 | } |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1325 | if (n_tads == MAX_TAD) { |
| 1326 | sprintf(msg, "Can't discover the memory channel"); |
| 1327 | return -EINVAL; |
| 1328 | } |
| 1329 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1330 | ch_way = TAD_CH(reg) + 1; |
| 1331 | sck_way = TAD_SOCK(reg) + 1; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1332 | |
| 1333 | if (ch_way == 3) |
| 1334 | idx = addr >> 6; |
| 1335 | else |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1336 | idx = (addr >> (6 + sck_way + shiftup)) & 0x3; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1337 | idx = idx % ch_way; |
| 1338 | |
| 1339 | /* |
| 1340 | * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? |
| 1341 | */ |
| 1342 | switch (idx) { |
| 1343 | case 0: |
| 1344 | base_ch = TAD_TGT0(reg); |
| 1345 | break; |
| 1346 | case 1: |
| 1347 | base_ch = TAD_TGT1(reg); |
| 1348 | break; |
| 1349 | case 2: |
| 1350 | base_ch = TAD_TGT2(reg); |
| 1351 | break; |
| 1352 | case 3: |
| 1353 | base_ch = TAD_TGT3(reg); |
| 1354 | break; |
| 1355 | default: |
| 1356 | sprintf(msg, "Can't discover the TAD target"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1357 | return -EINVAL; |
| 1358 | } |
| 1359 | *channel_mask = 1 << base_ch; |
| 1360 | |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1361 | pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1362 | tad_ch_nilv_offset[n_tads], |
| 1363 | &tad_offset); |
| 1364 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1365 | if (pvt->is_mirrored) { |
| 1366 | *channel_mask |= 1 << ((base_ch + 2) % 4); |
| 1367 | switch(ch_way) { |
| 1368 | case 2: |
| 1369 | case 4: |
| 1370 | sck_xch = 1 << sck_way * (ch_way >> 1); |
| 1371 | break; |
| 1372 | default: |
| 1373 | sprintf(msg, "Invalid mirror set. Can't decode addr"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1374 | return -EINVAL; |
| 1375 | } |
| 1376 | } else |
| 1377 | sck_xch = (1 << sck_way) * ch_way; |
| 1378 | |
| 1379 | if (pvt->is_lockstep) |
| 1380 | *channel_mask |= 1 << ((base_ch + 1) % 4); |
| 1381 | |
| 1382 | offset = TAD_OFFSET(tad_offset); |
| 1383 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1384 | edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", |
| 1385 | n_tads, |
| 1386 | addr, |
| 1387 | limit, |
| 1388 | (u32)TAD_SOCK(reg), |
| 1389 | ch_way, |
| 1390 | offset, |
| 1391 | idx, |
| 1392 | base_ch, |
| 1393 | *channel_mask); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1394 | |
| 1395 | /* Calculate channel address */ |
| 1396 | /* Remove the TAD offset */ |
| 1397 | |
| 1398 | if (offset > addr) { |
| 1399 | sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", |
| 1400 | offset, addr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1401 | return -EINVAL; |
| 1402 | } |
| 1403 | addr -= offset; |
| 1404 | /* Store the low bits [0:6] of the addr */ |
| 1405 | ch_addr = addr & 0x7f; |
| 1406 | /* Remove socket wayness and remove 6 bits */ |
| 1407 | addr >>= 6; |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 1408 | addr = div_u64(addr, sck_xch); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1409 | #if 0 |
| 1410 | /* Divide by channel way */ |
| 1411 | addr = addr / ch_way; |
| 1412 | #endif |
| 1413 | /* Recover the last 6 bits */ |
| 1414 | ch_addr |= addr << 6; |
| 1415 | |
| 1416 | /* |
| 1417 | * Step 3) Decode rank |
| 1418 | */ |
| 1419 | for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1420 | pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1421 | rir_way_limit[n_rir], |
| 1422 | ®); |
| 1423 | |
| 1424 | if (!IS_RIR_VALID(reg)) |
| 1425 | continue; |
| 1426 | |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 1427 | limit = pvt->info.rir_limit(reg); |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1428 | gb = div_u64_rem(limit >> 20, 1024, &mb); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1429 | edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", |
| 1430 | n_rir, |
Jim Snow | 8c00910 | 2014-11-18 14:51:09 +0100 | [diff] [blame] | 1431 | gb, (mb*1000)/1024, |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1432 | limit, |
| 1433 | 1 << RIR_WAY(reg)); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1434 | if (ch_addr <= limit) |
| 1435 | break; |
| 1436 | } |
| 1437 | if (n_rir == MAX_RIR_RANGES) { |
| 1438 | sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", |
| 1439 | ch_addr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1440 | return -EINVAL; |
| 1441 | } |
| 1442 | rir_way = RIR_WAY(reg); |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1443 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1444 | if (pvt->is_close_pg) |
| 1445 | idx = (ch_addr >> 6); |
| 1446 | else |
| 1447 | idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ |
| 1448 | idx %= 1 << rir_way; |
| 1449 | |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1450 | pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1451 | rir_offset[n_rir][idx], |
| 1452 | ®); |
| 1453 | *rank = RIR_RNK_TGT(reg); |
| 1454 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1455 | edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", |
| 1456 | n_rir, |
| 1457 | ch_addr, |
| 1458 | limit, |
| 1459 | rir_way, |
| 1460 | idx); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1461 | |
| 1462 | return 0; |
| 1463 | } |
| 1464 | |
| 1465 | /**************************************************************************** |
| 1466 | Device initialization routines: put/get, init/exit |
| 1467 | ****************************************************************************/ |
| 1468 | |
| 1469 | /* |
| 1470 | * sbridge_put_all_devices 'put' all the devices that we have |
| 1471 | * reserved via 'get' |
| 1472 | */ |
| 1473 | static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) |
| 1474 | { |
| 1475 | int i; |
| 1476 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1477 | edac_dbg(0, "\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1478 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
| 1479 | struct pci_dev *pdev = sbridge_dev->pdev[i]; |
| 1480 | if (!pdev) |
| 1481 | continue; |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1482 | edac_dbg(0, "Removing dev %02x:%02x.%d\n", |
| 1483 | pdev->bus->number, |
| 1484 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1485 | pci_dev_put(pdev); |
| 1486 | } |
| 1487 | } |
| 1488 | |
| 1489 | static void sbridge_put_all_devices(void) |
| 1490 | { |
| 1491 | struct sbridge_dev *sbridge_dev, *tmp; |
| 1492 | |
| 1493 | list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { |
| 1494 | sbridge_put_devices(sbridge_dev); |
| 1495 | free_sbridge_dev(sbridge_dev); |
| 1496 | } |
| 1497 | } |
| 1498 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1499 | static int sbridge_get_onedevice(struct pci_dev **prev, |
| 1500 | u8 *num_mc, |
| 1501 | const struct pci_id_table *table, |
| 1502 | const unsigned devno) |
| 1503 | { |
| 1504 | struct sbridge_dev *sbridge_dev; |
| 1505 | const struct pci_id_descr *dev_descr = &table->descr[devno]; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1506 | struct pci_dev *pdev = NULL; |
| 1507 | u8 bus = 0; |
| 1508 | |
Jiang Liu | ec5a0b3 | 2014-02-17 13:10:23 +0800 | [diff] [blame] | 1509 | sbridge_printk(KERN_DEBUG, |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1510 | "Seeking for: PCI ID %04x:%04x\n", |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1511 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1512 | |
| 1513 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 1514 | dev_descr->dev_id, *prev); |
| 1515 | |
| 1516 | if (!pdev) { |
| 1517 | if (*prev) { |
| 1518 | *prev = pdev; |
| 1519 | return 0; |
| 1520 | } |
| 1521 | |
| 1522 | if (dev_descr->optional) |
| 1523 | return 0; |
| 1524 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1525 | /* if the HA wasn't found */ |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1526 | if (devno == 0) |
| 1527 | return -ENODEV; |
| 1528 | |
| 1529 | sbridge_printk(KERN_INFO, |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1530 | "Device not found: %04x:%04x\n", |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1531 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1532 | |
| 1533 | /* End of list, leave */ |
| 1534 | return -ENODEV; |
| 1535 | } |
| 1536 | bus = pdev->bus->number; |
| 1537 | |
| 1538 | sbridge_dev = get_sbridge_dev(bus); |
| 1539 | if (!sbridge_dev) { |
| 1540 | sbridge_dev = alloc_sbridge_dev(bus, table); |
| 1541 | if (!sbridge_dev) { |
| 1542 | pci_dev_put(pdev); |
| 1543 | return -ENOMEM; |
| 1544 | } |
| 1545 | (*num_mc)++; |
| 1546 | } |
| 1547 | |
| 1548 | if (sbridge_dev->pdev[devno]) { |
| 1549 | sbridge_printk(KERN_ERR, |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1550 | "Duplicated device for %04x:%04x\n", |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1551 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1552 | pci_dev_put(pdev); |
| 1553 | return -ENODEV; |
| 1554 | } |
| 1555 | |
| 1556 | sbridge_dev->pdev[devno] = pdev; |
| 1557 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1558 | /* Be sure that the device is enabled */ |
| 1559 | if (unlikely(pci_enable_device(pdev) < 0)) { |
| 1560 | sbridge_printk(KERN_ERR, |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1561 | "Couldn't enable %04x:%04x\n", |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1562 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1563 | return -ENODEV; |
| 1564 | } |
| 1565 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1566 | edac_dbg(0, "Detected %04x:%04x\n", |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1567 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1568 | |
| 1569 | /* |
| 1570 | * As stated on drivers/pci/search.c, the reference count for |
| 1571 | * @from is always decremented if it is not %NULL. So, as we need |
| 1572 | * to get all devices up to null, we need to do a get for the device |
| 1573 | */ |
| 1574 | pci_dev_get(pdev); |
| 1575 | |
| 1576 | *prev = pdev; |
| 1577 | |
| 1578 | return 0; |
| 1579 | } |
| 1580 | |
Aristeu Rozanski | 5153a0f | 2013-10-30 13:27:03 -0300 | [diff] [blame] | 1581 | /* |
| 1582 | * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1583 | * devices we want to reference for this driver. |
Aristeu Rozanski | 5153a0f | 2013-10-30 13:27:03 -0300 | [diff] [blame] | 1584 | * @num_mc: pointer to the memory controllers count, to be incremented in case |
Mauro Carvalho Chehab | c41afdc | 2014-06-26 15:35:14 -0300 | [diff] [blame] | 1585 | * of success. |
Aristeu Rozanski | 5153a0f | 2013-10-30 13:27:03 -0300 | [diff] [blame] | 1586 | * @table: model specific table |
| 1587 | * |
| 1588 | * returns 0 in case of success or error code |
| 1589 | */ |
| 1590 | static int sbridge_get_all_devices(u8 *num_mc, |
| 1591 | const struct pci_id_table *table) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1592 | { |
| 1593 | int i, rc; |
| 1594 | struct pci_dev *pdev = NULL; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1595 | |
| 1596 | while (table && table->descr) { |
| 1597 | for (i = 0; i < table->n_devs; i++) { |
| 1598 | pdev = NULL; |
| 1599 | do { |
| 1600 | rc = sbridge_get_onedevice(&pdev, num_mc, |
| 1601 | table, i); |
| 1602 | if (rc < 0) { |
| 1603 | if (i == 0) { |
| 1604 | i = table->n_devs; |
| 1605 | break; |
| 1606 | } |
| 1607 | sbridge_put_all_devices(); |
| 1608 | return -ENODEV; |
| 1609 | } |
| 1610 | } while (pdev); |
| 1611 | } |
| 1612 | table++; |
| 1613 | } |
| 1614 | |
| 1615 | return 0; |
| 1616 | } |
| 1617 | |
Aristeu Rozanski | ea779b5 | 2013-10-30 13:27:04 -0300 | [diff] [blame] | 1618 | static int sbridge_mci_bind_devs(struct mem_ctl_info *mci, |
| 1619 | struct sbridge_dev *sbridge_dev) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1620 | { |
| 1621 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 1622 | struct pci_dev *pdev; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1623 | int i; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1624 | |
| 1625 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
| 1626 | pdev = sbridge_dev->pdev[i]; |
| 1627 | if (!pdev) |
| 1628 | continue; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1629 | |
| 1630 | switch (pdev->device) { |
| 1631 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: |
| 1632 | pvt->pci_sad0 = pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1633 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1634 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: |
| 1635 | pvt->pci_sad1 = pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1636 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1637 | case PCI_DEVICE_ID_INTEL_SBRIDGE_BR: |
| 1638 | pvt->pci_br0 = pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1639 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1640 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: |
| 1641 | pvt->pci_ha0 = pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1642 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1643 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: |
| 1644 | pvt->pci_ta = pdev; |
| 1645 | break; |
| 1646 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: |
| 1647 | pvt->pci_ras = pdev; |
| 1648 | break; |
| 1649 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: |
| 1650 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: |
| 1651 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: |
| 1652 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: |
| 1653 | { |
| 1654 | int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0; |
| 1655 | pvt->pci_tad[id] = pdev; |
| 1656 | } |
| 1657 | break; |
| 1658 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: |
| 1659 | pvt->pci_ddrio = pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1660 | break; |
| 1661 | default: |
| 1662 | goto error; |
| 1663 | } |
| 1664 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1665 | edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n", |
| 1666 | pdev->vendor, pdev->device, |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1667 | sbridge_dev->bus, |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1668 | pdev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1669 | } |
| 1670 | |
| 1671 | /* Check if everything were registered */ |
| 1672 | if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 || |
Luck, Tony | de4772c | 2013-03-28 09:59:15 -0700 | [diff] [blame] | 1673 | !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1674 | goto enodev; |
| 1675 | |
| 1676 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 1677 | if (!pvt->pci_tad[i]) |
| 1678 | goto enodev; |
| 1679 | } |
| 1680 | return 0; |
| 1681 | |
| 1682 | enodev: |
| 1683 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); |
| 1684 | return -ENODEV; |
| 1685 | |
| 1686 | error: |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1687 | sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n", |
| 1688 | PCI_VENDOR_ID_INTEL, pdev->device); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1689 | return -EINVAL; |
| 1690 | } |
| 1691 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1692 | static int ibridge_mci_bind_devs(struct mem_ctl_info *mci, |
| 1693 | struct sbridge_dev *sbridge_dev) |
| 1694 | { |
| 1695 | struct sbridge_pvt *pvt = mci->pvt_info; |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1696 | struct pci_dev *pdev; |
| 1697 | u8 saw_chan_mask = 0; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1698 | int i; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1699 | |
| 1700 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
| 1701 | pdev = sbridge_dev->pdev[i]; |
| 1702 | if (!pdev) |
| 1703 | continue; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1704 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1705 | switch (pdev->device) { |
| 1706 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0: |
| 1707 | pvt->pci_ha0 = pdev; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1708 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1709 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: |
| 1710 | pvt->pci_ta = pdev; |
| 1711 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS: |
| 1712 | pvt->pci_ras = pdev; |
| 1713 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1714 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0: |
| 1715 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1: |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1716 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2: |
| 1717 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3: |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1718 | { |
| 1719 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0; |
| 1720 | pvt->pci_tad[id] = pdev; |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1721 | saw_chan_mask |= 1 << id; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1722 | } |
| 1723 | break; |
| 1724 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0: |
| 1725 | pvt->pci_ddrio = pdev; |
| 1726 | break; |
| 1727 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0: |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1728 | pvt->pci_ddrio = pdev; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1729 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1730 | case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD: |
| 1731 | pvt->pci_sad0 = pdev; |
| 1732 | break; |
| 1733 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0: |
| 1734 | pvt->pci_br0 = pdev; |
| 1735 | break; |
| 1736 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1: |
| 1737 | pvt->pci_br1 = pdev; |
| 1738 | break; |
| 1739 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1: |
| 1740 | pvt->pci_ha1 = pdev; |
| 1741 | break; |
| 1742 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0: |
| 1743 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1: |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1744 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2: |
| 1745 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3: |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1746 | { |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1747 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1748 | pvt->pci_tad[id] = pdev; |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1749 | saw_chan_mask |= 1 << id; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1750 | } |
| 1751 | break; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1752 | default: |
| 1753 | goto error; |
| 1754 | } |
| 1755 | |
| 1756 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", |
| 1757 | sbridge_dev->bus, |
| 1758 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
| 1759 | pdev); |
| 1760 | } |
| 1761 | |
| 1762 | /* Check if everything were registered */ |
| 1763 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 || |
| 1764 | !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras || |
| 1765 | !pvt->pci_ta) |
| 1766 | goto enodev; |
| 1767 | |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1768 | if (saw_chan_mask != 0x0f && /* -EN */ |
| 1769 | saw_chan_mask != 0x33 && /* -EP */ |
| 1770 | saw_chan_mask != 0xff) /* -EX */ |
| 1771 | goto enodev; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1772 | return 0; |
| 1773 | |
| 1774 | enodev: |
| 1775 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); |
| 1776 | return -ENODEV; |
| 1777 | |
| 1778 | error: |
| 1779 | sbridge_printk(KERN_ERR, |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1780 | "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL, |
| 1781 | pdev->device); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1782 | return -EINVAL; |
| 1783 | } |
| 1784 | |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1785 | static int haswell_mci_bind_devs(struct mem_ctl_info *mci, |
| 1786 | struct sbridge_dev *sbridge_dev) |
| 1787 | { |
| 1788 | struct sbridge_pvt *pvt = mci->pvt_info; |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1789 | struct pci_dev *pdev; |
| 1790 | u8 saw_chan_mask = 0; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1791 | int i; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1792 | |
| 1793 | /* there's only one device per system; not tied to any bus */ |
| 1794 | if (pvt->info.pci_vtd == NULL) |
| 1795 | /* result will be checked later */ |
| 1796 | pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 1797 | PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC, |
| 1798 | NULL); |
| 1799 | |
| 1800 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
| 1801 | pdev = sbridge_dev->pdev[i]; |
| 1802 | if (!pdev) |
| 1803 | continue; |
| 1804 | |
| 1805 | switch (pdev->device) { |
| 1806 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0: |
| 1807 | pvt->pci_sad0 = pdev; |
| 1808 | break; |
| 1809 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1: |
| 1810 | pvt->pci_sad1 = pdev; |
| 1811 | break; |
| 1812 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: |
| 1813 | pvt->pci_ha0 = pdev; |
| 1814 | break; |
| 1815 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA: |
| 1816 | pvt->pci_ta = pdev; |
| 1817 | break; |
| 1818 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL: |
| 1819 | pvt->pci_ras = pdev; |
| 1820 | break; |
| 1821 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0: |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1822 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1: |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1823 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2: |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1824 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3: |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1825 | { |
| 1826 | int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0; |
| 1827 | |
| 1828 | pvt->pci_tad[id] = pdev; |
| 1829 | saw_chan_mask |= 1 << id; |
| 1830 | } |
| 1831 | break; |
| 1832 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0: |
| 1833 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1: |
| 1834 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2: |
| 1835 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3: |
| 1836 | { |
| 1837 | int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4; |
| 1838 | |
| 1839 | pvt->pci_tad[id] = pdev; |
| 1840 | saw_chan_mask |= 1 << id; |
| 1841 | } |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1842 | break; |
| 1843 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0: |
| 1844 | pvt->pci_ddrio = pdev; |
| 1845 | break; |
| 1846 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1: |
| 1847 | pvt->pci_ha1 = pdev; |
| 1848 | break; |
| 1849 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA: |
| 1850 | pvt->pci_ha1_ta = pdev; |
| 1851 | break; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1852 | default: |
| 1853 | break; |
| 1854 | } |
| 1855 | |
| 1856 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", |
| 1857 | sbridge_dev->bus, |
| 1858 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
| 1859 | pdev); |
| 1860 | } |
| 1861 | |
| 1862 | /* Check if everything were registered */ |
| 1863 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 || |
| 1864 | !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) |
| 1865 | goto enodev; |
| 1866 | |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1867 | if (saw_chan_mask != 0x0f && /* -EN */ |
| 1868 | saw_chan_mask != 0x33 && /* -EP */ |
| 1869 | saw_chan_mask != 0xff) /* -EX */ |
| 1870 | goto enodev; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 1871 | return 0; |
| 1872 | |
| 1873 | enodev: |
| 1874 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); |
| 1875 | return -ENODEV; |
| 1876 | } |
| 1877 | |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 1878 | static int broadwell_mci_bind_devs(struct mem_ctl_info *mci, |
| 1879 | struct sbridge_dev *sbridge_dev) |
| 1880 | { |
| 1881 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 1882 | struct pci_dev *pdev; |
| 1883 | int i; |
| 1884 | |
| 1885 | /* there's only one device per system; not tied to any bus */ |
| 1886 | if (pvt->info.pci_vtd == NULL) |
| 1887 | /* result will be checked later */ |
| 1888 | pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 1889 | PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC, |
| 1890 | NULL); |
| 1891 | |
| 1892 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
| 1893 | pdev = sbridge_dev->pdev[i]; |
| 1894 | if (!pdev) |
| 1895 | continue; |
| 1896 | |
| 1897 | switch (pdev->device) { |
| 1898 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0: |
| 1899 | pvt->pci_sad0 = pdev; |
| 1900 | break; |
| 1901 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1: |
| 1902 | pvt->pci_sad1 = pdev; |
| 1903 | break; |
| 1904 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0: |
| 1905 | pvt->pci_ha0 = pdev; |
| 1906 | break; |
| 1907 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA: |
| 1908 | pvt->pci_ta = pdev; |
| 1909 | break; |
| 1910 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL: |
| 1911 | pvt->pci_ras = pdev; |
| 1912 | break; |
| 1913 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0: |
| 1914 | pvt->pci_tad[0] = pdev; |
| 1915 | break; |
| 1916 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1: |
| 1917 | pvt->pci_tad[1] = pdev; |
| 1918 | break; |
| 1919 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2: |
| 1920 | pvt->pci_tad[2] = pdev; |
| 1921 | break; |
| 1922 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3: |
| 1923 | pvt->pci_tad[3] = pdev; |
| 1924 | break; |
| 1925 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0: |
| 1926 | pvt->pci_ddrio = pdev; |
| 1927 | break; |
| 1928 | default: |
| 1929 | break; |
| 1930 | } |
| 1931 | |
| 1932 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", |
| 1933 | sbridge_dev->bus, |
| 1934 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
| 1935 | pdev); |
| 1936 | } |
| 1937 | |
| 1938 | /* Check if everything were registered */ |
| 1939 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 || |
| 1940 | !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) |
| 1941 | goto enodev; |
| 1942 | |
| 1943 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 1944 | if (!pvt->pci_tad[i]) |
| 1945 | goto enodev; |
| 1946 | } |
| 1947 | return 0; |
| 1948 | |
| 1949 | enodev: |
| 1950 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); |
| 1951 | return -ENODEV; |
| 1952 | } |
| 1953 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1954 | /**************************************************************************** |
| 1955 | Error check routines |
| 1956 | ****************************************************************************/ |
| 1957 | |
| 1958 | /* |
| 1959 | * While Sandy Bridge has error count registers, SMI BIOS read values from |
| 1960 | * and resets the counters. So, they are not reliable for the OS to read |
| 1961 | * from them. So, we have no option but to just trust on whatever MCE is |
| 1962 | * telling us about the errors. |
| 1963 | */ |
| 1964 | static void sbridge_mce_output_error(struct mem_ctl_info *mci, |
| 1965 | const struct mce *m) |
| 1966 | { |
| 1967 | struct mem_ctl_info *new_mci; |
| 1968 | struct sbridge_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1969 | enum hw_event_mc_err_type tp_event; |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 1970 | char *type, *optype, msg[256]; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1971 | bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); |
| 1972 | bool overflow = GET_BITFIELD(m->status, 62, 62); |
| 1973 | bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1974 | bool recoverable; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1975 | u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); |
| 1976 | u32 mscod = GET_BITFIELD(m->status, 16, 31); |
| 1977 | u32 errcode = GET_BITFIELD(m->status, 0, 15); |
| 1978 | u32 channel = GET_BITFIELD(m->status, 0, 3); |
| 1979 | u32 optypenum = GET_BITFIELD(m->status, 4, 6); |
| 1980 | long channel_mask, first_channel; |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 1981 | u8 rank, socket, ha; |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1982 | int rc, dimm; |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 1983 | char *area_type = NULL; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1984 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1985 | if (pvt->info.type == IVY_BRIDGE) |
| 1986 | recoverable = true; |
| 1987 | else |
| 1988 | recoverable = GET_BITFIELD(m->status, 56, 56); |
| 1989 | |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1990 | if (uncorrected_error) { |
| 1991 | if (ripv) { |
| 1992 | type = "FATAL"; |
| 1993 | tp_event = HW_EVENT_ERR_FATAL; |
| 1994 | } else { |
| 1995 | type = "NON_FATAL"; |
| 1996 | tp_event = HW_EVENT_ERR_UNCORRECTED; |
| 1997 | } |
| 1998 | } else { |
| 1999 | type = "CORRECTED"; |
| 2000 | tp_event = HW_EVENT_ERR_CORRECTED; |
| 2001 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2002 | |
| 2003 | /* |
David Mackey | 15ed103 | 2012-04-17 11:30:52 -0700 | [diff] [blame] | 2004 | * According with Table 15-9 of the Intel Architecture spec vol 3A, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2005 | * memory errors should fit in this mask: |
| 2006 | * 000f 0000 1mmm cccc (binary) |
| 2007 | * where: |
| 2008 | * f = Correction Report Filtering Bit. If 1, subsequent errors |
| 2009 | * won't be shown |
| 2010 | * mmm = error type |
| 2011 | * cccc = channel |
| 2012 | * If the mask doesn't match, report an error to the parsing logic |
| 2013 | */ |
| 2014 | if (! ((errcode & 0xef80) == 0x80)) { |
| 2015 | optype = "Can't parse: it is not a mem"; |
| 2016 | } else { |
| 2017 | switch (optypenum) { |
| 2018 | case 0: |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2019 | optype = "generic undef request error"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2020 | break; |
| 2021 | case 1: |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2022 | optype = "memory read error"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2023 | break; |
| 2024 | case 2: |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2025 | optype = "memory write error"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2026 | break; |
| 2027 | case 3: |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2028 | optype = "addr/cmd error"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2029 | break; |
| 2030 | case 4: |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2031 | optype = "memory scrubbing error"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2032 | break; |
| 2033 | default: |
| 2034 | optype = "reserved"; |
| 2035 | break; |
| 2036 | } |
| 2037 | } |
| 2038 | |
Aristeu Rozanski | be3036d | 2013-10-30 13:27:05 -0300 | [diff] [blame] | 2039 | /* Only decode errors with an valid address (ADDRV) */ |
| 2040 | if (!GET_BITFIELD(m->status, 58, 58)) |
| 2041 | return; |
| 2042 | |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 2043 | rc = get_memory_error_data(mci, m->addr, &socket, &ha, |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 2044 | &channel_mask, &rank, &area_type, msg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2045 | if (rc < 0) |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2046 | goto err_parsing; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2047 | new_mci = get_mci_for_node_id(socket); |
| 2048 | if (!new_mci) { |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2049 | strcpy(msg, "Error: socket got corrupted!"); |
| 2050 | goto err_parsing; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2051 | } |
| 2052 | mci = new_mci; |
| 2053 | pvt = mci->pvt_info; |
| 2054 | |
| 2055 | first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); |
| 2056 | |
| 2057 | if (rank < 4) |
| 2058 | dimm = 0; |
| 2059 | else if (rank < 8) |
| 2060 | dimm = 1; |
| 2061 | else |
| 2062 | dimm = 2; |
| 2063 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2064 | |
| 2065 | /* |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 2066 | * FIXME: On some memory configurations (mirror, lockstep), the |
| 2067 | * Memory Controller can't point the error to a single DIMM. The |
| 2068 | * EDAC core should be handling the channel mask, in order to point |
| 2069 | * to the group of dimm's where the error may be happening. |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2070 | */ |
Aristeu Rozanski | d7c660b | 2014-06-02 15:15:28 -0300 | [diff] [blame] | 2071 | if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg) |
| 2072 | channel = first_channel; |
| 2073 | |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2074 | snprintf(msg, sizeof(msg), |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 2075 | "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d", |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 2076 | overflow ? " OVERFLOW" : "", |
| 2077 | (uncorrected_error && recoverable) ? " recoverable" : "", |
| 2078 | area_type, |
| 2079 | mscod, errcode, |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 2080 | socket, ha, |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 2081 | channel_mask, |
| 2082 | rank); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2083 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2084 | edac_dbg(0, "%s\n", msg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2085 | |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2086 | /* FIXME: need support for channel mask */ |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2087 | |
Seth Jennings | 351fc4a | 2014-09-05 14:28:47 -0500 | [diff] [blame] | 2088 | if (channel == CHANNEL_UNSPECIFIED) |
| 2089 | channel = -1; |
| 2090 | |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2091 | /* Call the helper to output message */ |
Mauro Carvalho Chehab | c105383 | 2012-06-04 13:40:05 -0300 | [diff] [blame] | 2092 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2093 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, |
Tony Luck | 7d375bf | 2015-05-18 17:50:42 -0300 | [diff] [blame^] | 2094 | 4*ha+channel, dimm, -1, |
Mauro Carvalho Chehab | 03f7eae | 2012-06-04 11:29:25 -0300 | [diff] [blame] | 2095 | optype, msg); |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2096 | return; |
| 2097 | err_parsing: |
Mauro Carvalho Chehab | c105383 | 2012-06-04 13:40:05 -0300 | [diff] [blame] | 2098 | edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2099 | -1, -1, -1, |
Mauro Carvalho Chehab | 03f7eae | 2012-06-04 11:29:25 -0300 | [diff] [blame] | 2100 | msg, ""); |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2101 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2102 | } |
| 2103 | |
| 2104 | /* |
| 2105 | * sbridge_check_error Retrieve and process errors reported by the |
| 2106 | * hardware. Called by the Core module. |
| 2107 | */ |
| 2108 | static void sbridge_check_error(struct mem_ctl_info *mci) |
| 2109 | { |
| 2110 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 2111 | int i; |
| 2112 | unsigned count = 0; |
| 2113 | struct mce *m; |
| 2114 | |
| 2115 | /* |
| 2116 | * MCE first step: Copy all mce errors into a temporary buffer |
| 2117 | * We use a double buffering here, to reduce the risk of |
| 2118 | * loosing an error. |
| 2119 | */ |
| 2120 | smp_rmb(); |
| 2121 | count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) |
| 2122 | % MCE_LOG_LEN; |
| 2123 | if (!count) |
| 2124 | return; |
| 2125 | |
| 2126 | m = pvt->mce_outentry; |
| 2127 | if (pvt->mce_in + count > MCE_LOG_LEN) { |
| 2128 | unsigned l = MCE_LOG_LEN - pvt->mce_in; |
| 2129 | |
| 2130 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); |
| 2131 | smp_wmb(); |
| 2132 | pvt->mce_in = 0; |
| 2133 | count -= l; |
| 2134 | m += l; |
| 2135 | } |
| 2136 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); |
| 2137 | smp_wmb(); |
| 2138 | pvt->mce_in += count; |
| 2139 | |
| 2140 | smp_rmb(); |
| 2141 | if (pvt->mce_overrun) { |
| 2142 | sbridge_printk(KERN_ERR, "Lost %d memory errors\n", |
| 2143 | pvt->mce_overrun); |
| 2144 | smp_wmb(); |
| 2145 | pvt->mce_overrun = 0; |
| 2146 | } |
| 2147 | |
| 2148 | /* |
| 2149 | * MCE second step: parse errors and display |
| 2150 | */ |
| 2151 | for (i = 0; i < count; i++) |
| 2152 | sbridge_mce_output_error(mci, &pvt->mce_outentry[i]); |
| 2153 | } |
| 2154 | |
| 2155 | /* |
| 2156 | * sbridge_mce_check_error Replicates mcelog routine to get errors |
| 2157 | * This routine simply queues mcelog errors, and |
| 2158 | * return. The error itself should be handled later |
| 2159 | * by sbridge_check_error. |
| 2160 | * WARNING: As this routine should be called at NMI time, extra care should |
| 2161 | * be taken to avoid deadlocks, and to be as fast as possible. |
| 2162 | */ |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 2163 | static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, |
| 2164 | void *data) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2165 | { |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 2166 | struct mce *mce = (struct mce *)data; |
| 2167 | struct mem_ctl_info *mci; |
| 2168 | struct sbridge_pvt *pvt; |
Aristeu Rozanski | cf40f80 | 2014-03-11 15:45:41 -0400 | [diff] [blame] | 2169 | char *type; |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 2170 | |
Chen, Gong | fd52103 | 2013-12-06 01:17:09 -0500 | [diff] [blame] | 2171 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
| 2172 | return NOTIFY_DONE; |
| 2173 | |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 2174 | mci = get_mci_for_node_id(mce->socketid); |
| 2175 | if (!mci) |
| 2176 | return NOTIFY_BAD; |
| 2177 | pvt = mci->pvt_info; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2178 | |
| 2179 | /* |
| 2180 | * Just let mcelog handle it if the error is |
| 2181 | * outside the memory controller. A memory error |
| 2182 | * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. |
| 2183 | * bit 12 has an special meaning. |
| 2184 | */ |
| 2185 | if ((mce->status & 0xefff) >> 7 != 1) |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 2186 | return NOTIFY_DONE; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2187 | |
Aristeu Rozanski | cf40f80 | 2014-03-11 15:45:41 -0400 | [diff] [blame] | 2188 | if (mce->mcgstatus & MCG_STATUS_MCIP) |
| 2189 | type = "Exception"; |
| 2190 | else |
| 2191 | type = "Event"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2192 | |
Aristeu Rozanski | 49856dc | 2014-03-11 15:45:42 -0400 | [diff] [blame] | 2193 | sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2194 | |
Aristeu Rozanski | 49856dc | 2014-03-11 15:45:42 -0400 | [diff] [blame] | 2195 | sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx " |
| 2196 | "Bank %d: %016Lx\n", mce->extcpu, type, |
| 2197 | mce->mcgstatus, mce->bank, mce->status); |
| 2198 | sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); |
| 2199 | sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); |
| 2200 | sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2201 | |
Aristeu Rozanski | 49856dc | 2014-03-11 15:45:42 -0400 | [diff] [blame] | 2202 | sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET " |
| 2203 | "%u APIC %x\n", mce->cpuvendor, mce->cpuid, |
| 2204 | mce->time, mce->socketid, mce->apicid); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2205 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2206 | smp_rmb(); |
| 2207 | if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { |
| 2208 | smp_wmb(); |
| 2209 | pvt->mce_overrun++; |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 2210 | return NOTIFY_DONE; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2211 | } |
| 2212 | |
| 2213 | /* Copy memory error at the ringbuffer */ |
| 2214 | memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); |
| 2215 | smp_wmb(); |
| 2216 | pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; |
| 2217 | |
| 2218 | /* Handle fatal errors immediately */ |
| 2219 | if (mce->mcgstatus & 1) |
| 2220 | sbridge_check_error(mci); |
| 2221 | |
| 2222 | /* Advice mcelog that the error were handled */ |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 2223 | return NOTIFY_STOP; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2224 | } |
| 2225 | |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 2226 | static struct notifier_block sbridge_mce_dec = { |
| 2227 | .notifier_call = sbridge_mce_check_error, |
| 2228 | }; |
| 2229 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2230 | /**************************************************************************** |
| 2231 | EDAC register/unregister logic |
| 2232 | ****************************************************************************/ |
| 2233 | |
| 2234 | static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) |
| 2235 | { |
| 2236 | struct mem_ctl_info *mci = sbridge_dev->mci; |
| 2237 | struct sbridge_pvt *pvt; |
| 2238 | |
| 2239 | if (unlikely(!mci || !mci->pvt_info)) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2240 | edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2241 | |
| 2242 | sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); |
| 2243 | return; |
| 2244 | } |
| 2245 | |
| 2246 | pvt = mci->pvt_info; |
| 2247 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2248 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
| 2249 | mci, &sbridge_dev->pdev[0]->dev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2250 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2251 | /* Remove MC sysfs nodes */ |
Mauro Carvalho Chehab | fd68750 | 2012-03-16 07:44:18 -0300 | [diff] [blame] | 2252 | edac_mc_del_mc(mci->pdev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2253 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2254 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2255 | kfree(mci->ctl_name); |
| 2256 | edac_mc_free(mci); |
| 2257 | sbridge_dev->mci = NULL; |
| 2258 | } |
| 2259 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2260 | static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2261 | { |
| 2262 | struct mem_ctl_info *mci; |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2263 | struct edac_mc_layer layers[2]; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2264 | struct sbridge_pvt *pvt; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2265 | struct pci_dev *pdev = sbridge_dev->pdev[0]; |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2266 | int rc; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2267 | |
| 2268 | /* Check the number of active and not disabled channels */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 2269 | rc = check_if_ecc_is_active(sbridge_dev->bus, type); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2270 | if (unlikely(rc < 0)) |
| 2271 | return rc; |
| 2272 | |
| 2273 | /* allocate a new MC control structure */ |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2274 | layers[0].type = EDAC_MC_LAYER_CHANNEL; |
| 2275 | layers[0].size = NUM_CHANNELS; |
| 2276 | layers[0].is_virt_csrow = false; |
| 2277 | layers[1].type = EDAC_MC_LAYER_SLOT; |
| 2278 | layers[1].size = MAX_DIMMS; |
| 2279 | layers[1].is_virt_csrow = true; |
Mauro Carvalho Chehab | ca0907b | 2012-05-02 14:37:00 -0300 | [diff] [blame] | 2280 | mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 2281 | sizeof(*pvt)); |
| 2282 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2283 | if (unlikely(!mci)) |
| 2284 | return -ENOMEM; |
| 2285 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2286 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2287 | mci, &pdev->dev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2288 | |
| 2289 | pvt = mci->pvt_info; |
| 2290 | memset(pvt, 0, sizeof(*pvt)); |
| 2291 | |
| 2292 | /* Associate sbridge_dev and mci for future usage */ |
| 2293 | pvt->sbridge_dev = sbridge_dev; |
| 2294 | sbridge_dev->mci = mci; |
| 2295 | |
| 2296 | mci->mtype_cap = MEM_FLAG_DDR3; |
| 2297 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
| 2298 | mci->edac_cap = EDAC_FLAG_NONE; |
| 2299 | mci->mod_name = "sbridge_edac.c"; |
| 2300 | mci->mod_ver = SBRIDGE_REVISION; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2301 | mci->dev_name = pci_name(pdev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2302 | mci->ctl_page_to_phys = NULL; |
| 2303 | |
| 2304 | /* Set the function pointer to an actual operation function */ |
| 2305 | mci->edac_check = sbridge_check_error; |
| 2306 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2307 | pvt->info.type = type; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 2308 | switch (type) { |
| 2309 | case IVY_BRIDGE: |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2310 | pvt->info.rankcfgr = IB_RANK_CFG_A; |
| 2311 | pvt->info.get_tolm = ibridge_get_tolm; |
| 2312 | pvt->info.get_tohm = ibridge_get_tohm; |
| 2313 | pvt->info.dram_rule = ibridge_dram_rule; |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 2314 | pvt->info.get_memory_type = get_memory_type; |
Aristeu Rozanski | f14d689 | 2014-06-02 15:15:23 -0300 | [diff] [blame] | 2315 | pvt->info.get_node_id = get_node_id; |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 2316 | pvt->info.rir_limit = rir_limit; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2317 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
| 2318 | pvt->info.interleave_list = ibridge_interleave_list; |
| 2319 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); |
| 2320 | pvt->info.interleave_pkg = ibridge_interleave_pkg; |
| 2321 | mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx); |
| 2322 | |
| 2323 | /* Store pci devices at mci for faster access */ |
| 2324 | rc = ibridge_mci_bind_devs(mci, sbridge_dev); |
| 2325 | if (unlikely(rc < 0)) |
| 2326 | goto fail0; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 2327 | break; |
| 2328 | case SANDY_BRIDGE: |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2329 | pvt->info.rankcfgr = SB_RANK_CFG_A; |
| 2330 | pvt->info.get_tolm = sbridge_get_tolm; |
| 2331 | pvt->info.get_tohm = sbridge_get_tohm; |
| 2332 | pvt->info.dram_rule = sbridge_dram_rule; |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 2333 | pvt->info.get_memory_type = get_memory_type; |
Aristeu Rozanski | f14d689 | 2014-06-02 15:15:23 -0300 | [diff] [blame] | 2334 | pvt->info.get_node_id = get_node_id; |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 2335 | pvt->info.rir_limit = rir_limit; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2336 | pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); |
| 2337 | pvt->info.interleave_list = sbridge_interleave_list; |
| 2338 | pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list); |
| 2339 | pvt->info.interleave_pkg = sbridge_interleave_pkg; |
| 2340 | mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx); |
| 2341 | |
| 2342 | /* Store pci devices at mci for faster access */ |
| 2343 | rc = sbridge_mci_bind_devs(mci, sbridge_dev); |
| 2344 | if (unlikely(rc < 0)) |
| 2345 | goto fail0; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 2346 | break; |
| 2347 | case HASWELL: |
| 2348 | /* rankcfgr isn't used */ |
| 2349 | pvt->info.get_tolm = haswell_get_tolm; |
| 2350 | pvt->info.get_tohm = haswell_get_tohm; |
| 2351 | pvt->info.dram_rule = ibridge_dram_rule; |
| 2352 | pvt->info.get_memory_type = haswell_get_memory_type; |
| 2353 | pvt->info.get_node_id = haswell_get_node_id; |
| 2354 | pvt->info.rir_limit = haswell_rir_limit; |
| 2355 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
| 2356 | pvt->info.interleave_list = ibridge_interleave_list; |
| 2357 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); |
| 2358 | pvt->info.interleave_pkg = ibridge_interleave_pkg; |
| 2359 | mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2360 | |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 2361 | /* Store pci devices at mci for faster access */ |
| 2362 | rc = haswell_mci_bind_devs(mci, sbridge_dev); |
| 2363 | if (unlikely(rc < 0)) |
| 2364 | goto fail0; |
| 2365 | break; |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 2366 | case BROADWELL: |
| 2367 | /* rankcfgr isn't used */ |
| 2368 | pvt->info.get_tolm = haswell_get_tolm; |
| 2369 | pvt->info.get_tohm = haswell_get_tohm; |
| 2370 | pvt->info.dram_rule = ibridge_dram_rule; |
| 2371 | pvt->info.get_memory_type = haswell_get_memory_type; |
| 2372 | pvt->info.get_node_id = haswell_get_node_id; |
| 2373 | pvt->info.rir_limit = haswell_rir_limit; |
| 2374 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
| 2375 | pvt->info.interleave_list = ibridge_interleave_list; |
| 2376 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); |
| 2377 | pvt->info.interleave_pkg = ibridge_interleave_pkg; |
| 2378 | mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx); |
| 2379 | |
| 2380 | /* Store pci devices at mci for faster access */ |
| 2381 | rc = broadwell_mci_bind_devs(mci, sbridge_dev); |
| 2382 | if (unlikely(rc < 0)) |
| 2383 | goto fail0; |
| 2384 | break; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 2385 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2386 | |
| 2387 | /* Get dimm basic config and the memory layout */ |
| 2388 | get_dimm_config(mci); |
| 2389 | get_memory_layout(mci); |
| 2390 | |
| 2391 | /* record ptr to the generic device */ |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2392 | mci->pdev = &pdev->dev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2393 | |
| 2394 | /* add this new MC control structure to EDAC's list of MCs */ |
| 2395 | if (unlikely(edac_mc_add_mc(mci))) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2396 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2397 | rc = -EINVAL; |
| 2398 | goto fail0; |
| 2399 | } |
| 2400 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2401 | return 0; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2402 | |
| 2403 | fail0: |
| 2404 | kfree(mci->ctl_name); |
| 2405 | edac_mc_free(mci); |
| 2406 | sbridge_dev->mci = NULL; |
| 2407 | return rc; |
| 2408 | } |
| 2409 | |
| 2410 | /* |
| 2411 | * sbridge_probe Probe for ONE instance of device to see if it is |
| 2412 | * present. |
| 2413 | * return: |
| 2414 | * 0 for FOUND a device |
| 2415 | * < 0 for error code |
| 2416 | */ |
| 2417 | |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 2418 | static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2419 | { |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 2420 | int rc = -ENODEV; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2421 | u8 mc, num_mc = 0; |
| 2422 | struct sbridge_dev *sbridge_dev; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 2423 | enum type type = SANDY_BRIDGE; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2424 | |
| 2425 | /* get the pci devices we want to reserve for our use */ |
| 2426 | mutex_lock(&sbridge_edac_lock); |
| 2427 | |
| 2428 | /* |
| 2429 | * All memory controllers are allocated at the first pass. |
| 2430 | */ |
| 2431 | if (unlikely(probed >= 1)) { |
| 2432 | mutex_unlock(&sbridge_edac_lock); |
| 2433 | return -ENODEV; |
| 2434 | } |
| 2435 | probed++; |
| 2436 | |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 2437 | switch (pdev->device) { |
| 2438 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2439 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table); |
| 2440 | type = IVY_BRIDGE; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 2441 | break; |
Borislav Petkov | 11249e7 | 2015-02-05 12:39:36 +0100 | [diff] [blame] | 2442 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2443 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table); |
| 2444 | type = SANDY_BRIDGE; |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 2445 | break; |
| 2446 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: |
| 2447 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table); |
| 2448 | type = HASWELL; |
| 2449 | break; |
Tony Luck | 1f39581 | 2014-12-02 09:27:30 -0800 | [diff] [blame] | 2450 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0: |
| 2451 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_broadwell_table); |
| 2452 | type = BROADWELL; |
| 2453 | break; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2454 | } |
Borislav Petkov | 11249e7 | 2015-02-05 12:39:36 +0100 | [diff] [blame] | 2455 | if (unlikely(rc < 0)) { |
| 2456 | edac_dbg(0, "couldn't get all devices for 0x%x\n", pdev->device); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2457 | goto fail0; |
Borislav Petkov | 11249e7 | 2015-02-05 12:39:36 +0100 | [diff] [blame] | 2458 | } |
| 2459 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2460 | mc = 0; |
| 2461 | |
| 2462 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2463 | edac_dbg(0, "Registering MC#%d (%d of %d)\n", |
| 2464 | mc, mc + 1, num_mc); |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 2465 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2466 | sbridge_dev->mc = mc++; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2467 | rc = sbridge_register_mci(sbridge_dev, type); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2468 | if (unlikely(rc < 0)) |
| 2469 | goto fail1; |
| 2470 | } |
| 2471 | |
Borislav Petkov | 11249e7 | 2015-02-05 12:39:36 +0100 | [diff] [blame] | 2472 | sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2473 | |
| 2474 | mutex_unlock(&sbridge_edac_lock); |
| 2475 | return 0; |
| 2476 | |
| 2477 | fail1: |
| 2478 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) |
| 2479 | sbridge_unregister_mci(sbridge_dev); |
| 2480 | |
| 2481 | sbridge_put_all_devices(); |
| 2482 | fail0: |
| 2483 | mutex_unlock(&sbridge_edac_lock); |
| 2484 | return rc; |
| 2485 | } |
| 2486 | |
| 2487 | /* |
| 2488 | * sbridge_remove destructor for one instance of device |
| 2489 | * |
| 2490 | */ |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 2491 | static void sbridge_remove(struct pci_dev *pdev) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2492 | { |
| 2493 | struct sbridge_dev *sbridge_dev; |
| 2494 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2495 | edac_dbg(0, "\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2496 | |
| 2497 | /* |
| 2498 | * we have a trouble here: pdev value for removal will be wrong, since |
| 2499 | * it will point to the X58 register used to detect that the machine |
| 2500 | * is a Nehalem or upper design. However, due to the way several PCI |
| 2501 | * devices are grouped together to provide MC functionality, we need |
| 2502 | * to use a different method for releasing the devices |
| 2503 | */ |
| 2504 | |
| 2505 | mutex_lock(&sbridge_edac_lock); |
| 2506 | |
| 2507 | if (unlikely(!probed)) { |
| 2508 | mutex_unlock(&sbridge_edac_lock); |
| 2509 | return; |
| 2510 | } |
| 2511 | |
| 2512 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) |
| 2513 | sbridge_unregister_mci(sbridge_dev); |
| 2514 | |
| 2515 | /* Release PCI resources */ |
| 2516 | sbridge_put_all_devices(); |
| 2517 | |
| 2518 | probed--; |
| 2519 | |
| 2520 | mutex_unlock(&sbridge_edac_lock); |
| 2521 | } |
| 2522 | |
| 2523 | MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl); |
| 2524 | |
| 2525 | /* |
| 2526 | * sbridge_driver pci_driver structure for this module |
| 2527 | * |
| 2528 | */ |
| 2529 | static struct pci_driver sbridge_driver = { |
| 2530 | .name = "sbridge_edac", |
| 2531 | .probe = sbridge_probe, |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 2532 | .remove = sbridge_remove, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2533 | .id_table = sbridge_pci_tbl, |
| 2534 | }; |
| 2535 | |
| 2536 | /* |
| 2537 | * sbridge_init Module entry function |
| 2538 | * Try to initialize this module for its devices |
| 2539 | */ |
| 2540 | static int __init sbridge_init(void) |
| 2541 | { |
| 2542 | int pci_rc; |
| 2543 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2544 | edac_dbg(2, "\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2545 | |
| 2546 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
| 2547 | opstate_init(); |
| 2548 | |
| 2549 | pci_rc = pci_register_driver(&sbridge_driver); |
Chen Gong | e35fca4 | 2012-05-08 20:40:12 -0300 | [diff] [blame] | 2550 | if (pci_rc >= 0) { |
| 2551 | mce_register_decode_chain(&sbridge_mce_dec); |
Chen, Gong | fd52103 | 2013-12-06 01:17:09 -0500 | [diff] [blame] | 2552 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
| 2553 | sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2554 | return 0; |
Chen Gong | e35fca4 | 2012-05-08 20:40:12 -0300 | [diff] [blame] | 2555 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2556 | |
| 2557 | sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", |
| 2558 | pci_rc); |
| 2559 | |
| 2560 | return pci_rc; |
| 2561 | } |
| 2562 | |
| 2563 | /* |
| 2564 | * sbridge_exit() Module exit function |
| 2565 | * Unregister the driver |
| 2566 | */ |
| 2567 | static void __exit sbridge_exit(void) |
| 2568 | { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2569 | edac_dbg(2, "\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2570 | pci_unregister_driver(&sbridge_driver); |
Chen Gong | e35fca4 | 2012-05-08 20:40:12 -0300 | [diff] [blame] | 2571 | mce_unregister_decode_chain(&sbridge_mce_dec); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2572 | } |
| 2573 | |
| 2574 | module_init(sbridge_init); |
| 2575 | module_exit(sbridge_exit); |
| 2576 | |
| 2577 | module_param(edac_op_state, int, 0444); |
| 2578 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |
| 2579 | |
| 2580 | MODULE_LICENSE("GPL"); |
Mauro Carvalho Chehab | 37e59f8 | 2014-02-07 08:03:07 -0200 | [diff] [blame] | 2581 | MODULE_AUTHOR("Mauro Carvalho Chehab"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2582 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2583 | MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2584 | SBRIDGE_REVISION); |