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Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001/*
2 * omap iommu: tlb and pagetable primitives
3 *
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -08004 * Copyright (C) 2008-2010 Nokia Corporation
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02005 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090016#include <linux/slab.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020017#include <linux/interrupt.h>
18#include <linux/ioport.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020019#include <linux/platform_device.h>
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030020#include <linux/iommu.h>
Tony Lindgrenc8d35c82012-11-02 12:24:03 -070021#include <linux/omap-iommu.h>
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030022#include <linux/mutex.h>
23#include <linux/spinlock.h>
Tony Lindgrened1c7de2012-11-02 12:24:06 -070024#include <linux/io.h>
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -060025#include <linux/pm_runtime.h>
Florian Vaussard3c927482014-02-28 14:42:36 -060026#include <linux/of.h>
27#include <linux/of_iommu.h>
28#include <linux/of_irq.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020029
30#include <asm/cacheflush.h>
31
Tony Lindgren2ab7c842012-11-02 12:24:14 -070032#include <linux/platform_data/iommu-omap.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020033
Ido Yariv2f7702a2012-11-02 12:24:00 -070034#include "omap-iopgtable.h"
Tony Lindgrened1c7de2012-11-02 12:24:06 -070035#include "omap-iommu.h"
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020036
Suman Anna5acc97d2014-03-17 20:31:34 -050037#define to_iommu(dev) \
38 ((struct omap_iommu *)platform_get_drvdata(to_platform_device(dev)))
39
Hiroshi DOYU37c28362010-04-27 05:37:12 +000040#define for_each_iotlb_cr(obj, n, __i, cr) \
41 for (__i = 0; \
42 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
43 __i++)
44
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +020045/* bitmap of the page sizes currently supported */
46#define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
47
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030048/**
49 * struct omap_iommu_domain - omap iommu domain
50 * @pgtable: the page table
51 * @iommu_dev: an omap iommu device attached to this domain. only a single
52 * iommu device can be attached for now.
Omar Ramirez Luna803b5272012-04-18 13:09:41 -050053 * @dev: Device using this domain.
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030054 * @lock: domain lock, should be taken when attaching/detaching
55 */
56struct omap_iommu_domain {
57 u32 *pgtable;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030058 struct omap_iommu *iommu_dev;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -050059 struct device *dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030060 spinlock_t lock;
61};
62
Ido Yariv7bd9e252012-11-02 12:24:09 -070063#define MMU_LOCK_BASE_SHIFT 10
64#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
65#define MMU_LOCK_BASE(x) \
66 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
67
68#define MMU_LOCK_VICT_SHIFT 4
69#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
70#define MMU_LOCK_VICT(x) \
71 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
72
73struct iotlb_lock {
74 short base;
75 short vict;
76};
77
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020078/* accommodate the difference between omap1 and omap2/3 */
79static const struct iommu_functions *arch_iommu;
80
81static struct platform_driver omap_iommu_driver;
82static struct kmem_cache *iopte_cachep;
83
84/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030085 * omap_install_iommu_arch - Install archtecure specific iommu functions
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020086 * @ops: a pointer to architecture specific iommu functions
87 *
88 * There are several kind of iommu algorithm(tlb, pagetable) among
89 * omap series. This interface installs such an iommu algorighm.
90 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030091int omap_install_iommu_arch(const struct iommu_functions *ops)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020092{
93 if (arch_iommu)
94 return -EBUSY;
95
96 arch_iommu = ops;
97 return 0;
98}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030099EXPORT_SYMBOL_GPL(omap_install_iommu_arch);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200100
101/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300102 * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200103 * @ops: a pointer to architecture specific iommu functions
104 *
105 * This interface uninstalls the iommu algorighm installed previously.
106 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300107void omap_uninstall_iommu_arch(const struct iommu_functions *ops)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200108{
109 if (arch_iommu != ops)
110 pr_err("%s: not your arch\n", __func__);
111
112 arch_iommu = NULL;
113}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300114EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200115
116/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300117 * omap_iommu_save_ctx - Save registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200118 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200119 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200120void omap_iommu_save_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200121{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200122 struct omap_iommu *obj = dev_to_omap_iommu(dev);
123
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200124 arch_iommu->save_ctx(obj);
125}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300126EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200127
128/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300129 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200130 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200131 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200132void omap_iommu_restore_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200133{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200134 struct omap_iommu *obj = dev_to_omap_iommu(dev);
135
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200136 arch_iommu->restore_ctx(obj);
137}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300138EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200139
140/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300141 * omap_iommu_arch_version - Return running iommu arch version
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200142 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300143u32 omap_iommu_arch_version(void)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200144{
145 return arch_iommu->version;
146}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300147EXPORT_SYMBOL_GPL(omap_iommu_arch_version);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200148
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300149static int iommu_enable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200150{
151 int err;
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600152 struct platform_device *pdev = to_platform_device(obj->dev);
153 struct iommu_platform_data *pdata = pdev->dev.platform_data;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200154
Martin Hostettleref4815a2011-02-24 12:51:31 -0800155 if (!arch_iommu)
156 return -ENODEV;
157
Florian Vaussard90e569c2014-02-28 14:42:34 -0600158 if (pdata && pdata->deassert_reset) {
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600159 err = pdata->deassert_reset(pdev, pdata->reset_name);
160 if (err) {
161 dev_err(obj->dev, "deassert_reset failed: %d\n", err);
162 return err;
163 }
164 }
165
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600166 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200167
168 err = arch_iommu->enable(obj);
169
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200170 return err;
171}
172
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300173static void iommu_disable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200174{
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600175 struct platform_device *pdev = to_platform_device(obj->dev);
176 struct iommu_platform_data *pdata = pdev->dev.platform_data;
177
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200178 arch_iommu->disable(obj);
179
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600180 pm_runtime_put_sync(obj->dev);
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600181
Florian Vaussard90e569c2014-02-28 14:42:34 -0600182 if (pdata && pdata->assert_reset)
Omar Ramirez Luna72b15b62012-11-19 19:05:50 -0600183 pdata->assert_reset(pdev, pdata->reset_name);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200184}
185
186/*
187 * TLB operations
188 */
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300189void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200190{
191 BUG_ON(!cr || !e);
192
193 arch_iommu->cr_to_e(cr, e);
194}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300195EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200196
197static inline int iotlb_cr_valid(struct cr_regs *cr)
198{
199 if (!cr)
200 return -EINVAL;
201
202 return arch_iommu->cr_valid(cr);
203}
204
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300205static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200206 struct iotlb_entry *e)
207{
208 if (!e)
209 return NULL;
210
211 return arch_iommu->alloc_cr(obj, e);
212}
213
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300214static u32 iotlb_cr_to_virt(struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200215{
216 return arch_iommu->cr_to_virt(cr);
217}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200218
219static u32 get_iopte_attr(struct iotlb_entry *e)
220{
221 return arch_iommu->get_pte_attr(e);
222}
223
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300224static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200225{
226 return arch_iommu->fault_isr(obj, da);
227}
228
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300229static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200230{
231 u32 val;
232
233 val = iommu_read_reg(obj, MMU_LOCK);
234
235 l->base = MMU_LOCK_BASE(val);
236 l->vict = MMU_LOCK_VICT(val);
237
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200238}
239
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300240static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200241{
242 u32 val;
243
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200244 val = (l->base << MMU_LOCK_BASE_SHIFT);
245 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
246
247 iommu_write_reg(obj, val, MMU_LOCK);
248}
249
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300250static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200251{
252 arch_iommu->tlb_read_cr(obj, cr);
253}
254
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300255static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200256{
257 arch_iommu->tlb_load_cr(obj, cr);
258
259 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
260 iommu_write_reg(obj, 1, MMU_LD_TLB);
261}
262
263/**
264 * iotlb_dump_cr - Dump an iommu tlb entry into buf
265 * @obj: target iommu
266 * @cr: contents of cam and ram register
267 * @buf: output buffer
268 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300269static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200270 char *buf)
271{
272 BUG_ON(!cr || !buf);
273
274 return arch_iommu->dump_cr(obj, cr, buf);
275}
276
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000277/* only used in iotlb iteration for-loop */
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300278static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000279{
280 struct cr_regs cr;
281 struct iotlb_lock l;
282
283 iotlb_lock_get(obj, &l);
284 l.vict = n;
285 iotlb_lock_set(obj, &l);
286 iotlb_read_cr(obj, &cr);
287
288 return cr;
289}
290
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200291/**
292 * load_iotlb_entry - Set an iommu tlb entry
293 * @obj: target iommu
294 * @e: an iommu tlb entry info
295 **/
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300296#ifdef PREFETCH_IOTLB
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300297static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200298{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200299 int err = 0;
300 struct iotlb_lock l;
301 struct cr_regs *cr;
302
303 if (!obj || !obj->nr_tlb_entries || !e)
304 return -EINVAL;
305
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600306 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200307
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000308 iotlb_lock_get(obj, &l);
309 if (l.base == obj->nr_tlb_entries) {
310 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200311 err = -EBUSY;
312 goto out;
313 }
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000314 if (!e->prsvd) {
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000315 int i;
316 struct cr_regs tmp;
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000317
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000318 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000319 if (!iotlb_cr_valid(&tmp))
320 break;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000321
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000322 if (i == obj->nr_tlb_entries) {
323 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
324 err = -EBUSY;
325 goto out;
326 }
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000327
328 iotlb_lock_get(obj, &l);
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000329 } else {
330 l.vict = l.base;
331 iotlb_lock_set(obj, &l);
332 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200333
334 cr = iotlb_alloc_cr(obj, e);
335 if (IS_ERR(cr)) {
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600336 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200337 return PTR_ERR(cr);
338 }
339
340 iotlb_load_cr(obj, cr);
341 kfree(cr);
342
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000343 if (e->prsvd)
344 l.base++;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200345 /* increment victim for next tlb load */
346 if (++l.vict == obj->nr_tlb_entries)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000347 l.vict = l.base;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200348 iotlb_lock_set(obj, &l);
349out:
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600350 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200351 return err;
352}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200353
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300354#else /* !PREFETCH_IOTLB */
355
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300356static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300357{
358 return 0;
359}
360
361#endif /* !PREFETCH_IOTLB */
362
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300363static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300364{
365 return load_iotlb_entry(obj, e);
366}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200367
368/**
369 * flush_iotlb_page - Clear an iommu tlb entry
370 * @obj: target iommu
371 * @da: iommu device virtual address
372 *
373 * Clear an iommu tlb entry which includes 'da' address.
374 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300375static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200376{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200377 int i;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000378 struct cr_regs cr;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200379
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600380 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200381
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000382 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200383 u32 start;
384 size_t bytes;
385
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200386 if (!iotlb_cr_valid(&cr))
387 continue;
388
389 start = iotlb_cr_to_virt(&cr);
390 bytes = iopgsz_to_bytes(cr.cam & 3);
391
392 if ((start <= da) && (da < start + bytes)) {
393 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
394 __func__, start, da, bytes);
Hari Kanigeri0fa035e2010-08-20 13:50:18 +0000395 iotlb_load_cr(obj, &cr);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200396 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
Laurent Pinchartf7129a02014-03-07 23:47:03 +0100397 break;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200398 }
399 }
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600400 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200401
402 if (i == obj->nr_tlb_entries)
403 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
404}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200405
406/**
407 * flush_iotlb_all - Clear all iommu tlb entries
408 * @obj: target iommu
409 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300410static void flush_iotlb_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200411{
412 struct iotlb_lock l;
413
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600414 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200415
416 l.base = 0;
417 l.vict = 0;
418 iotlb_lock_set(obj, &l);
419
420 iommu_write_reg(obj, 1, MMU_GFLUSH);
421
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600422 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200423}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200424
Arnd Bergmanne4efd942011-10-02 14:34:05 -0400425#if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
Kanigeri, Hariddfa9752010-05-24 02:01:51 +0000426
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300427ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200428{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200429 if (!obj || !buf)
430 return -EINVAL;
431
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600432 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200433
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700434 bytes = arch_iommu->dump_ctx(obj, buf, bytes);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200435
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600436 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200437
438 return bytes;
439}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300440EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200441
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300442static int
443__dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200444{
445 int i;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000446 struct iotlb_lock saved;
447 struct cr_regs tmp;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200448 struct cr_regs *p = crs;
449
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600450 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200451 iotlb_lock_get(obj, &saved);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200452
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000453 for_each_iotlb_cr(obj, num, i, tmp) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200454 if (!iotlb_cr_valid(&tmp))
455 continue;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200456 *p++ = tmp;
457 }
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000458
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200459 iotlb_lock_set(obj, &saved);
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600460 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200461
462 return p - crs;
463}
464
465/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300466 * omap_dump_tlb_entries - dump cr arrays to given buffer
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200467 * @obj: target iommu
468 * @buf: output buffer
469 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300470size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200471{
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700472 int i, num;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200473 struct cr_regs *cr;
474 char *p = buf;
475
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700476 num = bytes / sizeof(*cr);
477 num = min(obj->nr_tlb_entries, num);
478
479 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200480 if (!cr)
481 return 0;
482
Hiroshi DOYU14e0e672009-08-28 10:54:41 -0700483 num = __dump_tlb_entries(obj, cr, num);
484 for (i = 0; i < num; i++)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200485 p += iotlb_dump_cr(obj, cr + i, p);
486 kfree(cr);
487
488 return p - buf;
489}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300490EXPORT_SYMBOL_GPL(omap_dump_tlb_entries);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200491
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300492int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200493{
494 return driver_for_each_device(&omap_iommu_driver.driver,
495 NULL, data, fn);
496}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300497EXPORT_SYMBOL_GPL(omap_foreach_iommu_device);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200498
499#endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
500
501/*
502 * H/W pagetable operations
503 */
504static void flush_iopgd_range(u32 *first, u32 *last)
505{
506 /* FIXME: L2 cache should be taken care of if it exists */
507 do {
508 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
509 : : "r" (first));
510 first += L1_CACHE_BYTES / sizeof(*first);
511 } while (first <= last);
512}
513
514static void flush_iopte_range(u32 *first, u32 *last)
515{
516 /* FIXME: L2 cache should be taken care of if it exists */
517 do {
518 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
519 : : "r" (first));
520 first += L1_CACHE_BYTES / sizeof(*first);
521 } while (first <= last);
522}
523
524static void iopte_free(u32 *iopte)
525{
526 /* Note: freed iopte's must be clean ready for re-use */
Zhouyi Zhoue28045a2014-03-05 18:20:19 +0800527 if (iopte)
528 kmem_cache_free(iopte_cachep, iopte);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200529}
530
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300531static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200532{
533 u32 *iopte;
534
535 /* a table has already existed */
536 if (*iopgd)
537 goto pte_ready;
538
539 /*
540 * do the allocation outside the page table lock
541 */
542 spin_unlock(&obj->page_table_lock);
543 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
544 spin_lock(&obj->page_table_lock);
545
546 if (!*iopgd) {
547 if (!iopte)
548 return ERR_PTR(-ENOMEM);
549
550 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
551 flush_iopgd_range(iopgd, iopgd);
552
553 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
554 } else {
555 /* We raced, free the reduniovant table */
556 iopte_free(iopte);
557 }
558
559pte_ready:
560 iopte = iopte_offset(iopgd, da);
561
562 dev_vdbg(obj->dev,
563 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
564 __func__, da, iopgd, *iopgd, iopte, *iopte);
565
566 return iopte;
567}
568
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300569static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200570{
571 u32 *iopgd = iopgd_offset(obj, da);
572
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300573 if ((da | pa) & ~IOSECTION_MASK) {
574 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
575 __func__, da, pa, IOSECTION_SIZE);
576 return -EINVAL;
577 }
578
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200579 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
580 flush_iopgd_range(iopgd, iopgd);
581 return 0;
582}
583
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300584static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200585{
586 u32 *iopgd = iopgd_offset(obj, da);
587 int i;
588
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300589 if ((da | pa) & ~IOSUPER_MASK) {
590 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
591 __func__, da, pa, IOSUPER_SIZE);
592 return -EINVAL;
593 }
594
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200595 for (i = 0; i < 16; i++)
596 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
597 flush_iopgd_range(iopgd, iopgd + 15);
598 return 0;
599}
600
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300601static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200602{
603 u32 *iopgd = iopgd_offset(obj, da);
604 u32 *iopte = iopte_alloc(obj, iopgd, da);
605
606 if (IS_ERR(iopte))
607 return PTR_ERR(iopte);
608
609 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
610 flush_iopte_range(iopte, iopte);
611
612 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
613 __func__, da, pa, iopte, *iopte);
614
615 return 0;
616}
617
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300618static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200619{
620 u32 *iopgd = iopgd_offset(obj, da);
621 u32 *iopte = iopte_alloc(obj, iopgd, da);
622 int i;
623
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300624 if ((da | pa) & ~IOLARGE_MASK) {
625 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
626 __func__, da, pa, IOLARGE_SIZE);
627 return -EINVAL;
628 }
629
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200630 if (IS_ERR(iopte))
631 return PTR_ERR(iopte);
632
633 for (i = 0; i < 16; i++)
634 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
635 flush_iopte_range(iopte, iopte + 15);
636 return 0;
637}
638
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300639static int
640iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200641{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300642 int (*fn)(struct omap_iommu *, u32, u32, u32);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200643 u32 prot;
644 int err;
645
646 if (!obj || !e)
647 return -EINVAL;
648
649 switch (e->pgsz) {
650 case MMU_CAM_PGSZ_16M:
651 fn = iopgd_alloc_super;
652 break;
653 case MMU_CAM_PGSZ_1M:
654 fn = iopgd_alloc_section;
655 break;
656 case MMU_CAM_PGSZ_64K:
657 fn = iopte_alloc_large;
658 break;
659 case MMU_CAM_PGSZ_4K:
660 fn = iopte_alloc_page;
661 break;
662 default:
663 fn = NULL;
664 BUG();
665 break;
666 }
667
668 prot = get_iopte_attr(e);
669
670 spin_lock(&obj->page_table_lock);
671 err = fn(obj, e->da, e->pa, prot);
672 spin_unlock(&obj->page_table_lock);
673
674 return err;
675}
676
677/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300678 * omap_iopgtable_store_entry - Make an iommu pte entry
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200679 * @obj: target iommu
680 * @e: an iommu tlb entry info
681 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300682int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200683{
684 int err;
685
686 flush_iotlb_page(obj, e->da);
687 err = iopgtable_store_entry_core(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200688 if (!err)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300689 prefetch_iotlb_entry(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200690 return err;
691}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300692EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200693
694/**
695 * iopgtable_lookup_entry - Lookup an iommu pte entry
696 * @obj: target iommu
697 * @da: iommu device virtual address
698 * @ppgd: iommu pgd entry pointer to be returned
699 * @ppte: iommu pte entry pointer to be returned
700 **/
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300701static void
702iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200703{
704 u32 *iopgd, *iopte = NULL;
705
706 iopgd = iopgd_offset(obj, da);
707 if (!*iopgd)
708 goto out;
709
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300710 if (iopgd_is_table(*iopgd))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200711 iopte = iopte_offset(iopgd, da);
712out:
713 *ppgd = iopgd;
714 *ppte = iopte;
715}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200716
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300717static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200718{
719 size_t bytes;
720 u32 *iopgd = iopgd_offset(obj, da);
721 int nent = 1;
722
723 if (!*iopgd)
724 return 0;
725
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300726 if (iopgd_is_table(*iopgd)) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200727 int i;
728 u32 *iopte = iopte_offset(iopgd, da);
729
730 bytes = IOPTE_SIZE;
731 if (*iopte & IOPTE_LARGE) {
732 nent *= 16;
733 /* rewind to the 1st entry */
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -0800734 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200735 }
736 bytes *= nent;
737 memset(iopte, 0, nent * sizeof(*iopte));
738 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
739
740 /*
741 * do table walk to check if this table is necessary or not
742 */
743 iopte = iopte_offset(iopgd, 0);
744 for (i = 0; i < PTRS_PER_IOPTE; i++)
745 if (iopte[i])
746 goto out;
747
748 iopte_free(iopte);
749 nent = 1; /* for the next L1 entry */
750 } else {
751 bytes = IOPGD_SIZE;
Hiroshi DOYUdcc730d2009-10-22 14:46:32 -0700752 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200753 nent *= 16;
754 /* rewind to the 1st entry */
Hiroshi DOYU8d33ea52010-02-15 10:03:32 -0800755 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200756 }
757 bytes *= nent;
758 }
759 memset(iopgd, 0, nent * sizeof(*iopgd));
760 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
761out:
762 return bytes;
763}
764
765/**
766 * iopgtable_clear_entry - Remove an iommu pte entry
767 * @obj: target iommu
768 * @da: iommu device virtual address
769 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300770static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200771{
772 size_t bytes;
773
774 spin_lock(&obj->page_table_lock);
775
776 bytes = iopgtable_clear_entry_core(obj, da);
777 flush_iotlb_page(obj, da);
778
779 spin_unlock(&obj->page_table_lock);
780
781 return bytes;
782}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200783
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300784static void iopgtable_clear_entry_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200785{
786 int i;
787
788 spin_lock(&obj->page_table_lock);
789
790 for (i = 0; i < PTRS_PER_IOPGD; i++) {
791 u32 da;
792 u32 *iopgd;
793
794 da = i << IOPGD_SHIFT;
795 iopgd = iopgd_offset(obj, da);
796
797 if (!*iopgd)
798 continue;
799
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300800 if (iopgd_is_table(*iopgd))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200801 iopte_free(iopte_offset(iopgd, 0));
802
803 *iopgd = 0;
804 flush_iopgd_range(iopgd, iopgd);
805 }
806
807 flush_iotlb_all(obj);
808
809 spin_unlock(&obj->page_table_lock);
810}
811
812/*
813 * Device IOMMU generic operations
814 */
815static irqreturn_t iommu_fault_handler(int irq, void *data)
816{
David Cohend594f1f2011-02-16 19:35:51 +0000817 u32 da, errs;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200818 u32 *iopgd, *iopte;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300819 struct omap_iommu *obj = data;
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400820 struct iommu_domain *domain = obj->domain;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200821
822 if (!obj->refcount)
823 return IRQ_NONE;
824
David Cohend594f1f2011-02-16 19:35:51 +0000825 errs = iommu_report_fault(obj, &da);
Laurent Pinchartc56b2dd2011-05-10 16:56:46 +0200826 if (errs == 0)
827 return IRQ_HANDLED;
David Cohend594f1f2011-02-16 19:35:51 +0000828
829 /* Fault callback or TLB/PTE Dynamic loading */
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400830 if (!report_iommu_fault(domain, obj->dev, da, 0))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200831 return IRQ_HANDLED;
832
Hiroshi DOYU37b29812010-05-24 02:01:52 +0000833 iommu_disable(obj);
834
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200835 iopgd = iopgd_offset(obj, da);
836
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300837 if (!iopgd_is_table(*iopgd)) {
Suman Annab6c2e092013-05-30 18:10:59 -0500838 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n",
839 obj->name, errs, da, iopgd, *iopgd);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200840 return IRQ_NONE;
841 }
842
843 iopte = iopte_offset(iopgd, da);
844
Suman Annab6c2e092013-05-30 18:10:59 -0500845 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n",
846 obj->name, errs, da, iopgd, *iopgd, iopte, *iopte);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200847
848 return IRQ_NONE;
849}
850
851static int device_match_by_alias(struct device *dev, void *data)
852{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300853 struct omap_iommu *obj = to_iommu(dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200854 const char *name = data;
855
856 pr_debug("%s: %s %s\n", __func__, obj->name, name);
857
858 return strcmp(obj->name, name) == 0;
859}
860
861/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300862 * omap_iommu_attach() - attach iommu device to an iommu domain
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200863 * @name: name of target omap iommu device
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300864 * @iopgd: page table
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200865 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200866static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200867{
Suman Anna7ee08b9e2014-02-28 14:42:33 -0600868 int err;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200869 struct device *dev;
870 struct omap_iommu *obj;
871
872 dev = driver_find_device(&omap_iommu_driver.driver, NULL,
873 (void *)name,
874 device_match_by_alias);
875 if (!dev)
Suman Anna7ee08b9e2014-02-28 14:42:33 -0600876 return ERR_PTR(-ENODEV);
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200877
878 obj = to_iommu(dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200879
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300880 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200881
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300882 /* an iommu device can only be attached once */
883 if (++obj->refcount > 1) {
884 dev_err(dev, "%s: already attached!\n", obj->name);
885 err = -EBUSY;
886 goto err_enable;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200887 }
888
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300889 obj->iopgd = iopgd;
890 err = iommu_enable(obj);
891 if (err)
892 goto err_enable;
893 flush_iotlb_all(obj);
894
Suman Anna7ee08b9e2014-02-28 14:42:33 -0600895 if (!try_module_get(obj->owner)) {
896 err = -ENODEV;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200897 goto err_module;
Suman Anna7ee08b9e2014-02-28 14:42:33 -0600898 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200899
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300900 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200901
902 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
903 return obj;
904
905err_module:
906 if (obj->refcount == 1)
907 iommu_disable(obj);
908err_enable:
909 obj->refcount--;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300910 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200911 return ERR_PTR(err);
912}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200913
914/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300915 * omap_iommu_detach - release iommu device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200916 * @obj: target iommu
917 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300918static void omap_iommu_detach(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200919{
Roel Kluinacf9d462010-01-08 10:29:05 -0800920 if (!obj || IS_ERR(obj))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200921 return;
922
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300923 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200924
925 if (--obj->refcount == 0)
926 iommu_disable(obj);
927
928 module_put(obj->owner);
929
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300930 obj->iopgd = NULL;
931
932 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200933
934 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
935}
David Cohend594f1f2011-02-16 19:35:51 +0000936
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200937/*
938 * OMAP Device MMU(IOMMU) detection
939 */
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -0800940static int omap_iommu_probe(struct platform_device *pdev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200941{
942 int err = -ENODEV;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200943 int irq;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300944 struct omap_iommu *obj;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200945 struct resource *res;
946 struct iommu_platform_data *pdata = pdev->dev.platform_data;
Florian Vaussard3c927482014-02-28 14:42:36 -0600947 struct device_node *of = pdev->dev.of_node;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200948
Suman Annaf129b3d2014-02-28 14:42:32 -0600949 obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200950 if (!obj)
951 return -ENOMEM;
952
Florian Vaussard3c927482014-02-28 14:42:36 -0600953 if (of) {
954 obj->name = dev_name(&pdev->dev);
955 obj->nr_tlb_entries = 32;
956 err = of_property_read_u32(of, "ti,#tlb-entries",
957 &obj->nr_tlb_entries);
958 if (err && err != -EINVAL)
959 return err;
960 if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8)
961 return -EINVAL;
Suman Annab148d5f2014-02-28 14:42:37 -0600962 if (of_find_property(of, "ti,iommu-bus-err-back", NULL))
963 obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN;
Florian Vaussard3c927482014-02-28 14:42:36 -0600964 } else {
965 obj->nr_tlb_entries = pdata->nr_tlb_entries;
966 obj->name = pdata->name;
Florian Vaussard3c927482014-02-28 14:42:36 -0600967 }
Florian Vaussard3c927482014-02-28 14:42:36 -0600968
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200969 obj->dev = &pdev->dev;
970 obj->ctx = (void *)obj + sizeof(*obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200971
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300972 spin_lock_init(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200973 spin_lock_init(&obj->page_table_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200974
975 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Suman Annaf129b3d2014-02-28 14:42:32 -0600976 obj->regbase = devm_ioremap_resource(obj->dev, res);
977 if (IS_ERR(obj->regbase))
978 return PTR_ERR(obj->regbase);
Aaro Koskinenda4a0f72011-03-14 12:28:32 +0000979
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200980 irq = platform_get_irq(pdev, 0);
Suman Annaf129b3d2014-02-28 14:42:32 -0600981 if (irq < 0)
982 return -ENODEV;
983
984 err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED,
985 dev_name(obj->dev), obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200986 if (err < 0)
Suman Annaf129b3d2014-02-28 14:42:32 -0600987 return err;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200988 platform_set_drvdata(pdev, obj);
989
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600990 pm_runtime_irq_safe(obj->dev);
991 pm_runtime_enable(obj->dev);
992
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200993 dev_info(&pdev->dev, "%s registered\n", obj->name);
994 return 0;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200995}
996
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -0800997static int omap_iommu_remove(struct platform_device *pdev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200998{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300999 struct omap_iommu *obj = platform_get_drvdata(pdev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001000
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001001 iopgtable_clear_entry_all(obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001002
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -06001003 pm_runtime_disable(obj->dev);
1004
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001005 dev_info(&pdev->dev, "%s removed\n", obj->name);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001006 return 0;
1007}
1008
Florian Vaussard3c927482014-02-28 14:42:36 -06001009static struct of_device_id omap_iommu_of_match[] = {
1010 { .compatible = "ti,omap2-iommu" },
1011 { .compatible = "ti,omap4-iommu" },
1012 { .compatible = "ti,dra7-iommu" },
1013 {},
1014};
1015MODULE_DEVICE_TABLE(of, omap_iommu_of_match);
1016
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001017static struct platform_driver omap_iommu_driver = {
1018 .probe = omap_iommu_probe,
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -08001019 .remove = omap_iommu_remove,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001020 .driver = {
1021 .name = "omap-iommu",
Florian Vaussard3c927482014-02-28 14:42:36 -06001022 .of_match_table = of_match_ptr(omap_iommu_of_match),
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001023 },
1024};
1025
1026static void iopte_cachep_ctor(void *iopte)
1027{
1028 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1029}
1030
Laurent Pinchart286f6002014-03-08 00:44:38 +01001031static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz)
Tony Lindgrened1c7de2012-11-02 12:24:06 -07001032{
1033 memset(e, 0, sizeof(*e));
1034
1035 e->da = da;
1036 e->pa = pa;
Suman Annad760e3e2014-03-17 20:31:32 -05001037 e->valid = MMU_CAM_V;
Tony Lindgrened1c7de2012-11-02 12:24:06 -07001038 /* FIXME: add OMAP1 support */
Laurent Pinchart286f6002014-03-08 00:44:38 +01001039 e->pgsz = pgsz;
1040 e->endian = MMU_RAM_ENDIAN_LITTLE;
1041 e->elsz = MMU_RAM_ELSZ_8;
1042 e->mixed = 0;
Tony Lindgrened1c7de2012-11-02 12:24:06 -07001043
1044 return iopgsz_to_bytes(e->pgsz);
1045}
1046
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001047static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001048 phys_addr_t pa, size_t bytes, int prot)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001049{
1050 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001051 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001052 struct device *dev = oiommu->dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001053 struct iotlb_entry e;
1054 int omap_pgsz;
Laurent Pinchart286f6002014-03-08 00:44:38 +01001055 u32 ret;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001056
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001057 omap_pgsz = bytes_to_iopgsz(bytes);
1058 if (omap_pgsz < 0) {
1059 dev_err(dev, "invalid size to map: %d\n", bytes);
1060 return -EINVAL;
1061 }
1062
1063 dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes);
1064
Laurent Pinchart286f6002014-03-08 00:44:38 +01001065 iotlb_init_entry(&e, da, pa, omap_pgsz);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001066
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001067 ret = omap_iopgtable_store_entry(oiommu, &e);
Ohad Ben-Cohenb4550d42011-09-02 13:32:31 -04001068 if (ret)
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001069 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001070
Ohad Ben-Cohenb4550d42011-09-02 13:32:31 -04001071 return ret;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001072}
1073
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001074static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1075 size_t size)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001076{
1077 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001078 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001079 struct device *dev = oiommu->dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001080
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001081 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001082
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001083 return iopgtable_clear_entry(oiommu, da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001084}
1085
1086static int
1087omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1088{
1089 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001090 struct omap_iommu *oiommu;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001091 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001092 int ret = 0;
1093
1094 spin_lock(&omap_domain->lock);
1095
1096 /* only a single device is supported per domain for now */
1097 if (omap_domain->iommu_dev) {
1098 dev_err(dev, "iommu domain is already attached\n");
1099 ret = -EBUSY;
1100 goto out;
1101 }
1102
1103 /* get a handle to and enable the omap iommu */
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001104 oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001105 if (IS_ERR(oiommu)) {
1106 ret = PTR_ERR(oiommu);
1107 dev_err(dev, "can't get omap iommu: %d\n", ret);
1108 goto out;
1109 }
1110
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001111 omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001112 omap_domain->dev = dev;
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -04001113 oiommu->domain = domain;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001114
1115out:
1116 spin_unlock(&omap_domain->lock);
1117 return ret;
1118}
1119
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001120static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
1121 struct device *dev)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001122{
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001123 struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001124 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001125
1126 /* only a single device is supported per domain for now */
1127 if (omap_domain->iommu_dev != oiommu) {
1128 dev_err(dev, "invalid iommu device\n");
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001129 return;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001130 }
1131
1132 iopgtable_clear_entry_all(oiommu);
1133
1134 omap_iommu_detach(oiommu);
1135
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001136 omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001137 omap_domain->dev = NULL;
1138}
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001139
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001140static void omap_iommu_detach_dev(struct iommu_domain *domain,
1141 struct device *dev)
1142{
1143 struct omap_iommu_domain *omap_domain = domain->priv;
1144
1145 spin_lock(&omap_domain->lock);
1146 _omap_iommu_detach_dev(omap_domain, dev);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001147 spin_unlock(&omap_domain->lock);
1148}
1149
1150static int omap_iommu_domain_init(struct iommu_domain *domain)
1151{
1152 struct omap_iommu_domain *omap_domain;
1153
1154 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1155 if (!omap_domain) {
1156 pr_err("kzalloc failed\n");
1157 goto out;
1158 }
1159
1160 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1161 if (!omap_domain->pgtable) {
1162 pr_err("kzalloc failed\n");
1163 goto fail_nomem;
1164 }
1165
1166 /*
1167 * should never fail, but please keep this around to ensure
1168 * we keep the hardware happy
1169 */
1170 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1171
1172 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1173 spin_lock_init(&omap_domain->lock);
1174
1175 domain->priv = omap_domain;
1176
Joerg Roedel2c6edb02012-01-26 19:40:55 +01001177 domain->geometry.aperture_start = 0;
1178 domain->geometry.aperture_end = (1ULL << 32) - 1;
1179 domain->geometry.force_aperture = true;
1180
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001181 return 0;
1182
1183fail_nomem:
1184 kfree(omap_domain);
1185out:
1186 return -ENOMEM;
1187}
1188
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001189static void omap_iommu_domain_destroy(struct iommu_domain *domain)
1190{
1191 struct omap_iommu_domain *omap_domain = domain->priv;
1192
1193 domain->priv = NULL;
1194
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001195 /*
1196 * An iommu device is still attached
1197 * (currently, only one device can be attached) ?
1198 */
1199 if (omap_domain->iommu_dev)
1200 _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1201
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001202 kfree(omap_domain->pgtable);
1203 kfree(omap_domain);
1204}
1205
1206static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
Varun Sethibb5547ac2013-03-29 01:23:58 +05301207 dma_addr_t da)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001208{
1209 struct omap_iommu_domain *omap_domain = domain->priv;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001210 struct omap_iommu *oiommu = omap_domain->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001211 struct device *dev = oiommu->dev;
1212 u32 *pgd, *pte;
1213 phys_addr_t ret = 0;
1214
1215 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1216
1217 if (pte) {
1218 if (iopte_is_small(*pte))
1219 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1220 else if (iopte_is_large(*pte))
1221 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1222 else
Suman Anna2abfcfb2013-05-30 18:10:38 -05001223 dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte,
1224 (unsigned long long)da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001225 } else {
1226 if (iopgd_is_section(*pgd))
1227 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1228 else if (iopgd_is_super(*pgd))
1229 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1230 else
Suman Anna2abfcfb2013-05-30 18:10:38 -05001231 dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd,
1232 (unsigned long long)da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001233 }
1234
1235 return ret;
1236}
1237
Laurent Pinchart07a02032014-02-28 14:42:38 -06001238static int omap_iommu_add_device(struct device *dev)
1239{
1240 struct omap_iommu_arch_data *arch_data;
1241 struct device_node *np;
1242
1243 /*
1244 * Allocate the archdata iommu structure for DT-based devices.
1245 *
1246 * TODO: Simplify this when removing non-DT support completely from the
1247 * IOMMU users.
1248 */
1249 if (!dev->of_node)
1250 return 0;
1251
1252 np = of_parse_phandle(dev->of_node, "iommus", 0);
1253 if (!np)
1254 return 0;
1255
1256 arch_data = kzalloc(sizeof(*arch_data), GFP_KERNEL);
1257 if (!arch_data) {
1258 of_node_put(np);
1259 return -ENOMEM;
1260 }
1261
1262 arch_data->name = kstrdup(dev_name(dev), GFP_KERNEL);
1263 dev->archdata.iommu = arch_data;
1264
1265 of_node_put(np);
1266
1267 return 0;
1268}
1269
1270static void omap_iommu_remove_device(struct device *dev)
1271{
1272 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1273
1274 if (!dev->of_node || !arch_data)
1275 return;
1276
1277 kfree(arch_data->name);
1278 kfree(arch_data);
1279}
1280
Thierry Redingb22f6432014-06-27 09:03:12 +02001281static const struct iommu_ops omap_iommu_ops = {
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001282 .domain_init = omap_iommu_domain_init,
1283 .domain_destroy = omap_iommu_domain_destroy,
1284 .attach_dev = omap_iommu_attach_dev,
1285 .detach_dev = omap_iommu_detach_dev,
1286 .map = omap_iommu_map,
1287 .unmap = omap_iommu_unmap,
1288 .iova_to_phys = omap_iommu_iova_to_phys,
Laurent Pinchart07a02032014-02-28 14:42:38 -06001289 .add_device = omap_iommu_add_device,
1290 .remove_device = omap_iommu_remove_device,
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +02001291 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001292};
1293
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001294static int __init omap_iommu_init(void)
1295{
1296 struct kmem_cache *p;
1297 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1298 size_t align = 1 << 10; /* L2 pagetable alignement */
1299
1300 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1301 iopte_cachep_ctor);
1302 if (!p)
1303 return -ENOMEM;
1304 iopte_cachep = p;
1305
Joerg Roedela65bc642011-09-06 17:56:07 +02001306 bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001307
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001308 return platform_driver_register(&omap_iommu_driver);
1309}
Ohad Ben-Cohen435792d2012-02-26 12:14:14 +02001310/* must be ready before omap3isp is probed */
1311subsys_initcall(omap_iommu_init);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001312
1313static void __exit omap_iommu_exit(void)
1314{
1315 kmem_cache_destroy(iopte_cachep);
1316
1317 platform_driver_unregister(&omap_iommu_driver);
1318}
1319module_exit(omap_iommu_exit);
1320
1321MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
1322MODULE_ALIAS("platform:omap-iommu");
1323MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
1324MODULE_LICENSE("GPL v2");