Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 7f90fc965023d72589a4e5fc02ac812e3a6ac809 / . / drivers / gpu / drm / radeon / radeon_asic.h
blob: 01e7c0ad8f0127a1a758c5c4348059927785bfdb [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +0100[diff] [blame]36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]45void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]46u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]49
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]50/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]51 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]52 */
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]53struct r100_mc_save {
54 u32 GENMO_WT;
55 u32 CRTC_EXT_CNTL;
56 u32 CRTC_GEN_CNTL;
57 u32 CRTC2_GEN_CNTL;
58 u32 CUR_OFFSET;
59 u32 CUR2_OFFSET;
60};
61int r100_init(struct radeon_device *rdev);
62void r100_fini(struct radeon_device *rdev);
63int r100_suspend(struct radeon_device *rdev);
64int r100_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]65void r100_vga_set_state(struct radeon_device *rdev, bool state);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]66bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]67int r100_asic_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]68u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]69void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
Christian König7f90fc92014-06-04 15:29:57 +0200[diff] [blame^]70void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
71 uint64_t addr);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]72void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]73int r100_irq_set(struct radeon_device *rdev);
74int r100_irq_process(struct radeon_device *rdev);
75void r100_fence_ring_emit(struct radeon_device *rdev,
76 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]77bool r100_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]78 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]79 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]80 bool emit_wait);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]81int r100_cs_parse(struct radeon_cs_parser *p);
82void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
83uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
84int r100_copy_blit(struct radeon_device *rdev,
85 uint64_t src_offset,
86 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]87 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]88 struct radeon_fence **fence);
Dave Airliee024e112009-06-24 09:48:08 +1000[diff] [blame]89int r100_set_surface_reg(struct radeon_device *rdev, int reg,
90 uint32_t tiling_flags, uint32_t pitch,
91 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]92void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]93void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]94void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]95int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]96void r100_hpd_init(struct radeon_device *rdev);
97void r100_hpd_fini(struct radeon_device *rdev);
98bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
99void r100_hpd_set_polarity(struct radeon_device *rdev,
100 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]101int r100_debugfs_rbbm_init(struct radeon_device *rdev);
102int r100_debugfs_cp_init(struct radeon_device *rdev);
103void r100_cp_disable(struct radeon_device *rdev);
104int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
105void r100_cp_fini(struct radeon_device *rdev);
106int r100_pci_gart_init(struct radeon_device *rdev);
107void r100_pci_gart_fini(struct radeon_device *rdev);
108int r100_pci_gart_enable(struct radeon_device *rdev);
109void r100_pci_gart_disable(struct radeon_device *rdev);
110int r100_debugfs_mc_info_init(struct radeon_device *rdev);
111int r100_gui_wait_for_idle(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]112int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]113void r100_irq_disable(struct radeon_device *rdev);
114void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
115void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
116void r100_vram_init_sizes(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]117int r100_cp_reset(struct radeon_device *rdev);
118void r100_vga_render_disable(struct radeon_device *rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000[diff] [blame]119void r100_restore_sanity(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]120int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
121 struct radeon_cs_packet *pkt,
122 struct radeon_bo *robj);
123int r100_cs_parse_packet0(struct radeon_cs_parser *p,
124 struct radeon_cs_packet *pkt,
125 const unsigned *auth, unsigned n,
126 radeon_packet0_check_t check);
127int r100_cs_packet_parse(struct radeon_cs_parser *p,
128 struct radeon_cs_packet *pkt,
129 unsigned idx);
130void r100_enable_bm(struct radeon_device *rdev);
131void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]132void r100_bm_disable(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]133extern bool r100_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]134extern void r100_pm_misc(struct radeon_device *rdev);
135extern void r100_pm_prepare(struct radeon_device *rdev);
136extern void r100_pm_finish(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]137extern void r100_pm_init_profile(struct radeon_device *rdev);
138extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
Christian König157fa142014-05-27 16:49:20 +0200[diff] [blame]139extern void r100_page_flip(struct radeon_device *rdev, int crtc,
140 u64 crtc_base);
141extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]142extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]143extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucherbae6b5622010-04-22 13:38:05 -0400[diff] [blame]144
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]145u32 r100_gfx_get_rptr(struct radeon_device *rdev,
146 struct radeon_ring *ring);
147u32 r100_gfx_get_wptr(struct radeon_device *rdev,
148 struct radeon_ring *ring);
149void r100_gfx_set_wptr(struct radeon_device *rdev,
150 struct radeon_ring *ring);
151
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]152/*
153 * r200,rv250,rs300,rv280
154 */
155extern int r200_copy_dma(struct radeon_device *rdev,
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]156 uint64_t src_offset,
157 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]158 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]159 struct radeon_fence **fence);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]160void r200_set_safe_registers(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]161
162/*
163 * r300,r350,rv350,rv380
164 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]165extern int r300_init(struct radeon_device *rdev);
166extern void r300_fini(struct radeon_device *rdev);
167extern int r300_suspend(struct radeon_device *rdev);
168extern int r300_resume(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]169extern int r300_asic_reset(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]170extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]171extern void r300_fence_ring_emit(struct radeon_device *rdev,
172 struct radeon_fence *fence);
173extern int r300_cs_parse(struct radeon_cs_parser *p);
174extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
Christian König7f90fc92014-06-04 15:29:57 +0200[diff] [blame^]175extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
176 uint64_t addr);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]177extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500[diff] [blame]178extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]179extern void r300_set_reg_safe(struct radeon_device *rdev);
180extern void r300_mc_program(struct radeon_device *rdev);
181extern void r300_mc_init(struct radeon_device *rdev);
182extern void r300_clock_startup(struct radeon_device *rdev);
183extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
184extern int rv370_pcie_gart_init(struct radeon_device *rdev);
185extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
186extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
187extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]188extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]189
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]190/*
191 * r420,r423,rv410
192 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200[diff] [blame]193extern int r420_init(struct radeon_device *rdev);
194extern void r420_fini(struct radeon_device *rdev);
195extern int r420_suspend(struct radeon_device *rdev);
196extern int r420_resume(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]197extern void r420_pm_init_profile(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]198extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
199extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
200extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
201extern void r420_pipes_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]202
203/*
204 * rs400,rs480
205 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200[diff] [blame]206extern int rs400_init(struct radeon_device *rdev);
207extern void rs400_fini(struct radeon_device *rdev);
208extern int rs400_suspend(struct radeon_device *rdev);
209extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]210void rs400_gart_tlb_flush(struct radeon_device *rdev);
Christian König7f90fc92014-06-04 15:29:57 +0200[diff] [blame^]211void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
212 uint64_t addr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]213uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
214void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]215int rs400_gart_init(struct radeon_device *rdev);
216int rs400_gart_enable(struct radeon_device *rdev);
217void rs400_gart_adjust_size(struct radeon_device *rdev);
218void rs400_gart_disable(struct radeon_device *rdev);
219void rs400_gart_fini(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]220extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]221
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]222/*
223 * rs600.
224 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]225extern int rs600_asic_reset(struct radeon_device *rdev);
Jerome Glissec010f802009-09-30 22:09:06 +0200[diff] [blame]226extern int rs600_init(struct radeon_device *rdev);
227extern void rs600_fini(struct radeon_device *rdev);
228extern int rs600_suspend(struct radeon_device *rdev);
229extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]230int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]231int rs600_irq_process(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]232void rs600_irq_disable(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]233u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]234void rs600_gart_tlb_flush(struct radeon_device *rdev);
Christian König7f90fc92014-06-04 15:29:57 +0200[diff] [blame^]235void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
236 uint64_t addr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]237uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
238void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]239void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]240void rs600_hpd_init(struct radeon_device *rdev);
241void rs600_hpd_fini(struct radeon_device *rdev);
242bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
243void rs600_hpd_set_polarity(struct radeon_device *rdev,
244 enum radeon_hpd_id hpd);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]245extern void rs600_pm_misc(struct radeon_device *rdev);
246extern void rs600_pm_prepare(struct radeon_device *rdev);
247extern void rs600_pm_finish(struct radeon_device *rdev);
Christian König157fa142014-05-27 16:49:20 +0200[diff] [blame]248extern void rs600_page_flip(struct radeon_device *rdev, int crtc,
249 u64 crtc_base);
250extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]251void rs600_set_safe_registers(struct radeon_device *rdev);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]252extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]253extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]254
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]255/*
256 * rs690,rs740
257 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200[diff] [blame]258int rs690_init(struct radeon_device *rdev);
259void rs690_fini(struct radeon_device *rdev);
260int rs690_resume(struct radeon_device *rdev);
261int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]262uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
263void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]264void rs690_bandwidth_update(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]265void rs690_line_buffer_adjust(struct radeon_device *rdev,
266 struct drm_display_mode *mode1,
267 struct drm_display_mode *mode2);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]268extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]269
270/*
271 * rv515
272 */
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]273struct rv515_mc_save {
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]274 u32 vga_render_control;
275 u32 vga_hdp_control;
Alex Deucher6253e4c2012-12-12 14:30:32 -0500[diff] [blame]276 bool crtc_enabled[2];
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]277};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]278
Jerome Glisse068a1172009-06-17 13:28:30 +0200[diff] [blame]279int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]280void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]281uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
282void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]283void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]284void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]285int rv515_resume(struct radeon_device *rdev);
286int rv515_suspend(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]287void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
288void rv515_vga_render_disable(struct radeon_device *rdev);
289void rv515_set_safe_registers(struct radeon_device *rdev);
290void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
291void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
292void rv515_clock_startup(struct radeon_device *rdev);
293void rv515_debugfs(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]294int rv515_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]295
296/*
297 * r520,rv530,rv560,rv570,r580
298 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]299int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200[diff] [blame]300int r520_resume(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]301int r520_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]302
303/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]304 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]305 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]306int r600_init(struct radeon_device *rdev);
307void r600_fini(struct radeon_device *rdev);
308int r600_suspend(struct radeon_device *rdev);
309int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]310void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]311int r600_wb_init(struct radeon_device *rdev);
312void r600_wb_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]313void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]314uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
315void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]316int r600_cs_parse(struct radeon_cs_parser *p);
Alex Deuchercf4ccd02011-11-18 10:19:47 -0500[diff] [blame]317int r600_dma_cs_parse(struct radeon_cs_parser *p);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]318void r600_fence_ring_emit(struct radeon_device *rdev,
319 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]320bool r600_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]321 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]322 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]323 bool emit_wait);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]324void r600_dma_fence_ring_emit(struct radeon_device *rdev,
325 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]326bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]327 struct radeon_ring *ring,
328 struct radeon_semaphore *semaphore,
329 bool emit_wait);
330void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
331bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]332bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]333int r600_asic_reset(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]334int r600_set_surface_reg(struct radeon_device *rdev, int reg,
335 uint32_t tiling_flags, uint32_t pitch,
336 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]337void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]338int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]339int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]340void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]341int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]342int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher072b5ac2013-07-11 14:48:05 -0400[diff] [blame]343int r600_copy_cpdma(struct radeon_device *rdev,
344 uint64_t src_offset, uint64_t dst_offset,
345 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]346int r600_copy_dma(struct radeon_device *rdev,
347 uint64_t src_offset, uint64_t dst_offset,
348 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]349void r600_hpd_init(struct radeon_device *rdev);
350void r600_hpd_fini(struct radeon_device *rdev);
351bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
352void r600_hpd_set_polarity(struct radeon_device *rdev,
353 enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]354extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]355extern bool r600_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]356extern void r600_pm_misc(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]357extern void r600_pm_init_profile(struct radeon_device *rdev);
358extern void rs780_pm_init_profile(struct radeon_device *rdev);
Samuel Li65337e62013-04-05 17:50:53 -0400[diff] [blame]359extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
360extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]361extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]362extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
363extern int r600_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]364bool r600_card_posted(struct radeon_device *rdev);
365void r600_cp_stop(struct radeon_device *rdev);
366int r600_cp_start(struct radeon_device *rdev);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]367void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]368int r600_cp_resume(struct radeon_device *rdev);
369void r600_cp_fini(struct radeon_device *rdev);
370int r600_count_pipe_bits(uint32_t val);
371int r600_mc_wait_for_idle(struct radeon_device *rdev);
372int r600_pcie_gart_init(struct radeon_device *rdev);
373void r600_scratch_init(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]374int r600_init_microcode(struct radeon_device *rdev);
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]375u32 r600_gfx_get_rptr(struct radeon_device *rdev,
376 struct radeon_ring *ring);
377u32 r600_gfx_get_wptr(struct radeon_device *rdev,
378 struct radeon_ring *ring);
379void r600_gfx_set_wptr(struct radeon_device *rdev,
380 struct radeon_ring *ring);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]381/* r600 irq */
382int r600_irq_process(struct radeon_device *rdev);
383int r600_irq_init(struct radeon_device *rdev);
384void r600_irq_fini(struct radeon_device *rdev);
385void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
386int r600_irq_set(struct radeon_device *rdev);
387void r600_irq_suspend(struct radeon_device *rdev);
388void r600_disable_interrupts(struct radeon_device *rdev);
389void r600_rlc_stop(struct radeon_device *rdev);
390/* r600 audio */
391int r600_audio_init(struct radeon_device *rdev);
Alex Deucherb5306022013-07-31 16:51:33 -0400[diff] [blame]392struct r600_audio_pin r600_audio_status(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]393void r600_audio_fini(struct radeon_device *rdev);
Rafał Miłecki8f33a152014-05-16 11:36:24 +0200[diff] [blame]394void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
395void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
396 size_t size);
397void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);
398void r600_hdmi_audio_workaround(struct drm_encoder *encoder);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]399int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
400void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
Alex Deuchera973bea2013-04-18 11:32:16 -0400[diff] [blame]401void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
402void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]403int r600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]404u32 r600_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]405uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]406int rv6xx_get_temp(struct radeon_device *rdev);
Alex Deucher1b9ba702013-09-05 09:52:37 -0400[diff] [blame]407int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher98243912013-01-16 13:13:42 -0500[diff] [blame]408int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
409void r600_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deuchera4643ba2013-12-19 12:18:13 -0500[diff] [blame]410int r600_dpm_late_enable(struct radeon_device *rdev);
Christian König2e1e6da2013-08-13 11:56:52 +0200[diff] [blame]411/* r600 dma */
412uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
413 struct radeon_ring *ring);
414uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
415 struct radeon_ring *ring);
416void r600_dma_set_wptr(struct radeon_device *rdev,
417 struct radeon_ring *ring);
Alex Deucher4a6369e2013-04-12 14:04:10 -0400[diff] [blame]418/* rv6xx dpm */
419int rv6xx_dpm_init(struct radeon_device *rdev);
420int rv6xx_dpm_enable(struct radeon_device *rdev);
421void rv6xx_dpm_disable(struct radeon_device *rdev);
422int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
423void rv6xx_setup_asic(struct radeon_device *rdev);
424void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
425void rv6xx_dpm_fini(struct radeon_device *rdev);
426u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
427u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
428void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
429 struct radeon_ps *ps);
Alex Deucher242916a2013-06-28 14:20:53 -0400[diff] [blame]430void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
431 struct seq_file *m);
Alex Deucherf4f85a82013-07-25 20:07:25 -0400[diff] [blame]432int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
433 enum radeon_dpm_forced_level level);
Alex Deucher9d670062013-04-12 13:59:22 -0400[diff] [blame]434/* rs780 dpm */
435int rs780_dpm_init(struct radeon_device *rdev);
436int rs780_dpm_enable(struct radeon_device *rdev);
437void rs780_dpm_disable(struct radeon_device *rdev);
438int rs780_dpm_set_power_state(struct radeon_device *rdev);
439void rs780_dpm_setup_asic(struct radeon_device *rdev);
440void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
441void rs780_dpm_fini(struct radeon_device *rdev);
442u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
443u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
444void rs780_dpm_print_power_state(struct radeon_device *rdev,
445 struct radeon_ps *ps);
Alex Deucher444bddc2013-07-02 13:05:23 -0400[diff] [blame]446void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
447 struct seq_file *m);
Anthoine Bourgeois63580c32013-09-03 13:52:19 -0400[diff] [blame]448int rs780_dpm_force_performance_level(struct radeon_device *rdev,
449 enum radeon_dpm_forced_level level);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]450
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]451/*
452 * rv770,rv730,rv710,rv740
453 */
454int rv770_init(struct radeon_device *rdev);
455void rv770_fini(struct radeon_device *rdev);
456int rv770_suspend(struct radeon_device *rdev);
457int rv770_resume(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]458void rv770_pm_misc(struct radeon_device *rdev);
Christian König157fa142014-05-27 16:49:20 +0200[diff] [blame]459void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
460bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]461void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
462void r700_cp_stop(struct radeon_device *rdev);
463void r700_cp_fini(struct radeon_device *rdev);
Alex Deucher43fb7782013-01-04 09:24:18 -0500[diff] [blame]464int rv770_copy_dma(struct radeon_device *rdev,
465 uint64_t src_offset, uint64_t dst_offset,
466 unsigned num_gpu_pages,
467 struct radeon_fence **fence);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]468u32 rv770_get_xclk(struct radeon_device *rdev);
Christian Königef0e6e62013-04-08 12:41:35 +0200[diff] [blame]469int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]470int rv770_get_temp(struct radeon_device *rdev);
Rafał Miłecki8f33a152014-05-16 11:36:24 +0200[diff] [blame]471/* hdmi */
472void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher66229b22013-06-26 00:11:19 -0400[diff] [blame]473/* rv7xx pm */
474int rv770_dpm_init(struct radeon_device *rdev);
475int rv770_dpm_enable(struct radeon_device *rdev);
Alex Deuchera3f11242013-12-19 13:48:36 -0500[diff] [blame]476int rv770_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher66229b22013-06-26 00:11:19 -0400[diff] [blame]477void rv770_dpm_disable(struct radeon_device *rdev);
478int rv770_dpm_set_power_state(struct radeon_device *rdev);
479void rv770_dpm_setup_asic(struct radeon_device *rdev);
480void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
481void rv770_dpm_fini(struct radeon_device *rdev);
482u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
483u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
484void rv770_dpm_print_power_state(struct radeon_device *rdev,
485 struct radeon_ps *ps);
Alex Deucherbd210d12013-06-28 10:06:26 -0400[diff] [blame]486void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
487 struct seq_file *m);
Alex Deucher8b5e6b72013-07-02 18:40:35 -0400[diff] [blame]488int rv770_dpm_force_performance_level(struct radeon_device *rdev,
489 enum radeon_dpm_forced_level level);
Alex Deucherb06195d2013-07-08 11:49:48 -0400[diff] [blame]490bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]491
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]492/*
493 * evergreen
494 */
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]495struct evergreen_mc_save {
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]496 u32 vga_render_control;
497 u32 vga_hdp_control;
Alex Deucher62444b72012-08-15 17:18:42 -0400[diff] [blame]498 bool crtc_enabled[RADEON_MAX_CRTCS];
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]499};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]500
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]501void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]502int evergreen_init(struct radeon_device *rdev);
503void evergreen_fini(struct radeon_device *rdev);
504int evergreen_suspend(struct radeon_device *rdev);
505int evergreen_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]506bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
507bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]508int evergreen_asic_reset(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]509void evergreen_bandwidth_update(struct radeon_device *rdev);
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]510void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]511void evergreen_hpd_init(struct radeon_device *rdev);
512void evergreen_hpd_fini(struct radeon_device *rdev);
513bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
514void evergreen_hpd_set_polarity(struct radeon_device *rdev,
515 enum radeon_hpd_id hpd);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]516u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
517int evergreen_irq_set(struct radeon_device *rdev);
518int evergreen_irq_process(struct radeon_device *rdev);
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]519extern int evergreen_cs_parse(struct radeon_cs_parser *p);
Alex Deucherd2ead3e2012-12-13 09:55:45 -0500[diff] [blame]520extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]521extern void evergreen_pm_misc(struct radeon_device *rdev);
522extern void evergreen_pm_prepare(struct radeon_device *rdev);
523extern void evergreen_pm_finish(struct radeon_device *rdev);
Alex Deuchera4c9e2e2011-11-04 10:09:41 -0400[diff] [blame]524extern void sumo_pm_init_profile(struct radeon_device *rdev);
Alex Deucher27810fb2012-10-01 19:25:11 -0400[diff] [blame]525extern void btc_pm_init_profile(struct radeon_device *rdev);
Alex Deucher23d33ba2013-04-08 12:41:32 +0200[diff] [blame]526int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deuchera8b49252013-04-08 12:41:33 +0200[diff] [blame]527int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Christian König157fa142014-05-27 16:49:20 +0200[diff] [blame]528extern void evergreen_page_flip(struct radeon_device *rdev, int crtc,
529 u64 crtc_base);
530extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]531extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]532void evergreen_disable_interrupt_state(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]533int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher233d1ad2012-12-04 15:25:59 -0500[diff] [blame]534void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
535 struct radeon_fence *fence);
536void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
537 struct radeon_ib *ib);
538int evergreen_copy_dma(struct radeon_device *rdev,
539 uint64_t src_offset, uint64_t dst_offset,
540 unsigned num_gpu_pages,
541 struct radeon_fence **fence);
Alex Deuchera973bea2013-04-18 11:32:16 -0400[diff] [blame]542void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
543void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]544int evergreen_get_temp(struct radeon_device *rdev);
545int sumo_get_temp(struct radeon_device *rdev);
Alex Deucher29a15222012-12-14 11:57:36 -0500[diff] [blame]546int tn_get_temp(struct radeon_device *rdev);
Alex Deucherdc50ba72013-06-26 00:33:35 -0400[diff] [blame]547int cypress_dpm_init(struct radeon_device *rdev);
548void cypress_dpm_setup_asic(struct radeon_device *rdev);
549int cypress_dpm_enable(struct radeon_device *rdev);
550void cypress_dpm_disable(struct radeon_device *rdev);
551int cypress_dpm_set_power_state(struct radeon_device *rdev);
552void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
553void cypress_dpm_fini(struct radeon_device *rdev);
Alex Deucherd0b54bd2013-07-08 11:56:09 -0400[diff] [blame]554bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]555int btc_dpm_init(struct radeon_device *rdev);
556void btc_dpm_setup_asic(struct radeon_device *rdev);
557int btc_dpm_enable(struct radeon_device *rdev);
558void btc_dpm_disable(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]559int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]560int btc_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]561void btc_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]562void btc_dpm_fini(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]563u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
564u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
Alex Deuchera84301c2013-07-08 12:03:55 -0400[diff] [blame]565bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher9f3f63f2014-01-30 11:19:22 -0500[diff] [blame]566void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
567 struct seq_file *m);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]568int sumo_dpm_init(struct radeon_device *rdev);
569int sumo_dpm_enable(struct radeon_device *rdev);
Alex Deucher14ec9fa2013-12-19 11:56:52 -0500[diff] [blame]570int sumo_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]571void sumo_dpm_disable(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400[diff] [blame]572int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]573int sumo_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400[diff] [blame]574void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]575void sumo_dpm_setup_asic(struct radeon_device *rdev);
576void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
577void sumo_dpm_fini(struct radeon_device *rdev);
578u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
579u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
580void sumo_dpm_print_power_state(struct radeon_device *rdev,
581 struct radeon_ps *ps);
Alex Deucherfb701602013-06-28 10:47:56 -0400[diff] [blame]582void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
583 struct seq_file *m);
Alex Deucher5d5e5592013-07-02 18:50:09 -0400[diff] [blame]584int sumo_dpm_force_performance_level(struct radeon_device *rdev,
585 enum radeon_dpm_forced_level level);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]586
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]587/*
588 * cayman
589 */
Alex Deucherb40e7e12011-11-17 14:57:50 -0500[diff] [blame]590void cayman_fence_ring_emit(struct radeon_device *rdev,
591 struct radeon_fence *fence);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]592void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
593int cayman_init(struct radeon_device *rdev);
594void cayman_fini(struct radeon_device *rdev);
595int cayman_suspend(struct radeon_device *rdev);
596int cayman_resume(struct radeon_device *rdev);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]597int cayman_asic_reset(struct radeon_device *rdev);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]598void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
599int cayman_vm_init(struct radeon_device *rdev);
600void cayman_vm_fini(struct radeon_device *rdev);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]601void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Christian König089a7862012-08-11 11:54:05 +0200[diff] [blame]602uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]603int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deuchercd459e52012-12-13 12:17:38 -0500[diff] [blame]604int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]605void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
606 struct radeon_ib *ib);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]607bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]608bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]609void cayman_dma_vm_set_page(struct radeon_device *rdev,
610 struct radeon_ib *ib,
611 uint64_t pe,
612 uint64_t addr, unsigned count,
613 uint32_t incr, uint32_t flags);
614
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]615void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]616
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]617u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
618 struct radeon_ring *ring);
619u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
620 struct radeon_ring *ring);
621void cayman_gfx_set_wptr(struct radeon_device *rdev,
622 struct radeon_ring *ring);
623uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
624 struct radeon_ring *ring);
625uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
626 struct radeon_ring *ring);
627void cayman_dma_set_wptr(struct radeon_device *rdev,
628 struct radeon_ring *ring);
629
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]630int ni_dpm_init(struct radeon_device *rdev);
631void ni_dpm_setup_asic(struct radeon_device *rdev);
632int ni_dpm_enable(struct radeon_device *rdev);
633void ni_dpm_disable(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500[diff] [blame]634int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]635int ni_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500[diff] [blame]636void ni_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]637void ni_dpm_fini(struct radeon_device *rdev);
638u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
639u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
640void ni_dpm_print_power_state(struct radeon_device *rdev,
641 struct radeon_ps *ps);
Alex Deucherbdf0c4f2013-06-28 17:49:02 -0400[diff] [blame]642void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
643 struct seq_file *m);
Alex Deucher170a47f2013-07-02 18:43:53 -0400[diff] [blame]644int ni_dpm_force_performance_level(struct radeon_device *rdev,
645 enum radeon_dpm_forced_level level);
Alex Deucher76ad73e2013-07-08 12:09:41 -0400[diff] [blame]646bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]647int trinity_dpm_init(struct radeon_device *rdev);
648int trinity_dpm_enable(struct radeon_device *rdev);
Alex Deucherbda44c12013-12-19 12:03:35 -0500[diff] [blame]649int trinity_dpm_late_enable(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]650void trinity_dpm_disable(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500[diff] [blame]651int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]652int trinity_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500[diff] [blame]653void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]654void trinity_dpm_setup_asic(struct radeon_device *rdev);
655void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
656void trinity_dpm_fini(struct radeon_device *rdev);
657u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
658u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
659void trinity_dpm_print_power_state(struct radeon_device *rdev,
660 struct radeon_ps *ps);
Alex Deucher490ab932013-06-28 12:01:38 -0400[diff] [blame]661void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
662 struct seq_file *m);
Alex Deucher9b5de592013-07-02 18:52:10 -0400[diff] [blame]663int trinity_dpm_force_performance_level(struct radeon_device *rdev,
664 enum radeon_dpm_forced_level level);
Alex Deucher11877062013-09-09 19:19:52 -0400[diff] [blame]665void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]666
Alex Deucher43b3cd92012-03-20 17:18:00 -0400[diff] [blame]667/* DCE6 - SI */
668void dce6_bandwidth_update(struct radeon_device *rdev);
Alex Deucherb5306022013-07-31 16:51:33 -0400[diff] [blame]669int dce6_audio_init(struct radeon_device *rdev);
670void dce6_audio_fini(struct radeon_device *rdev);
Alex Deucher43b3cd92012-03-20 17:18:00 -0400[diff] [blame]671
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]672/*
673 * si
674 */
675void si_fence_ring_emit(struct radeon_device *rdev,
676 struct radeon_fence *fence);
677void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
678int si_init(struct radeon_device *rdev);
679void si_fini(struct radeon_device *rdev);
680int si_suspend(struct radeon_device *rdev);
681int si_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]682bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
683bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]684int si_asic_reset(struct radeon_device *rdev);
685void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
686int si_irq_set(struct radeon_device *rdev);
687int si_irq_process(struct radeon_device *rdev);
688int si_vm_init(struct radeon_device *rdev);
689void si_vm_fini(struct radeon_device *rdev);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]690void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]691int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucher8c5fd7e2012-12-04 15:28:18 -0500[diff] [blame]692int si_copy_dma(struct radeon_device *rdev,
693 uint64_t src_offset, uint64_t dst_offset,
694 unsigned num_gpu_pages,
695 struct radeon_fence **fence);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]696void si_dma_vm_set_page(struct radeon_device *rdev,
697 struct radeon_ib *ib,
698 uint64_t pe,
699 uint64_t addr, unsigned count,
700 uint32_t incr, uint32_t flags);
Alex Deucher8c5fd7e2012-12-04 15:28:18 -0500[diff] [blame]701void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]702u32 si_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]703uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
Christian König2539eb02013-04-08 12:41:34 +0200[diff] [blame]704int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]705int si_get_temp(struct radeon_device *rdev);
Alex Deuchera9e61412013-06-25 17:56:16 -0400[diff] [blame]706int si_dpm_init(struct radeon_device *rdev);
707void si_dpm_setup_asic(struct radeon_device *rdev);
708int si_dpm_enable(struct radeon_device *rdev);
Alex Deucher963c1152013-12-19 13:54:35 -0500[diff] [blame]709int si_dpm_late_enable(struct radeon_device *rdev);
Alex Deuchera9e61412013-06-25 17:56:16 -0400[diff] [blame]710void si_dpm_disable(struct radeon_device *rdev);
711int si_dpm_pre_set_power_state(struct radeon_device *rdev);
712int si_dpm_set_power_state(struct radeon_device *rdev);
713void si_dpm_post_set_power_state(struct radeon_device *rdev);
714void si_dpm_fini(struct radeon_device *rdev);
715void si_dpm_display_configuration_changed(struct radeon_device *rdev);
Alex Deucher79821282013-06-28 18:02:19 -0400[diff] [blame]716void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
717 struct seq_file *m);
Alex Deuchera160a6a2013-07-02 18:46:28 -0400[diff] [blame]718int si_dpm_force_performance_level(struct radeon_device *rdev,
719 enum radeon_dpm_forced_level level);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]720
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]721/* DCE8 - CIK */
722void dce8_bandwidth_update(struct radeon_device *rdev);
723
Alex Deucher44fa3462012-12-18 22:17:00 -0500[diff] [blame]724/*
725 * cik
726 */
727uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher2c679122013-04-09 13:32:18 -0400[diff] [blame]728u32 cik_get_xclk(struct radeon_device *rdev);
Alex Deucher6e2c3c02013-04-03 19:28:32 -0400[diff] [blame]729uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
730void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Christian König87167bb2013-04-09 13:39:21 -0400[diff] [blame]731int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher5ad6bf92013-08-22 17:09:06 -0400[diff] [blame]732int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]733void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
734 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]735bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]736 struct radeon_ring *ring,
737 struct radeon_semaphore *semaphore,
738 bool emit_wait);
739void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
740int cik_copy_dma(struct radeon_device *rdev,
741 uint64_t src_offset, uint64_t dst_offset,
742 unsigned num_gpu_pages,
743 struct radeon_fence **fence);
Alex Deucherc9dbd702013-10-01 16:36:51 -0400[diff] [blame]744int cik_copy_cpdma(struct radeon_device *rdev,
745 uint64_t src_offset, uint64_t dst_offset,
746 unsigned num_gpu_pages,
747 struct radeon_fence **fence);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]748int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
749int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
750bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
751void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
752 struct radeon_fence *fence);
753void cik_fence_compute_ring_emit(struct radeon_device *rdev,
754 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]755bool cik_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]756 struct radeon_ring *cp,
757 struct radeon_semaphore *semaphore,
758 bool emit_wait);
759void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
760int cik_init(struct radeon_device *rdev);
761void cik_fini(struct radeon_device *rdev);
762int cik_suspend(struct radeon_device *rdev);
763int cik_resume(struct radeon_device *rdev);
764bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
765int cik_asic_reset(struct radeon_device *rdev);
766void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
767int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
768int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
769int cik_irq_set(struct radeon_device *rdev);
770int cik_irq_process(struct radeon_device *rdev);
771int cik_vm_init(struct radeon_device *rdev);
772void cik_vm_fini(struct radeon_device *rdev);
773void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]774void cik_sdma_vm_set_page(struct radeon_device *rdev,
775 struct radeon_ib *ib,
776 uint64_t pe,
777 uint64_t addr, unsigned count,
778 uint32_t incr, uint32_t flags);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]779void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
780int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]781u32 cik_gfx_get_rptr(struct radeon_device *rdev,
782 struct radeon_ring *ring);
783u32 cik_gfx_get_wptr(struct radeon_device *rdev,
784 struct radeon_ring *ring);
785void cik_gfx_set_wptr(struct radeon_device *rdev,
786 struct radeon_ring *ring);
787u32 cik_compute_get_rptr(struct radeon_device *rdev,
788 struct radeon_ring *ring);
789u32 cik_compute_get_wptr(struct radeon_device *rdev,
790 struct radeon_ring *ring);
791void cik_compute_set_wptr(struct radeon_device *rdev,
792 struct radeon_ring *ring);
793u32 cik_sdma_get_rptr(struct radeon_device *rdev,
794 struct radeon_ring *ring);
795u32 cik_sdma_get_wptr(struct radeon_device *rdev,
796 struct radeon_ring *ring);
797void cik_sdma_set_wptr(struct radeon_device *rdev,
798 struct radeon_ring *ring);
Alex Deucher286d9cc2013-06-21 15:50:47 -0400[diff] [blame]799int ci_get_temp(struct radeon_device *rdev);
800int kv_get_temp(struct radeon_device *rdev);
Alex Deucher44fa3462012-12-18 22:17:00 -0500[diff] [blame]801
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]802int ci_dpm_init(struct radeon_device *rdev);
803int ci_dpm_enable(struct radeon_device *rdev);
Alex Deucher90208422013-12-19 13:59:46 -0500[diff] [blame]804int ci_dpm_late_enable(struct radeon_device *rdev);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]805void ci_dpm_disable(struct radeon_device *rdev);
806int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
807int ci_dpm_set_power_state(struct radeon_device *rdev);
808void ci_dpm_post_set_power_state(struct radeon_device *rdev);
809void ci_dpm_setup_asic(struct radeon_device *rdev);
810void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
811void ci_dpm_fini(struct radeon_device *rdev);
812u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
813u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
814void ci_dpm_print_power_state(struct radeon_device *rdev,
815 struct radeon_ps *ps);
Alex Deucher94b4adc2013-07-15 17:34:33 -0400[diff] [blame]816void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
817 struct seq_file *m);
Alex Deucher89536fd2013-07-15 18:14:24 -0400[diff] [blame]818int ci_dpm_force_performance_level(struct radeon_device *rdev,
819 enum radeon_dpm_forced_level level);
Alex Deucher54961312013-07-15 18:24:31 -0400[diff] [blame]820bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher942bdf72013-08-09 10:05:24 -0400[diff] [blame]821void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]822
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]823int kv_dpm_init(struct radeon_device *rdev);
824int kv_dpm_enable(struct radeon_device *rdev);
Alex Deucherd8852c32013-12-19 14:03:36 -0500[diff] [blame]825int kv_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]826void kv_dpm_disable(struct radeon_device *rdev);
827int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
828int kv_dpm_set_power_state(struct radeon_device *rdev);
829void kv_dpm_post_set_power_state(struct radeon_device *rdev);
830void kv_dpm_setup_asic(struct radeon_device *rdev);
831void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
832void kv_dpm_fini(struct radeon_device *rdev);
833u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
834u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
835void kv_dpm_print_power_state(struct radeon_device *rdev,
836 struct radeon_ps *ps);
Alex Deucherae3e40e2013-07-18 16:39:53 -0400[diff] [blame]837void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
838 struct seq_file *m);
Alex Deucher2b4c8022013-07-18 16:48:46 -0400[diff] [blame]839int kv_dpm_force_performance_level(struct radeon_device *rdev,
840 enum radeon_dpm_forced_level level);
Alex Deucher77df5082013-08-09 10:02:40 -0400[diff] [blame]841void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
Alex Deucherb7a5ae92013-09-09 19:33:08 -0400[diff] [blame]842void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]843
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]844/* uvd v1.0 */
845uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
846 struct radeon_ring *ring);
847uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
848 struct radeon_ring *ring);
849void uvd_v1_0_set_wptr(struct radeon_device *rdev,
850 struct radeon_ring *ring);
851
852int uvd_v1_0_init(struct radeon_device *rdev);
853void uvd_v1_0_fini(struct radeon_device *rdev);
854int uvd_v1_0_start(struct radeon_device *rdev);
855void uvd_v1_0_stop(struct radeon_device *rdev);
856
857int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
858int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]859bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]860 struct radeon_ring *ring,
861 struct radeon_semaphore *semaphore,
862 bool emit_wait);
863void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
864
865/* uvd v2.2 */
866int uvd_v2_2_resume(struct radeon_device *rdev);
867void uvd_v2_2_fence_emit(struct radeon_device *rdev,
868 struct radeon_fence *fence);
869
870/* uvd v3.1 */
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]871bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]872 struct radeon_ring *ring,
873 struct radeon_semaphore *semaphore,
874 bool emit_wait);
875
876/* uvd v4.2 */
877int uvd_v4_2_resume(struct radeon_device *rdev);
878
Christian Königd93f7932013-05-23 12:10:04 +0200[diff] [blame]879/* vce v1.0 */
880uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
881 struct radeon_ring *ring);
882uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
883 struct radeon_ring *ring);
884void vce_v1_0_set_wptr(struct radeon_device *rdev,
885 struct radeon_ring *ring);
886int vce_v1_0_init(struct radeon_device *rdev);
887int vce_v1_0_start(struct radeon_device *rdev);
888
889/* vce v2.0 */
890int vce_v2_0_resume(struct radeon_device *rdev);
891
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]892#endif