blob: 1ace6b6fd2861668a5fc9b49be906ed44502ca9b [file] [log] [blame]
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -08001/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#ifndef __H_VIDC_HFI_HELPER_H__
15#define __H_VIDC_HFI_HELPER_H__
16
17#define HFI_COMMON_BASE (0)
18#define HFI_OX_BASE (0x01000000)
19
20#define HFI_VIDEO_DOMAIN_ENCODER (HFI_COMMON_BASE + 0x1)
21#define HFI_VIDEO_DOMAIN_DECODER (HFI_COMMON_BASE + 0x2)
22#define HFI_VIDEO_DOMAIN_VPE (HFI_COMMON_BASE + 0x4)
23#define HFI_VIDEO_DOMAIN_MBI (HFI_COMMON_BASE + 0x8)
24
25#define HFI_DOMAIN_BASE_COMMON (HFI_COMMON_BASE + 0)
26#define HFI_DOMAIN_BASE_VDEC (HFI_COMMON_BASE + 0x01000000)
27#define HFI_DOMAIN_BASE_VENC (HFI_COMMON_BASE + 0x02000000)
28#define HFI_DOMAIN_BASE_VPE (HFI_COMMON_BASE + 0x03000000)
29
30#define HFI_VIDEO_ARCH_OX (HFI_COMMON_BASE + 0x1)
31
32#define HFI_ARCH_COMMON_OFFSET (0)
33#define HFI_ARCH_OX_OFFSET (0x00200000)
34
35#define HFI_CMD_START_OFFSET (0x00010000)
36#define HFI_MSG_START_OFFSET (0x00020000)
37
38#define HFI_ERR_NONE HFI_COMMON_BASE
39#define HFI_ERR_SYS_FATAL (HFI_COMMON_BASE + 0x1)
40#define HFI_ERR_SYS_INVALID_PARAMETER (HFI_COMMON_BASE + 0x2)
41#define HFI_ERR_SYS_VERSION_MISMATCH (HFI_COMMON_BASE + 0x3)
42#define HFI_ERR_SYS_INSUFFICIENT_RESOURCES (HFI_COMMON_BASE + 0x4)
43#define HFI_ERR_SYS_MAX_SESSIONS_REACHED (HFI_COMMON_BASE + 0x5)
44#define HFI_ERR_SYS_UNSUPPORTED_CODEC (HFI_COMMON_BASE + 0x6)
45#define HFI_ERR_SYS_SESSION_IN_USE (HFI_COMMON_BASE + 0x7)
46#define HFI_ERR_SYS_SESSION_ID_OUT_OF_RANGE (HFI_COMMON_BASE + 0x8)
47#define HFI_ERR_SYS_UNSUPPORTED_DOMAIN (HFI_COMMON_BASE + 0x9)
48
49#define HFI_ERR_SESSION_FATAL (HFI_COMMON_BASE + 0x1001)
50#define HFI_ERR_SESSION_INVALID_PARAMETER (HFI_COMMON_BASE + 0x1002)
51#define HFI_ERR_SESSION_BAD_POINTER (HFI_COMMON_BASE + 0x1003)
52#define HFI_ERR_SESSION_INVALID_SESSION_ID (HFI_COMMON_BASE + 0x1004)
53#define HFI_ERR_SESSION_INVALID_STREAM_ID (HFI_COMMON_BASE + 0x1005)
54#define HFI_ERR_SESSION_INCORRECT_STATE_OPERATION \
55 (HFI_COMMON_BASE + 0x1006)
56#define HFI_ERR_SESSION_UNSUPPORTED_PROPERTY (HFI_COMMON_BASE + 0x1007)
57
58#define HFI_ERR_SESSION_UNSUPPORTED_SETTING (HFI_COMMON_BASE + 0x1008)
59
60#define HFI_ERR_SESSION_INSUFFICIENT_RESOURCES (HFI_COMMON_BASE + 0x1009)
61
62#define HFI_ERR_SESSION_STREAM_CORRUPT_OUTPUT_STALLED \
63 (HFI_COMMON_BASE + 0x100A)
64
65#define HFI_ERR_SESSION_STREAM_CORRUPT (HFI_COMMON_BASE + 0x100B)
66#define HFI_ERR_SESSION_ENC_OVERFLOW (HFI_COMMON_BASE + 0x100C)
67#define HFI_ERR_SESSION_UNSUPPORTED_STREAM (HFI_COMMON_BASE + 0x100D)
68#define HFI_ERR_SESSION_CMDSIZE (HFI_COMMON_BASE + 0x100E)
69#define HFI_ERR_SESSION_UNSUPPORT_CMD (HFI_COMMON_BASE + 0x100F)
70#define HFI_ERR_SESSION_UNSUPPORT_BUFFERTYPE (HFI_COMMON_BASE + 0x1010)
71#define HFI_ERR_SESSION_BUFFERCOUNT_TOOSMALL (HFI_COMMON_BASE + 0x1011)
72#define HFI_ERR_SESSION_INVALID_SCALE_FACTOR (HFI_COMMON_BASE + 0x1012)
73#define HFI_ERR_SESSION_UPSCALE_NOT_SUPPORTED (HFI_COMMON_BASE + 0x1013)
74
75#define HFI_EVENT_SYS_ERROR (HFI_COMMON_BASE + 0x1)
76#define HFI_EVENT_SESSION_ERROR (HFI_COMMON_BASE + 0x2)
77
78#define HFI_VIDEO_CODEC_H264 0x00000002
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -080079#define HFI_VIDEO_CODEC_MPEG1 0x00000008
80#define HFI_VIDEO_CODEC_MPEG2 0x00000010
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -080081#define HFI_VIDEO_CODEC_VP8 0x00001000
82#define HFI_VIDEO_CODEC_HEVC 0x00002000
83#define HFI_VIDEO_CODEC_VP9 0x00004000
84#define HFI_VIDEO_CODEC_HEVC_HYBRID 0x80000000
85
Umesh Pandey3cfce632017-03-02 13:56:18 -080086#define HFI_PROFILE_UNKNOWN 0x00000000
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -080087#define HFI_H264_PROFILE_BASELINE 0x00000001
88#define HFI_H264_PROFILE_MAIN 0x00000002
89#define HFI_H264_PROFILE_HIGH 0x00000004
90#define HFI_H264_PROFILE_STEREO_HIGH 0x00000008
91#define HFI_H264_PROFILE_MULTIVIEW_HIGH 0x00000010
92#define HFI_H264_PROFILE_CONSTRAINED_BASE 0x00000020
93#define HFI_H264_PROFILE_CONSTRAINED_HIGH 0x00000040
94
Umesh Pandey3cfce632017-03-02 13:56:18 -080095#define HFI_LEVEL_UNKNOWN 0x00000000
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -080096#define HFI_H264_LEVEL_1 0x00000001
97#define HFI_H264_LEVEL_1b 0x00000002
98#define HFI_H264_LEVEL_11 0x00000004
99#define HFI_H264_LEVEL_12 0x00000008
100#define HFI_H264_LEVEL_13 0x00000010
101#define HFI_H264_LEVEL_2 0x00000020
102#define HFI_H264_LEVEL_21 0x00000040
103#define HFI_H264_LEVEL_22 0x00000080
104#define HFI_H264_LEVEL_3 0x00000100
105#define HFI_H264_LEVEL_31 0x00000200
106#define HFI_H264_LEVEL_32 0x00000400
107#define HFI_H264_LEVEL_4 0x00000800
108#define HFI_H264_LEVEL_41 0x00001000
109#define HFI_H264_LEVEL_42 0x00002000
110#define HFI_H264_LEVEL_5 0x00004000
111#define HFI_H264_LEVEL_51 0x00008000
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800112#define HFI_H264_LEVEL_52 0x00010000
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800113
114#define HFI_MPEG2_PROFILE_SIMPLE 0x00000001
115#define HFI_MPEG2_PROFILE_MAIN 0x00000002
116#define HFI_MPEG2_PROFILE_422 0x00000004
117#define HFI_MPEG2_PROFILE_SNR 0x00000008
118#define HFI_MPEG2_PROFILE_SPATIAL 0x00000010
119#define HFI_MPEG2_PROFILE_HIGH 0x00000020
120
121#define HFI_MPEG2_LEVEL_LL 0x00000001
122#define HFI_MPEG2_LEVEL_ML 0x00000002
123#define HFI_MPEG2_LEVEL_H14 0x00000004
124#define HFI_MPEG2_LEVEL_HL 0x00000008
125
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800126#define HFI_VPX_PROFILE_SIMPLE 0x00000001
127#define HFI_VPX_PROFILE_ADVANCED 0x00000002
128#define HFI_VPX_PROFILE_VERSION_0 0x00000004
129#define HFI_VPX_PROFILE_VERSION_1 0x00000008
130#define HFI_VPX_PROFILE_VERSION_2 0x00000010
131#define HFI_VPX_PROFILE_VERSION_3 0x00000020
132
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800133#define HFI_HEVC_PROFILE_MAIN 0x00000001
134#define HFI_HEVC_PROFILE_MAIN10 0x00000002
135#define HFI_HEVC_PROFILE_MAIN_STILL_PIC 0x00000004
136
137#define HFI_HEVC_LEVEL_1 0x00000001
138#define HFI_HEVC_LEVEL_2 0x00000002
139#define HFI_HEVC_LEVEL_21 0x00000004
140#define HFI_HEVC_LEVEL_3 0x00000008
141#define HFI_HEVC_LEVEL_31 0x00000010
142#define HFI_HEVC_LEVEL_4 0x00000020
143#define HFI_HEVC_LEVEL_41 0x00000040
144#define HFI_HEVC_LEVEL_5 0x00000080
145#define HFI_HEVC_LEVEL_51 0x00000100
146#define HFI_HEVC_LEVEL_52 0x00000200
147#define HFI_HEVC_LEVEL_6 0x00000400
148#define HFI_HEVC_LEVEL_61 0x00000800
149#define HFI_HEVC_LEVEL_62 0x00001000
150
151#define HFI_HEVC_TIER_MAIN 0x1
152#define HFI_HEVC_TIER_HIGH0 0x2
153
154#define HFI_BUFFER_INPUT (HFI_COMMON_BASE + 0x1)
155#define HFI_BUFFER_OUTPUT (HFI_COMMON_BASE + 0x2)
156#define HFI_BUFFER_OUTPUT2 (HFI_COMMON_BASE + 0x3)
157#define HFI_BUFFER_INTERNAL_PERSIST (HFI_COMMON_BASE + 0x4)
158#define HFI_BUFFER_INTERNAL_PERSIST_1 (HFI_COMMON_BASE + 0x5)
159
160#define HFI_BITDEPTH_8 (HFI_COMMON_BASE + 0x0)
161#define HFI_BITDEPTH_9 (HFI_COMMON_BASE + 0x1)
162#define HFI_BITDEPTH_10 (HFI_COMMON_BASE + 0x2)
163
164#define HFI_VENC_PERFMODE_MAX_QUALITY 0x1
165#define HFI_VENC_PERFMODE_POWER_SAVE 0x2
166
167struct hfi_buffer_info {
168 u32 buffer_addr;
169 u32 extra_data_addr;
170};
171
172#define HFI_PROPERTY_SYS_COMMON_START \
173 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x0000)
174#define HFI_PROPERTY_SYS_DEBUG_CONFIG \
175 (HFI_PROPERTY_SYS_COMMON_START + 0x001)
176#define HFI_PROPERTY_SYS_RESOURCE_OCMEM_REQUIREMENT_INFO \
177 (HFI_PROPERTY_SYS_COMMON_START + 0x002)
178#define HFI_PROPERTY_SYS_CONFIG_VCODEC_CLKFREQ \
179 (HFI_PROPERTY_SYS_COMMON_START + 0x003)
180#define HFI_PROPERTY_SYS_IDLE_INDICATOR \
181 (HFI_PROPERTY_SYS_COMMON_START + 0x004)
182#define HFI_PROPERTY_SYS_CODEC_POWER_PLANE_CTRL \
183 (HFI_PROPERTY_SYS_COMMON_START + 0x005)
184#define HFI_PROPERTY_SYS_IMAGE_VERSION \
185 (HFI_PROPERTY_SYS_COMMON_START + 0x006)
186#define HFI_PROPERTY_SYS_CONFIG_COVERAGE \
187 (HFI_PROPERTY_SYS_COMMON_START + 0x007)
188
189#define HFI_PROPERTY_PARAM_COMMON_START \
190 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x1000)
191#define HFI_PROPERTY_PARAM_FRAME_SIZE \
192 (HFI_PROPERTY_PARAM_COMMON_START + 0x001)
193#define HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO \
194 (HFI_PROPERTY_PARAM_COMMON_START + 0x002)
195#define HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT \
196 (HFI_PROPERTY_PARAM_COMMON_START + 0x003)
197#define HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SUPPORTED \
198 (HFI_PROPERTY_PARAM_COMMON_START + 0x004)
199#define HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT \
200 (HFI_PROPERTY_PARAM_COMMON_START + 0x005)
201#define HFI_PROPERTY_PARAM_PROFILE_LEVEL_SUPPORTED \
202 (HFI_PROPERTY_PARAM_COMMON_START + 0x006)
203#define HFI_PROPERTY_PARAM_CAPABILITY_SUPPORTED \
204 (HFI_PROPERTY_PARAM_COMMON_START + 0x007)
205#define HFI_PROPERTY_PARAM_PROPERTIES_SUPPORTED \
206 (HFI_PROPERTY_PARAM_COMMON_START + 0x008)
207#define HFI_PROPERTY_PARAM_CODEC_SUPPORTED \
208 (HFI_PROPERTY_PARAM_COMMON_START + 0x009)
209#define HFI_PROPERTY_PARAM_NAL_STREAM_FORMAT_SUPPORTED \
210 (HFI_PROPERTY_PARAM_COMMON_START + 0x00A)
211#define HFI_PROPERTY_PARAM_NAL_STREAM_FORMAT_SELECT \
212 (HFI_PROPERTY_PARAM_COMMON_START + 0x00B)
213#define HFI_PROPERTY_PARAM_MULTI_VIEW_FORMAT \
214 (HFI_PROPERTY_PARAM_COMMON_START + 0x00C)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800215#define HFI_PROPERTY_PARAM_CODEC_MASK_SUPPORTED \
216 (HFI_PROPERTY_PARAM_COMMON_START + 0x00E)
217#define HFI_PROPERTY_PARAM_MVC_BUFFER_LAYOUT \
218 (HFI_PROPERTY_PARAM_COMMON_START + 0x00F)
219#define HFI_PROPERTY_PARAM_MAX_SESSIONS_SUPPORTED \
220 (HFI_PROPERTY_PARAM_COMMON_START + 0x010)
221
222#define HFI_PROPERTY_CONFIG_COMMON_START \
223 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x2000)
224#define HFI_PROPERTY_CONFIG_FRAME_RATE \
225 (HFI_PROPERTY_CONFIG_COMMON_START + 0x001)
226
227#define HFI_PROPERTY_PARAM_VDEC_COMMON_START \
228 (HFI_DOMAIN_BASE_VDEC + HFI_ARCH_COMMON_OFFSET + 0x3000)
229#define HFI_PROPERTY_PARAM_VDEC_MULTI_STREAM \
230 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x001)
231#define HFI_PROPERTY_PARAM_VDEC_CONCEAL_COLOR \
232 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x002)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800233#define HFI_PROPERTY_PARAM_VDEC_PIXEL_BITDEPTH \
234 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x007)
235#define HFI_PROPERTY_PARAM_VDEC_PIC_STRUCT \
236 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x009)
237#define HFI_PROPERTY_PARAM_VDEC_COLOUR_SPACE \
238 (HFI_PROPERTY_PARAM_VDEC_COMMON_START + 0x00A)
239
240
241#define HFI_PROPERTY_CONFIG_VDEC_COMMON_START \
242 (HFI_DOMAIN_BASE_VDEC + HFI_ARCH_COMMON_OFFSET + 0x4000)
243
244#define HFI_PROPERTY_PARAM_VENC_COMMON_START \
245 (HFI_DOMAIN_BASE_VENC + HFI_ARCH_COMMON_OFFSET + 0x5000)
246#define HFI_PROPERTY_PARAM_VENC_SLICE_DELIVERY_MODE \
247 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x001)
248#define HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL \
249 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x002)
250#define HFI_PROPERTY_PARAM_VENC_H264_DEBLOCK_CONTROL \
251 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x003)
252#define HFI_PROPERTY_PARAM_VENC_RATE_CONTROL \
253 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x004)
Umesh Pandey3cfce632017-03-02 13:56:18 -0800254#define HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE \
255 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x009)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800256#define HFI_PROPERTY_PARAM_VENC_OPEN_GOP \
257 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00C)
258#define HFI_PROPERTY_PARAM_VENC_INTRA_REFRESH \
259 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00D)
260#define HFI_PROPERTY_PARAM_VENC_MULTI_SLICE_CONTROL \
261 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00E)
262#define HFI_PROPERTY_PARAM_VENC_VBV_HRD_BUF_SIZE \
263 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00F)
264#define HFI_PROPERTY_PARAM_VENC_QUALITY_VS_SPEED \
265 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x010)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800266#define HFI_PROPERTY_PARAM_VENC_H264_SPS_ID \
267 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x014)
268#define HFI_PROPERTY_PARAM_VENC_H264_PPS_ID \
269 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x015)
270#define HFI_PROPERTY_PARAM_VENC_H264_GENERATE_AUDNAL \
271 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x016)
272#define HFI_PROPERTY_PARAM_VENC_ASPECT_RATIO \
273 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x017)
274#define HFI_PROPERTY_PARAM_VENC_NUMREF \
275 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x018)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800276#define HFI_PROPERTY_PARAM_VENC_H264_NAL_SVC_EXT \
277 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01B)
278#define HFI_PROPERTY_PARAM_VENC_LTRMODE \
279 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01C)
280#define HFI_PROPERTY_PARAM_VENC_VIDEO_SIGNAL_INFO \
281 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01D)
282#define HFI_PROPERTY_PARAM_VENC_H264_VUI_TIMING_INFO \
283 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01E)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800284#define HFI_PROPERTY_PARAM_VENC_MAX_NUM_B_FRAMES \
285 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x020)
286#define HFI_PROPERTY_PARAM_VENC_H264_VUI_BITSTREAM_RESTRC \
287 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x021)
288#define HFI_PROPERTY_PARAM_VENC_LOW_LATENCY_MODE \
289 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x022)
290#define HFI_PROPERTY_PARAM_VENC_PRESERVE_TEXT_QUALITY \
291 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x023)
292#define HFI_PROPERTY_PARAM_VENC_H264_8X8_TRANSFORM \
293 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x025)
294#define HFI_PROPERTY_PARAM_VENC_HIER_P_MAX_NUM_ENH_LAYER \
295 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x026)
296#define HFI_PROPERTY_PARAM_VENC_DISABLE_RC_TIMESTAMP \
297 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x027)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800298#define HFI_PROPERTY_PARAM_VENC_VPX_ERROR_RESILIENCE_MODE \
299 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x029)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800300#define HFI_PROPERTY_PARAM_VENC_HIER_B_MAX_NUM_ENH_LAYER \
301 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x02C)
302#define HFI_PROPERTY_PARAM_VENC_HIER_P_HYBRID_MODE \
303 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x02F)
304#define HFI_PROPERTY_PARAM_VENC_BITRATE_TYPE \
305 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x031)
306#define HFI_PROPERTY_PARAM_VENC_VQZIP_SEI_TYPE \
307 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x033)
308#define HFI_PROPERTY_PARAM_VENC_IFRAMESIZE \
309 (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x034)
310
311#define HFI_PROPERTY_CONFIG_VENC_COMMON_START \
312 (HFI_DOMAIN_BASE_VENC + HFI_ARCH_COMMON_OFFSET + 0x6000)
313#define HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE \
314 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x001)
315#define HFI_PROPERTY_CONFIG_VENC_IDR_PERIOD \
316 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x002)
317#define HFI_PROPERTY_CONFIG_VENC_INTRA_PERIOD \
318 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x003)
319#define HFI_PROPERTY_CONFIG_VENC_REQUEST_SYNC_FRAME \
320 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x004)
321#define HFI_PROPERTY_CONFIG_VENC_SLICE_SIZE \
322 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x005)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800323#define HFI_PROPERTY_PARAM_VPE_COMMON_START \
324 (HFI_DOMAIN_BASE_VPE + HFI_ARCH_COMMON_OFFSET + 0x7000)
325#define HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER \
326 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x008)
327#define HFI_PROPERTY_CONFIG_VENC_MARKLTRFRAME \
328 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x009)
329#define HFI_PROPERTY_CONFIG_VENC_USELTRFRAME \
330 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00A)
331#define HFI_PROPERTY_CONFIG_VENC_HIER_P_ENH_LAYER \
332 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00B)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800333#define HFI_PROPERTY_CONFIG_VENC_PERF_MODE \
334 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00E)
335#define HFI_PROPERTY_CONFIG_VENC_BASELAYER_PRIORITYID \
336 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00F)
Praneeth Paladugu7fbd2792017-01-27 13:39:03 -0800337#define HFI_PROPERTY_CONFIG_VENC_SESSION_QP \
338 (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x012)
339
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800340
341#define HFI_PROPERTY_CONFIG_VPE_COMMON_START \
342 (HFI_DOMAIN_BASE_VPE + HFI_ARCH_COMMON_OFFSET + 0x8000)
343#define HFI_PROPERTY_CONFIG_VENC_BLUR_FRAME_SIZE \
344 (HFI_PROPERTY_CONFIG_COMMON_START + 0x010)
345#define HFI_PROPERTY_CONFIG_VPE_DEINTERLACE \
346 (HFI_PROPERTY_CONFIG_VPE_COMMON_START + 0x001)
347#define HFI_PROPERTY_CONFIG_VPE_OPERATIONS \
348 (HFI_PROPERTY_CONFIG_VPE_COMMON_START + 0x002)
349
350struct hfi_pic_struct {
351 u32 progressive_only;
352};
353
354struct hfi_bitrate {
355 u32 bit_rate;
356 u32 layer_id;
357};
358
359struct hfi_colour_space {
360 u32 colour_space;
361};
362
363#define HFI_CAPABILITY_FRAME_WIDTH (HFI_COMMON_BASE + 0x1)
364#define HFI_CAPABILITY_FRAME_HEIGHT (HFI_COMMON_BASE + 0x2)
365#define HFI_CAPABILITY_MBS_PER_FRAME (HFI_COMMON_BASE + 0x3)
366#define HFI_CAPABILITY_MBS_PER_SECOND (HFI_COMMON_BASE + 0x4)
367#define HFI_CAPABILITY_FRAMERATE (HFI_COMMON_BASE + 0x5)
368#define HFI_CAPABILITY_SCALE_X (HFI_COMMON_BASE + 0x6)
369#define HFI_CAPABILITY_SCALE_Y (HFI_COMMON_BASE + 0x7)
370#define HFI_CAPABILITY_BITRATE (HFI_COMMON_BASE + 0x8)
371#define HFI_CAPABILITY_BFRAME (HFI_COMMON_BASE + 0x9)
372#define HFI_CAPABILITY_PEAKBITRATE (HFI_COMMON_BASE + 0xa)
373#define HFI_CAPABILITY_HIER_P_NUM_ENH_LAYERS (HFI_COMMON_BASE + 0x10)
374#define HFI_CAPABILITY_ENC_LTR_COUNT (HFI_COMMON_BASE + 0x11)
375#define HFI_CAPABILITY_CP_OUTPUT2_THRESH (HFI_COMMON_BASE + 0x12)
376#define HFI_CAPABILITY_HIER_B_NUM_ENH_LAYERS (HFI_COMMON_BASE + 0x13)
377#define HFI_CAPABILITY_LCU_SIZE (HFI_COMMON_BASE + 0x14)
378#define HFI_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS (HFI_COMMON_BASE + 0x15)
379#define HFI_CAPABILITY_MBS_PER_SECOND_POWERSAVE (HFI_COMMON_BASE + 0x16)
Praneeth Paladugu520c7592017-01-26 13:53:14 -0800380#define HFI_CAPABILITY_EXTRADATA (HFI_COMMON_BASE + 0X17)
381#define HFI_CAPABILITY_PROFILE (HFI_COMMON_BASE + 0X18)
382#define HFI_CAPABILITY_LEVEL (HFI_COMMON_BASE + 0X19)
383#define HFI_CAPABILITY_I_FRAME_QP (HFI_COMMON_BASE + 0X20)
384#define HFI_CAPABILITY_P_FRAME_QP (HFI_COMMON_BASE + 0X21)
385#define HFI_CAPABILITY_B_FRAME_QP (HFI_COMMON_BASE + 0X22)
386#define HFI_CAPABILITY_RATE_CONTROL_MODES (HFI_COMMON_BASE + 0X23)
387#define HFI_CAPABILITY_BLUR_WIDTH (HFI_COMMON_BASE + 0X24)
388#define HFI_CAPABILITY_BLUR_HEIGHT (HFI_COMMON_BASE + 0X25)
389#define HFI_CAPABILITY_SLICE_DELIVERY_MODES (HFI_COMMON_BASE + 0X26)
390#define HFI_CAPABILITY_SLICE_BYTE (HFI_COMMON_BASE + 0X27)
391#define HFI_CAPABILITY_SLICE_MB (HFI_COMMON_BASE + 0X28)
392#define HFI_CAPABILITY_SECURE (HFI_COMMON_BASE + 0X29)
393#define HFI_CAPABILITY_MAX_NUM_B_FRAMES (HFI_COMMON_BASE + 0X2A)
394#define HFI_CAPABILITY_MAX_VIDEOCORES (HFI_COMMON_BASE + 0X2B)
395#define HFI_CAPABILITY_MAX_WORKMODES (HFI_COMMON_BASE + 0X2C)
396#define HFI_CAPABILITY_UBWC_CR_STATS (HFI_COMMON_BASE + 0X2D)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800397
398struct hfi_capability_supported {
399 u32 capability_type;
400 u32 min;
401 u32 max;
402 u32 step_size;
403};
404
405struct hfi_capability_supported_info {
406 u32 num_capabilities;
407 struct hfi_capability_supported rg_data[1];
408};
409
410#define HFI_DEBUG_MSG_LOW 0x00000001
411#define HFI_DEBUG_MSG_MEDIUM 0x00000002
412#define HFI_DEBUG_MSG_HIGH 0x00000004
413#define HFI_DEBUG_MSG_ERROR 0x00000008
414#define HFI_DEBUG_MSG_FATAL 0x00000010
415#define HFI_DEBUG_MSG_PERF 0x00000020
416
417#define HFI_DEBUG_MODE_QUEUE 0x00000001
418#define HFI_DEBUG_MODE_QDSS 0x00000002
419
420struct hfi_debug_config {
421 u32 debug_config;
422 u32 debug_mode;
423};
424
425struct hfi_enable {
426 u32 enable;
427};
428
429#define HFI_H264_DB_MODE_DISABLE (HFI_COMMON_BASE + 0x1)
430#define HFI_H264_DB_MODE_SKIP_SLICE_BOUNDARY \
431 (HFI_COMMON_BASE + 0x2)
432#define HFI_H264_DB_MODE_ALL_BOUNDARY (HFI_COMMON_BASE + 0x3)
433
434struct hfi_h264_db_control {
435 u32 mode;
436 u32 slice_alpha_offset;
437 u32 slice_beta_offset;
438};
439
440#define HFI_H264_ENTROPY_CAVLC (HFI_COMMON_BASE + 0x1)
441#define HFI_H264_ENTROPY_CABAC (HFI_COMMON_BASE + 0x2)
442
443#define HFI_H264_CABAC_MODEL_0 (HFI_COMMON_BASE + 0x1)
444#define HFI_H264_CABAC_MODEL_1 (HFI_COMMON_BASE + 0x2)
445#define HFI_H264_CABAC_MODEL_2 (HFI_COMMON_BASE + 0x3)
446
447struct hfi_h264_entropy_control {
448 u32 entropy_mode;
449 u32 cabac_model;
450};
451
452struct hfi_frame_rate {
453 u32 buffer_type;
454 u32 frame_rate;
455};
456
457#define HFI_INTRA_REFRESH_NONE (HFI_COMMON_BASE + 0x1)
458#define HFI_INTRA_REFRESH_CYCLIC (HFI_COMMON_BASE + 0x2)
459#define HFI_INTRA_REFRESH_ADAPTIVE (HFI_COMMON_BASE + 0x3)
460#define HFI_INTRA_REFRESH_CYCLIC_ADAPTIVE (HFI_COMMON_BASE + 0x4)
461#define HFI_INTRA_REFRESH_RANDOM (HFI_COMMON_BASE + 0x5)
462
463struct hfi_intra_refresh {
464 u32 mode;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800465 u32 mbs;
466};
467
468struct hfi_idr_period {
469 u32 idr_period;
470};
471
472struct hfi_operations_type {
473 u32 rotation;
474 u32 flip;
475};
476
477struct hfi_max_num_b_frames {
478 u32 max_num_b_frames;
479};
480
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800481struct hfi_conceal_color {
482 u32 conceal_color;
483};
484
485struct hfi_intra_period {
486 u32 pframes;
487 u32 bframes;
488};
489
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800490struct hfi_multi_stream {
491 u32 buffer_type;
492 u32 enable;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800493};
494
495struct hfi_multi_view_format {
496 u32 views;
497 u32 rg_view_order[1];
498};
499
500#define HFI_MULTI_SLICE_OFF (HFI_COMMON_BASE + 0x1)
501#define HFI_MULTI_SLICE_BY_MB_COUNT (HFI_COMMON_BASE + 0x2)
502#define HFI_MULTI_SLICE_BY_BYTE_COUNT (HFI_COMMON_BASE + 0x3)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800503
504struct hfi_multi_slice_control {
505 u32 multi_slice;
506 u32 slice_size;
507};
508
509#define HFI_NAL_FORMAT_STARTCODES 0x00000001
510#define HFI_NAL_FORMAT_ONE_NAL_PER_BUFFER 0x00000002
511#define HFI_NAL_FORMAT_ONE_BYTE_LENGTH 0x00000004
512#define HFI_NAL_FORMAT_TWO_BYTE_LENGTH 0x00000008
513#define HFI_NAL_FORMAT_FOUR_BYTE_LENGTH 0x00000010
514
515struct hfi_nal_stream_format_supported {
516 u32 nal_stream_format_supported;
517};
518
519struct hfi_nal_stream_format_select {
520 u32 nal_stream_format_select;
521};
522#define HFI_PICTURE_TYPE_I 0x01
523#define HFI_PICTURE_TYPE_P 0x02
524#define HFI_PICTURE_TYPE_B 0x04
525#define HFI_PICTURE_TYPE_IDR 0x08
526#define HFI_PICTURE_TYPE_CRA 0x10
527
528struct hfi_profile_level {
529 u32 profile;
530 u32 level;
531};
532
533struct hfi_profile_level_supported {
534 u32 profile_count;
535 struct hfi_profile_level rg_profile_level[1];
536};
537
538struct hfi_quality_vs_speed {
539 u32 quality_vs_speed;
540};
541
542struct hfi_quantization {
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800543 u32 qp_packed;
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800544 u32 layer_id;
Umesh Pandey3cfce632017-03-02 13:56:18 -0800545 u32 reserved[4];
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800546};
547
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800548struct hfi_quantization_range {
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800549 struct hfi_quantization min_qp;
550 struct hfi_quantization max_qp;
Umesh Pandey3cfce632017-03-02 13:56:18 -0800551 u32 reserved[4];
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800552};
553
554#define HFI_LTR_MODE_DISABLE 0x0
555#define HFI_LTR_MODE_MANUAL 0x1
556#define HFI_LTR_MODE_PERIODIC 0x2
557
558struct hfi_ltr_mode {
559 u32 ltr_mode;
560 u32 ltr_count;
561 u32 trust_mode;
562};
563
564struct hfi_ltr_use {
565 u32 ref_ltr;
566 u32 use_constrnt;
567 u32 frames;
568};
569
570struct hfi_ltr_mark {
571 u32 mark_frame;
572};
573
574struct hfi_frame_size {
575 u32 buffer_type;
576 u32 width;
577 u32 height;
578};
579
580struct hfi_video_signal_metadata {
581 u32 enable;
582 u32 video_format;
583 u32 video_full_range;
584 u32 color_description;
585 u32 color_primaries;
586 u32 transfer_characteristics;
587 u32 matrix_coeffs;
588};
589
590struct hfi_h264_vui_timing_info {
591 u32 enable;
592 u32 fixed_frame_rate;
593 u32 time_scale;
594};
595
596struct hfi_bit_depth {
597 u32 buffer_type;
598 u32 bit_depth;
599};
600
601struct hfi_picture_type {
602 u32 is_sync_frame;
603 u32 picture_type;
604};
605
606/* Base Offset for UBWC color formats */
607#define HFI_COLOR_FORMAT_UBWC_BASE (0x8000)
608/* Base Offset for 10-bit color formats */
609#define HFI_COLOR_FORMAT_10_BIT_BASE (0x4000)
610
611#define HFI_COLOR_FORMAT_MONOCHROME (HFI_COMMON_BASE + 0x1)
612#define HFI_COLOR_FORMAT_NV12 (HFI_COMMON_BASE + 0x2)
613#define HFI_COLOR_FORMAT_NV21 (HFI_COMMON_BASE + 0x3)
614#define HFI_COLOR_FORMAT_NV12_4x4TILE (HFI_COMMON_BASE + 0x4)
615#define HFI_COLOR_FORMAT_NV21_4x4TILE (HFI_COMMON_BASE + 0x5)
616#define HFI_COLOR_FORMAT_YUYV (HFI_COMMON_BASE + 0x6)
617#define HFI_COLOR_FORMAT_YVYU (HFI_COMMON_BASE + 0x7)
618#define HFI_COLOR_FORMAT_UYVY (HFI_COMMON_BASE + 0x8)
619#define HFI_COLOR_FORMAT_VYUY (HFI_COMMON_BASE + 0x9)
620#define HFI_COLOR_FORMAT_RGB565 (HFI_COMMON_BASE + 0xA)
621#define HFI_COLOR_FORMAT_BGR565 (HFI_COMMON_BASE + 0xB)
622#define HFI_COLOR_FORMAT_RGB888 (HFI_COMMON_BASE + 0xC)
623#define HFI_COLOR_FORMAT_BGR888 (HFI_COMMON_BASE + 0xD)
624#define HFI_COLOR_FORMAT_YUV444 (HFI_COMMON_BASE + 0xE)
625#define HFI_COLOR_FORMAT_RGBA8888 (HFI_COMMON_BASE + 0x10)
626
Chinmay Sawarkar2de3f772017-02-07 12:03:44 -0800627#define HFI_COLOR_FORMAT_YUV420_TP10 \
Umesh Pandey3cfce632017-03-02 13:56:18 -0800628 (HFI_COLOR_FORMAT_10_BIT_BASE + HFI_COLOR_FORMAT_NV12)
629#define HFI_COLOR_FORMAT_P010 \
630 (HFI_COLOR_FORMAT_10_BIT_BASE + HFI_COLOR_FORMAT_NV12 + 0x1)
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800631
632#define HFI_COLOR_FORMAT_NV12_UBWC \
633 (HFI_COLOR_FORMAT_UBWC_BASE + HFI_COLOR_FORMAT_NV12)
634
635#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC \
636 (HFI_COLOR_FORMAT_UBWC_BASE + HFI_COLOR_FORMAT_YUV420_TP10)
637
638#define HFI_COLOR_FORMAT_RGBA8888_UBWC \
639 (HFI_COLOR_FORMAT_UBWC_BASE + HFI_COLOR_FORMAT_RGBA8888)
640
641#define HFI_MAX_MATRIX_COEFFS 9
642#define HFI_MAX_BIAS_COEFFS 3
643#define HFI_MAX_LIMIT_COEFFS 6
644
645#define HFI_STATISTICS_MODE_DEFAULT 0x10
646#define HFI_STATISTICS_MODE_1 0x11
647#define HFI_STATISTICS_MODE_2 0x12
648#define HFI_STATISTICS_MODE_3 0x13
649
650struct hfi_uncompressed_format_select {
651 u32 buffer_type;
652 u32 format;
653};
654
655struct hfi_uncompressed_format_supported {
656 u32 buffer_type;
657 u32 format_entries;
658 u32 rg_format_info[1];
659};
660
661struct hfi_uncompressed_plane_actual {
662 u32 actual_stride;
663 u32 actual_plane_buffer_height;
664};
665
666struct hfi_uncompressed_plane_actual_info {
667 u32 buffer_type;
668 u32 num_planes;
669 struct hfi_uncompressed_plane_actual rg_plane_format[1];
670};
671
672struct hfi_uncompressed_plane_constraints {
673 u32 stride_multiples;
674 u32 max_stride;
675 u32 min_plane_buffer_height_multiple;
676 u32 buffer_alignment;
677};
678
679struct hfi_uncompressed_plane_info {
680 u32 format;
681 u32 num_planes;
682 struct hfi_uncompressed_plane_constraints rg_plane_format[1];
683};
684
685struct hfi_codec_supported {
686 u32 decoder_codec_supported;
687 u32 encoder_codec_supported;
688};
689
690struct hfi_properties_supported {
691 u32 num_properties;
692 u32 rg_properties[1];
693};
694
695struct hfi_max_sessions_supported {
696 u32 max_sessions;
697};
698
699struct hfi_vpe_color_space_conversion {
700 u32 csc_matrix[HFI_MAX_MATRIX_COEFFS];
701 u32 csc_bias[HFI_MAX_BIAS_COEFFS];
702 u32 csc_limit[HFI_MAX_LIMIT_COEFFS];
703};
704
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800705#define HFI_ROTATE_NONE (HFI_COMMON_BASE + 0x1)
706#define HFI_ROTATE_90 (HFI_COMMON_BASE + 0x2)
707#define HFI_ROTATE_180 (HFI_COMMON_BASE + 0x3)
708#define HFI_ROTATE_270 (HFI_COMMON_BASE + 0x4)
709
710#define HFI_FLIP_NONE (HFI_COMMON_BASE + 0x1)
711#define HFI_FLIP_HORIZONTAL (HFI_COMMON_BASE + 0x2)
712#define HFI_FLIP_VERTICAL (HFI_COMMON_BASE + 0x3)
713
714struct hfi_operations {
715 u32 rotate;
716 u32 flip;
717};
718
719#define HFI_RESOURCE_OCMEM 0x00000001
720
721struct hfi_resource_ocmem {
722 u32 size;
723 u32 mem;
724};
725
726struct hfi_resource_ocmem_requirement {
727 u32 session_domain;
728 u32 width;
729 u32 height;
730 u32 size;
731};
732
733struct hfi_resource_ocmem_requirement_info {
734 u32 num_entries;
735 struct hfi_resource_ocmem_requirement rg_requirements[1];
736};
737
738struct hfi_property_sys_image_version_info_type {
739 u32 string_size;
740 u8 str_image_version[1];
741};
742
743struct hfi_venc_config_advanced {
744 u8 pipe2d;
745 u8 hw_mode;
746 u8 low_delay_enforce;
747 u8 worker_vppsg_delay;
748 u32 close_gop;
749 u32 h264_constrain_intra_pred;
750 u32 h264_transform_8x8_flag;
751 u32 mpeg4_qpel_enable;
752 u32 multi_refp_en;
753 u32 qmatrix_en;
754 u8 vpp_info_packet_mode;
755 u8 ref_tile_mode;
756 u8 bitstream_flush_mode;
757 u32 vppsg_vspap_fb_sync_delay;
758 u32 rc_initial_delay;
759 u32 peak_bitrate_constraint;
760 u32 ds_display_frame_width;
761 u32 ds_display_frame_height;
762 u32 perf_tune_param_ptr;
763 u32 input_x_offset;
764 u32 input_y_offset;
765 u32 input_roi_width;
766 u32 input_roi_height;
767 u32 vsp_fifo_dma_sel;
768 u32 h264_num_ref_frames;
769};
770
771struct hfi_vbv_hrd_bufsize {
772 u32 buffer_size;
773};
774
775struct hfi_codec_mask_supported {
776 u32 codecs;
777 u32 video_domains;
778};
779
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800780struct hfi_aspect_ratio {
781 u32 aspect_width;
782 u32 aspect_height;
783};
784
785#define HFI_IFRAME_SIZE_DEFAULT (HFI_COMMON_BASE + 0x1)
786#define HFI_IFRAME_SIZE_MEDIUM (HFI_COMMON_BASE + 0x2)
787#define HFI_IFRAME_SIZE_HIGH (HFI_COMMON_BASE + 0x3)
788#define HFI_IFRAME_SIZE_UNLIMITED (HFI_COMMON_BASE + 0x4)
789struct hfi_iframe_size {
790 u32 type;
791};
792
793#define HFI_MVC_BUFFER_LAYOUT_TOP_BOTTOM (0)
794#define HFI_MVC_BUFFER_LAYOUT_SIDEBYSIDE (1)
795#define HFI_MVC_BUFFER_LAYOUT_SEQ (2)
796struct hfi_mvc_buffer_layout_descp_type {
797 u32 layout_type;
798 u32 bright_view_first;
799 u32 ngap;
800};
801
802
803#define HFI_CMD_SYS_COMMON_START \
804(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + HFI_CMD_START_OFFSET \
805 + 0x0000)
806#define HFI_CMD_SYS_INIT (HFI_CMD_SYS_COMMON_START + 0x001)
807#define HFI_CMD_SYS_PC_PREP (HFI_CMD_SYS_COMMON_START + 0x002)
808#define HFI_CMD_SYS_SET_RESOURCE (HFI_CMD_SYS_COMMON_START + 0x003)
809#define HFI_CMD_SYS_RELEASE_RESOURCE (HFI_CMD_SYS_COMMON_START + 0x004)
810#define HFI_CMD_SYS_SET_PROPERTY (HFI_CMD_SYS_COMMON_START + 0x005)
811#define HFI_CMD_SYS_GET_PROPERTY (HFI_CMD_SYS_COMMON_START + 0x006)
812#define HFI_CMD_SYS_SESSION_INIT (HFI_CMD_SYS_COMMON_START + 0x007)
813#define HFI_CMD_SYS_SESSION_END (HFI_CMD_SYS_COMMON_START + 0x008)
814#define HFI_CMD_SYS_SET_BUFFERS (HFI_CMD_SYS_COMMON_START + 0x009)
815#define HFI_CMD_SYS_TEST_START (HFI_CMD_SYS_COMMON_START + 0x100)
816
817#define HFI_CMD_SESSION_COMMON_START \
818 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
819 HFI_CMD_START_OFFSET + 0x1000)
820#define HFI_CMD_SESSION_SET_PROPERTY \
821 (HFI_CMD_SESSION_COMMON_START + 0x001)
822#define HFI_CMD_SESSION_SET_BUFFERS \
823 (HFI_CMD_SESSION_COMMON_START + 0x002)
824#define HFI_CMD_SESSION_GET_SEQUENCE_HEADER \
825 (HFI_CMD_SESSION_COMMON_START + 0x003)
826
827#define HFI_MSG_SYS_COMMON_START \
828 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
829 HFI_MSG_START_OFFSET + 0x0000)
830#define HFI_MSG_SYS_INIT_DONE (HFI_MSG_SYS_COMMON_START + 0x1)
831#define HFI_MSG_SYS_PC_PREP_DONE (HFI_MSG_SYS_COMMON_START + 0x2)
832#define HFI_MSG_SYS_RELEASE_RESOURCE (HFI_MSG_SYS_COMMON_START + 0x3)
833#define HFI_MSG_SYS_DEBUG (HFI_MSG_SYS_COMMON_START + 0x4)
834#define HFI_MSG_SYS_SESSION_INIT_DONE (HFI_MSG_SYS_COMMON_START + 0x6)
835#define HFI_MSG_SYS_SESSION_END_DONE (HFI_MSG_SYS_COMMON_START + 0x7)
836#define HFI_MSG_SYS_IDLE (HFI_MSG_SYS_COMMON_START + 0x8)
837#define HFI_MSG_SYS_COV (HFI_MSG_SYS_COMMON_START + 0x9)
838#define HFI_MSG_SYS_PROPERTY_INFO (HFI_MSG_SYS_COMMON_START + 0xA)
839#define HFI_MSG_SESSION_SYNC_DONE (HFI_MSG_SESSION_OX_START + 0xD)
840
841#define HFI_MSG_SESSION_COMMON_START \
842 (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
843 HFI_MSG_START_OFFSET + 0x1000)
844#define HFI_MSG_EVENT_NOTIFY (HFI_MSG_SESSION_COMMON_START + 0x1)
845#define HFI_MSG_SESSION_GET_SEQUENCE_HEADER_DONE \
846 (HFI_MSG_SESSION_COMMON_START + 0x2)
847
848#define HFI_CMD_SYS_TEST_SSR (HFI_CMD_SYS_TEST_START + 0x1)
849#define HFI_TEST_SSR_SW_ERR_FATAL 0x1
850#define HFI_TEST_SSR_SW_DIV_BY_ZERO 0x2
851#define HFI_TEST_SSR_HW_WDOG_IRQ 0x3
852
853struct vidc_hal_cmd_pkt_hdr {
854 u32 size;
855 u32 packet_type;
856};
857
858struct vidc_hal_msg_pkt_hdr {
859 u32 size;
860 u32 packet;
861};
862
863struct vidc_hal_session_cmd_pkt {
864 u32 size;
865 u32 packet_type;
866 u32 session_id;
867};
868
869struct hfi_cmd_sys_init_packet {
870 u32 size;
871 u32 packet_type;
872 u32 arch_type;
873};
874
875struct hfi_cmd_sys_pc_prep_packet {
876 u32 size;
877 u32 packet_type;
878};
879
880struct hfi_cmd_sys_set_resource_packet {
881 u32 size;
882 u32 packet_type;
883 u32 resource_handle;
884 u32 resource_type;
885 u32 rg_resource_data[1];
886};
887
888struct hfi_cmd_sys_release_resource_packet {
889 u32 size;
890 u32 packet_type;
891 u32 resource_type;
892 u32 resource_handle;
893};
894
895struct hfi_cmd_sys_set_property_packet {
896 u32 size;
897 u32 packet_type;
898 u32 num_properties;
899 u32 rg_property_data[1];
900};
901
902struct hfi_cmd_sys_get_property_packet {
903 u32 size;
904 u32 packet_type;
905 u32 num_properties;
906 u32 rg_property_data[1];
907};
908
909struct hfi_cmd_sys_session_init_packet {
910 u32 size;
911 u32 packet_type;
912 u32 session_id;
913 u32 session_domain;
914 u32 session_codec;
915};
916
917struct hfi_cmd_sys_session_end_packet {
918 u32 size;
919 u32 packet_type;
920 u32 session_id;
921};
922
923struct hfi_cmd_sys_set_buffers_packet {
924 u32 size;
925 u32 packet_type;
926 u32 buffer_type;
927 u32 buffer_size;
928 u32 num_buffers;
929 u32 rg_buffer_addr[1];
930};
931
932struct hfi_cmd_session_set_property_packet {
933 u32 size;
934 u32 packet_type;
935 u32 session_id;
936 u32 num_properties;
937 u32 rg_property_data[0];
938};
939
940struct hfi_cmd_session_set_buffers_packet {
941 u32 size;
942 u32 packet_type;
943 u32 session_id;
944 u32 buffer_type;
945 u32 buffer_size;
946 u32 extra_data_size;
947 u32 min_buffer_size;
948 u32 num_buffers;
949 u32 rg_buffer_info[1];
950};
951
Praneeth Paladugu6e6fbdb2017-01-16 15:43:01 -0800952struct hfi_cmd_session_sync_process_packet {
953 u32 size;
954 u32 packet_type;
955 u32 session_id;
956 u32 sync_id;
957 u32 rg_data[1];
958};
959
960struct hfi_msg_event_notify_packet {
961 u32 size;
962 u32 packet_type;
963 u32 session_id;
964 u32 event_id;
965 u32 event_data1;
966 u32 event_data2;
967 u32 rg_ext_event_data[1];
968};
969
970struct hfi_msg_release_buffer_ref_event_packet {
971 u32 packet_buffer;
972 u32 extra_data_buffer;
973 u32 output_tag;
974};
975
976struct hfi_msg_sys_init_done_packet {
977 u32 size;
978 u32 packet_type;
979 u32 error_type;
980 u32 num_properties;
981 u32 rg_property_data[1];
982};
983
984struct hfi_msg_sys_pc_prep_done_packet {
985 u32 size;
986 u32 packet_type;
987 u32 error_type;
988};
989
990struct hfi_msg_sys_release_resource_done_packet {
991 u32 size;
992 u32 packet_type;
993 u32 resource_handle;
994 u32 error_type;
995};
996
997struct hfi_msg_sys_session_init_done_packet {
998 u32 size;
999 u32 packet_type;
1000 u32 session_id;
1001 u32 error_type;
1002 u32 num_properties;
1003 u32 rg_property_data[1];
1004};
1005
1006struct hfi_msg_sys_session_end_done_packet {
1007 u32 size;
1008 u32 packet_type;
1009 u32 session_id;
1010 u32 error_type;
1011};
1012
1013struct hfi_msg_session_get_sequence_header_done_packet {
1014 u32 size;
1015 u32 packet_type;
1016 u32 session_id;
1017 u32 error_type;
1018 u32 header_len;
1019 u32 sequence_header;
1020};
1021
1022struct hfi_msg_sys_debug_packet {
1023 u32 size;
1024 u32 packet_type;
1025 u32 msg_type;
1026 u32 msg_size;
1027 u32 time_stamp_hi;
1028 u32 time_stamp_lo;
1029 u8 rg_msg_data[1];
1030};
1031
1032struct hfi_msg_sys_coverage_packet {
1033 u32 size;
1034 u32 packet_type;
1035 u32 msg_size;
1036 u32 time_stamp_hi;
1037 u32 time_stamp_lo;
1038 u8 rg_msg_data[1];
1039};
1040
1041enum HFI_VENUS_QTBL_STATUS {
1042 HFI_VENUS_QTBL_DISABLED = 0x00,
1043 HFI_VENUS_QTBL_ENABLED = 0x01,
1044 HFI_VENUS_QTBL_INITIALIZING = 0x02,
1045 HFI_VENUS_QTBL_DEINITIALIZING = 0x03
1046};
1047
1048enum HFI_VENUS_CTRL_INIT_STATUS {
1049 HFI_VENUS_CTRL_NOT_INIT = 0x0,
1050 HFI_VENUS_CTRL_READY = 0x1,
1051 HFI_VENUS_CTRL_ERROR_FATAL = 0x2
1052};
1053
1054struct hfi_sfr_struct {
1055 u32 bufSize;
1056 u8 rg_data[1];
1057};
1058
1059struct hfi_cmd_sys_test_ssr_packet {
1060 u32 size;
1061 u32 packet_type;
1062 u32 trigger_type;
1063};
1064#endif