Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * offload engine driver for the Marvell XOR engine |
| 3 | * Copyright (C) 2007, 2008, Marvell International Ltd. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <linux/init.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 16 | #include <linux/slab.h> |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 17 | #include <linux/delay.h> |
| 18 | #include <linux/dma-mapping.h> |
| 19 | #include <linux/spinlock.h> |
| 20 | #include <linux/interrupt.h> |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 21 | #include <linux/of_device.h> |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/memory.h> |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 24 | #include <linux/clk.h> |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 25 | #include <linux/of.h> |
| 26 | #include <linux/of_irq.h> |
| 27 | #include <linux/irqdomain.h> |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 28 | #include <linux/cpumask.h> |
Arnd Bergmann | c02cecb | 2012-08-24 15:21:54 +0200 | [diff] [blame] | 29 | #include <linux/platform_data/dma-mv_xor.h> |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 30 | |
| 31 | #include "dmaengine.h" |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 32 | #include "mv_xor.h" |
| 33 | |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame] | 34 | enum mv_xor_type { |
| 35 | XOR_ORION, |
| 36 | XOR_ARMADA_38X, |
Marcin Wojtas | ac5f0f3 | 2016-04-29 09:49:07 +0200 | [diff] [blame] | 37 | XOR_ARMADA_37XX, |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame] | 38 | }; |
| 39 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 40 | enum mv_xor_mode { |
| 41 | XOR_MODE_IN_REG, |
| 42 | XOR_MODE_IN_DESC, |
| 43 | }; |
| 44 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 45 | static void mv_xor_issue_pending(struct dma_chan *chan); |
| 46 | |
| 47 | #define to_mv_xor_chan(chan) \ |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 48 | container_of(chan, struct mv_xor_chan, dmachan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 49 | |
| 50 | #define to_mv_xor_slot(tx) \ |
| 51 | container_of(tx, struct mv_xor_desc_slot, async_tx) |
| 52 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 53 | #define mv_chan_to_devp(chan) \ |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 54 | ((chan)->dmadev.dev) |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 55 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 56 | static void mv_desc_init(struct mv_xor_desc_slot *desc, |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 57 | dma_addr_t addr, u32 byte_count, |
| 58 | enum dma_ctrl_flags flags) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 59 | { |
| 60 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 61 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 62 | hw_desc->status = XOR_DESC_DMA_OWNED; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 63 | hw_desc->phy_next_desc = 0; |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 64 | /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */ |
| 65 | hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ? |
| 66 | XOR_DESC_EOD_INT_EN : 0; |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 67 | hw_desc->phy_dest_addr = addr; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 68 | hw_desc->byte_count = byte_count; |
| 69 | } |
| 70 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 71 | static void mv_desc_set_mode(struct mv_xor_desc_slot *desc) |
| 72 | { |
| 73 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 74 | |
| 75 | switch (desc->type) { |
| 76 | case DMA_XOR: |
| 77 | case DMA_INTERRUPT: |
| 78 | hw_desc->desc_command |= XOR_DESC_OPERATION_XOR; |
| 79 | break; |
| 80 | case DMA_MEMCPY: |
| 81 | hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY; |
| 82 | break; |
| 83 | default: |
| 84 | BUG(); |
| 85 | return; |
| 86 | } |
| 87 | } |
| 88 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 89 | static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, |
| 90 | u32 next_desc_addr) |
| 91 | { |
| 92 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 93 | BUG_ON(hw_desc->phy_next_desc); |
| 94 | hw_desc->phy_next_desc = next_desc_addr; |
| 95 | } |
| 96 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 97 | static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, |
| 98 | int index, dma_addr_t addr) |
| 99 | { |
| 100 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
Thomas Petazzoni | e03bc65 | 2013-07-29 17:42:14 +0200 | [diff] [blame] | 101 | hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 102 | if (desc->type == DMA_XOR) |
| 103 | hw_desc->desc_command |= (1 << index); |
| 104 | } |
| 105 | |
| 106 | static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan) |
| 107 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 108 | return readl_relaxed(XOR_CURR_DESC(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan, |
| 112 | u32 next_desc_addr) |
| 113 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 114 | writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 115 | } |
| 116 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 117 | static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan) |
| 118 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 119 | u32 val = readl_relaxed(XOR_INTR_MASK(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 120 | val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 121 | writel_relaxed(val, XOR_INTR_MASK(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) |
| 125 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 126 | u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 127 | intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF; |
| 128 | return intr_cause; |
| 129 | } |
| 130 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 131 | static void mv_chan_clear_eoc_cause(struct mv_xor_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 132 | { |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 133 | u32 val; |
| 134 | |
| 135 | val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED; |
| 136 | val = ~(val << (chan->idx * 16)); |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 137 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 138 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 139 | } |
| 140 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 141 | static void mv_chan_clear_err_status(struct mv_xor_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 142 | { |
| 143 | u32 val = 0xFFFF0000 >> (chan->idx * 16); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 144 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 145 | } |
| 146 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 147 | static void mv_chan_set_mode(struct mv_xor_chan *chan, |
Thomas Petazzoni | 81aafb3 | 2015-12-22 11:43:28 +0100 | [diff] [blame] | 148 | u32 op_mode) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 149 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 150 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 151 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 152 | config &= ~0x7; |
| 153 | config |= op_mode; |
| 154 | |
Thomas Petazzoni | e03bc65 | 2013-07-29 17:42:14 +0200 | [diff] [blame] | 155 | #if defined(__BIG_ENDIAN) |
| 156 | config |= XOR_DESCRIPTOR_SWAP; |
| 157 | #else |
| 158 | config &= ~XOR_DESCRIPTOR_SWAP; |
| 159 | #endif |
| 160 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 161 | writel_relaxed(config, XOR_CONFIG(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | static void mv_chan_activate(struct mv_xor_chan *chan) |
| 165 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 166 | dev_dbg(mv_chan_to_devp(chan), " activate chan.\n"); |
Ezequiel Garcia | 5a9a55b | 2014-05-21 14:02:35 -0700 | [diff] [blame] | 167 | |
| 168 | /* writel ensures all descriptors are flushed before activation */ |
| 169 | writel(BIT(0), XOR_ACTIVATION(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | static char mv_chan_is_busy(struct mv_xor_chan *chan) |
| 173 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 174 | u32 state = readl_relaxed(XOR_ACTIVATION(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 175 | |
| 176 | state = (state >> 4) & 0x3; |
| 177 | |
| 178 | return (state == 1) ? 1 : 0; |
| 179 | } |
| 180 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 181 | /* |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 182 | * mv_chan_start_new_chain - program the engine to operate on new |
| 183 | * chain headed by sw_desc |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 184 | * Caller must hold &mv_chan->lock while calling this function |
| 185 | */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 186 | static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan, |
| 187 | struct mv_xor_desc_slot *sw_desc) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 188 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 189 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 190 | __func__, __LINE__, sw_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 191 | |
Bartlomiej Zolnierkiewicz | 48a9db4 | 2013-07-03 15:05:06 -0700 | [diff] [blame] | 192 | /* set the hardware chain */ |
| 193 | mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); |
| 194 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 195 | mv_chan->pending++; |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 196 | mv_xor_issue_pending(&mv_chan->dmachan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 197 | } |
| 198 | |
| 199 | static dma_cookie_t |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 200 | mv_desc_run_tx_complete_actions(struct mv_xor_desc_slot *desc, |
| 201 | struct mv_xor_chan *mv_chan, |
| 202 | dma_cookie_t cookie) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 203 | { |
| 204 | BUG_ON(desc->async_tx.cookie < 0); |
| 205 | |
| 206 | if (desc->async_tx.cookie > 0) { |
| 207 | cookie = desc->async_tx.cookie; |
| 208 | |
Dave Jiang | 8058e25 | 2016-07-25 10:34:08 -0700 | [diff] [blame^] | 209 | dma_descriptor_unmap(&desc->async_tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 210 | /* call the callback (must not sleep or submit new |
| 211 | * operations to this channel) |
| 212 | */ |
Dave Jiang | ee7681a | 2016-07-20 13:12:13 -0700 | [diff] [blame] | 213 | dmaengine_desc_get_callback_invoke(&desc->async_tx, NULL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | /* run dependent operations */ |
Dan Williams | 07f2211 | 2009-01-05 17:14:31 -0700 | [diff] [blame] | 217 | dma_run_dependencies(&desc->async_tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 218 | |
| 219 | return cookie; |
| 220 | } |
| 221 | |
| 222 | static int |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 223 | mv_chan_clean_completed_slots(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 224 | { |
| 225 | struct mv_xor_desc_slot *iter, *_iter; |
| 226 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 227 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 228 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 229 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 230 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 231 | if (async_tx_test_ack(&iter->async_tx)) |
| 232 | list_move_tail(&iter->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 233 | } |
| 234 | return 0; |
| 235 | } |
| 236 | |
| 237 | static int |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 238 | mv_desc_clean_slot(struct mv_xor_desc_slot *desc, |
| 239 | struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 240 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 241 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 242 | __func__, __LINE__, desc, desc->async_tx.flags); |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 243 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 244 | /* the client is allowed to attach dependent operations |
| 245 | * until 'ack' is set |
| 246 | */ |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 247 | if (!async_tx_test_ack(&desc->async_tx)) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 248 | /* move this slot to the completed_slots */ |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 249 | list_move_tail(&desc->node, &mv_chan->completed_slots); |
| 250 | else |
| 251 | list_move_tail(&desc->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 252 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 253 | return 0; |
| 254 | } |
| 255 | |
Ezequiel Garcia | fbeec99 | 2014-03-07 16:46:47 -0300 | [diff] [blame] | 256 | /* This function must be called with the mv_xor_chan spinlock held */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 257 | static void mv_chan_slot_cleanup(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 258 | { |
| 259 | struct mv_xor_desc_slot *iter, *_iter; |
| 260 | dma_cookie_t cookie = 0; |
| 261 | int busy = mv_chan_is_busy(mv_chan); |
| 262 | u32 current_desc = mv_chan_get_current_desc(mv_chan); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 263 | int current_cleaned = 0; |
| 264 | struct mv_xor_desc *hw_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 265 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 266 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
| 267 | dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 268 | mv_chan_clean_completed_slots(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 269 | |
| 270 | /* free completed slots from the chain starting with |
| 271 | * the oldest descriptor |
| 272 | */ |
| 273 | |
| 274 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 275 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 276 | |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 277 | /* clean finished descriptors */ |
| 278 | hw_desc = iter->hw_desc; |
| 279 | if (hw_desc->status & XOR_DESC_SUCCESS) { |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 280 | cookie = mv_desc_run_tx_complete_actions(iter, mv_chan, |
| 281 | cookie); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 282 | |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 283 | /* done processing desc, clean slot */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 284 | mv_desc_clean_slot(iter, mv_chan); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 285 | |
| 286 | /* break if we did cleaned the current */ |
| 287 | if (iter->async_tx.phys == current_desc) { |
| 288 | current_cleaned = 1; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 289 | break; |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 290 | } |
| 291 | } else { |
| 292 | if (iter->async_tx.phys == current_desc) { |
| 293 | current_cleaned = 0; |
| 294 | break; |
| 295 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 296 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | if ((busy == 0) && !list_empty(&mv_chan->chain)) { |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 300 | if (current_cleaned) { |
| 301 | /* |
| 302 | * current descriptor cleaned and removed, run |
| 303 | * from list head |
| 304 | */ |
| 305 | iter = list_entry(mv_chan->chain.next, |
| 306 | struct mv_xor_desc_slot, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 307 | node); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 308 | mv_chan_start_new_chain(mv_chan, iter); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 309 | } else { |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 310 | if (!list_is_last(&iter->node, &mv_chan->chain)) { |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 311 | /* |
| 312 | * descriptors are still waiting after |
| 313 | * current, trigger them |
| 314 | */ |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 315 | iter = list_entry(iter->node.next, |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 316 | struct mv_xor_desc_slot, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 317 | node); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 318 | mv_chan_start_new_chain(mv_chan, iter); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 319 | } else { |
| 320 | /* |
| 321 | * some descriptors are still waiting |
| 322 | * to be cleaned |
| 323 | */ |
| 324 | tasklet_schedule(&mv_chan->irq_tasklet); |
| 325 | } |
| 326 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | if (cookie > 0) |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 330 | mv_chan->dmachan.completed_cookie = cookie; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 331 | } |
| 332 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 333 | static void mv_xor_tasklet(unsigned long data) |
| 334 | { |
| 335 | struct mv_xor_chan *chan = (struct mv_xor_chan *) data; |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 336 | |
| 337 | spin_lock_bh(&chan->lock); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 338 | mv_chan_slot_cleanup(chan); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 339 | spin_unlock_bh(&chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 340 | } |
| 341 | |
| 342 | static struct mv_xor_desc_slot * |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 343 | mv_chan_alloc_slot(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 344 | { |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 345 | struct mv_xor_desc_slot *iter; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 346 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 347 | spin_lock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 348 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 349 | if (!list_empty(&mv_chan->free_slots)) { |
| 350 | iter = list_first_entry(&mv_chan->free_slots, |
| 351 | struct mv_xor_desc_slot, |
| 352 | node); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 353 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 354 | list_move_tail(&iter->node, &mv_chan->allocated_slots); |
| 355 | |
| 356 | spin_unlock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 357 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 358 | /* pre-ack descriptor */ |
| 359 | async_tx_ack(&iter->async_tx); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 360 | iter->async_tx.cookie = -EBUSY; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 361 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 362 | return iter; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 363 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 364 | } |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 365 | |
| 366 | spin_unlock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 367 | |
| 368 | /* try to free some slots if the allocation fails */ |
| 369 | tasklet_schedule(&mv_chan->irq_tasklet); |
| 370 | |
| 371 | return NULL; |
| 372 | } |
| 373 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 374 | /************************ DMA engine API functions ****************************/ |
| 375 | static dma_cookie_t |
| 376 | mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) |
| 377 | { |
| 378 | struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); |
| 379 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 380 | struct mv_xor_desc_slot *old_chain_tail; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 381 | dma_cookie_t cookie; |
| 382 | int new_hw_chain = 1; |
| 383 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 384 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 385 | "%s sw_desc %p: async_tx %p\n", |
| 386 | __func__, sw_desc, &sw_desc->async_tx); |
| 387 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 388 | spin_lock_bh(&mv_chan->lock); |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 389 | cookie = dma_cookie_assign(tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 390 | |
| 391 | if (list_empty(&mv_chan->chain)) |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 392 | list_move_tail(&sw_desc->node, &mv_chan->chain); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 393 | else { |
| 394 | new_hw_chain = 0; |
| 395 | |
| 396 | old_chain_tail = list_entry(mv_chan->chain.prev, |
| 397 | struct mv_xor_desc_slot, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 398 | node); |
| 399 | list_move_tail(&sw_desc->node, &mv_chan->chain); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 400 | |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 401 | dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n", |
| 402 | &old_chain_tail->async_tx.phys); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 403 | |
| 404 | /* fix up the hardware chain */ |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 405 | mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 406 | |
| 407 | /* if the channel is not busy */ |
| 408 | if (!mv_chan_is_busy(mv_chan)) { |
| 409 | u32 current_desc = mv_chan_get_current_desc(mv_chan); |
| 410 | /* |
| 411 | * and the curren desc is the end of the chain before |
| 412 | * the append, then we need to start the channel |
| 413 | */ |
| 414 | if (current_desc == old_chain_tail->async_tx.phys) |
| 415 | new_hw_chain = 1; |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | if (new_hw_chain) |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 420 | mv_chan_start_new_chain(mv_chan, sw_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 421 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 422 | spin_unlock_bh(&mv_chan->lock); |
| 423 | |
| 424 | return cookie; |
| 425 | } |
| 426 | |
| 427 | /* returns the number of allocated descriptors */ |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 428 | static int mv_xor_alloc_chan_resources(struct dma_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 429 | { |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 430 | void *virt_desc; |
| 431 | dma_addr_t dma_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 432 | int idx; |
| 433 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 434 | struct mv_xor_desc_slot *slot = NULL; |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 435 | int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 436 | |
| 437 | /* Allocate descriptor slots */ |
| 438 | idx = mv_chan->slots_allocated; |
| 439 | while (idx < num_descs_in_pool) { |
| 440 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); |
| 441 | if (!slot) { |
Ezequiel Garcia | b8291dd | 2014-08-27 10:52:49 -0300 | [diff] [blame] | 442 | dev_info(mv_chan_to_devp(mv_chan), |
| 443 | "channel only initialized %d descriptor slots", |
| 444 | idx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 445 | break; |
| 446 | } |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 447 | virt_desc = mv_chan->dma_desc_pool_virt; |
| 448 | slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 449 | |
| 450 | dma_async_tx_descriptor_init(&slot->async_tx, chan); |
| 451 | slot->async_tx.tx_submit = mv_xor_tx_submit; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 452 | INIT_LIST_HEAD(&slot->node); |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 453 | dma_desc = mv_chan->dma_desc_pool; |
| 454 | slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 455 | slot->idx = idx++; |
| 456 | |
| 457 | spin_lock_bh(&mv_chan->lock); |
| 458 | mv_chan->slots_allocated = idx; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 459 | list_add_tail(&slot->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 460 | spin_unlock_bh(&mv_chan->lock); |
| 461 | } |
| 462 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 463 | dev_dbg(mv_chan_to_devp(mv_chan), |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 464 | "allocated %d descriptor slots\n", |
| 465 | mv_chan->slots_allocated); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 466 | |
| 467 | return mv_chan->slots_allocated ? : -ENOMEM; |
| 468 | } |
| 469 | |
| 470 | static struct dma_async_tx_descriptor * |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 471 | mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
| 472 | unsigned int src_cnt, size_t len, unsigned long flags) |
| 473 | { |
| 474 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 475 | struct mv_xor_desc_slot *sw_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 476 | |
| 477 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) |
| 478 | return NULL; |
| 479 | |
Coly Li | 7912d30 | 2011-03-27 01:26:53 +0800 | [diff] [blame] | 480 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 481 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 482 | dev_dbg(mv_chan_to_devp(mv_chan), |
Gregory CLEMENT | bc822e1 | 2016-04-29 09:49:05 +0200 | [diff] [blame] | 483 | "%s src_cnt: %d len: %zu dest %pad flags: %ld\n", |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 484 | __func__, src_cnt, len, &dest, flags); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 485 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 486 | sw_desc = mv_chan_alloc_slot(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 487 | if (sw_desc) { |
| 488 | sw_desc->type = DMA_XOR; |
| 489 | sw_desc->async_tx.flags = flags; |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 490 | mv_desc_init(sw_desc, dest, len, flags); |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 491 | if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) |
| 492 | mv_desc_set_mode(sw_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 493 | while (src_cnt--) |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 494 | mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 495 | } |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 496 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 497 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 498 | "%s sw_desc %p async_tx %p \n", |
| 499 | __func__, sw_desc, &sw_desc->async_tx); |
| 500 | return sw_desc ? &sw_desc->async_tx : NULL; |
| 501 | } |
| 502 | |
Lior Amsalem | 3e4f52e | 2014-08-27 10:52:50 -0300 | [diff] [blame] | 503 | static struct dma_async_tx_descriptor * |
| 504 | mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 505 | size_t len, unsigned long flags) |
| 506 | { |
| 507 | /* |
| 508 | * A MEMCPY operation is identical to an XOR operation with only |
| 509 | * a single source address. |
| 510 | */ |
| 511 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); |
| 512 | } |
| 513 | |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 514 | static struct dma_async_tx_descriptor * |
| 515 | mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) |
| 516 | { |
| 517 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 518 | dma_addr_t src, dest; |
| 519 | size_t len; |
| 520 | |
| 521 | src = mv_chan->dummy_src_addr; |
| 522 | dest = mv_chan->dummy_dst_addr; |
| 523 | len = MV_XOR_MIN_BYTE_COUNT; |
| 524 | |
| 525 | /* |
| 526 | * We implement the DMA_INTERRUPT operation as a minimum sized |
| 527 | * XOR operation with a single dummy source address. |
| 528 | */ |
| 529 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); |
| 530 | } |
| 531 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 532 | static void mv_xor_free_chan_resources(struct dma_chan *chan) |
| 533 | { |
| 534 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 535 | struct mv_xor_desc_slot *iter, *_iter; |
| 536 | int in_use_descs = 0; |
| 537 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 538 | spin_lock_bh(&mv_chan->lock); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 539 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 540 | mv_chan_slot_cleanup(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 541 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 542 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 543 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 544 | in_use_descs++; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 545 | list_move_tail(&iter->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 546 | } |
| 547 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 548 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 549 | in_use_descs++; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 550 | list_move_tail(&iter->node, &mv_chan->free_slots); |
| 551 | } |
| 552 | list_for_each_entry_safe(iter, _iter, &mv_chan->allocated_slots, |
| 553 | node) { |
| 554 | in_use_descs++; |
| 555 | list_move_tail(&iter->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 556 | } |
| 557 | list_for_each_entry_safe_reverse( |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 558 | iter, _iter, &mv_chan->free_slots, node) { |
| 559 | list_del(&iter->node); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 560 | kfree(iter); |
| 561 | mv_chan->slots_allocated--; |
| 562 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 563 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 564 | dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 565 | __func__, mv_chan->slots_allocated); |
| 566 | spin_unlock_bh(&mv_chan->lock); |
| 567 | |
| 568 | if (in_use_descs) |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 569 | dev_err(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 570 | "freeing %d in use descriptors!\n", in_use_descs); |
| 571 | } |
| 572 | |
| 573 | /** |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 574 | * mv_xor_status - poll the status of an XOR transaction |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 575 | * @chan: XOR channel handle |
| 576 | * @cookie: XOR transaction identifier |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 577 | * @txstate: XOR transactions state holder (or NULL) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 578 | */ |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 579 | static enum dma_status mv_xor_status(struct dma_chan *chan, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 580 | dma_cookie_t cookie, |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 581 | struct dma_tx_state *txstate) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 582 | { |
| 583 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 584 | enum dma_status ret; |
| 585 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 586 | ret = dma_cookie_status(chan, cookie, txstate); |
Ezequiel Garcia | 890766d | 2014-03-07 16:46:45 -0300 | [diff] [blame] | 587 | if (ret == DMA_COMPLETE) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 588 | return ret; |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 589 | |
| 590 | spin_lock_bh(&mv_chan->lock); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 591 | mv_chan_slot_cleanup(mv_chan); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 592 | spin_unlock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 593 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 594 | return dma_cookie_status(chan, cookie, txstate); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 595 | } |
| 596 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 597 | static void mv_chan_dump_regs(struct mv_xor_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 598 | { |
| 599 | u32 val; |
| 600 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 601 | val = readl_relaxed(XOR_CONFIG(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 602 | dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 603 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 604 | val = readl_relaxed(XOR_ACTIVATION(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 605 | dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 606 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 607 | val = readl_relaxed(XOR_INTR_CAUSE(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 608 | dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 609 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 610 | val = readl_relaxed(XOR_INTR_MASK(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 611 | dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 612 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 613 | val = readl_relaxed(XOR_ERROR_CAUSE(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 614 | dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 615 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 616 | val = readl_relaxed(XOR_ERROR_ADDR(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 617 | dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 618 | } |
| 619 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 620 | static void mv_chan_err_interrupt_handler(struct mv_xor_chan *chan, |
| 621 | u32 intr_cause) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 622 | { |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 623 | if (intr_cause & XOR_INT_ERR_DECODE) { |
| 624 | dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n"); |
| 625 | return; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 626 | } |
| 627 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 628 | dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n", |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 629 | chan->idx, intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 630 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 631 | mv_chan_dump_regs(chan); |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 632 | WARN_ON(1); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 633 | } |
| 634 | |
| 635 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) |
| 636 | { |
| 637 | struct mv_xor_chan *chan = data; |
| 638 | u32 intr_cause = mv_chan_get_intr_cause(chan); |
| 639 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 640 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 641 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 642 | if (intr_cause & XOR_INTR_ERRORS) |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 643 | mv_chan_err_interrupt_handler(chan, intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 644 | |
| 645 | tasklet_schedule(&chan->irq_tasklet); |
| 646 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 647 | mv_chan_clear_eoc_cause(chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 648 | |
| 649 | return IRQ_HANDLED; |
| 650 | } |
| 651 | |
| 652 | static void mv_xor_issue_pending(struct dma_chan *chan) |
| 653 | { |
| 654 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 655 | |
| 656 | if (mv_chan->pending >= MV_XOR_THRESHOLD) { |
| 657 | mv_chan->pending = 0; |
| 658 | mv_chan_activate(mv_chan); |
| 659 | } |
| 660 | } |
| 661 | |
| 662 | /* |
| 663 | * Perform a transaction to verify the HW works. |
| 664 | */ |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 665 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 666 | static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 667 | { |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 668 | int i, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 669 | void *src, *dest; |
| 670 | dma_addr_t src_dma, dest_dma; |
| 671 | struct dma_chan *dma_chan; |
| 672 | dma_cookie_t cookie; |
| 673 | struct dma_async_tx_descriptor *tx; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 674 | struct dmaengine_unmap_data *unmap; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 675 | int err = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 676 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 677 | src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 678 | if (!src) |
| 679 | return -ENOMEM; |
| 680 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 681 | dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 682 | if (!dest) { |
| 683 | kfree(src); |
| 684 | return -ENOMEM; |
| 685 | } |
| 686 | |
| 687 | /* Fill in src buffer */ |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 688 | for (i = 0; i < PAGE_SIZE; i++) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 689 | ((u8 *) src)[i] = (u8)i; |
| 690 | |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 691 | dma_chan = &mv_chan->dmachan; |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 692 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 693 | err = -ENODEV; |
| 694 | goto out; |
| 695 | } |
| 696 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 697 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL); |
| 698 | if (!unmap) { |
| 699 | err = -ENOMEM; |
| 700 | goto free_resources; |
| 701 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 702 | |
Stefan Roese | 5156463 | 2016-06-01 12:43:32 +0200 | [diff] [blame] | 703 | src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), |
| 704 | (size_t)src & ~PAGE_MASK, PAGE_SIZE, |
| 705 | DMA_TO_DEVICE); |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 706 | unmap->addr[0] = src_dma; |
| 707 | |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 708 | ret = dma_mapping_error(dma_chan->device->dev, src_dma); |
| 709 | if (ret) { |
| 710 | err = -ENOMEM; |
| 711 | goto free_resources; |
| 712 | } |
| 713 | unmap->to_cnt = 1; |
| 714 | |
Stefan Roese | 5156463 | 2016-06-01 12:43:32 +0200 | [diff] [blame] | 715 | dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), |
| 716 | (size_t)dest & ~PAGE_MASK, PAGE_SIZE, |
| 717 | DMA_FROM_DEVICE); |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 718 | unmap->addr[1] = dest_dma; |
| 719 | |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 720 | ret = dma_mapping_error(dma_chan->device->dev, dest_dma); |
| 721 | if (ret) { |
| 722 | err = -ENOMEM; |
| 723 | goto free_resources; |
| 724 | } |
| 725 | unmap->from_cnt = 1; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 726 | unmap->len = PAGE_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 727 | |
| 728 | tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 729 | PAGE_SIZE, 0); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 730 | if (!tx) { |
| 731 | dev_err(dma_chan->device->dev, |
| 732 | "Self-test cannot prepare operation, disabling\n"); |
| 733 | err = -ENODEV; |
| 734 | goto free_resources; |
| 735 | } |
| 736 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 737 | cookie = mv_xor_tx_submit(tx); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 738 | if (dma_submit_error(cookie)) { |
| 739 | dev_err(dma_chan->device->dev, |
| 740 | "Self-test submit error, disabling\n"); |
| 741 | err = -ENODEV; |
| 742 | goto free_resources; |
| 743 | } |
| 744 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 745 | mv_xor_issue_pending(dma_chan); |
| 746 | async_tx_ack(tx); |
| 747 | msleep(1); |
| 748 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 749 | if (mv_xor_status(dma_chan, cookie, NULL) != |
Vinod Koul | b3efb8f | 2013-10-16 20:51:04 +0530 | [diff] [blame] | 750 | DMA_COMPLETE) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 751 | dev_err(dma_chan->device->dev, |
| 752 | "Self-test copy timed out, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 753 | err = -ENODEV; |
| 754 | goto free_resources; |
| 755 | } |
| 756 | |
Thomas Petazzoni | c35064c | 2012-11-15 13:01:59 +0100 | [diff] [blame] | 757 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 758 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 759 | if (memcmp(src, dest, PAGE_SIZE)) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 760 | dev_err(dma_chan->device->dev, |
| 761 | "Self-test copy failed compare, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 762 | err = -ENODEV; |
| 763 | goto free_resources; |
| 764 | } |
| 765 | |
| 766 | free_resources: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 767 | dmaengine_unmap_put(unmap); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 768 | mv_xor_free_chan_resources(dma_chan); |
| 769 | out: |
| 770 | kfree(src); |
| 771 | kfree(dest); |
| 772 | return err; |
| 773 | } |
| 774 | |
| 775 | #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */ |
Bill Pemberton | 463a1f8 | 2012-11-19 13:22:55 -0500 | [diff] [blame] | 776 | static int |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 777 | mv_chan_xor_self_test(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 778 | { |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 779 | int i, src_idx, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 780 | struct page *dest; |
| 781 | struct page *xor_srcs[MV_XOR_NUM_SRC_TEST]; |
| 782 | dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST]; |
| 783 | dma_addr_t dest_dma; |
| 784 | struct dma_async_tx_descriptor *tx; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 785 | struct dmaengine_unmap_data *unmap; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 786 | struct dma_chan *dma_chan; |
| 787 | dma_cookie_t cookie; |
| 788 | u8 cmp_byte = 0; |
| 789 | u32 cmp_word; |
| 790 | int err = 0; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 791 | int src_count = MV_XOR_NUM_SRC_TEST; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 792 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 793 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 794 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 795 | if (!xor_srcs[src_idx]) { |
| 796 | while (src_idx--) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 797 | __free_page(xor_srcs[src_idx]); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 798 | return -ENOMEM; |
| 799 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 800 | } |
| 801 | |
| 802 | dest = alloc_page(GFP_KERNEL); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 803 | if (!dest) { |
| 804 | while (src_idx--) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 805 | __free_page(xor_srcs[src_idx]); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 806 | return -ENOMEM; |
| 807 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 808 | |
| 809 | /* Fill in src buffers */ |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 810 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 811 | u8 *ptr = page_address(xor_srcs[src_idx]); |
| 812 | for (i = 0; i < PAGE_SIZE; i++) |
| 813 | ptr[i] = (1 << src_idx); |
| 814 | } |
| 815 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 816 | for (src_idx = 0; src_idx < src_count; src_idx++) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 817 | cmp_byte ^= (u8) (1 << src_idx); |
| 818 | |
| 819 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | |
| 820 | (cmp_byte << 8) | cmp_byte; |
| 821 | |
| 822 | memset(page_address(dest), 0, PAGE_SIZE); |
| 823 | |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 824 | dma_chan = &mv_chan->dmachan; |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 825 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 826 | err = -ENODEV; |
| 827 | goto out; |
| 828 | } |
| 829 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 830 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1, |
| 831 | GFP_KERNEL); |
| 832 | if (!unmap) { |
| 833 | err = -ENOMEM; |
| 834 | goto free_resources; |
| 835 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 836 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 837 | /* test xor */ |
| 838 | for (i = 0; i < src_count; i++) { |
| 839 | unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], |
| 840 | 0, PAGE_SIZE, DMA_TO_DEVICE); |
| 841 | dma_srcs[i] = unmap->addr[i]; |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 842 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]); |
| 843 | if (ret) { |
| 844 | err = -ENOMEM; |
| 845 | goto free_resources; |
| 846 | } |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 847 | unmap->to_cnt++; |
| 848 | } |
| 849 | |
| 850 | unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, |
| 851 | DMA_FROM_DEVICE); |
| 852 | dest_dma = unmap->addr[src_count]; |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 853 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]); |
| 854 | if (ret) { |
| 855 | err = -ENOMEM; |
| 856 | goto free_resources; |
| 857 | } |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 858 | unmap->from_cnt = 1; |
| 859 | unmap->len = PAGE_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 860 | |
| 861 | tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 862 | src_count, PAGE_SIZE, 0); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 863 | if (!tx) { |
| 864 | dev_err(dma_chan->device->dev, |
| 865 | "Self-test cannot prepare operation, disabling\n"); |
| 866 | err = -ENODEV; |
| 867 | goto free_resources; |
| 868 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 869 | |
| 870 | cookie = mv_xor_tx_submit(tx); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 871 | if (dma_submit_error(cookie)) { |
| 872 | dev_err(dma_chan->device->dev, |
| 873 | "Self-test submit error, disabling\n"); |
| 874 | err = -ENODEV; |
| 875 | goto free_resources; |
| 876 | } |
| 877 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 878 | mv_xor_issue_pending(dma_chan); |
| 879 | async_tx_ack(tx); |
| 880 | msleep(8); |
| 881 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 882 | if (mv_xor_status(dma_chan, cookie, NULL) != |
Vinod Koul | b3efb8f | 2013-10-16 20:51:04 +0530 | [diff] [blame] | 883 | DMA_COMPLETE) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 884 | dev_err(dma_chan->device->dev, |
| 885 | "Self-test xor timed out, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 886 | err = -ENODEV; |
| 887 | goto free_resources; |
| 888 | } |
| 889 | |
Thomas Petazzoni | c35064c | 2012-11-15 13:01:59 +0100 | [diff] [blame] | 890 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 891 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 892 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { |
| 893 | u32 *ptr = page_address(dest); |
| 894 | if (ptr[i] != cmp_word) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 895 | dev_err(dma_chan->device->dev, |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 896 | "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n", |
| 897 | i, ptr[i], cmp_word); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 898 | err = -ENODEV; |
| 899 | goto free_resources; |
| 900 | } |
| 901 | } |
| 902 | |
| 903 | free_resources: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 904 | dmaengine_unmap_put(unmap); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 905 | mv_xor_free_chan_resources(dma_chan); |
| 906 | out: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 907 | src_idx = src_count; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 908 | while (src_idx--) |
| 909 | __free_page(xor_srcs[src_idx]); |
| 910 | __free_page(dest); |
| 911 | return err; |
| 912 | } |
| 913 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 914 | static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 915 | { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 916 | struct dma_chan *chan, *_chan; |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 917 | struct device *dev = mv_chan->dmadev.dev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 918 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 919 | dma_async_device_unregister(&mv_chan->dmadev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 920 | |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 921 | dma_free_coherent(dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 922 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 923 | dma_unmap_single(dev, mv_chan->dummy_src_addr, |
| 924 | MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); |
| 925 | dma_unmap_single(dev, mv_chan->dummy_dst_addr, |
| 926 | MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 927 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 928 | list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 929 | device_node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 930 | list_del(&chan->device_node); |
| 931 | } |
| 932 | |
Thomas Petazzoni | 88eb92c | 2012-11-15 16:11:18 +0100 | [diff] [blame] | 933 | free_irq(mv_chan->irq, mv_chan); |
| 934 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 935 | return 0; |
| 936 | } |
| 937 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 938 | static struct mv_xor_chan * |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 939 | mv_xor_channel_add(struct mv_xor_device *xordev, |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 940 | struct platform_device *pdev, |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame] | 941 | int idx, dma_cap_mask_t cap_mask, int irq) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 942 | { |
| 943 | int ret = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 944 | struct mv_xor_chan *mv_chan; |
| 945 | struct dma_device *dma_dev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 946 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 947 | mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL); |
Sachin Kamat | a577659 | 2013-09-02 13:54:20 +0530 | [diff] [blame] | 948 | if (!mv_chan) |
| 949 | return ERR_PTR(-ENOMEM); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 950 | |
Thomas Petazzoni | 9aedbdb | 2012-11-15 15:36:37 +0100 | [diff] [blame] | 951 | mv_chan->idx = idx; |
Thomas Petazzoni | 88eb92c | 2012-11-15 16:11:18 +0100 | [diff] [blame] | 952 | mv_chan->irq = irq; |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame] | 953 | if (xordev->xor_type == XOR_ORION) |
| 954 | mv_chan->op_in_desc = XOR_MODE_IN_REG; |
| 955 | else |
| 956 | mv_chan->op_in_desc = XOR_MODE_IN_DESC; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 957 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 958 | dma_dev = &mv_chan->dmadev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 959 | |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 960 | /* |
| 961 | * These source and destination dummy buffers are used to implement |
| 962 | * a DMA_INTERRUPT operation as a minimum-sized XOR operation. |
| 963 | * Hence, we only need to map the buffers at initialization-time. |
| 964 | */ |
| 965 | mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev, |
| 966 | mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); |
| 967 | mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev, |
| 968 | mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); |
| 969 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 970 | /* allocate coherent memory for hardware descriptors |
| 971 | * note: writecombine gives slightly better performance, but |
| 972 | * requires that we explicitly flush the writes |
| 973 | */ |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 974 | mv_chan->dma_desc_pool_virt = |
Luis R. Rodriguez | f6e4566 | 2016-01-22 18:34:22 -0800 | [diff] [blame] | 975 | dma_alloc_wc(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool, |
| 976 | GFP_KERNEL); |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 977 | if (!mv_chan->dma_desc_pool_virt) |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 978 | return ERR_PTR(-ENOMEM); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 979 | |
| 980 | /* discover transaction capabilites from the platform data */ |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 981 | dma_dev->cap_mask = cap_mask; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 982 | |
| 983 | INIT_LIST_HEAD(&dma_dev->channels); |
| 984 | |
| 985 | /* set base routines */ |
| 986 | dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources; |
| 987 | dma_dev->device_free_chan_resources = mv_xor_free_chan_resources; |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 988 | dma_dev->device_tx_status = mv_xor_status; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 989 | dma_dev->device_issue_pending = mv_xor_issue_pending; |
| 990 | dma_dev->dev = &pdev->dev; |
| 991 | |
| 992 | /* set prep routines based on capability */ |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 993 | if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) |
| 994 | dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 995 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) |
| 996 | dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 997 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
Joe Perches | c019894 | 2009-06-28 09:26:21 -0700 | [diff] [blame] | 998 | dma_dev->max_xor = 8; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 999 | dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor; |
| 1000 | } |
| 1001 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1002 | mv_chan->mmr_base = xordev->xor_base; |
Ezequiel Garcia | 82a1402 | 2013-10-30 12:01:43 -0300 | [diff] [blame] | 1003 | mv_chan->mmr_high_base = xordev->xor_high_base; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1004 | tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long) |
| 1005 | mv_chan); |
| 1006 | |
| 1007 | /* clear errors before enabling interrupts */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 1008 | mv_chan_clear_err_status(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1009 | |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1010 | ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler, |
| 1011 | 0, dev_name(&pdev->dev), mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1012 | if (ret) |
| 1013 | goto err_free_dma; |
| 1014 | |
| 1015 | mv_chan_unmask_interrupts(mv_chan); |
| 1016 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1017 | if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) |
Thomas Petazzoni | 81aafb3 | 2015-12-22 11:43:28 +0100 | [diff] [blame] | 1018 | mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_IN_DESC); |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1019 | else |
Thomas Petazzoni | 81aafb3 | 2015-12-22 11:43:28 +0100 | [diff] [blame] | 1020 | mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_XOR); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1021 | |
| 1022 | spin_lock_init(&mv_chan->lock); |
| 1023 | INIT_LIST_HEAD(&mv_chan->chain); |
| 1024 | INIT_LIST_HEAD(&mv_chan->completed_slots); |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 1025 | INIT_LIST_HEAD(&mv_chan->free_slots); |
| 1026 | INIT_LIST_HEAD(&mv_chan->allocated_slots); |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 1027 | mv_chan->dmachan.device = dma_dev; |
| 1028 | dma_cookie_init(&mv_chan->dmachan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1029 | |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 1030 | list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1031 | |
| 1032 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 1033 | ret = mv_chan_memcpy_self_test(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1034 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); |
| 1035 | if (ret) |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1036 | goto err_free_irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1037 | } |
| 1038 | |
| 1039 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 1040 | ret = mv_chan_xor_self_test(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1041 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
| 1042 | if (ret) |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1043 | goto err_free_irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1044 | } |
| 1045 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1046 | dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n", |
| 1047 | mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode", |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1048 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1049 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
| 1050 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1051 | |
| 1052 | dma_async_device_register(dma_dev); |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1053 | return mv_chan; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1054 | |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1055 | err_free_irq: |
| 1056 | free_irq(mv_chan->irq, mv_chan); |
Stefan Roese | a4a1e53d | 2016-06-01 12:43:31 +0200 | [diff] [blame] | 1057 | err_free_dma: |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 1058 | dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1059 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1060 | return ERR_PTR(ret); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1061 | } |
| 1062 | |
| 1063 | static void |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1064 | mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1065 | const struct mbus_dram_target_info *dram) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1066 | { |
Ezequiel Garcia | 82a1402 | 2013-10-30 12:01:43 -0300 | [diff] [blame] | 1067 | void __iomem *base = xordev->xor_high_base; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1068 | u32 win_enable = 0; |
| 1069 | int i; |
| 1070 | |
| 1071 | for (i = 0; i < 8; i++) { |
| 1072 | writel(0, base + WINDOW_BASE(i)); |
| 1073 | writel(0, base + WINDOW_SIZE(i)); |
| 1074 | if (i < 4) |
| 1075 | writel(0, base + WINDOW_REMAP_HIGH(i)); |
| 1076 | } |
| 1077 | |
| 1078 | for (i = 0; i < dram->num_cs; i++) { |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1079 | const struct mbus_dram_window *cs = dram->cs + i; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1080 | |
| 1081 | writel((cs->base & 0xffff0000) | |
| 1082 | (cs->mbus_attr << 8) | |
| 1083 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); |
| 1084 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); |
| 1085 | |
| 1086 | win_enable |= (1 << i); |
| 1087 | win_enable |= 3 << (16 + (2 * i)); |
| 1088 | } |
| 1089 | |
| 1090 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); |
| 1091 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); |
Thomas Petazzoni | c4b4b73 | 2012-11-22 18:16:37 +0100 | [diff] [blame] | 1092 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
| 1093 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1094 | } |
| 1095 | |
Marcin Wojtas | ac5f0f3 | 2016-04-29 09:49:07 +0200 | [diff] [blame] | 1096 | static void |
| 1097 | mv_xor_conf_mbus_windows_a3700(struct mv_xor_device *xordev) |
| 1098 | { |
| 1099 | void __iomem *base = xordev->xor_high_base; |
| 1100 | u32 win_enable = 0; |
| 1101 | int i; |
| 1102 | |
| 1103 | for (i = 0; i < 8; i++) { |
| 1104 | writel(0, base + WINDOW_BASE(i)); |
| 1105 | writel(0, base + WINDOW_SIZE(i)); |
| 1106 | if (i < 4) |
| 1107 | writel(0, base + WINDOW_REMAP_HIGH(i)); |
| 1108 | } |
| 1109 | /* |
| 1110 | * For Armada3700 open default 4GB Mbus window. The dram |
| 1111 | * related configuration are done at AXIS level. |
| 1112 | */ |
| 1113 | writel(0xffff0000, base + WINDOW_SIZE(0)); |
| 1114 | win_enable |= 1; |
| 1115 | win_enable |= 3 << 16; |
| 1116 | |
| 1117 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); |
| 1118 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); |
| 1119 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
| 1120 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); |
| 1121 | } |
| 1122 | |
Thomas Petazzoni | 8b64843 | 2015-12-22 11:43:29 +0100 | [diff] [blame] | 1123 | /* |
| 1124 | * Since this XOR driver is basically used only for RAID5, we don't |
| 1125 | * need to care about synchronizing ->suspend with DMA activity, |
| 1126 | * because the DMA engine will naturally be quiet due to the block |
| 1127 | * devices being suspended. |
| 1128 | */ |
| 1129 | static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state) |
| 1130 | { |
| 1131 | struct mv_xor_device *xordev = platform_get_drvdata(pdev); |
| 1132 | int i; |
| 1133 | |
| 1134 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
| 1135 | struct mv_xor_chan *mv_chan = xordev->channels[i]; |
| 1136 | |
| 1137 | if (!mv_chan) |
| 1138 | continue; |
| 1139 | |
| 1140 | mv_chan->saved_config_reg = |
| 1141 | readl_relaxed(XOR_CONFIG(mv_chan)); |
| 1142 | mv_chan->saved_int_mask_reg = |
| 1143 | readl_relaxed(XOR_INTR_MASK(mv_chan)); |
| 1144 | } |
| 1145 | |
| 1146 | return 0; |
| 1147 | } |
| 1148 | |
| 1149 | static int mv_xor_resume(struct platform_device *dev) |
| 1150 | { |
| 1151 | struct mv_xor_device *xordev = platform_get_drvdata(dev); |
| 1152 | const struct mbus_dram_target_info *dram; |
| 1153 | int i; |
| 1154 | |
| 1155 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
| 1156 | struct mv_xor_chan *mv_chan = xordev->channels[i]; |
| 1157 | |
| 1158 | if (!mv_chan) |
| 1159 | continue; |
| 1160 | |
| 1161 | writel_relaxed(mv_chan->saved_config_reg, |
| 1162 | XOR_CONFIG(mv_chan)); |
| 1163 | writel_relaxed(mv_chan->saved_int_mask_reg, |
| 1164 | XOR_INTR_MASK(mv_chan)); |
| 1165 | } |
| 1166 | |
Marcin Wojtas | ac5f0f3 | 2016-04-29 09:49:07 +0200 | [diff] [blame] | 1167 | if (xordev->xor_type == XOR_ARMADA_37XX) { |
| 1168 | mv_xor_conf_mbus_windows_a3700(xordev); |
| 1169 | return 0; |
| 1170 | } |
| 1171 | |
Thomas Petazzoni | 8b64843 | 2015-12-22 11:43:29 +0100 | [diff] [blame] | 1172 | dram = mv_mbus_dram_info(); |
| 1173 | if (dram) |
| 1174 | mv_xor_conf_mbus_windows(xordev, dram); |
| 1175 | |
| 1176 | return 0; |
| 1177 | } |
| 1178 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1179 | static const struct of_device_id mv_xor_dt_ids[] = { |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame] | 1180 | { .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION }, |
| 1181 | { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X }, |
Marcin Wojtas | ac5f0f3 | 2016-04-29 09:49:07 +0200 | [diff] [blame] | 1182 | { .compatible = "marvell,armada-3700-xor", .data = (void *)XOR_ARMADA_37XX }, |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1183 | {}, |
| 1184 | }; |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1185 | |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1186 | static unsigned int mv_xor_engine_count; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1187 | |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1188 | static int mv_xor_probe(struct platform_device *pdev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1189 | { |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1190 | const struct mbus_dram_target_info *dram; |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1191 | struct mv_xor_device *xordev; |
Jingoo Han | d4adcc0 | 2013-07-30 17:09:11 +0900 | [diff] [blame] | 1192 | struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1193 | struct resource *res; |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1194 | unsigned int max_engines, max_channels; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1195 | int i, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1196 | |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1197 | dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1198 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1199 | xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL); |
| 1200 | if (!xordev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1201 | return -ENOMEM; |
| 1202 | |
| 1203 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1204 | if (!res) |
| 1205 | return -ENODEV; |
| 1206 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1207 | xordev->xor_base = devm_ioremap(&pdev->dev, res->start, |
| 1208 | resource_size(res)); |
| 1209 | if (!xordev->xor_base) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1210 | return -EBUSY; |
| 1211 | |
| 1212 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 1213 | if (!res) |
| 1214 | return -ENODEV; |
| 1215 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1216 | xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start, |
| 1217 | resource_size(res)); |
| 1218 | if (!xordev->xor_high_base) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1219 | return -EBUSY; |
| 1220 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1221 | platform_set_drvdata(pdev, xordev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1222 | |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame] | 1223 | |
| 1224 | /* |
| 1225 | * We need to know which type of XOR device we use before |
| 1226 | * setting up. In non-dt case it can only be the legacy one. |
| 1227 | */ |
| 1228 | xordev->xor_type = XOR_ORION; |
| 1229 | if (pdev->dev.of_node) { |
| 1230 | const struct of_device_id *of_id = |
| 1231 | of_match_device(mv_xor_dt_ids, |
| 1232 | &pdev->dev); |
| 1233 | |
| 1234 | xordev->xor_type = (uintptr_t)of_id->data; |
| 1235 | } |
| 1236 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1237 | /* |
| 1238 | * (Re-)program MBUS remapping windows if we are asked to. |
| 1239 | */ |
Marcin Wojtas | ac5f0f3 | 2016-04-29 09:49:07 +0200 | [diff] [blame] | 1240 | if (xordev->xor_type == XOR_ARMADA_37XX) { |
| 1241 | mv_xor_conf_mbus_windows_a3700(xordev); |
| 1242 | } else { |
| 1243 | dram = mv_mbus_dram_info(); |
| 1244 | if (dram) |
| 1245 | mv_xor_conf_mbus_windows(xordev, dram); |
| 1246 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1247 | |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1248 | /* Not all platforms can gate the clock, so it is not |
| 1249 | * an error if the clock does not exists. |
| 1250 | */ |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1251 | xordev->clk = clk_get(&pdev->dev, NULL); |
| 1252 | if (!IS_ERR(xordev->clk)) |
| 1253 | clk_prepare_enable(xordev->clk); |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1254 | |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1255 | /* |
| 1256 | * We don't want to have more than one channel per CPU in |
| 1257 | * order for async_tx to perform well. So we limit the number |
| 1258 | * of engines and channels so that we take into account this |
| 1259 | * constraint. Note that we also want to use channels from |
Marcin Wojtas | ac5f0f3 | 2016-04-29 09:49:07 +0200 | [diff] [blame] | 1260 | * separate engines when possible. For dual-CPU Armada 3700 |
| 1261 | * SoC with single XOR engine allow using its both channels. |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1262 | */ |
| 1263 | max_engines = num_present_cpus(); |
Marcin Wojtas | ac5f0f3 | 2016-04-29 09:49:07 +0200 | [diff] [blame] | 1264 | if (xordev->xor_type == XOR_ARMADA_37XX) |
| 1265 | max_channels = num_present_cpus(); |
| 1266 | else |
| 1267 | max_channels = min_t(unsigned int, |
| 1268 | MV_XOR_MAX_CHANNELS, |
| 1269 | DIV_ROUND_UP(num_present_cpus(), 2)); |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1270 | |
| 1271 | if (mv_xor_engine_count >= max_engines) |
| 1272 | return 0; |
| 1273 | |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1274 | if (pdev->dev.of_node) { |
| 1275 | struct device_node *np; |
| 1276 | int i = 0; |
| 1277 | |
| 1278 | for_each_child_of_node(pdev->dev.of_node, np) { |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1279 | struct mv_xor_chan *chan; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1280 | dma_cap_mask_t cap_mask; |
| 1281 | int irq; |
| 1282 | |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1283 | if (i >= max_channels) |
| 1284 | continue; |
| 1285 | |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1286 | dma_cap_zero(cap_mask); |
Thomas Petazzoni | 6d8f7ab | 2015-07-08 16:28:16 +0200 | [diff] [blame] | 1287 | dma_cap_set(DMA_MEMCPY, cap_mask); |
| 1288 | dma_cap_set(DMA_XOR, cap_mask); |
| 1289 | dma_cap_set(DMA_INTERRUPT, cap_mask); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1290 | |
| 1291 | irq = irq_of_parse_and_map(np, 0); |
Thomas Petazzoni | f8eb9e7 | 2012-11-22 18:22:12 +0100 | [diff] [blame] | 1292 | if (!irq) { |
| 1293 | ret = -ENODEV; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1294 | goto err_channel_add; |
| 1295 | } |
| 1296 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1297 | chan = mv_xor_channel_add(xordev, pdev, i, |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame] | 1298 | cap_mask, irq); |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1299 | if (IS_ERR(chan)) { |
| 1300 | ret = PTR_ERR(chan); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1301 | irq_dispose_mapping(irq); |
| 1302 | goto err_channel_add; |
| 1303 | } |
| 1304 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1305 | xordev->channels[i] = chan; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1306 | i++; |
| 1307 | } |
| 1308 | } else if (pdata && pdata->channels) { |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1309 | for (i = 0; i < max_channels; i++) { |
Thomas Petazzoni | e39f6ec | 2012-10-30 11:56:26 +0100 | [diff] [blame] | 1310 | struct mv_xor_channel_data *cd; |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1311 | struct mv_xor_chan *chan; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1312 | int irq; |
| 1313 | |
| 1314 | cd = &pdata->channels[i]; |
| 1315 | if (!cd) { |
| 1316 | ret = -ENODEV; |
| 1317 | goto err_channel_add; |
| 1318 | } |
| 1319 | |
| 1320 | irq = platform_get_irq(pdev, i); |
| 1321 | if (irq < 0) { |
| 1322 | ret = irq; |
| 1323 | goto err_channel_add; |
| 1324 | } |
| 1325 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1326 | chan = mv_xor_channel_add(xordev, pdev, i, |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame] | 1327 | cd->cap_mask, irq); |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1328 | if (IS_ERR(chan)) { |
| 1329 | ret = PTR_ERR(chan); |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1330 | goto err_channel_add; |
| 1331 | } |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1332 | |
| 1333 | xordev->channels[i] = chan; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1334 | } |
| 1335 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1336 | |
| 1337 | return 0; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1338 | |
| 1339 | err_channel_add: |
| 1340 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1341 | if (xordev->channels[i]) { |
Thomas Petazzoni | ab6e439 | 2013-01-06 11:10:43 +0100 | [diff] [blame] | 1342 | mv_xor_channel_remove(xordev->channels[i]); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1343 | if (pdev->dev.of_node) |
| 1344 | irq_dispose_mapping(xordev->channels[i]->irq); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1345 | } |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1346 | |
Thomas Petazzoni | dab9206 | 2013-01-06 11:10:44 +0100 | [diff] [blame] | 1347 | if (!IS_ERR(xordev->clk)) { |
| 1348 | clk_disable_unprepare(xordev->clk); |
| 1349 | clk_put(xordev->clk); |
| 1350 | } |
| 1351 | |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1352 | return ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1353 | } |
| 1354 | |
Thomas Petazzoni | 6197165 | 2012-10-30 12:05:40 +0100 | [diff] [blame] | 1355 | static struct platform_driver mv_xor_driver = { |
| 1356 | .probe = mv_xor_probe, |
Thomas Petazzoni | 8b64843 | 2015-12-22 11:43:29 +0100 | [diff] [blame] | 1357 | .suspend = mv_xor_suspend, |
| 1358 | .resume = mv_xor_resume, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1359 | .driver = { |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1360 | .name = MV_XOR_NAME, |
| 1361 | .of_match_table = of_match_ptr(mv_xor_dt_ids), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1362 | }, |
| 1363 | }; |
| 1364 | |
| 1365 | |
| 1366 | static int __init mv_xor_init(void) |
| 1367 | { |
Thomas Petazzoni | 6197165 | 2012-10-30 12:05:40 +0100 | [diff] [blame] | 1368 | return platform_driver_register(&mv_xor_driver); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1369 | } |
Paul Gortmaker | 25cf68d | 2015-08-21 16:27:49 -0400 | [diff] [blame] | 1370 | device_initcall(mv_xor_init); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1371 | |
Paul Gortmaker | 25cf68d | 2015-08-21 16:27:49 -0400 | [diff] [blame] | 1372 | /* |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1373 | MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>"); |
| 1374 | MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine"); |
| 1375 | MODULE_LICENSE("GPL"); |
Paul Gortmaker | 25cf68d | 2015-08-21 16:27:49 -0400 | [diff] [blame] | 1376 | */ |