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Viresh Kumarc5fa4fd2012-03-23 00:17:43 +05301/*
2 * DTS file for SPEAr320 SoC
3 *
Viresh Kumar10d89352012-06-20 12:53:02 -07004 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +05305 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
Viresh Kumare0373602012-03-29 08:30:19 +053021 ranges = <0x40000000 0x40000000 0x80000000
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +053022 0xd0000000 0xd0000000 0x30000000>;
23
Viresh Kumar4ddb1c22012-10-27 15:21:39 +053024 pinmux: pinmux@b3000000 {
Viresh Kumare0373602012-03-29 08:30:19 +053025 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>;
Viresh Kumar4ddb1c22012-10-27 15:21:39 +053027 #gpio-range-cells = <2>;
Viresh Kumare0373602012-03-29 08:30:19 +053028 };
29
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +053030 clcd@90000000 {
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +080031 compatible = "arm,pl110", "arm,primecell";
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +053032 reg = <0x90000000 0x1000>;
33 interrupts = <33>;
34 status = "disabled";
35 };
36
37 fsmc: flash@4c000000 {
38 compatible = "st,spear600-fsmc-nand";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 reg = <0x4c000000 0x1000 /* FSMC Register */
42 0x50000000 0x0010>; /* NAND Base */
43 reg-names = "fsmc_regs", "nand_data";
44 st,ale-off = <0x20000>;
45 st,cle-off = <0x10000>;
46 status = "disabled";
47 };
48
49 sdhci@70000000 {
50 compatible = "st,sdhci-spear";
51 reg = <0x70000000 0x100>;
52 interrupts = <29>;
53 status = "disabled";
54 };
55
56 spi1: spi@a5000000 {
57 compatible = "arm,pl022", "arm,primecell";
58 reg = <0xa5000000 0x1000>;
Shiraz Hashim8113ba92012-11-10 17:31:01 +053059 #address-cells = <1>;
60 #size-cells = <0>;
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +053061 status = "disabled";
62 };
63
64 spi2: spi@a6000000 {
65 compatible = "arm,pl022", "arm,primecell";
66 reg = <0xa6000000 0x1000>;
Shiraz Hashim8113ba92012-11-10 17:31:01 +053067 #address-cells = <1>;
68 #size-cells = <0>;
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +053069 status = "disabled";
70 };
71
Shiraz Hashim8113ba92012-11-10 17:31:01 +053072 pwm: pwm@a8000000 {
73 compatible ="st,spear-pwm";
74 reg = <0xa8000000 0x1000>;
75 #pwm-cells = <2>;
76 status = "disabled";
77 };
78
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +053079 apb {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "simple-bus";
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +080083 ranges = <0xa0000000 0xa0000000 0x20000000
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +053084 0xd0000000 0xd0000000 0x30000000>;
85
86 i2c1: i2c@a7000000 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 compatible = "snps,designware-i2c";
90 reg = <0xa7000000 0x1000>;
91 status = "disabled";
92 };
93
94 serial@a3000000 {
95 compatible = "arm,pl011", "arm,primecell";
96 reg = <0xa3000000 0x1000>;
97 status = "disabled";
98 };
99
100 serial@a4000000 {
101 compatible = "arm,pl011", "arm,primecell";
102 reg = <0xa4000000 0x1000>;
103 status = "disabled";
104 };
Viresh Kumar4ddb1c22012-10-27 15:21:39 +0530105
106 gpiopinctrl: gpio@b3000000 {
107 compatible = "st,spear-plgpio";
108 reg = <0xb3000000 0x1000>;
109 #interrupt-cells = <1>;
110 interrupt-controller;
111 gpio-controller;
112 #gpio-cells = <2>;
113 gpio-ranges = <&pinmux 0 102>;
114 status = "disabled";
115
116 st-plgpio,ngpio = <102>;
117 st-plgpio,enb-reg = <0x24>;
118 st-plgpio,wdata-reg = <0x34>;
119 st-plgpio,dir-reg = <0x44>;
120 st-plgpio,ie-reg = <0x64>;
121 st-plgpio,rdata-reg = <0x54>;
122 st-plgpio,mis-reg = <0x84>;
123 st-plgpio,eit-reg = <0x94>;
124 };
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530125 };
126 };
127};