blob: 8cba13df5f289d0e8fb0b5744944d665b4e2c692 [file] [log] [blame]
Shawn Guo95ceafd2012-09-06 07:09:11 +00001/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
Viresh Kumar748c8762014-08-28 11:22:24 +05304 * Copyright (C) 2014 Linaro.
5 * Viresh Kumar <viresh.kumar@linaro.org>
6 *
Viresh Kumarbbcf0712014-09-09 19:58:03 +05307 * The OPP code in function set_target() is reused from
Shawn Guo95ceafd2012-09-06 07:09:11 +00008 * drivers/cpufreq/omap-cpufreq.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/clk.h>
Sudeep KarkadaNageshae1825b22013-09-10 18:59:46 +010018#include <linux/cpu.h>
Eduardo Valentin77cff592013-07-15 09:09:14 -040019#include <linux/cpu_cooling.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000020#include <linux/cpufreq.h>
Thomas Petazzoni34e5a522014-10-19 11:30:28 +020021#include <linux/cpufreq-dt.h>
Eduardo Valentin77cff592013-07-15 09:09:14 -040022#include <linux/cpumask.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000023#include <linux/err.h>
24#include <linux/module.h>
25#include <linux/of.h>
Nishanth Menone4db1c72013-09-19 16:03:52 -050026#include <linux/pm_opp.h>
Shawn Guo5553f9e2013-01-30 14:27:49 +000027#include <linux/platform_device.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000028#include <linux/regulator/consumer.h>
29#include <linux/slab.h>
Eduardo Valentin77cff592013-07-15 09:09:14 -040030#include <linux/thermal.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000031
Viresh Kumard2f31f12014-08-28 11:22:28 +053032struct private_data {
33 struct device *cpu_dev;
34 struct regulator *cpu_reg;
35 struct thermal_cooling_device *cdev;
36 unsigned int voltage_tolerance; /* in percentage */
37};
Shawn Guo95ceafd2012-09-06 07:09:11 +000038
Viresh Kumarbbcf0712014-09-09 19:58:03 +053039static int set_target(struct cpufreq_policy *policy, unsigned int index)
Shawn Guo95ceafd2012-09-06 07:09:11 +000040{
Nishanth Menon47d43ba2013-09-19 16:03:51 -050041 struct dev_pm_opp *opp;
Viresh Kumard2f31f12014-08-28 11:22:28 +053042 struct cpufreq_frequency_table *freq_table = policy->freq_table;
43 struct clk *cpu_clk = policy->clk;
44 struct private_data *priv = policy->driver_data;
45 struct device *cpu_dev = priv->cpu_dev;
46 struct regulator *cpu_reg = priv->cpu_reg;
jhbird.choi@samsung.com5df60552013-03-18 08:09:42 +000047 unsigned long volt = 0, volt_old = 0, tol = 0;
Viresh Kumard4019f02013-08-14 19:38:24 +053048 unsigned int old_freq, new_freq;
Guennadi Liakhovetski0ca68432013-02-25 18:22:37 +010049 long freq_Hz, freq_exact;
Shawn Guo95ceafd2012-09-06 07:09:11 +000050 int ret;
51
Shawn Guo95ceafd2012-09-06 07:09:11 +000052 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
Paul Walmsley2209b0c2013-11-25 18:01:18 -080053 if (freq_Hz <= 0)
Shawn Guo95ceafd2012-09-06 07:09:11 +000054 freq_Hz = freq_table[index].frequency * 1000;
Shawn Guo95ceafd2012-09-06 07:09:11 +000055
Viresh Kumard4019f02013-08-14 19:38:24 +053056 freq_exact = freq_Hz;
57 new_freq = freq_Hz / 1000;
58 old_freq = clk_get_rate(cpu_clk) / 1000;
Shawn Guo95ceafd2012-09-06 07:09:11 +000059
Mark Brown4a511de2013-08-13 14:58:24 +020060 if (!IS_ERR(cpu_reg)) {
Stefan Wahren0a1e8792014-10-17 22:09:48 +000061 unsigned long opp_freq;
62
Nishanth Menon78e8eb82013-01-18 19:52:33 +000063 rcu_read_lock();
Nishanth Menon5d4879c2013-09-19 16:03:50 -050064 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
Shawn Guo95ceafd2012-09-06 07:09:11 +000065 if (IS_ERR(opp)) {
Nishanth Menon78e8eb82013-01-18 19:52:33 +000066 rcu_read_unlock();
Viresh Kumarfbd48ca2014-08-28 11:22:27 +053067 dev_err(cpu_dev, "failed to find OPP for %ld\n",
68 freq_Hz);
Viresh Kumard4019f02013-08-14 19:38:24 +053069 return PTR_ERR(opp);
Shawn Guo95ceafd2012-09-06 07:09:11 +000070 }
Nishanth Menon5d4879c2013-09-19 16:03:50 -050071 volt = dev_pm_opp_get_voltage(opp);
Stefan Wahren0a1e8792014-10-17 22:09:48 +000072 opp_freq = dev_pm_opp_get_freq(opp);
Nishanth Menon78e8eb82013-01-18 19:52:33 +000073 rcu_read_unlock();
Viresh Kumard2f31f12014-08-28 11:22:28 +053074 tol = volt * priv->voltage_tolerance / 100;
Shawn Guo95ceafd2012-09-06 07:09:11 +000075 volt_old = regulator_get_voltage(cpu_reg);
Stefan Wahren0a1e8792014-10-17 22:09:48 +000076 dev_dbg(cpu_dev, "Found OPP: %ld kHz, %ld uV\n",
77 opp_freq / 1000, volt);
Shawn Guo95ceafd2012-09-06 07:09:11 +000078 }
79
Viresh Kumarfbd48ca2014-08-28 11:22:27 +053080 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
Stefan Wahren8197bb12014-10-17 22:09:49 +000081 old_freq / 1000, (volt_old > 0) ? volt_old / 1000 : -1,
Viresh Kumarfbd48ca2014-08-28 11:22:27 +053082 new_freq / 1000, volt ? volt / 1000 : -1);
Shawn Guo95ceafd2012-09-06 07:09:11 +000083
84 /* scaling up? scale voltage before frequency */
Viresh Kumard4019f02013-08-14 19:38:24 +053085 if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
Shawn Guo95ceafd2012-09-06 07:09:11 +000086 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
87 if (ret) {
Viresh Kumarfbd48ca2014-08-28 11:22:27 +053088 dev_err(cpu_dev, "failed to scale voltage up: %d\n",
89 ret);
Viresh Kumard4019f02013-08-14 19:38:24 +053090 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +000091 }
92 }
93
Guennadi Liakhovetski0ca68432013-02-25 18:22:37 +010094 ret = clk_set_rate(cpu_clk, freq_exact);
Shawn Guo95ceafd2012-09-06 07:09:11 +000095 if (ret) {
Viresh Kumarfbd48ca2014-08-28 11:22:27 +053096 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
Stefan Wahren8197bb12014-10-17 22:09:49 +000097 if (!IS_ERR(cpu_reg) && volt_old > 0)
Shawn Guo95ceafd2012-09-06 07:09:11 +000098 regulator_set_voltage_tol(cpu_reg, volt_old, tol);
Viresh Kumard4019f02013-08-14 19:38:24 +053099 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000100 }
101
102 /* scaling down? scale voltage after frequency */
Viresh Kumard4019f02013-08-14 19:38:24 +0530103 if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
Shawn Guo95ceafd2012-09-06 07:09:11 +0000104 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
105 if (ret) {
Viresh Kumarfbd48ca2014-08-28 11:22:27 +0530106 dev_err(cpu_dev, "failed to scale voltage down: %d\n",
107 ret);
Viresh Kumard4019f02013-08-14 19:38:24 +0530108 clk_set_rate(cpu_clk, old_freq * 1000);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000109 }
110 }
111
Viresh Kumarfd143b42013-04-01 12:57:44 +0000112 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000113}
114
Viresh Kumar95b61052014-08-28 11:22:30 +0530115static int allocate_resources(int cpu, struct device **cdev,
Viresh Kumard2f31f12014-08-28 11:22:28 +0530116 struct regulator **creg, struct clk **cclk)
Shawn Guo95ceafd2012-09-06 07:09:11 +0000117{
Viresh Kumard2f31f12014-08-28 11:22:28 +0530118 struct device *cpu_dev;
119 struct regulator *cpu_reg;
120 struct clk *cpu_clk;
121 int ret = 0;
Viresh Kumar2d2c5e02014-08-28 11:22:29 +0530122 char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000123
Viresh Kumar95b61052014-08-28 11:22:30 +0530124 cpu_dev = get_cpu_device(cpu);
Sudeep KarkadaNageshae1825b22013-09-10 18:59:46 +0100125 if (!cpu_dev) {
Viresh Kumar95b61052014-08-28 11:22:30 +0530126 pr_err("failed to get cpu%d device\n", cpu);
Sudeep KarkadaNageshae1825b22013-09-10 18:59:46 +0100127 return -ENODEV;
128 }
Paolo Pisatif5c3ef22013-03-28 09:24:29 +0000129
Viresh Kumar2d2c5e02014-08-28 11:22:29 +0530130 /* Try "cpu0" for older DTs */
Viresh Kumar95b61052014-08-28 11:22:30 +0530131 if (!cpu)
132 reg = reg_cpu0;
133 else
134 reg = reg_cpu;
Viresh Kumar2d2c5e02014-08-28 11:22:29 +0530135
136try_again:
137 cpu_reg = regulator_get_optional(cpu_dev, reg);
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000138 if (IS_ERR(cpu_reg)) {
139 /*
Viresh Kumar95b61052014-08-28 11:22:30 +0530140 * If cpu's regulator supply node is present, but regulator is
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000141 * not yet registered, we should try defering probe.
142 */
143 if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
Viresh Kumar95b61052014-08-28 11:22:30 +0530144 dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n",
145 cpu);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530146 return -EPROBE_DEFER;
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000147 }
Viresh Kumar2d2c5e02014-08-28 11:22:29 +0530148
149 /* Try with "cpu-supply" */
150 if (reg == reg_cpu0) {
151 reg = reg_cpu;
152 goto try_again;
153 }
154
Thomas Petazzonia00de1a2014-10-19 11:30:29 +0200155 dev_dbg(cpu_dev, "no regulator for cpu%d: %ld\n",
156 cpu, PTR_ERR(cpu_reg));
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000157 }
158
Lucas Stache3beb0a2014-05-16 12:20:42 +0200159 cpu_clk = clk_get(cpu_dev, NULL);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000160 if (IS_ERR(cpu_clk)) {
Viresh Kumard2f31f12014-08-28 11:22:28 +0530161 /* put regulator */
162 if (!IS_ERR(cpu_reg))
163 regulator_put(cpu_reg);
164
Shawn Guo95ceafd2012-09-06 07:09:11 +0000165 ret = PTR_ERR(cpu_clk);
Viresh Kumar48a86242014-08-28 11:22:26 +0530166
167 /*
168 * If cpu's clk node is present, but clock is not yet
169 * registered, we should try defering probe.
170 */
171 if (ret == -EPROBE_DEFER)
Viresh Kumar95b61052014-08-28 11:22:30 +0530172 dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu);
Viresh Kumar48a86242014-08-28 11:22:26 +0530173 else
Abhilash Kesavan71796212014-10-31 18:09:33 +0530174 dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", cpu,
175 ret);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530176 } else {
177 *cdev = cpu_dev;
178 *creg = cpu_reg;
179 *cclk = cpu_clk;
180 }
Viresh Kumar48a86242014-08-28 11:22:26 +0530181
Viresh Kumard2f31f12014-08-28 11:22:28 +0530182 return ret;
183}
184
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530185static int cpufreq_init(struct cpufreq_policy *policy)
Viresh Kumard2f31f12014-08-28 11:22:28 +0530186{
Thomas Petazzoni34e5a522014-10-19 11:30:28 +0200187 struct cpufreq_dt_platform_data *pd;
Viresh Kumard2f31f12014-08-28 11:22:28 +0530188 struct cpufreq_frequency_table *freq_table;
189 struct thermal_cooling_device *cdev;
190 struct device_node *np;
191 struct private_data *priv;
192 struct device *cpu_dev;
193 struct regulator *cpu_reg;
194 struct clk *cpu_clk;
Lucas Stach045ee452014-10-24 15:05:55 +0200195 unsigned long min_uV = ~0, max_uV = 0;
Viresh Kumard2f31f12014-08-28 11:22:28 +0530196 unsigned int transition_latency;
197 int ret;
198
Viresh Kumar95b61052014-08-28 11:22:30 +0530199 ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530200 if (ret) {
201 pr_err("%s: Failed to allocate resources\n: %d", __func__, ret);
202 return ret;
203 }
204
205 np = of_node_get(cpu_dev->of_node);
206 if (!np) {
207 dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);
208 ret = -ENOENT;
209 goto out_put_reg_clk;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000210 }
211
Viresh Kumar1bf8cc32014-07-11 20:24:19 +0530212 /* OPPs might be populated at runtime, don't check for error here */
213 of_init_opp_table(cpu_dev);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000214
Viresh Kumard2f31f12014-08-28 11:22:28 +0530215 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
216 if (!priv) {
217 ret = -ENOMEM;
Lucas Stach045ee452014-10-24 15:05:55 +0200218 goto out_put_node;
Viresh Kumard2f31f12014-08-28 11:22:28 +0530219 }
220
221 of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000222
223 if (of_property_read_u32(np, "clock-latency", &transition_latency))
224 transition_latency = CPUFREQ_ETERNAL;
225
Philipp Zabel43c638e2013-09-26 11:19:37 +0200226 if (!IS_ERR(cpu_reg)) {
Lucas Stach045ee452014-10-24 15:05:55 +0200227 unsigned long opp_freq = 0;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000228
229 /*
Lucas Stach045ee452014-10-24 15:05:55 +0200230 * Disable any OPPs where the connected regulator isn't able to
231 * provide the specified voltage and record minimum and maximum
232 * voltage levels.
Shawn Guo95ceafd2012-09-06 07:09:11 +0000233 */
Lucas Stach045ee452014-10-24 15:05:55 +0200234 while (1) {
235 struct dev_pm_opp *opp;
236 unsigned long opp_uV, tol_uV;
237
238 rcu_read_lock();
239 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq);
240 if (IS_ERR(opp)) {
241 rcu_read_unlock();
242 break;
243 }
244 opp_uV = dev_pm_opp_get_voltage(opp);
245 rcu_read_unlock();
246
247 tol_uV = opp_uV * priv->voltage_tolerance / 100;
248 if (regulator_is_supported_voltage(cpu_reg, opp_uV,
249 opp_uV + tol_uV)) {
250 if (opp_uV < min_uV)
251 min_uV = opp_uV;
252 if (opp_uV > max_uV)
253 max_uV = opp_uV;
254 } else {
255 dev_pm_opp_disable(cpu_dev, opp_freq);
256 }
257
258 opp_freq++;
259 }
260
Shawn Guo95ceafd2012-09-06 07:09:11 +0000261 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
262 if (ret > 0)
263 transition_latency += ret * 1000;
264 }
265
Lucas Stach045ee452014-10-24 15:05:55 +0200266 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
267 if (ret) {
268 pr_err("failed to init cpufreq table: %d\n", ret);
269 goto out_free_priv;
270 }
271
Eduardo Valentin77cff592013-07-15 09:09:14 -0400272 /*
273 * For now, just loading the cooling device;
274 * thermal DT code takes care of matching them.
275 */
276 if (of_find_property(np, "#cooling-cells", NULL)) {
277 cdev = of_cpufreq_cooling_register(np, cpu_present_mask);
278 if (IS_ERR(cdev))
Viresh Kumarfbd48ca2014-08-28 11:22:27 +0530279 dev_err(cpu_dev,
280 "running cpufreq without cooling device: %ld\n",
281 PTR_ERR(cdev));
Viresh Kumard2f31f12014-08-28 11:22:28 +0530282 else
283 priv->cdev = cdev;
Eduardo Valentin77cff592013-07-15 09:09:14 -0400284 }
Viresh Kumard2f31f12014-08-28 11:22:28 +0530285
286 priv->cpu_dev = cpu_dev;
287 priv->cpu_reg = cpu_reg;
288 policy->driver_data = priv;
289
290 policy->clk = cpu_clk;
Thomas Petazzoni34e5a522014-10-19 11:30:28 +0200291 ret = cpufreq_table_validate_and_show(policy, freq_table);
292 if (ret) {
293 dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
294 ret);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530295 goto out_cooling_unregister;
Thomas Petazzoni34e5a522014-10-19 11:30:28 +0200296 }
297
298 policy->cpuinfo.transition_latency = transition_latency;
299
300 pd = cpufreq_get_driver_data();
Geert Uytterhoevenc81407f2014-10-27 14:44:40 +0100301 if (!pd || !pd->independent_clocks)
Thomas Petazzoni34e5a522014-10-19 11:30:28 +0200302 cpumask_setall(policy->cpus);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530303
Lucas Stachf9739d22014-09-26 15:33:46 +0200304 of_node_put(np);
305
Shawn Guo95ceafd2012-09-06 07:09:11 +0000306 return 0;
307
Viresh Kumard2f31f12014-08-28 11:22:28 +0530308out_cooling_unregister:
309 cpufreq_cooling_unregister(priv->cdev);
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500310 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
Lucas Stach045ee452014-10-24 15:05:55 +0200311out_free_priv:
312 kfree(priv);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000313out_put_node:
314 of_node_put(np);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530315out_put_reg_clk:
316 clk_put(cpu_clk);
317 if (!IS_ERR(cpu_reg))
318 regulator_put(cpu_reg);
319
320 return ret;
321}
322
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530323static int cpufreq_exit(struct cpufreq_policy *policy)
Viresh Kumard2f31f12014-08-28 11:22:28 +0530324{
325 struct private_data *priv = policy->driver_data;
326
327 cpufreq_cooling_unregister(priv->cdev);
328 dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
329 clk_put(policy->clk);
330 if (!IS_ERR(priv->cpu_reg))
331 regulator_put(priv->cpu_reg);
332 kfree(priv);
333
334 return 0;
335}
336
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530337static struct cpufreq_driver dt_cpufreq_driver = {
Viresh Kumard2f31f12014-08-28 11:22:28 +0530338 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
339 .verify = cpufreq_generic_frequency_table_verify,
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530340 .target_index = set_target,
Viresh Kumard2f31f12014-08-28 11:22:28 +0530341 .get = cpufreq_generic_get,
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530342 .init = cpufreq_init,
343 .exit = cpufreq_exit,
344 .name = "cpufreq-dt",
Viresh Kumard2f31f12014-08-28 11:22:28 +0530345 .attr = cpufreq_generic_attr,
346};
347
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530348static int dt_cpufreq_probe(struct platform_device *pdev)
Viresh Kumard2f31f12014-08-28 11:22:28 +0530349{
350 struct device *cpu_dev;
351 struct regulator *cpu_reg;
352 struct clk *cpu_clk;
353 int ret;
354
355 /*
356 * All per-cluster (CPUs sharing clock/voltages) initialization is done
357 * from ->init(). In probe(), we just need to make sure that clk and
358 * regulators are available. Else defer probe and retry.
359 *
360 * FIXME: Is checking this only for CPU0 sufficient ?
361 */
Viresh Kumar95b61052014-08-28 11:22:30 +0530362 ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530363 if (ret)
364 return ret;
365
366 clk_put(cpu_clk);
367 if (!IS_ERR(cpu_reg))
368 regulator_put(cpu_reg);
369
Thomas Petazzoni34e5a522014-10-19 11:30:28 +0200370 dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev);
371
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530372 ret = cpufreq_register_driver(&dt_cpufreq_driver);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530373 if (ret)
374 dev_err(cpu_dev, "failed register driver: %d\n", ret);
375
Shawn Guo95ceafd2012-09-06 07:09:11 +0000376 return ret;
377}
Shawn Guo5553f9e2013-01-30 14:27:49 +0000378
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530379static int dt_cpufreq_remove(struct platform_device *pdev)
Shawn Guo5553f9e2013-01-30 14:27:49 +0000380{
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530381 cpufreq_unregister_driver(&dt_cpufreq_driver);
Shawn Guo5553f9e2013-01-30 14:27:49 +0000382 return 0;
383}
384
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530385static struct platform_driver dt_cpufreq_platdrv = {
Shawn Guo5553f9e2013-01-30 14:27:49 +0000386 .driver = {
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530387 .name = "cpufreq-dt",
Shawn Guo5553f9e2013-01-30 14:27:49 +0000388 .owner = THIS_MODULE,
389 },
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530390 .probe = dt_cpufreq_probe,
391 .remove = dt_cpufreq_remove,
Shawn Guo5553f9e2013-01-30 14:27:49 +0000392};
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530393module_platform_driver(dt_cpufreq_platdrv);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000394
Viresh Kumar748c8762014-08-28 11:22:24 +0530395MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
Shawn Guo95ceafd2012-09-06 07:09:11 +0000396MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
Viresh Kumarbbcf0712014-09-09 19:58:03 +0530397MODULE_DESCRIPTION("Generic cpufreq driver");
Shawn Guo95ceafd2012-09-06 07:09:11 +0000398MODULE_LICENSE("GPL");