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gerrit-public.fairphone.software / kernel / msm-4.9 / 83125a3a189ec34fb22a04e8efad69ae6d52674a / . / arch / powerpc / sysdev / fsl_rio.h
blob: ae8e27405a0deeeb1df3715786ccd8003b44f3d8 [file] [log] [blame]
Liu Gang6ec4bed2011-11-12 20:02:28 +0800[diff] [blame]1/*
2 * Freescale MPC85xx/MPC86xx RapidIO support
3 *
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
7 *
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
12 *
13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
15 * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
16 * Liu Gang <Gang.Liu@freescale.com>
17 *
18 * Copyright 2005 MontaVista Software, Inc.
19 * Matt Porter <mporter@kernel.crashing.org>
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
25 */
26
27#ifndef __FSL_RIO_H
28#define __FSL_RIO_H
29
30#include <linux/rio.h>
31#include <linux/rio_drv.h>
32#include <linux/kfifo.h>
33
34#define RIO_REGS_WIN(mport) (((struct rio_priv *)(mport->priv))->regs_win)
35
36#define RIO_MAINT_WIN_SIZE 0x400000
37#define RIO_LTLEDCSR 0x0608
38
Liu Gangabc3aea2011-11-12 20:02:29 +0800[diff] [blame]39#define DOORBELL_ROWAR_EN 0x80000000
40#define DOORBELL_ROWAR_TFLOWLV 0x08000000 /* highest priority level */
41#define DOORBELL_ROWAR_PCI 0x02000000 /* PCI window */
42#define DOORBELL_ROWAR_NREAD 0x00040000 /* NREAD */
43#define DOORBELL_ROWAR_MAINTRD 0x00070000 /* maintenance read */
44#define DOORBELL_ROWAR_RES 0x00002000 /* wrtpy: reserverd */
45#define DOORBELL_ROWAR_MAINTWD 0x00007000
46#define DOORBELL_ROWAR_SIZE 0x0000000b /* window size is 4k */
47
48#define RIO_ATMU_REGS_PORT1_OFFSET 0x10c00
49#define RIO_ATMU_REGS_PORT2_OFFSET 0x10e00
50#define RIO_S_DBELL_REGS_OFFSET 0x13400
51#define RIO_S_PW_REGS_OFFSET 0x134e0
52#define RIO_ATMU_REGS_DBELL_OFFSET 0x10C40
53
54#define MAX_MSG_UNIT_NUM 2
55#define MAX_PORT_NUM 4
56
Liu Gang6ec4bed2011-11-12 20:02:28 +0800[diff] [blame]57struct rio_atmu_regs {
58 u32 rowtar;
59 u32 rowtear;
60 u32 rowbar;
Liu Gangabc3aea2011-11-12 20:02:29 +0800[diff] [blame]61 u32 pad1;
Liu Gang6ec4bed2011-11-12 20:02:28 +0800[diff] [blame]62 u32 rowar;
Liu Gangabc3aea2011-11-12 20:02:29 +0800[diff] [blame]63 u32 pad2[3];
64};
65
66struct rio_dbell_ring {
67 void *virt;
68 dma_addr_t phys;
Liu Gang6ec4bed2011-11-12 20:02:28 +0800[diff] [blame]69};
70
71struct rio_port_write_msg {
72 void *virt;
73 dma_addr_t phys;
74 u32 msg_count;
75 u32 err_count;
76 u32 discard_count;
77};
78
Liu Gangabc3aea2011-11-12 20:02:29 +0800[diff] [blame]79struct fsl_rio_dbell {
80 struct rio_mport *mport[MAX_PORT_NUM];
81 struct device *dev;
82 struct rio_dbell_regs __iomem *dbell_regs;
83 struct rio_dbell_ring dbell_ring;
84 int bellirq;
85};
86
87struct fsl_rio_pw {
88 struct device *dev;
89 struct rio_pw_regs __iomem *pw_regs;
90 struct rio_port_write_msg port_write_msg;
91 int pwirq;
92 struct work_struct pw_work;
93 struct kfifo pw_fifo;
94 spinlock_t pw_fifo_lock;
95};
96
Liu Gang6ec4bed2011-11-12 20:02:28 +0800[diff] [blame]97struct rio_priv {
98 struct device *dev;
99 void __iomem *regs_win;
100 struct rio_atmu_regs __iomem *atmu_regs;
101 struct rio_atmu_regs __iomem *maint_atmu_regs;
102 void __iomem *maint_win;
Liu Gang6ec4bed2011-11-12 20:02:28 +0800[diff] [blame]103 void *rmm_handle; /* RapidIO message manager(unit) Handle */
104};
105
106extern void __iomem *rio_regs_win;
Liu Gangabc3aea2011-11-12 20:02:29 +0800[diff] [blame]107extern void __iomem *rmu_regs_win;
108
109extern resource_size_t rio_law_start;
110
111extern struct fsl_rio_dbell *dbell;
112extern struct fsl_rio_pw *pw;
Liu Gang6ec4bed2011-11-12 20:02:28 +0800[diff] [blame]113
114extern int fsl_rio_setup_rmu(struct rio_mport *mport,
115 struct device_node *node);
Liu Gangabc3aea2011-11-12 20:02:29 +0800[diff] [blame]116extern int fsl_rio_port_write_init(struct fsl_rio_pw *pw);
Liu Gang6ec4bed2011-11-12 20:02:28 +0800[diff] [blame]117extern int fsl_rio_pw_enable(struct rio_mport *mport, int enable);
Liu Gangabc3aea2011-11-12 20:02:29 +0800[diff] [blame]118extern void fsl_rio_port_error_handler(int offset);
119extern int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell);
120
121extern int fsl_rio_doorbell_send(struct rio_mport *mport,
122 int index, u16 destid, u16 data);
123extern int fsl_add_outb_message(struct rio_mport *mport,
124 struct rio_dev *rdev,
125 int mbox, void *buffer, size_t len);
126extern int fsl_open_outb_mbox(struct rio_mport *mport,
127 void *dev_id, int mbox, int entries);
128extern void fsl_close_outb_mbox(struct rio_mport *mport, int mbox);
129extern int fsl_open_inb_mbox(struct rio_mport *mport,
130 void *dev_id, int mbox, int entries);
131extern void fsl_close_inb_mbox(struct rio_mport *mport, int mbox);
132extern int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf);
133extern void *fsl_get_inb_message(struct rio_mport *mport, int mbox);
Liu Gang6ec4bed2011-11-12 20:02:28 +0800[diff] [blame]134
135#endif