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gerrit-public.fairphone.software / kernel / msm-4.9 / 84a47e8cf6f87952efa16773bb39fe0c4a3cde28 / . / arch / arm64 / boot / dts / qcom / sdm845-sde.dtsi
blob: 0618f92610b26aa07e7569e92cf83f1b19dc46dd [file] [log] [blame]
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]1/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
14 mdss_mdp: qcom,mdss_mdp@ae00000 {
15 compatible = "qcom,sde-kms";
Lloyd Atkinson8f2bd8c2017-04-06 11:55:49 -0700[diff] [blame]16 reg = <0x0ae00000 0x81d40>,
Gopikrishnaiah Anandan06629532017-08-23 18:24:57 -0700[diff] [blame]17 <0x0aeb0000 0x2008>,
18 <0x0aeac000 0xf0>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]19 reg-names = "mdp_phys",
Gopikrishnaiah Anandan06629532017-08-23 18:24:57 -0700[diff] [blame]20 "vbif_phys",
21 "regdma_phys";
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]22
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]23 clocks =
24 <&clock_gcc GCC_DISP_AHB_CLK>,
25 <&clock_gcc GCC_DISP_AXI_CLK>,
26 <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]27 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]28 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
29 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
Dhaval Patel2cd94b12017-04-21 19:39:53 -0700[diff] [blame]30 clock-names = "gcc_iface", "gcc_bus", "iface_clk",
31 "bus_clk", "core_clk", "vsync_clk";
32 clock-rate = <0 0 0 0 300000000 19200000 0>;
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700[diff] [blame]33 clock-max-rate = <0 0 0 0 412500000 19200000 0>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]34
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]35 sde-vdd-supply = <&mdss_core_gdsc>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]36
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]37 /* interrupt config */
Archana Sathyakumar00a36ab2017-03-03 14:38:26 -0700[diff] [blame]38 interrupt-parent = <&pdc>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]39 interrupts = <0 83 0>;
40 interrupt-controller;
41 #interrupt-cells = <1>;
Patrick Dalycaf09c92017-04-18 16:30:52 -0700[diff] [blame]42 iommus = <&apps_smmu 0x880 0x8>,
43 <&apps_smmu 0xc80 0x8>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]44
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]45 #address-cells = <1>;
46 #size-cells = <0>;
47
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]48 /* hw blocks */
49 qcom,sde-off = <0x1000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]50 qcom,sde-len = <0x45C>;
51
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]52 qcom,sde-ctl-off = <0x2000 0x2200 0x2400
53 0x2600 0x2800>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]54 qcom,sde-ctl-size = <0xE4>;
55
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]56 qcom,sde-mixer-off = <0x45000 0x46000 0x47000
57 0x48000 0x49000 0x4a000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]58 qcom,sde-mixer-size = <0x320>;
59
Rajesh Yadavec93afb2017-06-08 19:28:33 +0530[diff] [blame]60 qcom,sde-dspp-top-off = <0x1300>;
61 qcom,sde-dspp-top-size = <0xc>;
62
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]63 qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
Ping Li2d6c5f92017-05-04 14:17:03 -0700[diff] [blame]64 qcom,sde-dspp-size = <0x17e0>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]65
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]66 qcom,sde-wb-off = <0x66000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]67 qcom,sde-wb-size = <0x2c8>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]68 qcom,sde-wb-xin-id = <6>;
69 qcom,sde-wb-id = <2>;
Steve Cohen76bc0982017-06-20 13:19:04 -0400[diff] [blame]70 qcom,sde-wb-clk-ctrl = <0x3b8 24>;
71
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]72 qcom,sde-intf-off = <0x6b000 0x6b800
73 0x6c000 0x6c800>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]74 qcom,sde-intf-size = <0x280>;
75
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]76 qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
77 qcom,sde-pp-off = <0x71000 0x71800
78 0x72000 0x72800 0x73000>;
79 qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x1>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]80 qcom,sde-pp-size = <0xd4>;
81
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]82 qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0>;
83 qcom,sde-cdm-off = <0x7a200>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]84 qcom,sde-cdm-size = <0x224>;
85
86 qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>;
87 qcom,sde-dsc-size = <0x140>;
88
Narendra Muppallaa0826c62017-06-12 11:55:33 -0700[diff] [blame]89 qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0 0x0>;
Ping Lic7dd65f2017-03-08 12:11:01 -0800[diff] [blame]90 qcom,sde-dither-version = <0x00010000>;
91 qcom,sde-dither-size = <0x20>;
92
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]93 qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
94 "dma", "dma", "dma", "dma";
95
96 qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
97 0x25000 0x27000 0x29000 0x2b000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]98 qcom,sde-sspp-src-size = <0x1c8>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]99
100 qcom,sde-sspp-xin-id = <0 4 8 12
101 1 5 9 13>;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]102 qcom,sde-sspp-excl-rect = <1 1 1 1
103 1 1 1 1>;
Jeykumar Sankaran07515162017-05-16 13:02:33 -0700[diff] [blame]104 qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
105 qcom,sde-smart-dma-rev = "smart_dma_v2";
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]106
Veera Sundaram Sankaran370b9912017-01-10 18:03:42 -0800[diff] [blame]107 qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>;
108
109 qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
110 0xb0 0xc8 0xe0 0xf8 0x110>;
111
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]112 /* offsets are relative to "mdp_phys + qcom,sde-off */
113 qcom,sde-sspp-clk-ctrl =
114 <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
115 <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
116 qcom,sde-sspp-csc-off = <0x1a00>;
117 qcom,sde-csc-type = "csc-10bit";
118 qcom,sde-qseed-type = "qseedv3";
119 qcom,sde-sspp-qseed-off = <0xa00>;
120 qcom,sde-mixer-linewidth = <2560>;
121 qcom,sde-sspp-linewidth = <2560>;
Alan Kwongd939be42017-03-08 19:37:38 -0800[diff] [blame]122 qcom,sde-wb-linewidth = <4096>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]123 qcom,sde-mixer-blendstages = <0xb>;
124 qcom,sde-highest-bank-bit = <0x2>;
Clarence Ip03f2ffe2017-04-28 16:12:17 -0700[diff] [blame]125 qcom,sde-ubwc-version = <0x200>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]126 qcom,sde-panic-per-pipe;
127 qcom,sde-has-cdp;
128 qcom,sde-has-src-split;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]129 qcom,sde-has-dim-layer;
Veera Sundaram Sankarana92444a2017-04-07 15:48:07 -0700[diff] [blame]130 qcom,sde-has-idle-pc;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]131 qcom,sde-max-bw-low-kbps = <9600000>;
132 qcom,sde-max-bw-high-kbps = <9600000>;
133 qcom,sde-dram-channels = <2>;
134 qcom,sde-num-nrt-paths = <0>;
Gopikrishnaiah Anandanaaf6dcd2017-02-08 14:10:18 -0800[diff] [blame]135 qcom,sde-dspp-ad-version = <0x00040000>;
136 qcom,sde-dspp-ad-off = <0x28000 0x27000>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]137
138 qcom,sde-vbif-off = <0>;
139 qcom,sde-vbif-size = <0x1040>;
140 qcom,sde-vbif-id = <0>;
Clarence Ip0b5f4412017-05-17 11:29:24 -0400[diff] [blame]141 qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
142 qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]143
Alan Kwong1641b0b2017-04-19 09:01:13 -0700[diff] [blame]144 qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
145 qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
146
Alan Kwonge67b3792017-04-27 15:57:50 -0700[diff] [blame]147 qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000
148 0x00000000>;
149 qcom,sde-safe-lut = <0xfffc 0xff00 0xffff 0xffff>;
150 qcom,sde-qos-lut-linear =
151 <4 0x00000000 0x00000357>,
152 <5 0x00000000 0x00003357>,
153 <6 0x00000000 0x00023357>,
154 <7 0x00000000 0x00223357>,
155 <8 0x00000000 0x02223357>,
156 <9 0x00000000 0x22223357>,
157 <10 0x00000002 0x22223357>,
158 <11 0x00000022 0x22223357>,
159 <12 0x00000222 0x22223357>,
160 <13 0x00002222 0x22223357>,
161 <14 0x00012222 0x22223357>,
162 <0 0x00112222 0x22223357>;
163 qcom,sde-qos-lut-macrotile =
164 <10 0x00000003 0x44556677>,
165 <11 0x00000033 0x44556677>,
166 <12 0x00000233 0x44556677>,
167 <13 0x00002233 0x44556677>,
168 <14 0x00012233 0x44556677>,
169 <0 0x00112233 0x44556677>;
170 qcom,sde-qos-lut-nrt =
171 <0 0x00000000 0x00000000>;
172 qcom,sde-qos-lut-cwb =
173 <0 0x75300000 0x00000000>;
174
Alan Kwong23ef3f392017-04-28 11:09:06 -0700[diff] [blame]175 qcom,sde-cdp-setting = <1 1>, <1 0>;
176
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]177 qcom,sde-inline-rotator = <&mdss_rotator 0>;
Veera Sundaram Sankaran5f9ef0d2017-05-24 18:49:53 -0700[diff] [blame]178 qcom,sde-inline-rot-xin = <10 11>;
179 qcom,sde-inline-rot-xin-type = "sspp", "wb";
180
181 /* offsets are relative to "mdp_phys + qcom,sde-off */
182 qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>;
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]183
Gopikrishnaiah Anandan06629532017-08-23 18:24:57 -0700[diff] [blame]184 qcom,sde-reg-dma-off = <0>;
185 qcom,sde-reg-dma-version = <0x1>;
186 qcom,sde-reg-dma-trigger-off = <0x119c>;
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]187
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]188 qcom,sde-sspp-vig-blocks {
189 qcom,sde-vig-csc-off = <0x1a00>;
190 qcom,sde-vig-qseed-off = <0xa00>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]191 qcom,sde-vig-qseed-size = <0xa0>;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]192 };
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]193
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]194 qcom,sde-dspp-blocks {
Rajesh Yadavec93afb2017-06-08 19:28:33 +0530[diff] [blame]195 qcom,sde-dspp-igc = <0x0 0x00030001>;
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]196 qcom,sde-dspp-vlut = <0xa00 0x00010008>;
197 qcom,sde-dspp-gamut = <0x1000 0x00040000>;
Rajesh Yadavd490cb62017-07-04 13:20:42 +0530[diff] [blame]198 qcom,sde-dspp-pcc = <0x1700 0x00040000>;
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]199 qcom,sde-dspp-gc = <0x17c0 0x00010008>;
200 };
201
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]202 qcom,platform-supply-entries {
203 #address-cells = <1>;
204 #size-cells = <0>;
205
206 qcom,platform-supply-entry@0 {
207 reg = <0>;
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]208 qcom,supply-name = "sde-vdd";
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]209 qcom,supply-min-voltage = <0>;
210 qcom,supply-max-voltage = <0>;
211 qcom,supply-enable-load = <0>;
212 qcom,supply-disable-load = <0>;
213 };
214 };
215
Abhijit Kulkarni1774dac2017-05-01 10:51:02 -0700[diff] [blame]216 smmu_sde_sec: qcom,smmu_sde_sec_cb {
217 compatible = "qcom,smmu_sde_sec";
218 iommus = <&apps_smmu 0x881 0x8>,
219 <&apps_smmu 0xc81 0x8>;
220 };
221
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]222 /* data and reg bus scale settings */
223 qcom,sde-data-bus {
Alan Kwonge9b257b2017-05-16 11:40:50 -0700[diff] [blame]224 qcom,msm-bus,name = "mdss_sde_mnoc";
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]225 qcom,msm-bus,num-cases = <3>;
226 qcom,msm-bus,num-paths = <2>;
227 qcom,msm-bus,vectors-KBps =
Alan Kwonge9b257b2017-05-16 11:40:50 -0700[diff] [blame]228 <22 773 0 0>, <23 773 0 0>,
229 <22 773 0 6400000>, <23 773 0 6400000>,
230 <22 773 0 6400000>, <23 773 0 6400000>;
231 };
232
233 qcom,sde-llcc-bus {
234 qcom,msm-bus,name = "mdss_sde_llcc";
235 qcom,msm-bus,num-cases = <3>;
236 qcom,msm-bus,num-paths = <1>;
237 qcom,msm-bus,vectors-KBps =
238 <132 770 0 0>,
239 <132 770 0 6400000>,
240 <132 770 0 6400000>;
241 };
242
243 qcom,sde-ebi-bus {
244 qcom,msm-bus,name = "mdss_sde_ebi";
245 qcom,msm-bus,num-cases = <3>;
246 qcom,msm-bus,num-paths = <1>;
247 qcom,msm-bus,vectors-KBps =
248 <129 512 0 0>,
249 <129 512 0 6400000>,
250 <129 512 0 6400000>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]251 };
252
253 qcom,sde-reg-bus {
254 qcom,msm-bus,name = "mdss_reg";
255 qcom,msm-bus,num-cases = <4>;
256 qcom,msm-bus,num-paths = <1>;
257 qcom,msm-bus,active-only;
258 qcom,msm-bus,vectors-KBps =
259 <1 590 0 0>,
260 <1 590 0 76800>,
261 <1 590 0 150000>,
262 <1 590 0 300000>;
263 };
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]264 };
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]265
266 sde_rscc: qcom,sde_rscc@af20000 {
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]267 cell-index = <0>;
268 compatible = "qcom,sde-rsc";
269 reg = <0xaf20000 0x1c44>,
270 <0xaf30000 0x3fd4>;
271 reg-names = "drv", "wrapper";
272 qcom,sde-rsc-version = <1>;
273
274 vdd-supply = <&mdss_core_gdsc>;
Dhaval Patel7556ced2017-02-10 19:53:10 -0800[diff] [blame]275 clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
276 <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
277 clock-names = "vsync_clk", "iface_clk";
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]278 clock-rate = <0 0>;
279
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]280 qcom,sde-dram-channels = <2>;
281
Dhaval Patel7556ced2017-02-10 19:53:10 -0800[diff] [blame]282 mboxes = <&disp_rsc 0>;
283 mbox-names = "disp_rsc";
284
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]285 /* data and reg bus scale settings */
286 qcom,sde-data-bus {
Alan Kwonge9b257b2017-05-16 11:40:50 -0700[diff] [blame]287 qcom,msm-bus,name = "disp_rsc_mnoc";
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]288 qcom,msm-bus,active-only;
289 qcom,msm-bus,num-cases = <3>;
290 qcom,msm-bus,num-paths = <2>;
291 qcom,msm-bus,vectors-KBps =
Alan Kwonge9b257b2017-05-16 11:40:50 -0700[diff] [blame]292 <20003 20515 0 0>, <20004 20515 0 0>,
293 <20003 20515 0 6400000>, <20004 20515 0 6400000>,
294 <20003 20515 0 6400000>, <20004 20515 0 6400000>;
295 };
296
297 qcom,sde-llcc-bus {
298 qcom,msm-bus,name = "disp_rsc_llcc";
299 qcom,msm-bus,active-only;
300 qcom,msm-bus,num-cases = <3>;
301 qcom,msm-bus,num-paths = <1>;
302 qcom,msm-bus,vectors-KBps =
303 <20001 20513 0 0>,
304 <20001 20513 0 6400000>,
305 <20001 20513 0 6400000>;
306 };
307
308 qcom,sde-ebi-bus {
309 qcom,msm-bus,name = "disp_rsc_ebi";
310 qcom,msm-bus,active-only;
311 qcom,msm-bus,num-cases = <3>;
312 qcom,msm-bus,num-paths = <1>;
313 qcom,msm-bus,vectors-KBps =
314 <20000 20512 0 0>,
315 <20000 20512 0 6400000>,
316 <20000 20512 0 6400000>;
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]317 };
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]318 };
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]319
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]320 mdss_rotator: qcom,mdss_rotator@ae00000 {
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]321 compatible = "qcom,sde_rotator";
322 reg = <0x0ae00000 0xac000>,
323 <0x0aeb8000 0x3000>;
324 reg-names = "mdp_phys",
325 "rot_vbif_phys";
326
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]327 #list-cells = <1>;
328
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]329 qcom,mdss-rot-mode = <1>;
330 qcom,mdss-highest-bank-bit = <0x2>;
331
332 /* Bus Scale Settings */
333 qcom,msm-bus,name = "mdss_rotator";
334 qcom,msm-bus,num-cases = <3>;
335 qcom,msm-bus,num-paths = <1>;
336 qcom,msm-bus,vectors-KBps =
337 <25 512 0 0>,
338 <25 512 0 6400000>,
339 <25 512 0 6400000>;
340
341 rot-vdd-supply = <&mdss_core_gdsc>;
342 qcom,supply-names = "rot-vdd";
343
344 clocks =
345 <&clock_gcc GCC_DISP_AHB_CLK>,
346 <&clock_gcc GCC_DISP_AXI_CLK>,
347 <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]348 <&clock_dispcc DISP_CC_MDSS_ROT_CLK>,
349 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>;
350 clock-names = "gcc_iface", "gcc_bus",
Clarence Ip015924e2017-05-01 13:28:03 -0700[diff] [blame]351 "iface_clk", "rot_clk", "axi_clk";
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]352
353 interrupt-parent = <&mdss_mdp>;
354 interrupts = <2 0>;
355
Veera Sundaram Sankaran04883492017-05-12 12:35:36 -0700[diff] [blame]356 /* Offline rotator QoS setting */
Veera Sundaram Sankaranf28be032017-04-20 08:16:41 -0700[diff] [blame]357 qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
Alan Kwong8efe4a82017-06-30 16:05:50 -0400[diff] [blame]358 qcom,mdss-rot-vbif-memtype = <3 3>;
Veera Sundaram Sankaranfd4b37d2017-05-11 12:44:38 -0700[diff] [blame]359 qcom,mdss-rot-cdp-setting = <1 1>;
Veera Sundaram Sankaran04883492017-05-12 12:35:36 -0700[diff] [blame]360 qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
361 qcom,mdss-rot-danger-lut = <0x0 0x0>;
362 qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
363
364 /* Inline rotator QoS Setting */
365 /* setting default register values for RD - qos/danger/safe */
366 qcom,mdss-inline-rot-qos-lut = <0x44556677 0x00112233
367 0x44556677 0x00112233>;
368 qcom,mdss-inline-rot-danger-lut = <0x0055aaff 0x0000ffff>;
369 qcom,mdss-inline-rot-safe-lut = <0x0000f000 0x0000ff00>;
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]370
371 qcom,mdss-default-ot-rd-limit = <32>;
372 qcom,mdss-default-ot-wr-limit = <32>;
373
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]374 qcom,mdss-sbuf-headroom = <20>;
375
376 cache-slice-names = "rotator";
377 cache-slices = <&llcc 4>;
378
Veera Sundaram Sankaran06418032017-06-30 14:12:58 -0700[diff] [blame]379 /* reg bus scale settings */
380 rot_reg: qcom,rot-reg-bus {
381 qcom,msm-bus,name = "mdss_rot_reg";
382 qcom,msm-bus,num-cases = <2>;
383 qcom,msm-bus,num-paths = <1>;
384 qcom,msm-bus,active-only;
385 qcom,msm-bus,vectors-KBps =
386 <1 590 0 0>,
387 <1 590 0 76800>;
388 };
389
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]390 smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
391 compatible = "qcom,smmu_sde_rot_unsec";
Patrick Dalyc4aaa902017-04-24 12:45:11 -0700[diff] [blame]392 iommus = <&apps_smmu 0x1090 0x0>;
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]393 };
394
395 smmu_rot_sec: qcom,smmu_rot_sec_cb {
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]396 compatible = "qcom,smmu_sde_rot_sec";
Patrick Dalyc4aaa902017-04-24 12:45:11 -0700[diff] [blame]397 iommus = <&apps_smmu 0x1091 0x0>;
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]398 };
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]399 };
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]400
401 mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]402 compatible = "qcom,dsi-ctrl-hw-v2.2";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]403 label = "dsi-ctrl-0";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]404 cell-index = <0>;
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]405 reg = <0xae94000 0x400>,
406 <0xaf08000 0x4>;
407 reg-names = "dsi_ctrl", "disp_cc_base";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]408 interrupt-parent = <&mdss_mdp>;
409 interrupts = <4 0>;
410 vdda-1p2-supply = <&pm8998_l26>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]411 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
412 <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
413 <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
414 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]415 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
416 <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]417 clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]418 "pixel_clk", "pixel_clk_rcg",
419 "esc_clk";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]420
421 qcom,ctrl-supply-entries {
422 #address-cells = <1>;
423 #size-cells = <0>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]424
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]425 qcom,ctrl-supply-entry@0 {
426 reg = <0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]427 qcom,supply-name = "vdda-1p2";
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]428 qcom,supply-min-voltage = <1200000>;
429 qcom,supply-max-voltage = <1200000>;
430 qcom,supply-enable-load = <21800>;
431 qcom,supply-disable-load = <4>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]432 };
433 };
434 };
435
436 mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]437 compatible = "qcom,dsi-ctrl-hw-v2.2";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]438 label = "dsi-ctrl-1";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]439 cell-index = <1>;
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]440 reg = <0xae96000 0x400>,
441 <0xaf08000 0x4>;
442 reg-names = "dsi_ctrl", "disp_cc_base";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]443 interrupt-parent = <&mdss_mdp>;
444 interrupts = <5 0>;
445 vdda-1p2-supply = <&pm8998_l26>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]446 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
447 <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
448 <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
449 <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
450 <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
451 <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]452 clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]453 "pixel_clk", "pixel_clk_rcg", "esc_clk";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]454 qcom,ctrl-supply-entries {
455 #address-cells = <1>;
456 #size-cells = <0>;
457
458 qcom,ctrl-supply-entry@0 {
459 reg = <0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]460 qcom,supply-name = "vdda-1p2";
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]461 qcom,supply-min-voltage = <1200000>;
462 qcom,supply-max-voltage = <1200000>;
463 qcom,supply-enable-load = <21800>;
464 qcom,supply-disable-load = <4>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]465 };
466 };
467 };
468
469 mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
470 compatible = "qcom,dsi-phy-v3.0";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]471 label = "dsi-phy-0";
472 cell-index = <0>;
473 reg = <0xae94400 0x7c0>;
474 reg-names = "dsi_phy";
475 gdsc-supply = <&mdss_core_gdsc>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]476 vdda-0p9-supply = <&pm8998_l1>;
Shashank Babu Chinta Venkata5292d192017-04-05 15:19:17 -0700[diff] [blame]477 qcom,platform-strength-ctrl = [55 03
478 55 03
479 55 03
480 55 03
481 55 00];
482 qcom,platform-lane-config = [00 00 00 00
483 00 00 00 00
484 00 00 00 00
485 00 00 00 00
486 00 00 00 80];
487 qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]488 qcom,phy-supply-entries {
489 #address-cells = <1>;
490 #size-cells = <0>;
491 qcom,phy-supply-entry@0 {
492 reg = <0>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]493 qcom,supply-name = "vdda-0p9";
494 qcom,supply-min-voltage = <880000>;
495 qcom,supply-max-voltage = <880000>;
496 qcom,supply-enable-load = <36000>;
497 qcom,supply-disable-load = <32>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]498 };
499 };
500 };
501
502 mdss_dsi_phy1: qcom,mdss_dsi_phy0@ae96400 {
503 compatible = "qcom,dsi-phy-v3.0";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]504 label = "dsi-phy-1";
505 cell-index = <1>;
506 reg = <0xae96400 0x7c0>;
507 reg-names = "dsi_phy";
508 gdsc-supply = <&mdss_core_gdsc>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]509 vdda-0p9-supply = <&pm8998_l1>;
Shashank Babu Chinta Venkata5292d192017-04-05 15:19:17 -0700[diff] [blame]510 qcom,platform-strength-ctrl = [55 03
511 55 03
512 55 03
513 55 03
514 55 00];
515 qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
516 qcom,platform-lane-config = [00 00 00 00
517 00 00 00 00
518 00 00 00 00
519 00 00 00 00
520 00 00 00 80];
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]521 qcom,phy-supply-entries {
522 #address-cells = <1>;
523 #size-cells = <0>;
524 qcom,phy-supply-entry@0 {
525 reg = <0>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]526 qcom,supply-name = "vdda-0p9";
527 qcom,supply-min-voltage = <880000>;
528 qcom,supply-max-voltage = <880000>;
529 qcom,supply-enable-load = <36000>;
530 qcom,supply-disable-load = <32>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]531 };
532 };
533 };
534
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]535};