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Philipp Zabelb7482f52008-05-28 17:58:06 +01001/*
2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
Philipp Zabel1abd9182009-06-15 22:18:23 +02008 * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>
Philipp Zabelb7482f52008-05-28 17:58:06 +01009 *
10 * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
11 * codec model.
12 *
13 * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
14 * Copyright 2005 Openedhand Ltd.
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/types.h>
Philipp Zabelb7482f52008-05-28 17:58:06 +010020#include <linux/slab.h>
21#include <linux/errno.h>
Philipp Zabel1abd9182009-06-15 22:18:23 +020022#include <linux/gpio.h>
Philipp Zabelb7482f52008-05-28 17:58:06 +010023#include <linux/delay.h>
24#include <linux/i2c.h>
Philipp Zabelef9e5e52009-03-03 16:10:54 +010025#include <linux/workqueue.h>
Philipp Zabelb7482f52008-05-28 17:58:06 +010026#include <sound/core.h>
27#include <sound/control.h>
28#include <sound/initval.h>
Philipp Zabelb7482f52008-05-28 17:58:06 +010029#include <sound/soc.h>
Philipp Zabelb7482f52008-05-28 17:58:06 +010030#include <sound/tlv.h>
Philipp Zabel1abd9182009-06-15 22:18:23 +020031#include <sound/uda1380.h>
Philipp Zabelb7482f52008-05-28 17:58:06 +010032
33#include "uda1380.h"
34
Philipp Zabel1abd9182009-06-15 22:18:23 +020035/* codec private data */
36struct uda1380_priv {
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +000037 struct snd_soc_codec *codec;
Philipp Zabel1abd9182009-06-15 22:18:23 +020038 unsigned int dac_clk;
39 struct work_struct work;
Vasily Khoruzhick8614d312010-08-30 11:28:07 +030040 void *control_data;
Philipp Zabel1abd9182009-06-15 22:18:23 +020041};
42
Philipp Zabelb7482f52008-05-28 17:58:06 +010043/*
44 * uda1380 register cache
45 */
46static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
47 0x0502, 0x0000, 0x0000, 0x3f3f,
48 0x0202, 0x0000, 0x0000, 0x0000,
49 0x0000, 0x0000, 0x0000, 0x0000,
50 0x0000, 0x0000, 0x0000, 0x0000,
51 0x0000, 0xff00, 0x0000, 0x4800,
52 0x0000, 0x0000, 0x0000, 0x0000,
53 0x0000, 0x0000, 0x0000, 0x0000,
54 0x0000, 0x0000, 0x0000, 0x0000,
55 0x0000, 0x8000, 0x0002, 0x0000,
56};
57
Philipp Zabelef9e5e52009-03-03 16:10:54 +010058static unsigned long uda1380_cache_dirty;
59
Philipp Zabelb7482f52008-05-28 17:58:06 +010060/*
61 * read uda1380 register cache
62 */
63static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
64 unsigned int reg)
65{
66 u16 *cache = codec->reg_cache;
67 if (reg == UDA1380_RESET)
68 return 0;
69 if (reg >= UDA1380_CACHEREGNUM)
70 return -1;
71 return cache[reg];
72}
73
74/*
75 * write uda1380 register cache
76 */
77static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
78 u16 reg, unsigned int value)
79{
80 u16 *cache = codec->reg_cache;
Philipp Zabelef9e5e52009-03-03 16:10:54 +010081
Philipp Zabelb7482f52008-05-28 17:58:06 +010082 if (reg >= UDA1380_CACHEREGNUM)
83 return;
Philipp Zabelef9e5e52009-03-03 16:10:54 +010084 if ((reg >= 0x10) && (cache[reg] != value))
85 set_bit(reg - 0x10, &uda1380_cache_dirty);
Philipp Zabelb7482f52008-05-28 17:58:06 +010086 cache[reg] = value;
87}
88
89/*
90 * write to the UDA1380 register space
91 */
92static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
93 unsigned int value)
94{
95 u8 data[3];
96
97 /* data is
98 * data[0] is register offset
99 * data[1] is MS byte
100 * data[2] is LS byte
101 */
102 data[0] = reg;
103 data[1] = (value & 0xff00) >> 8;
104 data[2] = value & 0x00ff;
105
106 uda1380_write_reg_cache(codec, reg, value);
107
108 /* the interpolator & decimator regs must only be written when the
109 * codec DAI is active.
110 */
Lars-Peter Clausen5c898e72014-03-05 13:17:45 +0100111 if (!snd_soc_codec_is_active(codec) && (reg >= UDA1380_MVOL))
Philipp Zabelb7482f52008-05-28 17:58:06 +0100112 return 0;
113 pr_debug("uda1380: hw write %x val %x\n", reg, value);
114 if (codec->hw_write(codec->control_data, data, 3) == 3) {
115 unsigned int val;
116 i2c_master_send(codec->control_data, data, 1);
117 i2c_master_recv(codec->control_data, data, 2);
118 val = (data[0]<<8) | data[1];
119 if (val != value) {
120 pr_debug("uda1380: READ BACK VAL %x\n",
121 (data[0]<<8) | data[1]);
122 return -EIO;
123 }
Philipp Zabelef9e5e52009-03-03 16:10:54 +0100124 if (reg >= 0x10)
125 clear_bit(reg - 0x10, &uda1380_cache_dirty);
Philipp Zabelb7482f52008-05-28 17:58:06 +0100126 return 0;
127 } else
128 return -EIO;
129}
130
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300131static void uda1380_sync_cache(struct snd_soc_codec *codec)
132{
133 int reg;
134 u8 data[3];
135 u16 *cache = codec->reg_cache;
136
137 /* Sync reg_cache with the hardware */
138 for (reg = 0; reg < UDA1380_MVOL; reg++) {
139 data[0] = reg;
140 data[1] = (cache[reg] & 0xff00) >> 8;
141 data[2] = cache[reg] & 0x00ff;
142 if (codec->hw_write(codec->control_data, data, 3) != 3)
143 dev_err(codec->dev, "%s: write to reg 0x%x failed\n",
144 __func__, reg);
145 }
146}
147
148static int uda1380_reset(struct snd_soc_codec *codec)
149{
150 struct uda1380_platform_data *pdata = codec->dev->platform_data;
151
152 if (gpio_is_valid(pdata->gpio_reset)) {
153 gpio_set_value(pdata->gpio_reset, 1);
154 mdelay(1);
155 gpio_set_value(pdata->gpio_reset, 0);
156 } else {
157 u8 data[3];
158
159 data[0] = UDA1380_RESET;
160 data[1] = 0;
161 data[2] = 0;
162
163 if (codec->hw_write(codec->control_data, data, 3) != 3) {
164 dev_err(codec->dev, "%s: failed\n", __func__);
165 return -EIO;
166 }
167 }
168
169 return 0;
170}
Philipp Zabelb7482f52008-05-28 17:58:06 +0100171
Philipp Zabelef9e5e52009-03-03 16:10:54 +0100172static void uda1380_flush_work(struct work_struct *work)
173{
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000174 struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
175 struct snd_soc_codec *uda1380_codec = uda1380->codec;
Philipp Zabelef9e5e52009-03-03 16:10:54 +0100176 int bit, reg;
177
Akinobu Mita984b3f52010-03-05 13:41:37 -0800178 for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
Philipp Zabelef9e5e52009-03-03 16:10:54 +0100179 reg = 0x10 + bit;
180 pr_debug("uda1380: flush reg %x val %x:\n", reg,
181 uda1380_read_reg_cache(uda1380_codec, reg));
182 uda1380_write(uda1380_codec, reg,
183 uda1380_read_reg_cache(uda1380_codec, reg));
184 clear_bit(bit, &uda1380_cache_dirty);
185 }
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000186
Philipp Zabelef9e5e52009-03-03 16:10:54 +0100187}
188
Philipp Zabelb7482f52008-05-28 17:58:06 +0100189/* declarations of ALSA reg_elem_REAL controls */
190static const char *uda1380_deemp[] = {
191 "None",
192 "32kHz",
193 "44.1kHz",
194 "48kHz",
195 "96kHz",
196};
197static const char *uda1380_input_sel[] = {
198 "Line",
199 "Mic + Line R",
200 "Line L",
201 "Mic",
202};
203static const char *uda1380_output_sel[] = {
204 "DAC",
205 "Analog Mixer",
206};
207static const char *uda1380_spf_mode[] = {
208 "Flat",
209 "Minimum1",
210 "Minimum2",
211 "Maximum"
212};
213static const char *uda1380_capture_sel[] = {
214 "ADC",
215 "Digital Mixer"
216};
217static const char *uda1380_sel_ns[] = {
218 "3rd-order",
219 "5th-order"
220};
221static const char *uda1380_mix_control[] = {
222 "off",
223 "PCM only",
224 "before sound processing",
225 "after sound processing"
226};
227static const char *uda1380_sdet_setting[] = {
228 "3200",
229 "4800",
230 "9600",
231 "19200"
232};
233static const char *uda1380_os_setting[] = {
234 "single-speed",
235 "double-speed (no mixing)",
236 "quad-speed (no mixing)"
237};
238
239static const struct soc_enum uda1380_deemp_enum[] = {
Takashi Iwai1dbb3482014-02-18 10:32:16 +0100240 SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, ARRAY_SIZE(uda1380_deemp),
241 uda1380_deemp),
242 SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, ARRAY_SIZE(uda1380_deemp),
243 uda1380_deemp),
Philipp Zabelb7482f52008-05-28 17:58:06 +0100244};
Takashi Iwai1dbb3482014-02-18 10:32:16 +0100245static SOC_ENUM_SINGLE_DECL(uda1380_input_sel_enum,
246 UDA1380_ADC, 2, uda1380_input_sel); /* SEL_MIC, SEL_LNA */
247static SOC_ENUM_SINGLE_DECL(uda1380_output_sel_enum,
248 UDA1380_PM, 7, uda1380_output_sel); /* R02_EN_AVC */
249static SOC_ENUM_SINGLE_DECL(uda1380_spf_enum,
250 UDA1380_MODE, 14, uda1380_spf_mode); /* M */
251static SOC_ENUM_SINGLE_DECL(uda1380_capture_sel_enum,
252 UDA1380_IFACE, 6, uda1380_capture_sel); /* SEL_SOURCE */
253static SOC_ENUM_SINGLE_DECL(uda1380_sel_ns_enum,
254 UDA1380_MIXER, 14, uda1380_sel_ns); /* SEL_NS */
255static SOC_ENUM_SINGLE_DECL(uda1380_mix_enum,
256 UDA1380_MIXER, 12, uda1380_mix_control); /* MIX, MIX_POS */
257static SOC_ENUM_SINGLE_DECL(uda1380_sdet_enum,
258 UDA1380_MIXER, 4, uda1380_sdet_setting); /* SD_VALUE */
259static SOC_ENUM_SINGLE_DECL(uda1380_os_enum,
260 UDA1380_MIXER, 0, uda1380_os_setting); /* OS */
Philipp Zabelb7482f52008-05-28 17:58:06 +0100261
262/*
263 * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
264 */
265static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
266
267/*
268 * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
269 * from -66 dB in 0.5 dB steps (2 dB steps, really) and
270 * from -52 dB in 0.25 dB steps
271 */
272static const unsigned int mvol_tlv[] = {
273 TLV_DB_RANGE_HEAD(3),
274 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
275 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
276 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
277};
278
279/*
280 * from -72 dB in 1.5 dB steps (6 dB steps really),
281 * from -66 dB in 0.75 dB steps (3 dB steps really),
282 * from -60 dB in 0.5 dB steps (2 dB steps really) and
283 * from -46 dB in 0.25 dB steps
284 */
285static const unsigned int vc_tlv[] = {
286 TLV_DB_RANGE_HEAD(4),
287 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
288 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
289 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
290 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
291};
292
293/* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
294static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
295
296/* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
297 * off at 18 dB max) */
298static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
299
300/* from -63 to 24 dB in 0.5 dB steps (-128...48) */
301static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
302
303/* from 0 to 24 dB in 3 dB steps */
304static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
305
306/* from 0 to 30 dB in 2 dB steps */
307static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
308
309static const struct snd_kcontrol_new uda1380_snd_controls[] = {
310 SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */
311 SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
312 SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */
313 SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */
314 SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */
315 SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */
316 SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */
317/**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */
318 SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */
319 SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */
320 SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */
321 SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */
322 SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
323 SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
324 SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
Philipp Zabelb7482f52008-05-28 17:58:06 +0100325 SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
326 SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
327 SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
328 SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */
329/**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */
330 SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
331 SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
332 SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */
333 SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */
334 SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */
335 SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */
336 SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */
337 /* -5.5, -8, -11.5, -14 dBFS */
338 SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
339};
340
Philipp Zabelb7482f52008-05-28 17:58:06 +0100341/* Input mux */
342static const struct snd_kcontrol_new uda1380_input_mux_control =
343 SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
344
345/* Output mux */
346static const struct snd_kcontrol_new uda1380_output_mux_control =
347 SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
348
349/* Capture mux */
350static const struct snd_kcontrol_new uda1380_capture_mux_control =
351 SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
352
353
354static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
355 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
356 &uda1380_input_mux_control),
357 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
358 &uda1380_output_mux_control),
359 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
360 &uda1380_capture_mux_control),
361 SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
362 SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
363 SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
364 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
365 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
366 SND_SOC_DAPM_INPUT("VINM"),
367 SND_SOC_DAPM_INPUT("VINL"),
368 SND_SOC_DAPM_INPUT("VINR"),
369 SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
370 SND_SOC_DAPM_OUTPUT("VOUTLHP"),
371 SND_SOC_DAPM_OUTPUT("VOUTRHP"),
372 SND_SOC_DAPM_OUTPUT("VOUTL"),
373 SND_SOC_DAPM_OUTPUT("VOUTR"),
374 SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
375 SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
376};
377
Axel Lin58fa8e42011-12-19 13:54:38 +0800378static const struct snd_soc_dapm_route uda1380_dapm_routes[] = {
Philipp Zabelb7482f52008-05-28 17:58:06 +0100379
380 /* output mux */
381 {"HeadPhone Driver", NULL, "Output Mux"},
382 {"VOUTR", NULL, "Output Mux"},
383 {"VOUTL", NULL, "Output Mux"},
384
385 {"Analog Mixer", NULL, "VINR"},
386 {"Analog Mixer", NULL, "VINL"},
387 {"Analog Mixer", NULL, "DAC"},
388
389 {"Output Mux", "DAC", "DAC"},
390 {"Output Mux", "Analog Mixer", "Analog Mixer"},
391
392 /* {"DAC", "Digital Mixer", "I2S" } */
393
394 /* headphone driver */
395 {"VOUTLHP", NULL, "HeadPhone Driver"},
396 {"VOUTRHP", NULL, "HeadPhone Driver"},
397
398 /* input mux */
399 {"Left ADC", NULL, "Input Mux"},
400 {"Input Mux", "Mic", "Mic LNA"},
401 {"Input Mux", "Mic + Line R", "Mic LNA"},
402 {"Input Mux", "Line L", "Left PGA"},
403 {"Input Mux", "Line", "Left PGA"},
404
405 /* right input */
406 {"Right ADC", "Mic + Line R", "Right PGA"},
407 {"Right ADC", "Line", "Right PGA"},
408
409 /* inputs */
410 {"Mic LNA", NULL, "VINM"},
411 {"Left PGA", NULL, "VINL"},
412 {"Right PGA", NULL, "VINR"},
413};
414
Philipp Zabel5b247442009-02-03 17:19:40 +0100415static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
Philipp Zabelb7482f52008-05-28 17:58:06 +0100416 unsigned int fmt)
417{
418 struct snd_soc_codec *codec = codec_dai->codec;
419 int iface;
420
421 /* set up DAI based upon fmt */
422 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
423 iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
424
Philipp Zabelb7482f52008-05-28 17:58:06 +0100425 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
426 case SND_SOC_DAIFMT_I2S:
427 iface |= R01_SFORI_I2S | R01_SFORO_I2S;
428 break;
429 case SND_SOC_DAIFMT_LSB:
Philipp Zabel5b247442009-02-03 17:19:40 +0100430 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
Philipp Zabelb7482f52008-05-28 17:58:06 +0100431 break;
432 case SND_SOC_DAIFMT_MSB:
Philipp Zabel5b247442009-02-03 17:19:40 +0100433 iface |= R01_SFORI_MSB | R01_SFORO_MSB;
434 }
435
Philipp Zabel5f2a9382009-03-03 16:10:52 +0100436 /* DATAI is slave only, so in single-link mode, this has to be slave */
437 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
438 return -EINVAL;
Philipp Zabel5b247442009-02-03 17:19:40 +0100439
Vasily Khoruzhick810e4422015-05-03 21:11:47 +0300440 uda1380_write_reg_cache(codec, UDA1380_IFACE, iface);
Philipp Zabel5b247442009-02-03 17:19:40 +0100441
442 return 0;
443}
444
445static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
446 unsigned int fmt)
447{
448 struct snd_soc_codec *codec = codec_dai->codec;
449 int iface;
450
451 /* set up DAI based upon fmt */
452 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
453 iface &= ~R01_SFORI_MASK;
454
455 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
456 case SND_SOC_DAIFMT_I2S:
457 iface |= R01_SFORI_I2S;
458 break;
459 case SND_SOC_DAIFMT_LSB:
460 iface |= R01_SFORI_LSB16;
461 break;
462 case SND_SOC_DAIFMT_MSB:
463 iface |= R01_SFORI_MSB;
464 }
465
Philipp Zabel5f2a9382009-03-03 16:10:52 +0100466 /* DATAI is slave only, so this has to be slave */
467 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
468 return -EINVAL;
469
Philipp Zabel5b247442009-02-03 17:19:40 +0100470 uda1380_write(codec, UDA1380_IFACE, iface);
471
472 return 0;
473}
474
475static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
476 unsigned int fmt)
477{
478 struct snd_soc_codec *codec = codec_dai->codec;
479 int iface;
480
481 /* set up DAI based upon fmt */
482 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
483 iface &= ~(R01_SIM | R01_SFORO_MASK);
484
485 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
486 case SND_SOC_DAIFMT_I2S:
487 iface |= R01_SFORO_I2S;
488 break;
489 case SND_SOC_DAIFMT_LSB:
490 iface |= R01_SFORO_LSB16;
491 break;
492 case SND_SOC_DAIFMT_MSB:
493 iface |= R01_SFORO_MSB;
Philipp Zabelb7482f52008-05-28 17:58:06 +0100494 }
495
496 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
497 iface |= R01_SIM;
498
499 uda1380_write(codec, UDA1380_IFACE, iface);
500
501 return 0;
502}
503
Philipp Zabelef9e5e52009-03-03 16:10:54 +0100504static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
505 struct snd_soc_dai *dai)
Philipp Zabelb7482f52008-05-28 17:58:06 +0100506{
Mark Browne6968a12012-04-04 15:58:16 +0100507 struct snd_soc_codec *codec = dai->codec;
Mark Brownb2c812e2010-04-14 15:35:19 +0900508 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
Philipp Zabelef9e5e52009-03-03 16:10:54 +0100509 int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
Philipp Zabelb7482f52008-05-28 17:58:06 +0100510
Philipp Zabelef9e5e52009-03-03 16:10:54 +0100511 switch (cmd) {
512 case SNDRV_PCM_TRIGGER_START:
513 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
514 uda1380_write_reg_cache(codec, UDA1380_MIXER,
515 mixer & ~R14_SILENCE);
Philipp Zabel1abd9182009-06-15 22:18:23 +0200516 schedule_work(&uda1380->work);
Philipp Zabelef9e5e52009-03-03 16:10:54 +0100517 break;
518 case SNDRV_PCM_TRIGGER_STOP:
519 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
520 uda1380_write_reg_cache(codec, UDA1380_MIXER,
521 mixer | R14_SILENCE);
Philipp Zabel1abd9182009-06-15 22:18:23 +0200522 schedule_work(&uda1380->work);
Philipp Zabelef9e5e52009-03-03 16:10:54 +0100523 break;
Philipp Zabelb7482f52008-05-28 17:58:06 +0100524 }
Philipp Zabelb7482f52008-05-28 17:58:06 +0100525 return 0;
526}
527
528static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
Mark Browndee89c42008-11-18 22:11:38 +0000529 struct snd_pcm_hw_params *params,
530 struct snd_soc_dai *dai)
Philipp Zabelb7482f52008-05-28 17:58:06 +0100531{
Mark Browne6968a12012-04-04 15:58:16 +0100532 struct snd_soc_codec *codec = dai->codec;
Philipp Zabelb7482f52008-05-28 17:58:06 +0100533 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
534
535 /* set WSPLL power and divider if running from this clock */
536 if (clk & R00_DAC_CLK) {
537 int rate = params_rate(params);
538 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
539 clk &= ~0x3; /* clear SEL_LOOP_DIV */
540 switch (rate) {
541 case 6250 ... 12500:
542 clk |= 0x0;
543 break;
544 case 12501 ... 25000:
545 clk |= 0x1;
546 break;
547 case 25001 ... 50000:
548 clk |= 0x2;
549 break;
550 case 50001 ... 100000:
551 clk |= 0x3;
552 break;
553 }
554 uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
555 }
556
557 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
558 clk |= R00_EN_DAC | R00_EN_INT;
559 else
560 clk |= R00_EN_ADC | R00_EN_DEC;
561
562 uda1380_write(codec, UDA1380_CLK, clk);
563 return 0;
564}
565
Mark Browndee89c42008-11-18 22:11:38 +0000566static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
567 struct snd_soc_dai *dai)
Philipp Zabelb7482f52008-05-28 17:58:06 +0100568{
Lars-Peter Clausenab642462014-03-13 21:24:54 +0100569 struct snd_soc_codec *codec = dai->codec;
Philipp Zabelb7482f52008-05-28 17:58:06 +0100570 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
571
572 /* shut down WSPLL power if running from this clock */
573 if (clk & R00_DAC_CLK) {
574 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
575 uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
576 }
577
578 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
579 clk &= ~(R00_EN_DAC | R00_EN_INT);
580 else
581 clk &= ~(R00_EN_ADC | R00_EN_DEC);
582
583 uda1380_write(codec, UDA1380_CLK, clk);
584}
585
Philipp Zabelb7482f52008-05-28 17:58:06 +0100586static int uda1380_set_bias_level(struct snd_soc_codec *codec,
587 enum snd_soc_bias_level level)
588{
589 int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300590 int reg;
591 struct uda1380_platform_data *pdata = codec->dev->platform_data;
592
Philipp Zabelb7482f52008-05-28 17:58:06 +0100593 switch (level) {
594 case SND_SOC_BIAS_ON:
595 case SND_SOC_BIAS_PREPARE:
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300596 /* ADC, DAC on */
Philipp Zabelb7482f52008-05-28 17:58:06 +0100597 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
598 break;
599 case SND_SOC_BIAS_STANDBY:
Lars-Peter Clausen9f061712015-05-11 09:42:34 +0200600 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300601 if (gpio_is_valid(pdata->gpio_power)) {
602 gpio_set_value(pdata->gpio_power, 1);
Vasily Khoruzhick8e3dce42010-09-07 17:04:17 +0300603 mdelay(1);
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300604 uda1380_reset(codec);
605 }
606
607 uda1380_sync_cache(codec);
608 }
Philipp Zabelb7482f52008-05-28 17:58:06 +0100609 uda1380_write(codec, UDA1380_PM, 0x0);
610 break;
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300611 case SND_SOC_BIAS_OFF:
612 if (!gpio_is_valid(pdata->gpio_power))
613 break;
614
615 gpio_set_value(pdata->gpio_power, 0);
616
617 /* Mark mixer regs cache dirty to sync them with
618 * codec regs on power on.
619 */
620 for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
621 set_bit(reg - 0x10, &uda1380_cache_dirty);
Philipp Zabelb7482f52008-05-28 17:58:06 +0100622 }
Philipp Zabelb7482f52008-05-28 17:58:06 +0100623 return 0;
624}
625
626#define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
627 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
628 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
629
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100630static const struct snd_soc_dai_ops uda1380_dai_ops = {
Eric Miao6335d052009-03-03 09:41:00 +0800631 .hw_params = uda1380_pcm_hw_params,
632 .shutdown = uda1380_pcm_shutdown,
Mark Brown65ec1cd2009-03-11 16:51:31 +0000633 .trigger = uda1380_trigger,
Eric Miao6335d052009-03-03 09:41:00 +0800634 .set_fmt = uda1380_set_dai_fmt_both,
635};
636
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100637static const struct snd_soc_dai_ops uda1380_dai_ops_playback = {
Eric Miao6335d052009-03-03 09:41:00 +0800638 .hw_params = uda1380_pcm_hw_params,
639 .shutdown = uda1380_pcm_shutdown,
Mark Brown65ec1cd2009-03-11 16:51:31 +0000640 .trigger = uda1380_trigger,
Eric Miao6335d052009-03-03 09:41:00 +0800641 .set_fmt = uda1380_set_dai_fmt_playback,
642};
643
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100644static const struct snd_soc_dai_ops uda1380_dai_ops_capture = {
Eric Miao6335d052009-03-03 09:41:00 +0800645 .hw_params = uda1380_pcm_hw_params,
646 .shutdown = uda1380_pcm_shutdown,
Mark Brown65ec1cd2009-03-11 16:51:31 +0000647 .trigger = uda1380_trigger,
Eric Miao6335d052009-03-03 09:41:00 +0800648 .set_fmt = uda1380_set_dai_fmt_capture,
649};
650
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000651static struct snd_soc_dai_driver uda1380_dai[] = {
Philipp Zabelb7482f52008-05-28 17:58:06 +0100652{
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000653 .name = "uda1380-hifi",
Philipp Zabelb7482f52008-05-28 17:58:06 +0100654 .playback = {
655 .stream_name = "Playback",
656 .channels_min = 1,
657 .channels_max = 2,
658 .rates = UDA1380_RATES,
659 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
660 .capture = {
661 .stream_name = "Capture",
662 .channels_min = 1,
663 .channels_max = 2,
664 .rates = UDA1380_RATES,
665 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
Eric Miao6335d052009-03-03 09:41:00 +0800666 .ops = &uda1380_dai_ops,
Philipp Zabelb7482f52008-05-28 17:58:06 +0100667},
668{ /* playback only - dual interface */
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000669 .name = "uda1380-hifi-playback",
Philipp Zabelb7482f52008-05-28 17:58:06 +0100670 .playback = {
671 .stream_name = "Playback",
672 .channels_min = 1,
673 .channels_max = 2,
674 .rates = UDA1380_RATES,
675 .formats = SNDRV_PCM_FMTBIT_S16_LE,
676 },
Eric Miao6335d052009-03-03 09:41:00 +0800677 .ops = &uda1380_dai_ops_playback,
Philipp Zabelb7482f52008-05-28 17:58:06 +0100678},
679{ /* capture only - dual interface*/
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000680 .name = "uda1380-hifi-capture",
Philipp Zabelb7482f52008-05-28 17:58:06 +0100681 .capture = {
682 .stream_name = "Capture",
683 .channels_min = 1,
684 .channels_max = 2,
685 .rates = UDA1380_RATES,
686 .formats = SNDRV_PCM_FMTBIT_S16_LE,
687 },
Eric Miao6335d052009-03-03 09:41:00 +0800688 .ops = &uda1380_dai_ops_capture,
Philipp Zabelb7482f52008-05-28 17:58:06 +0100689},
690};
Philipp Zabelb7482f52008-05-28 17:58:06 +0100691
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000692static int uda1380_probe(struct snd_soc_codec *codec)
Philipp Zabelb7482f52008-05-28 17:58:06 +0100693{
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000694 struct uda1380_platform_data *pdata =codec->dev->platform_data;
695 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
696 int ret;
Philipp Zabelb7482f52008-05-28 17:58:06 +0100697
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300698 uda1380->codec = codec;
Philipp Zabelb7482f52008-05-28 17:58:06 +0100699
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300700 codec->hw_write = (hw_write_t)i2c_master_send;
701 codec->control_data = uda1380->control_data;
702
703 if (!pdata)
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000704 return -EINVAL;
Philipp Zabelef9e5e52009-03-03 16:10:54 +0100705
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300706 if (gpio_is_valid(pdata->gpio_reset)) {
Axel Lin68020db2011-12-05 07:58:25 +0800707 ret = gpio_request_one(pdata->gpio_reset, GPIOF_OUT_INIT_LOW,
708 "uda1380 reset");
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300709 if (ret)
710 goto err_out;
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300711 }
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000712
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300713 if (gpio_is_valid(pdata->gpio_power)) {
Axel Lin68020db2011-12-05 07:58:25 +0800714 ret = gpio_request_one(pdata->gpio_power, GPIOF_OUT_INIT_LOW,
715 "uda1380 power");
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300716 if (ret)
Axel Lin68020db2011-12-05 07:58:25 +0800717 goto err_free_gpio;
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300718 } else {
719 ret = uda1380_reset(codec);
Axel Lin68020db2011-12-05 07:58:25 +0800720 if (ret)
721 goto err_free_gpio;
Philipp Zabelb7482f52008-05-28 17:58:06 +0100722 }
723
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000724 INIT_WORK(&uda1380->work, uda1380_flush_work);
725
Philipp Zabelb7482f52008-05-28 17:58:06 +0100726 /* set clock input */
Philipp Zabel1abd9182009-06-15 22:18:23 +0200727 switch (pdata->dac_clk) {
Philipp Zabelb7482f52008-05-28 17:58:06 +0100728 case UDA1380_DAC_CLK_SYSCLK:
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300729 uda1380_write_reg_cache(codec, UDA1380_CLK, 0);
Philipp Zabelb7482f52008-05-28 17:58:06 +0100730 break;
731 case UDA1380_DAC_CLK_WSPLL:
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300732 uda1380_write_reg_cache(codec, UDA1380_CLK,
733 R00_DAC_CLK);
Philipp Zabelb7482f52008-05-28 17:58:06 +0100734 break;
735 }
736
Philipp Zabel1abd9182009-06-15 22:18:23 +0200737 return 0;
738
Axel Lin68020db2011-12-05 07:58:25 +0800739err_free_gpio:
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300740 if (gpio_is_valid(pdata->gpio_reset))
741 gpio_free(pdata->gpio_reset);
742err_out:
Philipp Zabel1abd9182009-06-15 22:18:23 +0200743 return ret;
744}
745
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000746/* power down chip */
747static int uda1380_remove(struct snd_soc_codec *codec)
Philipp Zabel1abd9182009-06-15 22:18:23 +0200748{
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000749 struct uda1380_platform_data *pdata =codec->dev->platform_data;
Philipp Zabel1abd9182009-06-15 22:18:23 +0200750
Philipp Zabel1abd9182009-06-15 22:18:23 +0200751 gpio_free(pdata->gpio_reset);
752 gpio_free(pdata->gpio_power);
753
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000754 return 0;
Philipp Zabel1abd9182009-06-15 22:18:23 +0200755}
Philipp Zabelb7482f52008-05-28 17:58:06 +0100756
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000757static struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
758 .probe = uda1380_probe,
759 .remove = uda1380_remove,
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300760 .read = uda1380_read_reg_cache,
761 .write = uda1380_write,
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000762 .set_bias_level = uda1380_set_bias_level,
Lars-Peter Clausene8125f02014-11-23 15:04:14 +0100763 .suspend_bias_off = true,
764
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000765 .reg_cache_size = ARRAY_SIZE(uda1380_reg),
766 .reg_word_size = sizeof(u16),
767 .reg_cache_default = uda1380_reg,
768 .reg_cache_step = 1,
Axel Lin58fa8e42011-12-19 13:54:38 +0800769
770 .controls = uda1380_snd_controls,
771 .num_controls = ARRAY_SIZE(uda1380_snd_controls),
772 .dapm_widgets = uda1380_dapm_widgets,
773 .num_dapm_widgets = ARRAY_SIZE(uda1380_dapm_widgets),
774 .dapm_routes = uda1380_dapm_routes,
775 .num_dapm_routes = ARRAY_SIZE(uda1380_dapm_routes),
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000776};
777
Fabio Estevam06b2bd22013-11-20 15:37:52 -0200778#if IS_ENABLED(CONFIG_I2C)
Bill Pemberton7a79e942012-12-07 09:26:37 -0500779static int uda1380_i2c_probe(struct i2c_client *i2c,
780 const struct i2c_device_id *id)
Philipp Zabelb7482f52008-05-28 17:58:06 +0100781{
Philipp Zabel1abd9182009-06-15 22:18:23 +0200782 struct uda1380_priv *uda1380;
Philipp Zabelb7482f52008-05-28 17:58:06 +0100783 int ret;
784
Axel Lin6ce91ad2011-12-26 20:58:14 +0800785 uda1380 = devm_kzalloc(&i2c->dev, sizeof(struct uda1380_priv),
786 GFP_KERNEL);
Philipp Zabel1abd9182009-06-15 22:18:23 +0200787 if (uda1380 == NULL)
788 return -ENOMEM;
789
Philipp Zabel1abd9182009-06-15 22:18:23 +0200790 i2c_set_clientdata(i2c, uda1380);
Vasily Khoruzhick8614d312010-08-30 11:28:07 +0300791 uda1380->control_data = i2c;
Philipp Zabelb7482f52008-05-28 17:58:06 +0100792
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000793 ret = snd_soc_register_codec(&i2c->dev,
794 &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
Philipp Zabelb7482f52008-05-28 17:58:06 +0100795 return ret;
796}
797
Bill Pemberton7a79e942012-12-07 09:26:37 -0500798static int uda1380_i2c_remove(struct i2c_client *i2c)
Philipp Zabelb7482f52008-05-28 17:58:06 +0100799{
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000800 snd_soc_unregister_codec(&i2c->dev);
Philipp Zabelb7482f52008-05-28 17:58:06 +0100801 return 0;
802}
803
Jean Delvare88fc39d2008-09-01 18:46:58 +0100804static const struct i2c_device_id uda1380_i2c_id[] = {
805 { "uda1380", 0 },
806 { }
807};
808MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
Philipp Zabelb7482f52008-05-28 17:58:06 +0100809
810static struct i2c_driver uda1380_i2c_driver = {
811 .driver = {
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000812 .name = "uda1380-codec",
Philipp Zabelb7482f52008-05-28 17:58:06 +0100813 .owner = THIS_MODULE,
814 },
Jean Delvare88fc39d2008-09-01 18:46:58 +0100815 .probe = uda1380_i2c_probe,
Bill Pemberton7a79e942012-12-07 09:26:37 -0500816 .remove = uda1380_i2c_remove,
Jean Delvare88fc39d2008-09-01 18:46:58 +0100817 .id_table = uda1380_i2c_id,
Philipp Zabelb7482f52008-05-28 17:58:06 +0100818};
Philipp Zabelb7482f52008-05-28 17:58:06 +0100819#endif
820
Takashi Iwaic9b3a402008-12-10 07:47:22 +0100821static int __init uda1380_modinit(void)
Mark Brown64089b82008-12-08 19:17:58 +0000822{
Axel Linef149772011-12-04 19:35:20 +0800823 int ret = 0;
Fabio Estevam06b2bd22013-11-20 15:37:52 -0200824#if IS_ENABLED(CONFIG_I2C)
Philipp Zabel1abd9182009-06-15 22:18:23 +0200825 ret = i2c_add_driver(&uda1380_i2c_driver);
826 if (ret != 0)
827 pr_err("Failed to register UDA1380 I2C driver: %d\n", ret);
828#endif
Axel Linef149772011-12-04 19:35:20 +0800829 return ret;
Mark Brown64089b82008-12-08 19:17:58 +0000830}
831module_init(uda1380_modinit);
832
833static void __exit uda1380_exit(void)
834{
Fabio Estevam06b2bd22013-11-20 15:37:52 -0200835#if IS_ENABLED(CONFIG_I2C)
Philipp Zabel1abd9182009-06-15 22:18:23 +0200836 i2c_del_driver(&uda1380_i2c_driver);
837#endif
Mark Brown64089b82008-12-08 19:17:58 +0000838}
839module_exit(uda1380_exit);
840
Philipp Zabelb7482f52008-05-28 17:58:06 +0100841MODULE_AUTHOR("Giorgio Padrin");
842MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
843MODULE_LICENSE("GPL");