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gerrit-public.fairphone.software / kernel / msm-4.9 / 861d21074bbb141b0cc165a61c11f571571cda12 / . / drivers / gpu / drm / nouveau / core / subdev / device / nv40.c
blob: c7ea921e03098629b9385a092f2446c6dc064f32 [file] [log] [blame]
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/device.h>
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]26#include <subdev/bios.h>
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]27#include <subdev/gpio.h>
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]28#include <subdev/i2c.h>
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]29#include <subdev/clock.h>
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]30#include <subdev/devinit.h>
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]31#include <subdev/mc.h>
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]32#include <subdev/timer.h>
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]33#include <subdev/fb.h>
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]34
35int
36nv40_identify(struct nouveau_device *device)
37{
38 switch (device->chipset) {
39 case 0x40:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]40 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]41 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]42 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]43 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]44 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]45 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]46 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]47 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]48 break;
49 case 0x41:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]50 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]51 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]52 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]53 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]54 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]55 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]56 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]57 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]58 break;
59 case 0x42:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]60 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]61 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]62 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]63 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]64 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]65 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]66 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]67 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]68 break;
69 case 0x43:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]70 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]71 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]72 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]73 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]74 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]75 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]76 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]77 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]78 break;
79 case 0x45:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]80 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]81 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]82 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]83 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]84 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]85 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]86 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]87 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]88 break;
89 case 0x47:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]90 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]91 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]92 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]93 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]94 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]95 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]97 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]98 break;
99 case 0x49:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]100 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]101 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]102 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]103 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]104 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]105 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]106 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]107 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]108 break;
109 case 0x4b:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]110 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]111 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]112 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]113 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]114 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]115 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]116 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]117 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]118 break;
119 case 0x44:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]120 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]121 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]122 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]123 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]124 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]125 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]126 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]127 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]128 break;
129 case 0x46:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]130 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]131 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]132 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]133 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]134 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]135 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]136 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]137 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]138 break;
139 case 0x4a:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]140 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]141 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]142 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]143 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]144 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]145 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]146 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]147 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]148 break;
149 case 0x4c:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]150 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]151 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]152 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]153 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]154 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]155 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]156 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]157 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]158 break;
159 case 0x4e:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]160 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]161 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]162 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]163 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]164 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]165 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]166 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]167 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]168 break;
169 case 0x63:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]170 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]171 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]172 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]173 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]174 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]175 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]176 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]177 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]178 break;
179 case 0x67:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]180 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]181 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]182 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]183 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]184 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]185 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]186 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]187 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]188 break;
189 case 0x68:
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]190 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]191 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]192 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]193 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]194 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]195 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]196 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame^]197 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]198 break;
199 default:
200 nv_fatal(device, "unknown Curie chipset\n");
201 return -EINVAL;
202 }
203
204 return 0;
205}