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Francois Romieu1202d6f2007-09-17 17:13:55 -07001/*
Francois Romieu1202d6f2007-09-17 17:13:55 -07002 * Include file for Gigabit Ethernet device driver for Network
3 * Interface Cards (NICs) utilizing the Tamarack Microelectronics
4 * Inc. IPG Gigabit or Triple Speed Ethernet Media Access
5 * Controller.
Francois Romieu1202d6f2007-09-17 17:13:55 -07006 */
7#ifndef __LINUX_IPG_H
8#define __LINUX_IPG_H
9
10#include <linux/version.h>
11#include <linux/module.h>
12
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/ioport.h>
16#include <linux/errno.h>
17#include <asm/io.h>
18#include <linux/delay.h>
19#include <linux/types.h>
20#include <linux/netdevice.h>
21#include <linux/etherdevice.h>
22#include <linux/init.h>
23#include <linux/skbuff.h>
24#include <linux/version.h>
25#include <asm/bitops.h>
Francois Romieu1202d6f2007-09-17 17:13:55 -070026
Francois Romieu1202d6f2007-09-17 17:13:55 -070027/*
28 * Constants
29 */
30
31/* GMII based PHY IDs */
32#define NS 0x2000
33#define MARVELL 0x0141
34#define ICPLUS_PHY 0x243
35
36/* NIC Physical Layer Device MII register fields. */
37#define MII_PHY_SELECTOR_IEEE8023 0x0001
38#define MII_PHY_TECHABILITYFIELD 0x1FE0
39
40/* GMII_PHY_1000 need to set to prefer master */
41#define GMII_PHY_1000BASETCONTROL_PreferMaster 0x0400
42
43/* NIC Physical Layer Device GMII constants. */
44#define GMII_PREAMBLE 0xFFFFFFFF
45#define GMII_ST 0x1
46#define GMII_READ 0x2
47#define GMII_WRITE 0x1
48#define GMII_TA_READ_MASK 0x1
49#define GMII_TA_WRITE 0x2
50
51/* I/O register offsets. */
52enum ipg_regs {
53 DMA_CTRL = 0x00,
Pekka Enberg8da5bb72007-11-30 09:55:43 +020054 RX_DMA_STATUS = 0x08, /* Unused + reserved */
Francois Romieu1202d6f2007-09-17 17:13:55 -070055 TFD_LIST_PTR_0 = 0x10,
56 TFD_LIST_PTR_1 = 0x14,
57 TX_DMA_BURST_THRESH = 0x18,
58 TX_DMA_URGENT_THRESH = 0x19,
59 TX_DMA_POLL_PERIOD = 0x1a,
60 RFD_LIST_PTR_0 = 0x1c,
61 RFD_LIST_PTR_1 = 0x20,
62 RX_DMA_BURST_THRESH = 0x24,
63 RX_DMA_URGENT_THRESH = 0x25,
64 RX_DMA_POLL_PERIOD = 0x26,
65 DEBUG_CTRL = 0x2c,
66 ASIC_CTRL = 0x30,
Pekka Enberg8da5bb72007-11-30 09:55:43 +020067 FIFO_CTRL = 0x38, /* Unused */
Francois Romieu1202d6f2007-09-17 17:13:55 -070068 FLOW_OFF_THRESH = 0x3c,
69 FLOW_ON_THRESH = 0x3e,
70 EEPROM_DATA = 0x48,
71 EEPROM_CTRL = 0x4a,
Pekka Enberg8da5bb72007-11-30 09:55:43 +020072 EXPROM_ADDR = 0x4c, /* Unused */
73 EXPROM_DATA = 0x50, /* Unused */
74 WAKE_EVENT = 0x51, /* Unused */
75 COUNTDOWN = 0x54, /* Unused */
Francois Romieu1202d6f2007-09-17 17:13:55 -070076 INT_STATUS_ACK = 0x5a,
77 INT_ENABLE = 0x5c,
Pekka Enberg8da5bb72007-11-30 09:55:43 +020078 INT_STATUS = 0x5e, /* Unused */
Francois Romieu1202d6f2007-09-17 17:13:55 -070079 TX_STATUS = 0x60,
80 MAC_CTRL = 0x6c,
Pekka Enberg8da5bb72007-11-30 09:55:43 +020081 VLAN_TAG = 0x70, /* Unused */
Pekka Enbergdea4a872007-11-30 09:54:51 +020082 PHY_SET = 0x75,
Francois Romieu1202d6f2007-09-17 17:13:55 -070083 PHY_CTRL = 0x76,
84 STATION_ADDRESS_0 = 0x78,
85 STATION_ADDRESS_1 = 0x7a,
86 STATION_ADDRESS_2 = 0x7c,
87 MAX_FRAME_SIZE = 0x86,
88 RECEIVE_MODE = 0x88,
89 HASHTABLE_0 = 0x8c,
90 HASHTABLE_1 = 0x90,
91 RMON_STATISTICS_MASK = 0x98,
92 STATISTICS_MASK = 0x9c,
Pekka Enberg8da5bb72007-11-30 09:55:43 +020093 RX_JUMBO_FRAMES = 0xbc, /* Unused */
94 TCP_CHECKSUM_ERRORS = 0xc0, /* Unused */
95 IP_CHECKSUM_ERRORS = 0xc2, /* Unused */
96 UDP_CHECKSUM_ERRORS = 0xc4, /* Unused */
97 TX_JUMBO_FRAMES = 0xf4 /* Unused */
Francois Romieu1202d6f2007-09-17 17:13:55 -070098};
99
100/* Ethernet MIB statistic register offsets. */
101#define IPG_OCTETRCVOK 0xA8
102#define IPG_MCSTOCTETRCVDOK 0xAC
103#define IPG_BCSTOCTETRCVOK 0xB0
104#define IPG_FRAMESRCVDOK 0xB4
105#define IPG_MCSTFRAMESRCVDOK 0xB8
106#define IPG_BCSTFRAMESRCVDOK 0xBE
107#define IPG_MACCONTROLFRAMESRCVD 0xC6
108#define IPG_FRAMETOOLONGERRRORS 0xC8
109#define IPG_INRANGELENGTHERRORS 0xCA
110#define IPG_FRAMECHECKSEQERRORS 0xCC
111#define IPG_FRAMESLOSTRXERRORS 0xCE
112#define IPG_OCTETXMTOK 0xD0
113#define IPG_MCSTOCTETXMTOK 0xD4
114#define IPG_BCSTOCTETXMTOK 0xD8
115#define IPG_FRAMESXMTDOK 0xDC
116#define IPG_MCSTFRAMESXMTDOK 0xE0
117#define IPG_FRAMESWDEFERREDXMT 0xE4
118#define IPG_LATECOLLISIONS 0xE8
119#define IPG_MULTICOLFRAMES 0xEC
120#define IPG_SINGLECOLFRAMES 0xF0
121#define IPG_BCSTFRAMESXMTDOK 0xF6
122#define IPG_CARRIERSENSEERRORS 0xF8
123#define IPG_MACCONTROLFRAMESXMTDOK 0xFA
124#define IPG_FRAMESABORTXSCOLLS 0xFC
125#define IPG_FRAMESWEXDEFERRAL 0xFE
126
127/* RMON statistic register offsets. */
128#define IPG_ETHERSTATSCOLLISIONS 0x100
129#define IPG_ETHERSTATSOCTETSTRANSMIT 0x104
130#define IPG_ETHERSTATSPKTSTRANSMIT 0x108
131#define IPG_ETHERSTATSPKTS64OCTESTSTRANSMIT 0x10C
132#define IPG_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT 0x110
133#define IPG_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT 0x114
134#define IPG_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT 0x118
135#define IPG_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT 0x11C
136#define IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT 0x120
137#define IPG_ETHERSTATSCRCALIGNERRORS 0x124
138#define IPG_ETHERSTATSUNDERSIZEPKTS 0x128
139#define IPG_ETHERSTATSFRAGMENTS 0x12C
140#define IPG_ETHERSTATSJABBERS 0x130
141#define IPG_ETHERSTATSOCTETS 0x134
142#define IPG_ETHERSTATSPKTS 0x138
143#define IPG_ETHERSTATSPKTS64OCTESTS 0x13C
144#define IPG_ETHERSTATSPKTS65TO127OCTESTS 0x140
145#define IPG_ETHERSTATSPKTS128TO255OCTESTS 0x144
146#define IPG_ETHERSTATSPKTS256TO511OCTESTS 0x148
147#define IPG_ETHERSTATSPKTS512TO1023OCTESTS 0x14C
148#define IPG_ETHERSTATSPKTS1024TO1518OCTESTS 0x150
149
150/* RMON statistic register equivalents. */
151#define IPG_ETHERSTATSMULTICASTPKTSTRANSMIT 0xE0
152#define IPG_ETHERSTATSBROADCASTPKTSTRANSMIT 0xF6
153#define IPG_ETHERSTATSMULTICASTPKTS 0xB8
154#define IPG_ETHERSTATSBROADCASTPKTS 0xBE
155#define IPG_ETHERSTATSOVERSIZEPKTS 0xC8
156#define IPG_ETHERSTATSDROPEVENTS 0xCE
157
158/* Serial EEPROM offsets */
159#define IPG_EEPROM_CONFIGPARAM 0x00
160#define IPG_EEPROM_ASICCTRL 0x01
161#define IPG_EEPROM_SUBSYSTEMVENDORID 0x02
162#define IPG_EEPROM_SUBSYSTEMID 0x03
163#define IPG_EEPROM_STATIONADDRESS0 0x10
164#define IPG_EEPROM_STATIONADDRESS1 0x11
165#define IPG_EEPROM_STATIONADDRESS2 0x12
166
167/* Register & data structure bit masks */
168
169/* PCI register masks. */
170
171/* IOBaseAddress */
172#define IPG_PIB_RSVD_MASK 0xFFFFFE01
173#define IPG_PIB_IOBASEADDRESS 0xFFFFFF00
174#define IPG_PIB_IOBASEADDRIND 0x00000001
175
176/* MemBaseAddress */
177#define IPG_PMB_RSVD_MASK 0xFFFFFE07
178#define IPG_PMB_MEMBASEADDRIND 0x00000001
179#define IPG_PMB_MEMMAPTYPE 0x00000006
180#define IPG_PMB_MEMMAPTYPE0 0x00000002
181#define IPG_PMB_MEMMAPTYPE1 0x00000004
182#define IPG_PMB_MEMBASEADDRESS 0xFFFFFE00
183
184/* ConfigStatus */
185#define IPG_CS_RSVD_MASK 0xFFB0
186#define IPG_CS_CAPABILITIES 0x0010
187#define IPG_CS_66MHZCAPABLE 0x0020
188#define IPG_CS_FASTBACK2BACK 0x0080
189#define IPG_CS_DATAPARITYREPORTED 0x0100
190#define IPG_CS_DEVSELTIMING 0x0600
191#define IPG_CS_SIGNALEDTARGETABORT 0x0800
192#define IPG_CS_RECEIVEDTARGETABORT 0x1000
193#define IPG_CS_RECEIVEDMASTERABORT 0x2000
194#define IPG_CS_SIGNALEDSYSTEMERROR 0x4000
195#define IPG_CS_DETECTEDPARITYERROR 0x8000
196
197/* TFD data structure masks. */
198
199/* TFDList, TFC */
200#define IPG_TFC_RSVD_MASK 0x0000FFFF9FFFFFFF
201#define IPG_TFC_FRAMEID 0x000000000000FFFF
202#define IPG_TFC_WORDALIGN 0x0000000000030000
203#define IPG_TFC_WORDALIGNTODWORD 0x0000000000000000
204#define IPG_TFC_WORDALIGNTOWORD 0x0000000000020000
205#define IPG_TFC_WORDALIGNDISABLED 0x0000000000030000
206#define IPG_TFC_TCPCHECKSUMENABLE 0x0000000000040000
207#define IPG_TFC_UDPCHECKSUMENABLE 0x0000000000080000
208#define IPG_TFC_IPCHECKSUMENABLE 0x0000000000100000
209#define IPG_TFC_FCSAPPENDDISABLE 0x0000000000200000
210#define IPG_TFC_TXINDICATE 0x0000000000400000
211#define IPG_TFC_TXDMAINDICATE 0x0000000000800000
212#define IPG_TFC_FRAGCOUNT 0x000000000F000000
213#define IPG_TFC_VLANTAGINSERT 0x0000000010000000
214#define IPG_TFC_TFDDONE 0x0000000080000000
215#define IPG_TFC_VID 0x00000FFF00000000
216#define IPG_TFC_CFI 0x0000100000000000
217#define IPG_TFC_USERPRIORITY 0x0000E00000000000
218
219/* TFDList, FragInfo */
220#define IPG_TFI_RSVD_MASK 0xFFFF00FFFFFFFFFF
221#define IPG_TFI_FRAGADDR 0x000000FFFFFFFFFF
222#define IPG_TFI_FRAGLEN 0xFFFF000000000000LL
223
224/* RFD data structure masks. */
225
226/* RFDList, RFS */
227#define IPG_RFS_RSVD_MASK 0x0000FFFFFFFFFFFF
228#define IPG_RFS_RXFRAMELEN 0x000000000000FFFF
229#define IPG_RFS_RXFIFOOVERRUN 0x0000000000010000
230#define IPG_RFS_RXRUNTFRAME 0x0000000000020000
231#define IPG_RFS_RXALIGNMENTERROR 0x0000000000040000
232#define IPG_RFS_RXFCSERROR 0x0000000000080000
233#define IPG_RFS_RXOVERSIZEDFRAME 0x0000000000100000
234#define IPG_RFS_RXLENGTHERROR 0x0000000000200000
235#define IPG_RFS_VLANDETECTED 0x0000000000400000
236#define IPG_RFS_TCPDETECTED 0x0000000000800000
237#define IPG_RFS_TCPERROR 0x0000000001000000
238#define IPG_RFS_UDPDETECTED 0x0000000002000000
239#define IPG_RFS_UDPERROR 0x0000000004000000
240#define IPG_RFS_IPDETECTED 0x0000000008000000
241#define IPG_RFS_IPERROR 0x0000000010000000
242#define IPG_RFS_FRAMESTART 0x0000000020000000
243#define IPG_RFS_FRAMEEND 0x0000000040000000
244#define IPG_RFS_RFDDONE 0x0000000080000000
245#define IPG_RFS_TCI 0x0000FFFF00000000
246
247/* RFDList, FragInfo */
248#define IPG_RFI_RSVD_MASK 0xFFFF00FFFFFFFFFF
249#define IPG_RFI_FRAGADDR 0x000000FFFFFFFFFF
250#define IPG_RFI_FRAGLEN 0xFFFF000000000000LL
251
252/* I/O Register masks. */
253
254/* RMON Statistics Mask */
255#define IPG_RZ_ALL 0x0FFFFFFF
256
257/* Statistics Mask */
258#define IPG_SM_ALL 0x0FFFFFFF
259#define IPG_SM_OCTETRCVOK_FRAMESRCVDOK 0x00000001
260#define IPG_SM_MCSTOCTETRCVDOK_MCSTFRAMESRCVDOK 0x00000002
261#define IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK 0x00000004
262#define IPG_SM_RXJUMBOFRAMES 0x00000008
263#define IPG_SM_TCPCHECKSUMERRORS 0x00000010
264#define IPG_SM_IPCHECKSUMERRORS 0x00000020
265#define IPG_SM_UDPCHECKSUMERRORS 0x00000040
266#define IPG_SM_MACCONTROLFRAMESRCVD 0x00000080
267#define IPG_SM_FRAMESTOOLONGERRORS 0x00000100
268#define IPG_SM_INRANGELENGTHERRORS 0x00000200
269#define IPG_SM_FRAMECHECKSEQERRORS 0x00000400
270#define IPG_SM_FRAMESLOSTRXERRORS 0x00000800
271#define IPG_SM_OCTETXMTOK_FRAMESXMTOK 0x00001000
272#define IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK 0x00002000
273#define IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK 0x00004000
274#define IPG_SM_FRAMESWDEFERREDXMT 0x00008000
275#define IPG_SM_LATECOLLISIONS 0x00010000
276#define IPG_SM_MULTICOLFRAMES 0x00020000
277#define IPG_SM_SINGLECOLFRAMES 0x00040000
278#define IPG_SM_TXJUMBOFRAMES 0x00080000
279#define IPG_SM_CARRIERSENSEERRORS 0x00100000
280#define IPG_SM_MACCONTROLFRAMESXMTD 0x00200000
281#define IPG_SM_FRAMESABORTXSCOLLS 0x00400000
282#define IPG_SM_FRAMESWEXDEFERAL 0x00800000
283
284/* Countdown */
285#define IPG_CD_RSVD_MASK 0x0700FFFF
286#define IPG_CD_COUNT 0x0000FFFF
287#define IPG_CD_COUNTDOWNSPEED 0x01000000
288#define IPG_CD_COUNTDOWNMODE 0x02000000
289#define IPG_CD_COUNTINTENABLED 0x04000000
290
291/* TxDMABurstThresh */
292#define IPG_TB_RSVD_MASK 0xFF
293
294/* TxDMAUrgentThresh */
295#define IPG_TU_RSVD_MASK 0xFF
296
297/* TxDMAPollPeriod */
298#define IPG_TP_RSVD_MASK 0xFF
299
300/* RxDMAUrgentThresh */
301#define IPG_RU_RSVD_MASK 0xFF
302
303/* RxDMAPollPeriod */
304#define IPG_RP_RSVD_MASK 0xFF
305
306/* ReceiveMode */
307#define IPG_RM_RSVD_MASK 0x3F
308#define IPG_RM_RECEIVEUNICAST 0x01
309#define IPG_RM_RECEIVEMULTICAST 0x02
310#define IPG_RM_RECEIVEBROADCAST 0x04
311#define IPG_RM_RECEIVEALLFRAMES 0x08
312#define IPG_RM_RECEIVEMULTICASTHASH 0x10
313#define IPG_RM_RECEIVEIPMULTICAST 0x20
314
Pekka Enbergdea4a872007-11-30 09:54:51 +0200315/* PhySet */
Francois Romieu1202d6f2007-09-17 17:13:55 -0700316#define IPG_PS_MEM_LENB9B 0x01
317#define IPG_PS_MEM_LEN9 0x02
318#define IPG_PS_NON_COMPDET 0x04
319
320/* PhyCtrl */
321#define IPG_PC_RSVD_MASK 0xFF
322#define IPG_PC_MGMTCLK_LO 0x00
323#define IPG_PC_MGMTCLK_HI 0x01
324#define IPG_PC_MGMTCLK 0x01
325#define IPG_PC_MGMTDATA 0x02
326#define IPG_PC_MGMTDIR 0x04
327#define IPG_PC_DUPLEX_POLARITY 0x08
328#define IPG_PC_DUPLEX_STATUS 0x10
329#define IPG_PC_LINK_POLARITY 0x20
330#define IPG_PC_LINK_SPEED 0xC0
331#define IPG_PC_LINK_SPEED_10MBPS 0x40
332#define IPG_PC_LINK_SPEED_100MBPS 0x80
333#define IPG_PC_LINK_SPEED_1000MBPS 0xC0
334
335/* DMACtrl */
336#define IPG_DC_RSVD_MASK 0xC07D9818
337#define IPG_DC_RX_DMA_COMPLETE 0x00000008
338#define IPG_DC_RX_DMA_POLL_NOW 0x00000010
339#define IPG_DC_TX_DMA_COMPLETE 0x00000800
340#define IPG_DC_TX_DMA_POLL_NOW 0x00001000
341#define IPG_DC_TX_DMA_IN_PROG 0x00008000
342#define IPG_DC_RX_EARLY_DISABLE 0x00010000
343#define IPG_DC_MWI_DISABLE 0x00040000
344#define IPG_DC_TX_WRITE_BACK_DISABLE 0x00080000
345#define IPG_DC_TX_BURST_LIMIT 0x00700000
346#define IPG_DC_TARGET_ABORT 0x40000000
347#define IPG_DC_MASTER_ABORT 0x80000000
348
349/* ASICCtrl */
350#define IPG_AC_RSVD_MASK 0x07FFEFF2
351#define IPG_AC_EXP_ROM_SIZE 0x00000002
352#define IPG_AC_PHY_SPEED10 0x00000010
353#define IPG_AC_PHY_SPEED100 0x00000020
354#define IPG_AC_PHY_SPEED1000 0x00000040
355#define IPG_AC_PHY_MEDIA 0x00000080
356#define IPG_AC_FORCED_CFG 0x00000700
357#define IPG_AC_D3RESETDISABLE 0x00000800
358#define IPG_AC_SPEED_UP_MODE 0x00002000
359#define IPG_AC_LED_MODE 0x00004000
360#define IPG_AC_RST_OUT_POLARITY 0x00008000
361#define IPG_AC_GLOBAL_RESET 0x00010000
362#define IPG_AC_RX_RESET 0x00020000
363#define IPG_AC_TX_RESET 0x00040000
364#define IPG_AC_DMA 0x00080000
365#define IPG_AC_FIFO 0x00100000
366#define IPG_AC_NETWORK 0x00200000
367#define IPG_AC_HOST 0x00400000
368#define IPG_AC_AUTO_INIT 0x00800000
369#define IPG_AC_RST_OUT 0x01000000
370#define IPG_AC_INT_REQUEST 0x02000000
371#define IPG_AC_RESET_BUSY 0x04000000
Pekka Enbergdea4a872007-11-30 09:54:51 +0200372#define IPG_AC_LED_SPEED 0x08000000
373#define IPG_AC_LED_MODE_BIT_1 0x20000000
Francois Romieu1202d6f2007-09-17 17:13:55 -0700374
375/* EepromCtrl */
376#define IPG_EC_RSVD_MASK 0x83FF
377#define IPG_EC_EEPROM_ADDR 0x00FF
378#define IPG_EC_EEPROM_OPCODE 0x0300
379#define IPG_EC_EEPROM_SUBCOMMAD 0x0000
380#define IPG_EC_EEPROM_WRITEOPCODE 0x0100
381#define IPG_EC_EEPROM_READOPCODE 0x0200
382#define IPG_EC_EEPROM_ERASEOPCODE 0x0300
383#define IPG_EC_EEPROM_BUSY 0x8000
384
385/* FIFOCtrl */
386#define IPG_FC_RSVD_MASK 0xC001
387#define IPG_FC_RAM_TEST_MODE 0x0001
388#define IPG_FC_TRANSMITTING 0x4000
389#define IPG_FC_RECEIVING 0x8000
390
391/* TxStatus */
392#define IPG_TS_RSVD_MASK 0xFFFF00DD
393#define IPG_TS_TX_ERROR 0x00000001
394#define IPG_TS_LATE_COLLISION 0x00000004
395#define IPG_TS_TX_MAX_COLL 0x00000008
396#define IPG_TS_TX_UNDERRUN 0x00000010
397#define IPG_TS_TX_IND_REQD 0x00000040
398#define IPG_TS_TX_COMPLETE 0x00000080
399#define IPG_TS_TX_FRAMEID 0xFFFF0000
400
401/* WakeEvent */
402#define IPG_WE_WAKE_PKT_ENABLE 0x01
403#define IPG_WE_MAGIC_PKT_ENABLE 0x02
404#define IPG_WE_LINK_EVT_ENABLE 0x04
405#define IPG_WE_WAKE_POLARITY 0x08
406#define IPG_WE_WAKE_PKT_EVT 0x10
407#define IPG_WE_MAGIC_PKT_EVT 0x20
408#define IPG_WE_LINK_EVT 0x40
409#define IPG_WE_WOL_ENABLE 0x80
410
411/* IntEnable */
412#define IPG_IE_RSVD_MASK 0x1FFE
413#define IPG_IE_HOST_ERROR 0x0002
414#define IPG_IE_TX_COMPLETE 0x0004
415#define IPG_IE_MAC_CTRL_FRAME 0x0008
416#define IPG_IE_RX_COMPLETE 0x0010
417#define IPG_IE_RX_EARLY 0x0020
418#define IPG_IE_INT_REQUESTED 0x0040
419#define IPG_IE_UPDATE_STATS 0x0080
420#define IPG_IE_LINK_EVENT 0x0100
421#define IPG_IE_TX_DMA_COMPLETE 0x0200
422#define IPG_IE_RX_DMA_COMPLETE 0x0400
423#define IPG_IE_RFD_LIST_END 0x0800
424#define IPG_IE_RX_DMA_PRIORITY 0x1000
425
426/* IntStatus */
427#define IPG_IS_RSVD_MASK 0x1FFF
428#define IPG_IS_INTERRUPT_STATUS 0x0001
429#define IPG_IS_HOST_ERROR 0x0002
430#define IPG_IS_TX_COMPLETE 0x0004
431#define IPG_IS_MAC_CTRL_FRAME 0x0008
432#define IPG_IS_RX_COMPLETE 0x0010
433#define IPG_IS_RX_EARLY 0x0020
434#define IPG_IS_INT_REQUESTED 0x0040
435#define IPG_IS_UPDATE_STATS 0x0080
436#define IPG_IS_LINK_EVENT 0x0100
437#define IPG_IS_TX_DMA_COMPLETE 0x0200
438#define IPG_IS_RX_DMA_COMPLETE 0x0400
439#define IPG_IS_RFD_LIST_END 0x0800
440#define IPG_IS_RX_DMA_PRIORITY 0x1000
441
442/* MACCtrl */
443#define IPG_MC_RSVD_MASK 0x7FE33FA3
444#define IPG_MC_IFS_SELECT 0x00000003
445#define IPG_MC_IFS_4352BIT 0x00000003
446#define IPG_MC_IFS_1792BIT 0x00000002
447#define IPG_MC_IFS_1024BIT 0x00000001
448#define IPG_MC_IFS_96BIT 0x00000000
449#define IPG_MC_DUPLEX_SELECT 0x00000020
450#define IPG_MC_DUPLEX_SELECT_FD 0x00000020
451#define IPG_MC_DUPLEX_SELECT_HD 0x00000000
452#define IPG_MC_TX_FLOW_CONTROL_ENABLE 0x00000080
453#define IPG_MC_RX_FLOW_CONTROL_ENABLE 0x00000100
454#define IPG_MC_RCV_FCS 0x00000200
455#define IPG_MC_FIFO_LOOPBACK 0x00000400
456#define IPG_MC_MAC_LOOPBACK 0x00000800
457#define IPG_MC_AUTO_VLAN_TAGGING 0x00001000
458#define IPG_MC_AUTO_VLAN_UNTAGGING 0x00002000
459#define IPG_MC_COLLISION_DETECT 0x00010000
460#define IPG_MC_CARRIER_SENSE 0x00020000
461#define IPG_MC_STATISTICS_ENABLE 0x00200000
462#define IPG_MC_STATISTICS_DISABLE 0x00400000
463#define IPG_MC_STATISTICS_ENABLED 0x00800000
464#define IPG_MC_TX_ENABLE 0x01000000
465#define IPG_MC_TX_DISABLE 0x02000000
466#define IPG_MC_TX_ENABLED 0x04000000
467#define IPG_MC_RX_ENABLE 0x08000000
468#define IPG_MC_RX_DISABLE 0x10000000
469#define IPG_MC_RX_ENABLED 0x20000000
470#define IPG_MC_PAUSED 0x40000000
471
472/*
473 * Tune
474 */
475
Francois Romieu1202d6f2007-09-17 17:13:55 -0700476/* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS append on TX. */
Pekka Enberg4602e662007-11-30 09:53:33 +0200477#define IPG_APPEND_FCS_ON_TX 1
Francois Romieu1202d6f2007-09-17 17:13:55 -0700478
479/* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS strip on RX. */
Pekka Enberg4602e662007-11-30 09:53:33 +0200480#define IPG_STRIP_FCS_ON_RX 1
Francois Romieu1202d6f2007-09-17 17:13:55 -0700481
482/* Assign IPG_DROP_ON_RX_ETH_ERRORS > 0 to drop RX frames with
483 * Ethernet errors.
484 */
Pekka Enberg4602e662007-11-30 09:53:33 +0200485#define IPG_DROP_ON_RX_ETH_ERRORS 1
Francois Romieu1202d6f2007-09-17 17:13:55 -0700486
487/* Assign IPG_INSERT_MANUAL_VLAN_TAG > 0 to insert VLAN tags manually
488 * (via TFC).
489 */
Pekka Enberg4602e662007-11-30 09:53:33 +0200490#define IPG_INSERT_MANUAL_VLAN_TAG 0
Francois Romieu1202d6f2007-09-17 17:13:55 -0700491
492/* Assign IPG_ADD_IPCHECKSUM_ON_TX > 0 for auto IP checksum on TX. */
Pekka Enberg4602e662007-11-30 09:53:33 +0200493#define IPG_ADD_IPCHECKSUM_ON_TX 0
Francois Romieu1202d6f2007-09-17 17:13:55 -0700494
495/* Assign IPG_ADD_TCPCHECKSUM_ON_TX > 0 for auto TCP checksum on TX.
496 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
497 */
Pekka Enberg4602e662007-11-30 09:53:33 +0200498#define IPG_ADD_TCPCHECKSUM_ON_TX 0
Francois Romieu1202d6f2007-09-17 17:13:55 -0700499
500/* Assign IPG_ADD_UDPCHECKSUM_ON_TX > 0 for auto UDP checksum on TX.
501 * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
502 */
Pekka Enberg4602e662007-11-30 09:53:33 +0200503#define IPG_ADD_UDPCHECKSUM_ON_TX 0
Francois Romieu1202d6f2007-09-17 17:13:55 -0700504
505/* If inserting VLAN tags manually, assign the IPG_MANUAL_VLAN_xx
506 * constants as desired.
507 */
508#define IPG_MANUAL_VLAN_VID 0xABC
509#define IPG_MANUAL_VLAN_CFI 0x1
510#define IPG_MANUAL_VLAN_USERPRIORITY 0x5
511
512#define IPG_IO_REG_RANGE 0xFF
513#define IPG_MEM_REG_RANGE 0x154
514#define IPG_DRIVER_NAME "Sundance Technology IPG Triple-Speed Ethernet"
515#define IPG_NIC_PHY_ADDRESS 0x01
516#define IPG_DMALIST_ALIGN_PAD 0x07
517#define IPG_MULTICAST_HASHTABLE_SIZE 0x40
518
519/* Number of miliseconds to wait after issuing a software reset.
520 * 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation.
521 */
522#define IPG_AC_RESETWAIT 0x05
523
524/* Number of IPG_AC_RESETWAIT timeperiods before declaring timeout. */
525#define IPG_AC_RESET_TIMEOUT 0x0A
526
527/* Minimum number of nanoseconds used to toggle MDC clock during
528 * MII/GMII register access.
529 */
530#define IPG_PC_PHYCTRLWAIT_NS 200
531
532#define IPG_TFDLIST_LENGTH 0x100
533
534/* Number of frames between TxDMAComplete interrupt.
535 * 0 < IPG_FRAMESBETWEENTXDMACOMPLETES <= IPG_TFDLIST_LENGTH
536 */
537#define IPG_FRAMESBETWEENTXDMACOMPLETES 0x1
538
539#ifdef JUMBO_FRAME
540
541# ifdef JUMBO_FRAME_SIZE_2K
542# define JUMBO_FRAME_SIZE 2048
543# define __IPG_RXFRAG_SIZE 2048
544# else
545# ifdef JUMBO_FRAME_SIZE_3K
546# define JUMBO_FRAME_SIZE 3072
547# define __IPG_RXFRAG_SIZE 3072
548# else
549# ifdef JUMBO_FRAME_SIZE_4K
550# define JUMBO_FRAME_SIZE 4096
551# define __IPG_RXFRAG_SIZE 4088
552# else
553# ifdef JUMBO_FRAME_SIZE_5K
554# define JUMBO_FRAME_SIZE 5120
555# define __IPG_RXFRAG_SIZE 4088
556# else
557# ifdef JUMBO_FRAME_SIZE_6K
558# define JUMBO_FRAME_SIZE 6144
559# define __IPG_RXFRAG_SIZE 4088
560# else
561# ifdef JUMBO_FRAME_SIZE_7K
562# define JUMBO_FRAME_SIZE 7168
563# define __IPG_RXFRAG_SIZE 4088
564# else
565# ifdef JUMBO_FRAME_SIZE_8K
566# define JUMBO_FRAME_SIZE 8192
567# define __IPG_RXFRAG_SIZE 4088
568# else
569# ifdef JUMBO_FRAME_SIZE_9K
570# define JUMBO_FRAME_SIZE 9216
571# define __IPG_RXFRAG_SIZE 4088
572# else
573# ifdef JUMBO_FRAME_SIZE_10K
574# define JUMBO_FRAME_SIZE 10240
575# define __IPG_RXFRAG_SIZE 4088
576# else
577# define JUMBO_FRAME_SIZE 4096
578# endif
579# endif
580# endif
581# endif
582# endif
583# endif
584# endif
585# endif
586# endif
587#endif
588
589/* Size of allocated received buffers. Nominally 0x0600.
590 * Define larger if expecting jumbo frames.
591 */
592#ifdef JUMBO_FRAME
Pekka Enberg8da5bb72007-11-30 09:55:43 +0200593/* IPG_TXFRAG_SIZE must <= 0x2b00, or TX will crash */
Francois Romieu1202d6f2007-09-17 17:13:55 -0700594#define IPG_TXFRAG_SIZE JUMBO_FRAME_SIZE
595#endif
596
597/* Size of allocated received buffers. Nominally 0x0600.
598 * Define larger if expecting jumbo frames.
599 */
600#ifdef JUMBO_FRAME
Pekka Enberg8da5bb72007-11-30 09:55:43 +0200601/* 4088 = 4096 - 8 */
Francois Romieu1202d6f2007-09-17 17:13:55 -0700602#define IPG_RXFRAG_SIZE __IPG_RXFRAG_SIZE
603#define IPG_RXSUPPORT_SIZE IPG_MAX_RXFRAME_SIZE
604#else
605#define IPG_RXFRAG_SIZE 0x0600
606#define IPG_RXSUPPORT_SIZE IPG_RXFRAG_SIZE
607#endif
608
609/* IPG_MAX_RXFRAME_SIZE <= IPG_RXFRAG_SIZE */
610#ifdef JUMBO_FRAME
611#define IPG_MAX_RXFRAME_SIZE JUMBO_FRAME_SIZE
612#else
613#define IPG_MAX_RXFRAME_SIZE 0x0600
614#endif
615
616#define IPG_RFDLIST_LENGTH 0x100
617
618/* Maximum number of RFDs to process per interrupt.
619 * 1 < IPG_MAXRFDPROCESS_COUNT < IPG_RFDLIST_LENGTH
620 */
621#define IPG_MAXRFDPROCESS_COUNT 0x80
622
623/* Minimum margin between last freed RFD, and current RFD.
624 * 1 < IPG_MINUSEDRFDSTOFREE < IPG_RFDLIST_LENGTH
625 */
626#define IPG_MINUSEDRFDSTOFREE 0x80
627
628/* specify the jumbo frame maximum size
Pekka Enberg9893ba12008-01-24 02:01:17 -0800629 * per unit is 0x600 (the rx_buffer size that one RFD can carry)
Francois Romieu1202d6f2007-09-17 17:13:55 -0700630 */
Pekka Enberg8da5bb72007-11-30 09:55:43 +0200631#define MAX_JUMBOSIZE 0x8 /* max is 12K */
Francois Romieu1202d6f2007-09-17 17:13:55 -0700632
633/* Key register values loaded at driver start up. */
634
635/* TXDMAPollPeriod is specified in 320ns increments.
636 *
637 * Value Time
638 * ---------------------
639 * 0x00-0x01 320ns
640 * 0x03 ~1us
641 * 0x1F ~10us
642 * 0xFF ~82us
643 */
644#define IPG_TXDMAPOLLPERIOD_VALUE 0x26
645
646/* TxDMAUrgentThresh specifies the minimum amount of
647 * data in the transmit FIFO before asserting an
648 * urgent transmit DMA request.
649 *
650 * Value Min TxFIFO occupied space before urgent TX request
651 * ---------------------------------------------------------------
652 * 0x00-0x04 128 bytes (1024 bits)
653 * 0x27 1248 bytes (~10000 bits)
654 * 0x30 1536 bytes (12288 bits)
655 * 0xFF 8192 bytes (65535 bits)
656 */
657#define IPG_TXDMAURGENTTHRESH_VALUE 0x04
658
659/* TxDMABurstThresh specifies the minimum amount of
660 * free space in the transmit FIFO before asserting an
661 * transmit DMA request.
662 *
663 * Value Min TxFIFO free space before TX request
664 * ----------------------------------------------------
665 * 0x00-0x08 256 bytes
666 * 0x30 1536 bytes
667 * 0xFF 8192 bytes
668 */
669#define IPG_TXDMABURSTTHRESH_VALUE 0x30
670
671/* RXDMAPollPeriod is specified in 320ns increments.
672 *
673 * Value Time
674 * ---------------------
675 * 0x00-0x01 320ns
676 * 0x03 ~1us
677 * 0x1F ~10us
678 * 0xFF ~82us
679 */
680#define IPG_RXDMAPOLLPERIOD_VALUE 0x01
681
682/* RxDMAUrgentThresh specifies the minimum amount of
683 * free space within the receive FIFO before asserting
684 * a urgent receive DMA request.
685 *
686 * Value Min RxFIFO free space before urgent RX request
687 * ---------------------------------------------------------------
688 * 0x00-0x04 128 bytes (1024 bits)
689 * 0x27 1248 bytes (~10000 bits)
690 * 0x30 1536 bytes (12288 bits)
691 * 0xFF 8192 bytes (65535 bits)
692 */
693#define IPG_RXDMAURGENTTHRESH_VALUE 0x30
694
695/* RxDMABurstThresh specifies the minimum amount of
696 * occupied space within the receive FIFO before asserting
697 * a receive DMA request.
698 *
699 * Value Min TxFIFO free space before TX request
700 * ----------------------------------------------------
701 * 0x00-0x08 256 bytes
702 * 0x30 1536 bytes
703 * 0xFF 8192 bytes
704 */
705#define IPG_RXDMABURSTTHRESH_VALUE 0x30
706
707/* FlowOnThresh specifies the maximum amount of occupied
708 * space in the receive FIFO before a PAUSE frame with
709 * maximum pause time transmitted.
710 *
711 * Value Max RxFIFO occupied space before PAUSE
712 * ---------------------------------------------------
713 * 0x0000 0 bytes
714 * 0x0740 29,696 bytes
715 * 0x07FF 32,752 bytes
716 */
717#define IPG_FLOWONTHRESH_VALUE 0x0740
718
719/* FlowOffThresh specifies the minimum amount of occupied
720 * space in the receive FIFO before a PAUSE frame with
721 * zero pause time is transmitted.
722 *
723 * Value Max RxFIFO occupied space before PAUSE
724 * ---------------------------------------------------
725 * 0x0000 0 bytes
726 * 0x00BF 3056 bytes
727 * 0x07FF 32,752 bytes
728 */
729#define IPG_FLOWOFFTHRESH_VALUE 0x00BF
730
731/*
732 * Miscellaneous macros.
733 */
734
Pekka Enberg6d3b2cb2007-11-30 09:54:33 +0200735/* Marco for printing debug statements. */
Francois Romieu1202d6f2007-09-17 17:13:55 -0700736#ifdef IPG_DEBUG
737# define IPG_DEBUG_MSG(args...)
738# define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " args)
739# define IPG_DUMPRFDLIST(args) ipg_dump_rfdlist(args)
740# define IPG_DUMPTFDLIST(args) ipg_dump_tfdlist(args)
741#else
742# define IPG_DEBUG_MSG(args...)
743# define IPG_DDEBUG_MSG(args...)
744# define IPG_DUMPRFDLIST(args)
745# define IPG_DUMPTFDLIST(args)
746#endif
747
748/*
749 * End miscellaneous macros.
750 */
751
752/* Transmit Frame Descriptor. The IPG supports 15 fragments,
753 * however Linux requires only a single fragment. Note, each
754 * TFD field is 64 bits wide.
755 */
756struct ipg_tx {
Al Viro857e37d2007-10-14 19:41:19 +0100757 __le64 next_desc;
758 __le64 tfc;
759 __le64 frag_info;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700760};
761
762/* Receive Frame Descriptor. Note, each RFD field is 64 bits wide.
763 */
764struct ipg_rx {
Al Viro857e37d2007-10-14 19:41:19 +0100765 __le64 next_desc;
766 __le64 rfs;
767 __le64 frag_info;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700768};
769
Pekka Enberg9893ba12008-01-24 02:01:17 -0800770struct ipg_jumbo {
771 int found_start;
772 int current_size;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700773 struct sk_buff *skb;
774};
Pekka Enberg9893ba12008-01-24 02:01:17 -0800775
Francois Romieu1202d6f2007-09-17 17:13:55 -0700776/* Structure of IPG NIC specific data. */
777struct ipg_nic_private {
778 void __iomem *ioaddr;
779 struct ipg_tx *txd;
780 struct ipg_rx *rxd;
781 dma_addr_t txd_map;
782 dma_addr_t rxd_map;
Pekka Enberg9893ba12008-01-24 02:01:17 -0800783 struct sk_buff *tx_buff[IPG_TFDLIST_LENGTH];
784 struct sk_buff *rx_buff[IPG_RFDLIST_LENGTH];
Francois Romieu1202d6f2007-09-17 17:13:55 -0700785 unsigned int tx_current;
786 unsigned int tx_dirty;
787 unsigned int rx_current;
788 unsigned int rx_dirty;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700789#ifdef JUMBO_FRAME
Pekka Enberg9893ba12008-01-24 02:01:17 -0800790 struct ipg_jumbo jumbo;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700791#endif
792 unsigned int rx_buf_sz;
793 struct pci_dev *pdev;
794 struct net_device *dev;
795 struct net_device_stats stats;
796 spinlock_t lock;
797 int tenmbpsmode;
798
Pekka Enberg9893ba12008-01-24 02:01:17 -0800799 u16 led_mode;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700800 u16 station_addr[3]; /* Station Address in EEPROM Reg 0x10..0x12 */
801
802 struct mutex mii_mutex;
803 struct mii_if_info mii_if;
Pekka Enberg9893ba12008-01-24 02:01:17 -0800804 int reset_current_tfd;
Francois Romieu1202d6f2007-09-17 17:13:55 -0700805#ifdef IPG_DEBUG
806 int RFDlistendCount;
807 int RFDListCheckedCount;
808 int EmptyRFDListCount;
809#endif
810 struct delayed_work task;
811};
812
Francois Romieu1202d6f2007-09-17 17:13:55 -0700813#endif /* __LINUX_IPG_H */