Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * PHY functions |
| 3 | * |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 4 | * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> |
Nick Kossifidis | 33a3182 | 2009-02-09 06:00:34 +0200 | [diff] [blame] | 5 | * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 6 | * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 7 | * |
| 8 | * Permission to use, copy, modify, and distribute this software for any |
| 9 | * purpose with or without fee is hereby granted, provided that the above |
| 10 | * copyright notice and this permission notice appear in all copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 19 | * |
| 20 | */ |
| 21 | |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 22 | #define _ATH5K_PHY |
| 23 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 24 | #include <linux/delay.h> |
| 25 | |
| 26 | #include "ath5k.h" |
| 27 | #include "reg.h" |
| 28 | #include "base.h" |
Nick Kossifidis | 33a3182 | 2009-02-09 06:00:34 +0200 | [diff] [blame] | 29 | #include "rfbuffer.h" |
| 30 | #include "rfgain.h" |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 31 | |
| 32 | /* |
| 33 | * Used to modify RF Banks before writing them to AR5K_RF_BUFFER |
| 34 | */ |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 35 | static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, |
| 36 | const struct ath5k_rf_reg *rf_regs, |
| 37 | u32 val, u8 reg_id, bool set) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 38 | { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 39 | const struct ath5k_rf_reg *rfreg = NULL; |
| 40 | u8 offset, bank, num_bits, col, position; |
| 41 | u16 entry; |
| 42 | u32 mask, data, last_bit, bits_shifted, first_bit; |
| 43 | u32 *rfb; |
| 44 | s32 bits_left; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 45 | int i; |
| 46 | |
| 47 | data = 0; |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 48 | rfb = ah->ah_rf_banks; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 49 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 50 | for (i = 0; i < ah->ah_rf_regs_count; i++) { |
| 51 | if (rf_regs[i].index == reg_id) { |
| 52 | rfreg = &rf_regs[i]; |
| 53 | break; |
| 54 | } |
| 55 | } |
| 56 | |
| 57 | if (rfb == NULL || rfreg == NULL) { |
| 58 | ATH5K_PRINTF("Rf register not found!\n"); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 59 | /* should not happen */ |
| 60 | return 0; |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 61 | } |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 62 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 63 | bank = rfreg->bank; |
| 64 | num_bits = rfreg->field.len; |
| 65 | first_bit = rfreg->field.pos; |
| 66 | col = rfreg->field.col; |
| 67 | |
| 68 | /* first_bit is an offset from bank's |
| 69 | * start. Since we have all banks on |
| 70 | * the same array, we use this offset |
| 71 | * to mark each bank's start */ |
| 72 | offset = ah->ah_offset[bank]; |
| 73 | |
| 74 | /* Boundary check */ |
| 75 | if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 76 | ATH5K_PRINTF("invalid values at offset %u\n", offset); |
| 77 | return 0; |
| 78 | } |
| 79 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 80 | entry = ((first_bit - 1) / 8) + offset; |
| 81 | position = (first_bit - 1) % 8; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 82 | |
Joe Perches | e9010e2 | 2008-03-07 14:21:16 -0800 | [diff] [blame] | 83 | if (set) |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 84 | data = ath5k_hw_bitswap(val, num_bits); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 85 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 86 | for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; |
| 87 | position = 0, entry++) { |
| 88 | |
| 89 | last_bit = (position + bits_left > 8) ? 8 : |
| 90 | position + bits_left; |
| 91 | |
| 92 | mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << |
| 93 | (col * 8); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 94 | |
Joe Perches | e9010e2 | 2008-03-07 14:21:16 -0800 | [diff] [blame] | 95 | if (set) { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 96 | rfb[entry] &= ~mask; |
| 97 | rfb[entry] |= ((data << position) << (col * 8)) & mask; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 98 | data >>= (8 - position); |
| 99 | } else { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 100 | data |= (((rfb[entry] & mask) >> (col * 8)) >> position) |
| 101 | << bits_shifted; |
| 102 | bits_shifted += last_bit - position; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 103 | } |
| 104 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 105 | bits_left -= 8 - position; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 106 | } |
| 107 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 108 | data = set ? 1 : ath5k_hw_bitswap(data, num_bits); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 109 | |
| 110 | return data; |
| 111 | } |
| 112 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 113 | /**********************\ |
| 114 | * RF Gain optimization * |
| 115 | \**********************/ |
| 116 | |
| 117 | /* |
| 118 | * This code is used to optimize rf gain on different environments |
| 119 | * (temprature mostly) based on feedback from a power detector. |
| 120 | * |
| 121 | * It's only used on RF5111 and RF5112, later RF chips seem to have |
| 122 | * auto adjustment on hw -notice they have a much smaller BANK 7 and |
| 123 | * no gain optimization ladder-. |
| 124 | * |
| 125 | * For more infos check out this patent doc |
| 126 | * http://www.freepatentsonline.com/7400691.html |
| 127 | * |
| 128 | * This paper describes power drops as seen on the receiver due to |
| 129 | * probe packets |
| 130 | * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues |
| 131 | * %20of%20Power%20Control.pdf |
| 132 | * |
| 133 | * And this is the MadWiFi bug entry related to the above |
| 134 | * http://madwifi-project.org/ticket/1659 |
| 135 | * with various measurements and diagrams |
| 136 | * |
| 137 | * TODO: Deal with power drops due to probes by setting an apropriate |
| 138 | * tx power on the probe packets ! Make this part of the calibration process. |
| 139 | */ |
| 140 | |
| 141 | /* Initialize ah_gain durring attach */ |
| 142 | int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) |
| 143 | { |
| 144 | /* Initialize the gain optimization values */ |
| 145 | switch (ah->ah_radio) { |
| 146 | case AR5K_RF5111: |
| 147 | ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; |
| 148 | ah->ah_gain.g_low = 20; |
| 149 | ah->ah_gain.g_high = 35; |
| 150 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; |
| 151 | break; |
| 152 | case AR5K_RF5112: |
| 153 | ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; |
| 154 | ah->ah_gain.g_low = 20; |
| 155 | ah->ah_gain.g_high = 85; |
| 156 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; |
| 157 | break; |
| 158 | default: |
| 159 | return -EINVAL; |
| 160 | } |
| 161 | |
| 162 | return 0; |
| 163 | } |
| 164 | |
| 165 | /* Schedule a gain probe check on the next transmited packet. |
| 166 | * That means our next packet is going to be sent with lower |
| 167 | * tx power and a Peak to Average Power Detector (PAPD) will try |
| 168 | * to measure the gain. |
| 169 | * |
| 170 | * TODO: Use propper tx power setting for the probe packet so |
| 171 | * that we don't observe a serious power drop on the receiver |
| 172 | * |
| 173 | * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) |
| 174 | * just after we enable the probe so that we don't mess with |
| 175 | * standard traffic ? Maybe it's time to use sw interrupts and |
| 176 | * a probe tasklet !!! |
| 177 | */ |
| 178 | static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) |
| 179 | { |
| 180 | |
| 181 | /* Skip if gain calibration is inactive or |
| 182 | * we already handle a probe request */ |
| 183 | if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) |
| 184 | return; |
| 185 | |
| 186 | ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max, |
| 187 | AR5K_PHY_PAPD_PROBE_TXPOWER) | |
| 188 | AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); |
| 189 | |
| 190 | ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; |
| 191 | |
| 192 | } |
| 193 | |
| 194 | /* Calculate gain_F measurement correction |
| 195 | * based on the current step for RF5112 rev. 2 */ |
| 196 | static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 197 | { |
| 198 | u32 mix, step; |
| 199 | u32 *rf; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 200 | const struct ath5k_gain_opt *go; |
| 201 | const struct ath5k_gain_opt_step *g_step; |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 202 | const struct ath5k_rf_reg *rf_regs; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 203 | |
| 204 | /* Only RF5112 Rev. 2 supports it */ |
| 205 | if ((ah->ah_radio != AR5K_RF5112) || |
| 206 | (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) |
| 207 | return 0; |
| 208 | |
| 209 | go = &rfgain_opt_5112; |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 210 | rf_regs = rf_regs_5112a; |
| 211 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 212 | |
| 213 | g_step = &go->go_step[ah->ah_gain.g_step_idx]; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 214 | |
| 215 | if (ah->ah_rf_banks == NULL) |
| 216 | return 0; |
| 217 | |
| 218 | rf = ah->ah_rf_banks; |
| 219 | ah->ah_gain.g_f_corr = 0; |
| 220 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 221 | /* No VGA (Variable Gain Amplifier) override, skip */ |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 222 | if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 223 | return 0; |
| 224 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 225 | /* Mix gain stepping */ |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 226 | step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 227 | |
| 228 | /* Mix gain override */ |
| 229 | mix = g_step->gos_param[0]; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 230 | |
| 231 | switch (mix) { |
| 232 | case 3: |
| 233 | ah->ah_gain.g_f_corr = step * 2; |
| 234 | break; |
| 235 | case 2: |
| 236 | ah->ah_gain.g_f_corr = (step - 5) * 2; |
| 237 | break; |
| 238 | case 1: |
| 239 | ah->ah_gain.g_f_corr = step; |
| 240 | break; |
| 241 | default: |
| 242 | ah->ah_gain.g_f_corr = 0; |
| 243 | break; |
| 244 | } |
| 245 | |
| 246 | return ah->ah_gain.g_f_corr; |
| 247 | } |
| 248 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 249 | /* Check if current gain_F measurement is in the range of our |
| 250 | * power detector windows. If we get a measurement outside range |
| 251 | * we know it's not accurate (detectors can't measure anything outside |
| 252 | * their detection window) so we must ignore it */ |
| 253 | static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 254 | { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 255 | const struct ath5k_rf_reg *rf_regs; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 256 | u32 step, mix_ovr, level[4]; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 257 | u32 *rf; |
| 258 | |
| 259 | if (ah->ah_rf_banks == NULL) |
| 260 | return false; |
| 261 | |
| 262 | rf = ah->ah_rf_banks; |
| 263 | |
| 264 | if (ah->ah_radio == AR5K_RF5111) { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 265 | |
| 266 | rf_regs = rf_regs_5111; |
| 267 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); |
| 268 | |
| 269 | step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, |
| 270 | false); |
| 271 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 272 | level[0] = 0; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 273 | level[1] = (step == 63) ? 50 : step + 4; |
| 274 | level[2] = (step != 63) ? 64 : level[0]; |
| 275 | level[3] = level[2] + 50 ; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 276 | |
| 277 | ah->ah_gain.g_high = level[3] - |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 278 | (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 279 | ah->ah_gain.g_low = level[0] + |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 280 | (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 281 | } else { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 282 | |
| 283 | rf_regs = rf_regs_5112; |
| 284 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); |
| 285 | |
| 286 | mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, |
| 287 | false); |
| 288 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 289 | level[0] = level[2] = 0; |
| 290 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 291 | if (mix_ovr == 1) { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 292 | level[1] = level[3] = 83; |
| 293 | } else { |
| 294 | level[1] = level[3] = 107; |
| 295 | ah->ah_gain.g_high = 55; |
| 296 | } |
| 297 | } |
| 298 | |
| 299 | return (ah->ah_gain.g_current >= level[0] && |
| 300 | ah->ah_gain.g_current <= level[1]) || |
| 301 | (ah->ah_gain.g_current >= level[2] && |
| 302 | ah->ah_gain.g_current <= level[3]); |
| 303 | } |
| 304 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 305 | /* Perform gain_F adjustment by choosing the right set |
| 306 | * of parameters from rf gain optimization ladder */ |
| 307 | static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 308 | { |
| 309 | const struct ath5k_gain_opt *go; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 310 | const struct ath5k_gain_opt_step *g_step; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 311 | int ret = 0; |
| 312 | |
| 313 | switch (ah->ah_radio) { |
| 314 | case AR5K_RF5111: |
| 315 | go = &rfgain_opt_5111; |
| 316 | break; |
| 317 | case AR5K_RF5112: |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 318 | go = &rfgain_opt_5112; |
| 319 | break; |
| 320 | default: |
| 321 | return 0; |
| 322 | } |
| 323 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 324 | g_step = &go->go_step[ah->ah_gain.g_step_idx]; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 325 | |
| 326 | if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 327 | |
| 328 | /* Reached maximum */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 329 | if (ah->ah_gain.g_step_idx == 0) |
| 330 | return -1; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 331 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 332 | for (ah->ah_gain.g_target = ah->ah_gain.g_current; |
| 333 | ah->ah_gain.g_target >= ah->ah_gain.g_high && |
| 334 | ah->ah_gain.g_step_idx > 0; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 335 | g_step = &go->go_step[ah->ah_gain.g_step_idx]) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 336 | ah->ah_gain.g_target -= 2 * |
| 337 | (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 338 | g_step->gos_gain); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 339 | |
| 340 | ret = 1; |
| 341 | goto done; |
| 342 | } |
| 343 | |
| 344 | if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 345 | |
| 346 | /* Reached minimum */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 347 | if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) |
| 348 | return -2; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 349 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 350 | for (ah->ah_gain.g_target = ah->ah_gain.g_current; |
| 351 | ah->ah_gain.g_target <= ah->ah_gain.g_low && |
| 352 | ah->ah_gain.g_step_idx < go->go_steps_count-1; |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 353 | g_step = &go->go_step[ah->ah_gain.g_step_idx]) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 354 | ah->ah_gain.g_target -= 2 * |
| 355 | (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 356 | g_step->gos_gain); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 357 | |
| 358 | ret = 2; |
| 359 | goto done; |
| 360 | } |
| 361 | |
| 362 | done: |
| 363 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, |
| 364 | "ret %d, gain step %u, current gain %u, target gain %u\n", |
| 365 | ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, |
| 366 | ah->ah_gain.g_target); |
| 367 | |
| 368 | return ret; |
| 369 | } |
| 370 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 371 | /* Main callback for thermal rf gain calibration engine |
| 372 | * Check for a new gain reading and schedule an adjustment |
| 373 | * if needed. |
| 374 | * |
| 375 | * TODO: Use sw interrupt to schedule reset if gain_F needs |
| 376 | * adjustment */ |
| 377 | enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) |
| 378 | { |
| 379 | u32 data, type; |
| 380 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 381 | |
| 382 | ATH5K_TRACE(ah->ah_sc); |
| 383 | |
| 384 | if (ah->ah_rf_banks == NULL || |
| 385 | ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) |
| 386 | return AR5K_RFGAIN_INACTIVE; |
| 387 | |
| 388 | /* No check requested, either engine is inactive |
| 389 | * or an adjustment is already requested */ |
| 390 | if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) |
| 391 | goto done; |
| 392 | |
| 393 | /* Read the PAPD (Peak to Average Power Detector) |
| 394 | * register */ |
| 395 | data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); |
| 396 | |
| 397 | /* No probe is scheduled, read gain_F measurement */ |
| 398 | if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { |
| 399 | ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; |
| 400 | type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); |
| 401 | |
| 402 | /* If tx packet is CCK correct the gain_F measurement |
| 403 | * by cck ofdm gain delta */ |
| 404 | if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { |
| 405 | if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) |
| 406 | ah->ah_gain.g_current += |
| 407 | ee->ee_cck_ofdm_gain_delta; |
| 408 | else |
| 409 | ah->ah_gain.g_current += |
| 410 | AR5K_GAIN_CCK_PROBE_CORR; |
| 411 | } |
| 412 | |
| 413 | /* Further correct gain_F measurement for |
| 414 | * RF5112A radios */ |
| 415 | if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { |
| 416 | ath5k_hw_rf_gainf_corr(ah); |
| 417 | ah->ah_gain.g_current = |
| 418 | ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? |
| 419 | (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : |
| 420 | 0; |
| 421 | } |
| 422 | |
| 423 | /* Check if measurement is ok and if we need |
| 424 | * to adjust gain, schedule a gain adjustment, |
| 425 | * else switch back to the acive state */ |
| 426 | if (ath5k_hw_rf_check_gainf_readback(ah) && |
| 427 | AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && |
| 428 | ath5k_hw_rf_gainf_adjust(ah)) { |
| 429 | ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; |
| 430 | } else { |
| 431 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | done: |
| 436 | return ah->ah_gain.g_state; |
| 437 | } |
| 438 | |
| 439 | /* Write initial rf gain table to set the RF sensitivity |
| 440 | * this one works on all RF chips and has nothing to do |
| 441 | * with gain_F calibration */ |
| 442 | int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq) |
| 443 | { |
| 444 | const struct ath5k_ini_rfgain *ath5k_rfg; |
| 445 | unsigned int i, size; |
| 446 | |
| 447 | switch (ah->ah_radio) { |
| 448 | case AR5K_RF5111: |
| 449 | ath5k_rfg = rfgain_5111; |
| 450 | size = ARRAY_SIZE(rfgain_5111); |
| 451 | break; |
| 452 | case AR5K_RF5112: |
| 453 | ath5k_rfg = rfgain_5112; |
| 454 | size = ARRAY_SIZE(rfgain_5112); |
| 455 | break; |
| 456 | case AR5K_RF2413: |
| 457 | ath5k_rfg = rfgain_2413; |
| 458 | size = ARRAY_SIZE(rfgain_2413); |
| 459 | break; |
| 460 | case AR5K_RF2316: |
| 461 | ath5k_rfg = rfgain_2316; |
| 462 | size = ARRAY_SIZE(rfgain_2316); |
| 463 | break; |
| 464 | case AR5K_RF5413: |
| 465 | ath5k_rfg = rfgain_5413; |
| 466 | size = ARRAY_SIZE(rfgain_5413); |
| 467 | break; |
| 468 | case AR5K_RF2317: |
| 469 | case AR5K_RF2425: |
| 470 | ath5k_rfg = rfgain_2425; |
| 471 | size = ARRAY_SIZE(rfgain_2425); |
| 472 | break; |
| 473 | default: |
| 474 | return -EINVAL; |
| 475 | } |
| 476 | |
| 477 | switch (freq) { |
| 478 | case AR5K_INI_RFGAIN_2GHZ: |
| 479 | case AR5K_INI_RFGAIN_5GHZ: |
| 480 | break; |
| 481 | default: |
| 482 | return -EINVAL; |
| 483 | } |
| 484 | |
| 485 | for (i = 0; i < size; i++) { |
| 486 | AR5K_REG_WAIT(i); |
| 487 | ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], |
| 488 | (u32)ath5k_rfg[i].rfg_register); |
| 489 | } |
| 490 | |
| 491 | return 0; |
| 492 | } |
| 493 | |
| 494 | |
| 495 | |
| 496 | /********************\ |
| 497 | * RF Registers setup * |
| 498 | \********************/ |
| 499 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 500 | |
| 501 | /* |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 502 | * Setup RF registers by writing rf buffer on hw |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 503 | */ |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 504 | int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 505 | unsigned int mode) |
| 506 | { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 507 | const struct ath5k_rf_reg *rf_regs; |
| 508 | const struct ath5k_ini_rfbuffer *ini_rfb; |
| 509 | const struct ath5k_gain_opt *go = NULL; |
| 510 | const struct ath5k_gain_opt_step *g_step; |
| 511 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
| 512 | u8 ee_mode = 0; |
| 513 | u32 *rfb; |
| 514 | int i, obdb = -1, bank = -1; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 515 | |
| 516 | switch (ah->ah_radio) { |
| 517 | case AR5K_RF5111: |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 518 | rf_regs = rf_regs_5111; |
| 519 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); |
| 520 | ini_rfb = rfb_5111; |
| 521 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); |
| 522 | go = &rfgain_opt_5111; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 523 | break; |
| 524 | case AR5K_RF5112: |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 525 | if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { |
| 526 | rf_regs = rf_regs_5112a; |
| 527 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); |
| 528 | ini_rfb = rfb_5112a; |
| 529 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); |
| 530 | } else { |
| 531 | rf_regs = rf_regs_5112; |
| 532 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); |
| 533 | ini_rfb = rfb_5112; |
| 534 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); |
| 535 | } |
| 536 | go = &rfgain_opt_5112; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 537 | break; |
Nick Kossifidis | f714dd6 | 2008-02-28 14:43:51 -0500 | [diff] [blame] | 538 | case AR5K_RF2413: |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 539 | rf_regs = rf_regs_2413; |
| 540 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); |
| 541 | ini_rfb = rfb_2413; |
| 542 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); |
| 543 | break; |
| 544 | case AR5K_RF2316: |
| 545 | rf_regs = rf_regs_2316; |
| 546 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); |
| 547 | ini_rfb = rfb_2316; |
| 548 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); |
| 549 | break; |
| 550 | case AR5K_RF5413: |
| 551 | rf_regs = rf_regs_5413; |
| 552 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); |
| 553 | ini_rfb = rfb_5413; |
| 554 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); |
| 555 | break; |
| 556 | case AR5K_RF2317: |
| 557 | rf_regs = rf_regs_2425; |
| 558 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); |
| 559 | ini_rfb = rfb_2317; |
| 560 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); |
Nick Kossifidis | f714dd6 | 2008-02-28 14:43:51 -0500 | [diff] [blame] | 561 | break; |
Nick Kossifidis | 136bfc7 | 2008-04-16 18:42:48 +0300 | [diff] [blame] | 562 | case AR5K_RF2425: |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 563 | rf_regs = rf_regs_2425; |
| 564 | ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); |
| 565 | if (ah->ah_mac_srev < AR5K_SREV_AR2417) { |
| 566 | ini_rfb = rfb_2425; |
| 567 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); |
| 568 | } else { |
| 569 | ini_rfb = rfb_2417; |
| 570 | ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); |
| 571 | } |
Nick Kossifidis | 136bfc7 | 2008-04-16 18:42:48 +0300 | [diff] [blame] | 572 | break; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 573 | default: |
| 574 | return -EINVAL; |
| 575 | } |
| 576 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 577 | /* If it's the first time we set rf buffer, allocate |
| 578 | * ah->ah_rf_banks based on ah->ah_rf_banks_size |
| 579 | * we set above */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 580 | if (ah->ah_rf_banks == NULL) { |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 581 | ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, |
| 582 | GFP_KERNEL); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 583 | if (ah->ah_rf_banks == NULL) { |
| 584 | ATH5K_ERR(ah->ah_sc, "out of memory\n"); |
| 585 | return -ENOMEM; |
| 586 | } |
| 587 | } |
| 588 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 589 | /* Copy values to modify them */ |
| 590 | rfb = ah->ah_rf_banks; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 591 | |
Nick Kossifidis | 8892e4e | 2009-02-09 06:06:34 +0200 | [diff] [blame^] | 592 | for (i = 0; i < ah->ah_rf_banks_size; i++) { |
| 593 | if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { |
| 594 | ATH5K_ERR(ah->ah_sc, "invalid bank\n"); |
| 595 | return -EINVAL; |
| 596 | } |
| 597 | |
| 598 | /* Bank changed, write down the offset */ |
| 599 | if (bank != ini_rfb[i].rfb_bank) { |
| 600 | bank = ini_rfb[i].rfb_bank; |
| 601 | ah->ah_offset[bank] = i; |
| 602 | } |
| 603 | |
| 604 | rfb[i] = ini_rfb[i].rfb_mode_data[mode]; |
| 605 | } |
| 606 | |
| 607 | /* Set Output and Driver bias current (OB/DB) */ |
| 608 | if (channel->hw_value & CHANNEL_2GHZ) { |
| 609 | |
| 610 | if (channel->hw_value & CHANNEL_CCK) |
| 611 | ee_mode = AR5K_EEPROM_MODE_11B; |
| 612 | else |
| 613 | ee_mode = AR5K_EEPROM_MODE_11G; |
| 614 | |
| 615 | /* For RF511X/RF211X combination we |
| 616 | * use b_OB and b_DB parameters stored |
| 617 | * in eeprom on ee->ee_ob[ee_mode][0] |
| 618 | * |
| 619 | * For all other chips we use OB/DB for 2Ghz |
| 620 | * stored in the b/g modal section just like |
| 621 | * 802.11a on ee->ee_ob[ee_mode][1] */ |
| 622 | if ((ah->ah_radio == AR5K_RF5111) || |
| 623 | (ah->ah_radio == AR5K_RF5112)) |
| 624 | obdb = 0; |
| 625 | else |
| 626 | obdb = 1; |
| 627 | |
| 628 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], |
| 629 | AR5K_RF_OB_2GHZ, true); |
| 630 | |
| 631 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], |
| 632 | AR5K_RF_DB_2GHZ, true); |
| 633 | |
| 634 | /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ |
| 635 | } else if ((channel->hw_value & CHANNEL_5GHZ) || |
| 636 | (ah->ah_radio == AR5K_RF5111)) { |
| 637 | |
| 638 | /* For 11a, Turbo and XR we need to choose |
| 639 | * OB/DB based on frequency range */ |
| 640 | ee_mode = AR5K_EEPROM_MODE_11A; |
| 641 | obdb = channel->center_freq >= 5725 ? 3 : |
| 642 | (channel->center_freq >= 5500 ? 2 : |
| 643 | (channel->center_freq >= 5260 ? 1 : |
| 644 | (channel->center_freq > 4000 ? 0 : -1))); |
| 645 | |
| 646 | if (obdb < 0) |
| 647 | return -EINVAL; |
| 648 | |
| 649 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], |
| 650 | AR5K_RF_OB_5GHZ, true); |
| 651 | |
| 652 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], |
| 653 | AR5K_RF_DB_5GHZ, true); |
| 654 | } |
| 655 | |
| 656 | g_step = &go->go_step[ah->ah_gain.g_step_idx]; |
| 657 | |
| 658 | /* Bank Modifications (chip-specific) */ |
| 659 | if (ah->ah_radio == AR5K_RF5111) { |
| 660 | |
| 661 | /* Set gain_F settings according to current step */ |
| 662 | if (channel->hw_value & CHANNEL_OFDM) { |
| 663 | |
| 664 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, |
| 665 | AR5K_PHY_FRAME_CTL_TX_CLIP, |
| 666 | g_step->gos_param[0]); |
| 667 | |
| 668 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], |
| 669 | AR5K_RF_PWD_90, true); |
| 670 | |
| 671 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], |
| 672 | AR5K_RF_PWD_84, true); |
| 673 | |
| 674 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], |
| 675 | AR5K_RF_RFGAIN_SEL, true); |
| 676 | |
| 677 | /* We programmed gain_F parameters, switch back |
| 678 | * to active state */ |
| 679 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; |
| 680 | |
| 681 | } |
| 682 | |
| 683 | /* Bank 6/7 setup */ |
| 684 | |
| 685 | ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], |
| 686 | AR5K_RF_PWD_XPD, true); |
| 687 | |
| 688 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], |
| 689 | AR5K_RF_XPD_GAIN, true); |
| 690 | |
| 691 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], |
| 692 | AR5K_RF_GAIN_I, true); |
| 693 | |
| 694 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], |
| 695 | AR5K_RF_PLO_SEL, true); |
| 696 | |
| 697 | /* TODO: Half/quarter channel support */ |
| 698 | } |
| 699 | |
| 700 | if (ah->ah_radio == AR5K_RF5112) { |
| 701 | |
| 702 | /* Set gain_F settings according to current step */ |
| 703 | if (channel->hw_value & CHANNEL_OFDM) { |
| 704 | |
| 705 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], |
| 706 | AR5K_RF_MIXGAIN_OVR, true); |
| 707 | |
| 708 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], |
| 709 | AR5K_RF_PWD_138, true); |
| 710 | |
| 711 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], |
| 712 | AR5K_RF_PWD_137, true); |
| 713 | |
| 714 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], |
| 715 | AR5K_RF_PWD_136, true); |
| 716 | |
| 717 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], |
| 718 | AR5K_RF_PWD_132, true); |
| 719 | |
| 720 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], |
| 721 | AR5K_RF_PWD_131, true); |
| 722 | |
| 723 | ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], |
| 724 | AR5K_RF_PWD_130, true); |
| 725 | |
| 726 | /* We programmed gain_F parameters, switch back |
| 727 | * to active state */ |
| 728 | ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; |
| 729 | } |
| 730 | |
| 731 | /* Bank 6/7 setup */ |
| 732 | |
| 733 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], |
| 734 | AR5K_RF_XPD_SEL, true); |
| 735 | |
| 736 | if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { |
| 737 | /* Rev. 1 supports only one xpd */ |
| 738 | ath5k_hw_rfb_op(ah, rf_regs, |
| 739 | ee->ee_x_gain[ee_mode], |
| 740 | AR5K_RF_XPD_GAIN, true); |
| 741 | |
| 742 | } else { |
| 743 | /* TODO: Set high and low gain bits */ |
| 744 | ath5k_hw_rfb_op(ah, rf_regs, |
| 745 | ee->ee_x_gain[ee_mode], |
| 746 | AR5K_RF_PD_GAIN_LO, true); |
| 747 | ath5k_hw_rfb_op(ah, rf_regs, |
| 748 | ee->ee_x_gain[ee_mode], |
| 749 | AR5K_RF_PD_GAIN_HI, true); |
| 750 | |
| 751 | /* Lower synth voltage on Rev 2 */ |
| 752 | ath5k_hw_rfb_op(ah, rf_regs, 2, |
| 753 | AR5K_RF_HIGH_VC_CP, true); |
| 754 | |
| 755 | ath5k_hw_rfb_op(ah, rf_regs, 2, |
| 756 | AR5K_RF_MID_VC_CP, true); |
| 757 | |
| 758 | ath5k_hw_rfb_op(ah, rf_regs, 2, |
| 759 | AR5K_RF_LOW_VC_CP, true); |
| 760 | |
| 761 | ath5k_hw_rfb_op(ah, rf_regs, 2, |
| 762 | AR5K_RF_PUSH_UP, true); |
| 763 | |
| 764 | /* Decrease power consumption on 5213+ BaseBand */ |
| 765 | if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { |
| 766 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
| 767 | AR5K_RF_PAD2GND, true); |
| 768 | |
| 769 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
| 770 | AR5K_RF_XB2_LVL, true); |
| 771 | |
| 772 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
| 773 | AR5K_RF_XB5_LVL, true); |
| 774 | |
| 775 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
| 776 | AR5K_RF_PWD_167, true); |
| 777 | |
| 778 | ath5k_hw_rfb_op(ah, rf_regs, 1, |
| 779 | AR5K_RF_PWD_166, true); |
| 780 | } |
| 781 | } |
| 782 | |
| 783 | ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], |
| 784 | AR5K_RF_GAIN_I, true); |
| 785 | |
| 786 | /* TODO: Half/quarter channel support */ |
| 787 | |
| 788 | } |
| 789 | |
| 790 | if (ah->ah_radio == AR5K_RF5413 && |
| 791 | channel->hw_value & CHANNEL_2GHZ) { |
| 792 | |
| 793 | ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, |
| 794 | true); |
| 795 | |
| 796 | /* Set optimum value for early revisions (on pci-e chips) */ |
| 797 | if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && |
| 798 | ah->ah_mac_srev < AR5K_SREV_AR5413) |
| 799 | ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), |
| 800 | AR5K_RF_PWD_ICLOBUF_2G, true); |
| 801 | |
| 802 | } |
| 803 | |
| 804 | /* Write RF banks on hw */ |
| 805 | for (i = 0; i < ah->ah_rf_banks_size; i++) { |
| 806 | AR5K_REG_WAIT(i); |
| 807 | ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); |
| 808 | } |
| 809 | |
| 810 | return 0; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 811 | } |
| 812 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 813 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 814 | /**************************\ |
| 815 | PHY/RF channel functions |
| 816 | \**************************/ |
| 817 | |
| 818 | /* |
| 819 | * Check if a channel is supported |
| 820 | */ |
| 821 | bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags) |
| 822 | { |
| 823 | /* Check if the channel is in our supported range */ |
| 824 | if (flags & CHANNEL_2GHZ) { |
| 825 | if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && |
| 826 | (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) |
| 827 | return true; |
| 828 | } else if (flags & CHANNEL_5GHZ) |
| 829 | if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && |
| 830 | (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) |
| 831 | return true; |
| 832 | |
| 833 | return false; |
| 834 | } |
| 835 | |
| 836 | /* |
| 837 | * Convertion needed for RF5110 |
| 838 | */ |
| 839 | static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) |
| 840 | { |
| 841 | u32 athchan; |
| 842 | |
| 843 | /* |
| 844 | * Convert IEEE channel/MHz to an internal channel value used |
| 845 | * by the AR5210 chipset. This has not been verified with |
| 846 | * newer chipsets like the AR5212A who have a completely |
| 847 | * different RF/PHY part. |
| 848 | */ |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 849 | athchan = (ath5k_hw_bitswap( |
| 850 | (ieee80211_frequency_to_channel( |
| 851 | channel->center_freq) - 24) / 2, 5) |
| 852 | << 1) | (1 << 6) | 0x1; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 853 | return athchan; |
| 854 | } |
| 855 | |
| 856 | /* |
| 857 | * Set channel on RF5110 |
| 858 | */ |
| 859 | static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, |
| 860 | struct ieee80211_channel *channel) |
| 861 | { |
| 862 | u32 data; |
| 863 | |
| 864 | /* |
| 865 | * Set the channel and wait |
| 866 | */ |
| 867 | data = ath5k_hw_rf5110_chan2athchan(channel); |
| 868 | ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); |
| 869 | ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); |
| 870 | mdelay(1); |
| 871 | |
| 872 | return 0; |
| 873 | } |
| 874 | |
| 875 | /* |
| 876 | * Convertion needed for 5111 |
| 877 | */ |
| 878 | static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, |
| 879 | struct ath5k_athchan_2ghz *athchan) |
| 880 | { |
| 881 | int channel; |
| 882 | |
| 883 | /* Cast this value to catch negative channel numbers (>= -19) */ |
| 884 | channel = (int)ieee; |
| 885 | |
| 886 | /* |
| 887 | * Map 2GHz IEEE channel to 5GHz Atheros channel |
| 888 | */ |
| 889 | if (channel <= 13) { |
| 890 | athchan->a2_athchan = 115 + channel; |
| 891 | athchan->a2_flags = 0x46; |
| 892 | } else if (channel == 14) { |
| 893 | athchan->a2_athchan = 124; |
| 894 | athchan->a2_flags = 0x44; |
| 895 | } else if (channel >= 15 && channel <= 26) { |
| 896 | athchan->a2_athchan = ((channel - 14) * 4) + 132; |
| 897 | athchan->a2_flags = 0x46; |
| 898 | } else |
| 899 | return -EINVAL; |
| 900 | |
| 901 | return 0; |
| 902 | } |
| 903 | |
| 904 | /* |
| 905 | * Set channel on 5111 |
| 906 | */ |
| 907 | static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, |
| 908 | struct ieee80211_channel *channel) |
| 909 | { |
| 910 | struct ath5k_athchan_2ghz ath5k_channel_2ghz; |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 911 | unsigned int ath5k_channel = |
| 912 | ieee80211_frequency_to_channel(channel->center_freq); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 913 | u32 data0, data1, clock; |
| 914 | int ret; |
| 915 | |
| 916 | /* |
| 917 | * Set the channel on the RF5111 radio |
| 918 | */ |
| 919 | data0 = data1 = 0; |
| 920 | |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 921 | if (channel->hw_value & CHANNEL_2GHZ) { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 922 | /* Map 2GHz channel to 5GHz Atheros channel ID */ |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 923 | ret = ath5k_hw_rf5111_chan2athchan( |
| 924 | ieee80211_frequency_to_channel(channel->center_freq), |
| 925 | &ath5k_channel_2ghz); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 926 | if (ret) |
| 927 | return ret; |
| 928 | |
| 929 | ath5k_channel = ath5k_channel_2ghz.a2_athchan; |
| 930 | data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) |
| 931 | << 5) | (1 << 4); |
| 932 | } |
| 933 | |
| 934 | if (ath5k_channel < 145 || !(ath5k_channel & 1)) { |
| 935 | clock = 1; |
| 936 | data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | |
| 937 | (clock << 1) | (1 << 10) | 1; |
| 938 | } else { |
| 939 | clock = 0; |
| 940 | data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) |
| 941 | << 2) | (clock << 1) | (1 << 10) | 1; |
| 942 | } |
| 943 | |
| 944 | ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), |
| 945 | AR5K_RF_BUFFER); |
| 946 | ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), |
| 947 | AR5K_RF_BUFFER_CONTROL_3); |
| 948 | |
| 949 | return 0; |
| 950 | } |
| 951 | |
| 952 | /* |
| 953 | * Set channel on 5112 and newer |
| 954 | */ |
| 955 | static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, |
| 956 | struct ieee80211_channel *channel) |
| 957 | { |
| 958 | u32 data, data0, data1, data2; |
| 959 | u16 c; |
| 960 | |
| 961 | data = data0 = data1 = data2 = 0; |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 962 | c = channel->center_freq; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 963 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 964 | if (c < 4800) { |
| 965 | if (!((c - 2224) % 5)) { |
| 966 | data0 = ((2 * (c - 704)) - 3040) / 10; |
| 967 | data1 = 1; |
| 968 | } else if (!((c - 2192) % 5)) { |
| 969 | data0 = ((2 * (c - 672)) - 3040) / 10; |
| 970 | data1 = 0; |
| 971 | } else |
| 972 | return -EINVAL; |
| 973 | |
| 974 | data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); |
Nick Kossifidis | cc6323c | 2008-07-20 06:44:43 +0300 | [diff] [blame] | 975 | } else if ((c - (c % 5)) != 2 || c > 5435) { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 976 | if (!(c % 20) && c >= 5120) { |
| 977 | data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); |
| 978 | data2 = ath5k_hw_bitswap(3, 2); |
| 979 | } else if (!(c % 10)) { |
| 980 | data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); |
| 981 | data2 = ath5k_hw_bitswap(2, 2); |
| 982 | } else if (!(c % 5)) { |
| 983 | data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); |
| 984 | data2 = ath5k_hw_bitswap(1, 2); |
| 985 | } else |
| 986 | return -EINVAL; |
Nick Kossifidis | cc6323c | 2008-07-20 06:44:43 +0300 | [diff] [blame] | 987 | } else { |
| 988 | data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); |
| 989 | data2 = ath5k_hw_bitswap(0, 2); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 990 | } |
| 991 | |
| 992 | data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; |
| 993 | |
| 994 | ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); |
| 995 | ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); |
| 996 | |
| 997 | return 0; |
| 998 | } |
| 999 | |
| 1000 | /* |
Nick Kossifidis | cc6323c | 2008-07-20 06:44:43 +0300 | [diff] [blame] | 1001 | * Set the channel on the RF2425 |
| 1002 | */ |
| 1003 | static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, |
| 1004 | struct ieee80211_channel *channel) |
| 1005 | { |
| 1006 | u32 data, data0, data2; |
| 1007 | u16 c; |
| 1008 | |
| 1009 | data = data0 = data2 = 0; |
| 1010 | c = channel->center_freq; |
| 1011 | |
| 1012 | if (c < 4800) { |
| 1013 | data0 = ath5k_hw_bitswap((c - 2272), 8); |
| 1014 | data2 = 0; |
| 1015 | /* ? 5GHz ? */ |
| 1016 | } else if ((c - (c % 5)) != 2 || c > 5435) { |
| 1017 | if (!(c % 20) && c < 5120) |
| 1018 | data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); |
| 1019 | else if (!(c % 10)) |
| 1020 | data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); |
| 1021 | else if (!(c % 5)) |
| 1022 | data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); |
| 1023 | else |
| 1024 | return -EINVAL; |
| 1025 | data2 = ath5k_hw_bitswap(1, 2); |
| 1026 | } else { |
| 1027 | data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); |
| 1028 | data2 = ath5k_hw_bitswap(0, 2); |
| 1029 | } |
| 1030 | |
| 1031 | data = (data0 << 4) | data2 << 2 | 0x1001; |
| 1032 | |
| 1033 | ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); |
| 1034 | ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); |
| 1035 | |
| 1036 | return 0; |
| 1037 | } |
| 1038 | |
| 1039 | /* |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1040 | * Set a channel on the radio chip |
| 1041 | */ |
| 1042 | int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) |
| 1043 | { |
| 1044 | int ret; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1045 | /* |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 1046 | * Check bounds supported by the PHY (we don't care about regultory |
| 1047 | * restrictions at this point). Note: hw_value already has the band |
| 1048 | * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() |
| 1049 | * of the band by that */ |
| 1050 | if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1051 | ATH5K_ERR(ah->ah_sc, |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 1052 | "channel frequency (%u MHz) out of supported " |
| 1053 | "band range\n", |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 1054 | channel->center_freq); |
Luis R. Rodriguez | 400ec45 | 2008-02-03 21:51:49 -0500 | [diff] [blame] | 1055 | return -EINVAL; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1056 | } |
| 1057 | |
| 1058 | /* |
| 1059 | * Set the channel and wait |
| 1060 | */ |
| 1061 | switch (ah->ah_radio) { |
| 1062 | case AR5K_RF5110: |
| 1063 | ret = ath5k_hw_rf5110_channel(ah, channel); |
| 1064 | break; |
| 1065 | case AR5K_RF5111: |
| 1066 | ret = ath5k_hw_rf5111_channel(ah, channel); |
| 1067 | break; |
Nick Kossifidis | cc6323c | 2008-07-20 06:44:43 +0300 | [diff] [blame] | 1068 | case AR5K_RF2425: |
| 1069 | ret = ath5k_hw_rf2425_channel(ah, channel); |
| 1070 | break; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1071 | default: |
| 1072 | ret = ath5k_hw_rf5112_channel(ah, channel); |
| 1073 | break; |
| 1074 | } |
| 1075 | |
| 1076 | if (ret) |
| 1077 | return ret; |
| 1078 | |
Nick Kossifidis | cc6323c | 2008-07-20 06:44:43 +0300 | [diff] [blame] | 1079 | /* Set JAPAN setting for channel 14 */ |
| 1080 | if (channel->center_freq == 2484) { |
| 1081 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, |
| 1082 | AR5K_PHY_CCKTXCTL_JAPAN); |
| 1083 | } else { |
| 1084 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, |
| 1085 | AR5K_PHY_CCKTXCTL_WORLD); |
| 1086 | } |
| 1087 | |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 1088 | ah->ah_current_channel.center_freq = channel->center_freq; |
| 1089 | ah->ah_current_channel.hw_value = channel->hw_value; |
| 1090 | ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1091 | |
| 1092 | return 0; |
| 1093 | } |
| 1094 | |
| 1095 | /*****************\ |
| 1096 | PHY calibration |
| 1097 | \*****************/ |
| 1098 | |
| 1099 | /** |
| 1100 | * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration |
| 1101 | * |
| 1102 | * @ah: struct ath5k_hw pointer we are operating on |
| 1103 | * @freq: the channel frequency, just used for error logging |
| 1104 | * |
| 1105 | * This function performs a noise floor calibration of the PHY and waits for |
| 1106 | * it to complete. Then the noise floor value is compared to some maximum |
| 1107 | * noise floor we consider valid. |
| 1108 | * |
| 1109 | * Note that this is different from what the madwifi HAL does: it reads the |
| 1110 | * noise floor and afterwards initiates the calibration. Since the noise floor |
| 1111 | * calibration can take some time to finish, depending on the current channel |
| 1112 | * use, that avoids the occasional timeout warnings we are seeing now. |
| 1113 | * |
| 1114 | * See the following link for an Atheros patent on noise floor calibration: |
| 1115 | * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \ |
| 1116 | * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7 |
| 1117 | * |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1118 | * XXX: Since during noise floor calibration antennas are detached according to |
| 1119 | * the patent, we should stop tx queues here. |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1120 | */ |
| 1121 | int |
| 1122 | ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq) |
| 1123 | { |
| 1124 | int ret; |
| 1125 | unsigned int i; |
| 1126 | s32 noise_floor; |
| 1127 | |
| 1128 | /* |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1129 | * Enable noise floor calibration |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1130 | */ |
| 1131 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, |
| 1132 | AR5K_PHY_AGCCTL_NF); |
| 1133 | |
| 1134 | ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, |
| 1135 | AR5K_PHY_AGCCTL_NF, 0, false); |
| 1136 | if (ret) { |
| 1137 | ATH5K_ERR(ah->ah_sc, |
| 1138 | "noise floor calibration timeout (%uMHz)\n", freq); |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1139 | return -EAGAIN; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1140 | } |
| 1141 | |
| 1142 | /* Wait until the noise floor is calibrated and read the value */ |
| 1143 | for (i = 20; i > 0; i--) { |
| 1144 | mdelay(1); |
| 1145 | noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF); |
| 1146 | noise_floor = AR5K_PHY_NF_RVAL(noise_floor); |
| 1147 | if (noise_floor & AR5K_PHY_NF_ACTIVE) { |
| 1148 | noise_floor = AR5K_PHY_NF_AVAL(noise_floor); |
| 1149 | |
| 1150 | if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) |
| 1151 | break; |
| 1152 | } |
| 1153 | } |
| 1154 | |
| 1155 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, |
| 1156 | "noise floor %d\n", noise_floor); |
| 1157 | |
| 1158 | if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { |
| 1159 | ATH5K_ERR(ah->ah_sc, |
| 1160 | "noise floor calibration failed (%uMHz)\n", freq); |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1161 | return -EAGAIN; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1162 | } |
| 1163 | |
| 1164 | ah->ah_noise_floor = noise_floor; |
| 1165 | |
| 1166 | return 0; |
| 1167 | } |
| 1168 | |
| 1169 | /* |
| 1170 | * Perform a PHY calibration on RF5110 |
| 1171 | * -Fix BPSK/QAM Constellation (I/Q correction) |
| 1172 | * -Calculate Noise Floor |
| 1173 | */ |
| 1174 | static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, |
| 1175 | struct ieee80211_channel *channel) |
| 1176 | { |
| 1177 | u32 phy_sig, phy_agc, phy_sat, beacon; |
| 1178 | int ret; |
| 1179 | |
| 1180 | /* |
| 1181 | * Disable beacons and RX/TX queues, wait |
| 1182 | */ |
| 1183 | AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, |
| 1184 | AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); |
| 1185 | beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); |
| 1186 | ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); |
| 1187 | |
Nick Kossifidis | 84e463f | 2008-09-17 03:33:19 +0300 | [diff] [blame] | 1188 | mdelay(2); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1189 | |
| 1190 | /* |
| 1191 | * Set the channel (with AGC turned off) |
| 1192 | */ |
| 1193 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); |
| 1194 | udelay(10); |
| 1195 | ret = ath5k_hw_channel(ah, channel); |
| 1196 | |
| 1197 | /* |
| 1198 | * Activate PHY and wait |
| 1199 | */ |
| 1200 | ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); |
| 1201 | mdelay(1); |
| 1202 | |
| 1203 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); |
| 1204 | |
| 1205 | if (ret) |
| 1206 | return ret; |
| 1207 | |
| 1208 | /* |
| 1209 | * Calibrate the radio chip |
| 1210 | */ |
| 1211 | |
| 1212 | /* Remember normal state */ |
| 1213 | phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); |
| 1214 | phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); |
| 1215 | phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); |
| 1216 | |
| 1217 | /* Update radio registers */ |
| 1218 | ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | |
| 1219 | AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); |
| 1220 | |
| 1221 | ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | |
| 1222 | AR5K_PHY_AGCCOARSE_LO)) | |
| 1223 | AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | |
| 1224 | AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); |
| 1225 | |
| 1226 | ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | |
| 1227 | AR5K_PHY_ADCSAT_THR)) | |
| 1228 | AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | |
| 1229 | AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); |
| 1230 | |
| 1231 | udelay(20); |
| 1232 | |
| 1233 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); |
| 1234 | udelay(10); |
| 1235 | ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); |
| 1236 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); |
| 1237 | |
| 1238 | mdelay(1); |
| 1239 | |
| 1240 | /* |
| 1241 | * Enable calibration and wait until completion |
| 1242 | */ |
| 1243 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); |
| 1244 | |
| 1245 | ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, |
| 1246 | AR5K_PHY_AGCCTL_CAL, 0, false); |
| 1247 | |
| 1248 | /* Reset to normal state */ |
| 1249 | ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); |
| 1250 | ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); |
| 1251 | ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); |
| 1252 | |
| 1253 | if (ret) { |
| 1254 | ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 1255 | channel->center_freq); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1256 | return ret; |
| 1257 | } |
| 1258 | |
Felix Fietkau | 8b0162a | 2008-11-03 11:27:38 +0100 | [diff] [blame] | 1259 | ath5k_hw_noise_floor_calibration(ah, channel->center_freq); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1260 | |
| 1261 | /* |
| 1262 | * Re-enable RX/TX and beacons |
| 1263 | */ |
| 1264 | AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, |
| 1265 | AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210); |
| 1266 | ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); |
| 1267 | |
| 1268 | return 0; |
| 1269 | } |
| 1270 | |
| 1271 | /* |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1272 | * Perform a PHY calibration on RF5111/5112 and newer chips |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1273 | */ |
| 1274 | static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, |
| 1275 | struct ieee80211_channel *channel) |
| 1276 | { |
| 1277 | u32 i_pwr, q_pwr; |
| 1278 | s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1279 | int i; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1280 | ATH5K_TRACE(ah->ah_sc); |
| 1281 | |
Joe Perches | e9010e2 | 2008-03-07 14:21:16 -0800 | [diff] [blame] | 1282 | if (!ah->ah_calibration || |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1283 | ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1284 | goto done; |
| 1285 | |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1286 | /* Calibration has finished, get the results and re-run */ |
| 1287 | for (i = 0; i <= 10; i++) { |
| 1288 | iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); |
| 1289 | i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); |
| 1290 | q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); |
| 1291 | } |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1292 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1293 | i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1294 | q_coffd = q_pwr >> 7; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1295 | |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1296 | /* No correction */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1297 | if (i_coffd == 0 || q_coffd == 0) |
| 1298 | goto done; |
| 1299 | |
| 1300 | i_coff = ((-iq_corr) / i_coffd) & 0x3f; |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1301 | |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1302 | /* Boundary check */ |
| 1303 | if (i_coff > 31) |
| 1304 | i_coff = 31; |
| 1305 | if (i_coff < -32) |
| 1306 | i_coff = -32; |
| 1307 | |
| 1308 | q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f; |
| 1309 | |
| 1310 | /* Boundary check */ |
| 1311 | if (q_coff > 15) |
| 1312 | q_coff = 15; |
| 1313 | if (q_coff < -16) |
| 1314 | q_coff = -16; |
| 1315 | |
| 1316 | /* Commit new I/Q value */ |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1317 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | |
| 1318 | ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); |
| 1319 | |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1320 | /* Re-enable calibration -if we don't we'll commit |
| 1321 | * the same values again and again */ |
| 1322 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, |
| 1323 | AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); |
| 1324 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); |
| 1325 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1326 | done: |
Nick Kossifidis | f860ee2 | 2008-07-20 06:47:12 +0300 | [diff] [blame] | 1327 | |
| 1328 | /* TODO: Separate noise floor calibration from I/Q calibration |
| 1329 | * since noise floor calibration interrupts rx path while I/Q |
| 1330 | * calibration doesn't. We don't need to run noise floor calibration |
| 1331 | * as often as I/Q calibration.*/ |
Luis R. Rodriguez | d8ee398 | 2008-02-03 21:51:04 -0500 | [diff] [blame] | 1332 | ath5k_hw_noise_floor_calibration(ah, channel->center_freq); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1333 | |
Nick Kossifidis | 6f3b414 | 2009-02-09 06:03:41 +0200 | [diff] [blame] | 1334 | /* Initiate a gain_F calibration */ |
| 1335 | ath5k_hw_request_rfgain_probe(ah); |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1336 | |
| 1337 | return 0; |
| 1338 | } |
| 1339 | |
| 1340 | /* |
| 1341 | * Perform a PHY calibration |
| 1342 | */ |
| 1343 | int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, |
| 1344 | struct ieee80211_channel *channel) |
| 1345 | { |
| 1346 | int ret; |
| 1347 | |
| 1348 | if (ah->ah_radio == AR5K_RF5110) |
| 1349 | ret = ath5k_hw_rf5110_calibrate(ah, channel); |
| 1350 | else |
| 1351 | ret = ath5k_hw_rf511x_calibrate(ah, channel); |
| 1352 | |
| 1353 | return ret; |
| 1354 | } |
| 1355 | |
| 1356 | int ath5k_hw_phy_disable(struct ath5k_hw *ah) |
| 1357 | { |
| 1358 | ATH5K_TRACE(ah->ah_sc); |
| 1359 | /*Just a try M.F.*/ |
| 1360 | ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); |
| 1361 | |
| 1362 | return 0; |
| 1363 | } |
| 1364 | |
| 1365 | /********************\ |
| 1366 | Misc PHY functions |
| 1367 | \********************/ |
| 1368 | |
| 1369 | /* |
| 1370 | * Get the PHY Chip revision |
| 1371 | */ |
| 1372 | u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan) |
| 1373 | { |
| 1374 | unsigned int i; |
| 1375 | u32 srev; |
| 1376 | u16 ret; |
| 1377 | |
| 1378 | ATH5K_TRACE(ah->ah_sc); |
| 1379 | |
| 1380 | /* |
| 1381 | * Set the radio chip access register |
| 1382 | */ |
| 1383 | switch (chan) { |
| 1384 | case CHANNEL_2GHZ: |
| 1385 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); |
| 1386 | break; |
| 1387 | case CHANNEL_5GHZ: |
| 1388 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); |
| 1389 | break; |
| 1390 | default: |
| 1391 | return 0; |
| 1392 | } |
| 1393 | |
| 1394 | mdelay(2); |
| 1395 | |
| 1396 | /* ...wait until PHY is ready and read the selected radio revision */ |
| 1397 | ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); |
| 1398 | |
| 1399 | for (i = 0; i < 8; i++) |
| 1400 | ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); |
| 1401 | |
| 1402 | if (ah->ah_version == AR5K_AR5210) { |
| 1403 | srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; |
| 1404 | ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; |
| 1405 | } else { |
| 1406 | srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; |
| 1407 | ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | |
| 1408 | ((srev & 0x0f) << 4), 8); |
| 1409 | } |
| 1410 | |
| 1411 | /* Reset to the 5GHz mode */ |
| 1412 | ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); |
| 1413 | |
| 1414 | return ret; |
| 1415 | } |
| 1416 | |
| 1417 | void /*TODO:Boundary check*/ |
| 1418 | ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant) |
| 1419 | { |
| 1420 | ATH5K_TRACE(ah->ah_sc); |
| 1421 | /*Just a try M.F.*/ |
| 1422 | if (ah->ah_version != AR5K_AR5210) |
| 1423 | ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA); |
| 1424 | } |
| 1425 | |
| 1426 | unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah) |
| 1427 | { |
| 1428 | ATH5K_TRACE(ah->ah_sc); |
| 1429 | /*Just a try M.F.*/ |
| 1430 | if (ah->ah_version != AR5K_AR5210) |
| 1431 | return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); |
| 1432 | |
| 1433 | return false; /*XXX: What do we return for 5210 ?*/ |
| 1434 | } |
| 1435 | |
| 1436 | /* |
| 1437 | * TX power setup |
| 1438 | */ |
| 1439 | |
| 1440 | /* |
| 1441 | * Initialize the tx power table (not fully implemented) |
| 1442 | */ |
| 1443 | static void ath5k_txpower_table(struct ath5k_hw *ah, |
| 1444 | struct ieee80211_channel *channel, s16 max_power) |
| 1445 | { |
| 1446 | unsigned int i, min, max, n; |
| 1447 | u16 txpower, *rates; |
| 1448 | |
| 1449 | rates = ah->ah_txpower.txp_rates; |
| 1450 | |
| 1451 | txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2; |
| 1452 | if (max_power > txpower) |
| 1453 | txpower = max_power > AR5K_TUNE_MAX_TXPOWER ? |
| 1454 | AR5K_TUNE_MAX_TXPOWER : max_power; |
| 1455 | |
| 1456 | for (i = 0; i < AR5K_MAX_RATES; i++) |
| 1457 | rates[i] = txpower; |
| 1458 | |
| 1459 | /* XXX setup target powers by rate */ |
| 1460 | |
| 1461 | ah->ah_txpower.txp_min = rates[7]; |
| 1462 | ah->ah_txpower.txp_max = rates[0]; |
| 1463 | ah->ah_txpower.txp_ofdm = rates[0]; |
| 1464 | |
| 1465 | /* Calculate the power table */ |
| 1466 | n = ARRAY_SIZE(ah->ah_txpower.txp_pcdac); |
| 1467 | min = AR5K_EEPROM_PCDAC_START; |
| 1468 | max = AR5K_EEPROM_PCDAC_STOP; |
| 1469 | for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP) |
| 1470 | ah->ah_txpower.txp_pcdac[i] = |
| 1471 | #ifdef notyet |
| 1472 | min + ((i * (max - min)) / n); |
| 1473 | #else |
| 1474 | min; |
| 1475 | #endif |
| 1476 | } |
| 1477 | |
| 1478 | /* |
| 1479 | * Set transmition power |
| 1480 | */ |
| 1481 | int /*O.K. - txpower_table is unimplemented so this doesn't work*/ |
| 1482 | ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, |
| 1483 | unsigned int txpower) |
| 1484 | { |
| 1485 | bool tpc = ah->ah_txpower.txp_tpc; |
| 1486 | unsigned int i; |
| 1487 | |
| 1488 | ATH5K_TRACE(ah->ah_sc); |
| 1489 | if (txpower > AR5K_TUNE_MAX_TXPOWER) { |
| 1490 | ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); |
| 1491 | return -EINVAL; |
| 1492 | } |
| 1493 | |
Nick Kossifidis | 903b474 | 2008-02-28 14:50:50 -0500 | [diff] [blame] | 1494 | /* |
| 1495 | * RF2413 for some reason can't |
| 1496 | * transmit anything if we call |
| 1497 | * this funtion, so we skip it |
| 1498 | * until we fix txpower. |
Nick Kossifidis | 136bfc7 | 2008-04-16 18:42:48 +0300 | [diff] [blame] | 1499 | * |
| 1500 | * XXX: Assume same for RF2425 |
| 1501 | * to be safe. |
Nick Kossifidis | 903b474 | 2008-02-28 14:50:50 -0500 | [diff] [blame] | 1502 | */ |
Nick Kossifidis | 136bfc7 | 2008-04-16 18:42:48 +0300 | [diff] [blame] | 1503 | if ((ah->ah_radio == AR5K_RF2413) || (ah->ah_radio == AR5K_RF2425)) |
Nick Kossifidis | 903b474 | 2008-02-28 14:50:50 -0500 | [diff] [blame] | 1504 | return 0; |
| 1505 | |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1506 | /* Reset TX power values */ |
| 1507 | memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); |
| 1508 | ah->ah_txpower.txp_tpc = tpc; |
| 1509 | |
| 1510 | /* Initialize TX power table */ |
| 1511 | ath5k_txpower_table(ah, channel, txpower); |
| 1512 | |
| 1513 | /* |
| 1514 | * Write TX power values |
| 1515 | */ |
| 1516 | for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { |
| 1517 | ath5k_hw_reg_write(ah, |
| 1518 | ((((ah->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) | |
| 1519 | (((ah->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff), |
| 1520 | AR5K_PHY_PCDAC_TXPOWER(i)); |
| 1521 | } |
| 1522 | |
| 1523 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | |
| 1524 | AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | |
| 1525 | AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); |
| 1526 | |
| 1527 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | |
| 1528 | AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | |
| 1529 | AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); |
| 1530 | |
| 1531 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | |
| 1532 | AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | |
| 1533 | AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); |
| 1534 | |
| 1535 | ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | |
| 1536 | AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | |
| 1537 | AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); |
| 1538 | |
Joe Perches | e9010e2 | 2008-03-07 14:21:16 -0800 | [diff] [blame] | 1539 | if (ah->ah_txpower.txp_tpc) |
Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame] | 1540 | ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | |
| 1541 | AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); |
| 1542 | else |
| 1543 | ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | |
| 1544 | AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); |
| 1545 | |
| 1546 | return 0; |
| 1547 | } |
| 1548 | |
| 1549 | int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power) |
| 1550 | { |
| 1551 | /*Just a try M.F.*/ |
| 1552 | struct ieee80211_channel *channel = &ah->ah_current_channel; |
| 1553 | |
| 1554 | ATH5K_TRACE(ah->ah_sc); |
| 1555 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, |
| 1556 | "changing txpower to %d\n", power); |
| 1557 | |
| 1558 | return ath5k_hw_txpower(ah, channel, power); |
| 1559 | } |
Nick Kossifidis | c6e387a | 2008-08-29 22:45:39 +0300 | [diff] [blame] | 1560 | |
| 1561 | #undef _ATH5K_PHY |