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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
Russell King68b65f72010-12-22 17:24:39 +00008 * Copyright (C) 2010 ST-Ericsson SA
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070024 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
Chanho Mincb06ff12013-03-27 18:38:11 +090032
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34#define SUPPORT_SYSRQ
35#endif
36
37#include <linux/module.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/sysrq.h>
42#include <linux/device.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
Russell Kinga62c80e2006-01-07 13:52:45 +000047#include <linux/amba/bus.h>
48#include <linux/amba/serial.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000049#include <linux/clk.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090050#include <linux/slab.h>
Russell King68b65f72010-12-22 17:24:39 +000051#include <linux/dmaengine.h>
52#include <linux/dma-mapping.h>
53#include <linux/scatterlist.h>
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +020054#include <linux/delay.h>
Viresh Kumar258aea72012-02-01 16:12:19 +053055#include <linux/types.h>
Matthew Leach32614aa2012-08-28 16:41:28 +010056#include <linux/of.h>
57#include <linux/of_device.h>
Shawn Guo258e0552012-05-06 22:53:35 +080058#include <linux/pinctrl/consumer.h>
Alessandro Rubinicb707062012-06-24 12:46:37 +010059#include <linux/sizes.h>
Linus Walleijde609582012-10-15 13:36:01 +020060#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
62#define UART_NR 14
63
64#define SERIAL_AMBA_MAJOR 204
65#define SERIAL_AMBA_MINOR 64
66#define SERIAL_AMBA_NR UART_NR
67
68#define AMBA_ISR_PASS_LIMIT 256
69
Russell Kingb63d4f02005-11-19 11:10:35 +000070#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
71#define UART_DUMMY_DR_RX (1 << 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -070072
Alessandro Rubini5926a292009-06-04 17:43:04 +010073/* There is by now at least one vendor with differing details, so handle it */
74struct vendor_data {
75 unsigned int ifls;
76 unsigned int fifosize;
Linus Walleijec489aa2010-06-02 08:13:52 +010077 unsigned int lcrh_tx;
78 unsigned int lcrh_rx;
Linus Walleijac3e3fb2010-06-02 20:40:22 +010079 bool oversampling;
Russell King38d62432010-12-22 17:59:16 +000080 bool dma_threshold;
Rajanikanth H.V4fd06902012-03-26 11:17:02 +020081 bool cts_event_workaround;
Alessandro Rubini5926a292009-06-04 17:43:04 +010082};
83
84static struct vendor_data vendor_arm = {
85 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
86 .fifosize = 16,
Linus Walleijec489aa2010-06-02 08:13:52 +010087 .lcrh_tx = UART011_LCRH,
88 .lcrh_rx = UART011_LCRH,
Linus Walleijac3e3fb2010-06-02 20:40:22 +010089 .oversampling = false,
Russell King38d62432010-12-22 17:59:16 +000090 .dma_threshold = false,
Rajanikanth H.V4fd06902012-03-26 11:17:02 +020091 .cts_event_workaround = false,
Alessandro Rubini5926a292009-06-04 17:43:04 +010092};
93
94static struct vendor_data vendor_st = {
95 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
96 .fifosize = 64,
Linus Walleijec489aa2010-06-02 08:13:52 +010097 .lcrh_tx = ST_UART011_LCRH_TX,
98 .lcrh_rx = ST_UART011_LCRH_RX,
Linus Walleijac3e3fb2010-06-02 20:40:22 +010099 .oversampling = true,
Russell King38d62432010-12-22 17:59:16 +0000100 .dma_threshold = true,
Rajanikanth H.V4fd06902012-03-26 11:17:02 +0200101 .cts_event_workaround = true,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102};
103
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +0200104static struct uart_amba_port *amba_ports[UART_NR];
105
Russell King68b65f72010-12-22 17:24:39 +0000106/* Deals with DMA transactions */
Linus Walleijead76f32011-02-24 13:21:08 +0100107
108struct pl011_sgbuf {
109 struct scatterlist sg;
110 char *buf;
111};
112
113struct pl011_dmarx_data {
114 struct dma_chan *chan;
115 struct completion complete;
116 bool use_buf_b;
117 struct pl011_sgbuf sgbuf_a;
118 struct pl011_sgbuf sgbuf_b;
119 dma_cookie_t cookie;
120 bool running;
Chanho Mincb06ff12013-03-27 18:38:11 +0900121 struct timer_list timer;
122 unsigned int last_residue;
123 unsigned long last_jiffies;
124 bool auto_poll_rate;
125 unsigned int poll_rate;
126 unsigned int poll_timeout;
Linus Walleijead76f32011-02-24 13:21:08 +0100127};
128
Russell King68b65f72010-12-22 17:24:39 +0000129struct pl011_dmatx_data {
130 struct dma_chan *chan;
131 struct scatterlist sg;
132 char *buf;
133 bool queued;
134};
135
Russell Kingc19f12b2010-12-22 17:48:26 +0000136/*
137 * We wrap our port structure around the generic uart_port.
138 */
139struct uart_amba_port {
140 struct uart_port port;
141 struct clk *clk;
Linus Walleij78d80c52012-05-23 21:18:46 +0200142 /* Two optional pin states - default & sleep */
143 struct pinctrl *pinctrl;
144 struct pinctrl_state *pins_default;
145 struct pinctrl_state *pins_sleep;
Russell Kingc19f12b2010-12-22 17:48:26 +0000146 const struct vendor_data *vendor;
Russell King68b65f72010-12-22 17:24:39 +0000147 unsigned int dmacr; /* dma control reg */
Russell Kingc19f12b2010-12-22 17:48:26 +0000148 unsigned int im; /* interrupt mask */
149 unsigned int old_status;
Russell Kingffca2b12010-12-22 17:13:05 +0000150 unsigned int fifosize; /* vendor-specific */
Russell Kingc19f12b2010-12-22 17:48:26 +0000151 unsigned int lcrh_tx; /* vendor-specific */
152 unsigned int lcrh_rx; /* vendor-specific */
Shreshtha Kumar Sahud8d8ffa2012-01-18 15:53:59 +0530153 unsigned int old_cr; /* state during shutdown */
Russell Kingc19f12b2010-12-22 17:48:26 +0000154 bool autorts;
155 char type[12];
Russell King68b65f72010-12-22 17:24:39 +0000156#ifdef CONFIG_DMA_ENGINE
157 /* DMA stuff */
Linus Walleijead76f32011-02-24 13:21:08 +0100158 bool using_tx_dma;
159 bool using_rx_dma;
160 struct pl011_dmarx_data dmarx;
Russell King68b65f72010-12-22 17:24:39 +0000161 struct pl011_dmatx_data dmatx;
162#endif
Russell Kingc19f12b2010-12-22 17:48:26 +0000163};
164
Russell King68b65f72010-12-22 17:24:39 +0000165/*
Linus Walleij29772c42011-02-24 13:21:36 +0100166 * Reads up to 256 characters from the FIFO or until it's empty and
167 * inserts them into the TTY layer. Returns the number of characters
168 * read from the FIFO.
169 */
170static int pl011_fifo_to_tty(struct uart_amba_port *uap)
171{
172 u16 status, ch;
173 unsigned int flag, max_count = 256;
174 int fifotaken = 0;
175
176 while (max_count--) {
177 status = readw(uap->port.membase + UART01x_FR);
178 if (status & UART01x_FR_RXFE)
179 break;
180
181 /* Take chars from the FIFO and update status */
182 ch = readw(uap->port.membase + UART01x_DR) |
183 UART_DUMMY_DR_RX;
184 flag = TTY_NORMAL;
185 uap->port.icount.rx++;
186 fifotaken++;
187
188 if (unlikely(ch & UART_DR_ERROR)) {
189 if (ch & UART011_DR_BE) {
190 ch &= ~(UART011_DR_FE | UART011_DR_PE);
191 uap->port.icount.brk++;
192 if (uart_handle_break(&uap->port))
193 continue;
194 } else if (ch & UART011_DR_PE)
195 uap->port.icount.parity++;
196 else if (ch & UART011_DR_FE)
197 uap->port.icount.frame++;
198 if (ch & UART011_DR_OE)
199 uap->port.icount.overrun++;
200
201 ch &= uap->port.read_status_mask;
202
203 if (ch & UART011_DR_BE)
204 flag = TTY_BREAK;
205 else if (ch & UART011_DR_PE)
206 flag = TTY_PARITY;
207 else if (ch & UART011_DR_FE)
208 flag = TTY_FRAME;
209 }
210
211 if (uart_handle_sysrq_char(&uap->port, ch & 255))
212 continue;
213
214 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
215 }
216
217 return fifotaken;
218}
219
220
221/*
Russell King68b65f72010-12-22 17:24:39 +0000222 * All the DMA operation mode stuff goes inside this ifdef.
223 * This assumes that you have a generic DMA device interface,
224 * no custom DMA interfaces are supported.
225 */
226#ifdef CONFIG_DMA_ENGINE
227
228#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
229
Linus Walleijead76f32011-02-24 13:21:08 +0100230static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
231 enum dma_data_direction dir)
232{
Chanho Mincb06ff12013-03-27 18:38:11 +0900233 dma_addr_t dma_addr;
234
235 sg->buf = dma_alloc_coherent(chan->device->dev,
236 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
Linus Walleijead76f32011-02-24 13:21:08 +0100237 if (!sg->buf)
238 return -ENOMEM;
239
Chanho Mincb06ff12013-03-27 18:38:11 +0900240 sg_init_table(&sg->sg, 1);
241 sg_set_page(&sg->sg, phys_to_page(dma_addr),
242 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
243 sg_dma_address(&sg->sg) = dma_addr;
Linus Walleijead76f32011-02-24 13:21:08 +0100244
Linus Walleijead76f32011-02-24 13:21:08 +0100245 return 0;
246}
247
248static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
249 enum dma_data_direction dir)
250{
251 if (sg->buf) {
Chanho Mincb06ff12013-03-27 18:38:11 +0900252 dma_free_coherent(chan->device->dev,
253 PL011_DMA_BUFFER_SIZE, sg->buf,
254 sg_dma_address(&sg->sg));
Linus Walleijead76f32011-02-24 13:21:08 +0100255 }
256}
257
Russell King68b65f72010-12-22 17:24:39 +0000258static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
259{
260 /* DMA is the sole user of the platform data right now */
261 struct amba_pl011_data *plat = uap->port.dev->platform_data;
262 struct dma_slave_config tx_conf = {
263 .dst_addr = uap->port.mapbase + UART01x_DR,
264 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
Vinod Koula485df42011-10-14 10:47:38 +0530265 .direction = DMA_MEM_TO_DEV,
Russell King68b65f72010-12-22 17:24:39 +0000266 .dst_maxburst = uap->fifosize >> 1,
Viresh Kumar258aea72012-02-01 16:12:19 +0530267 .device_fc = false,
Russell King68b65f72010-12-22 17:24:39 +0000268 };
269 struct dma_chan *chan;
270 dma_cap_mask_t mask;
271
272 /* We need platform data */
273 if (!plat || !plat->dma_filter) {
274 dev_info(uap->port.dev, "no DMA platform data\n");
275 return;
276 }
277
Linus Walleijead76f32011-02-24 13:21:08 +0100278 /* Try to acquire a generic DMA engine slave TX channel */
Russell King68b65f72010-12-22 17:24:39 +0000279 dma_cap_zero(mask);
280 dma_cap_set(DMA_SLAVE, mask);
281
282 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
283 if (!chan) {
284 dev_err(uap->port.dev, "no TX DMA channel!\n");
285 return;
286 }
287
288 dmaengine_slave_config(chan, &tx_conf);
289 uap->dmatx.chan = chan;
290
291 dev_info(uap->port.dev, "DMA channel TX %s\n",
292 dma_chan_name(uap->dmatx.chan));
Linus Walleijead76f32011-02-24 13:21:08 +0100293
294 /* Optionally make use of an RX channel as well */
295 if (plat->dma_rx_param) {
296 struct dma_slave_config rx_conf = {
297 .src_addr = uap->port.mapbase + UART01x_DR,
298 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
Vinod Koula485df42011-10-14 10:47:38 +0530299 .direction = DMA_DEV_TO_MEM,
Linus Walleijead76f32011-02-24 13:21:08 +0100300 .src_maxburst = uap->fifosize >> 1,
Viresh Kumar258aea72012-02-01 16:12:19 +0530301 .device_fc = false,
Linus Walleijead76f32011-02-24 13:21:08 +0100302 };
303
304 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
305 if (!chan) {
306 dev_err(uap->port.dev, "no RX DMA channel!\n");
307 return;
308 }
309
310 dmaengine_slave_config(chan, &rx_conf);
311 uap->dmarx.chan = chan;
312
Chanho Mincb06ff12013-03-27 18:38:11 +0900313 if (plat->dma_rx_poll_enable) {
314 /* Set poll rate if specified. */
315 if (plat->dma_rx_poll_rate) {
316 uap->dmarx.auto_poll_rate = false;
317 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
318 } else {
319 /*
320 * 100 ms defaults to poll rate if not
321 * specified. This will be adjusted with
322 * the baud rate at set_termios.
323 */
324 uap->dmarx.auto_poll_rate = true;
325 uap->dmarx.poll_rate = 100;
326 }
327 /* 3 secs defaults poll_timeout if not specified. */
328 if (plat->dma_rx_poll_timeout)
329 uap->dmarx.poll_timeout =
330 plat->dma_rx_poll_timeout;
331 else
332 uap->dmarx.poll_timeout = 3000;
333 } else
334 uap->dmarx.auto_poll_rate = false;
335
Linus Walleijead76f32011-02-24 13:21:08 +0100336 dev_info(uap->port.dev, "DMA channel RX %s\n",
337 dma_chan_name(uap->dmarx.chan));
338 }
Russell King68b65f72010-12-22 17:24:39 +0000339}
340
341#ifndef MODULE
342/*
343 * Stack up the UARTs and let the above initcall be done at device
344 * initcall time, because the serial driver is called as an arch
345 * initcall, and at this time the DMA subsystem is not yet registered.
346 * At this point the driver will switch over to using DMA where desired.
347 */
348struct dma_uap {
349 struct list_head node;
350 struct uart_amba_port *uap;
351};
352
353static LIST_HEAD(pl011_dma_uarts);
354
355static int __init pl011_dma_initcall(void)
356{
357 struct list_head *node, *tmp;
358
359 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
360 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
361 pl011_dma_probe_initcall(dmau->uap);
362 list_del(node);
363 kfree(dmau);
364 }
365 return 0;
366}
367
368device_initcall(pl011_dma_initcall);
369
370static void pl011_dma_probe(struct uart_amba_port *uap)
371{
372 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
373 if (dmau) {
374 dmau->uap = uap;
375 list_add_tail(&dmau->node, &pl011_dma_uarts);
376 }
377}
378#else
379static void pl011_dma_probe(struct uart_amba_port *uap)
380{
381 pl011_dma_probe_initcall(uap);
382}
383#endif
384
385static void pl011_dma_remove(struct uart_amba_port *uap)
386{
387 /* TODO: remove the initcall if it has not yet executed */
388 if (uap->dmatx.chan)
389 dma_release_channel(uap->dmatx.chan);
Linus Walleijead76f32011-02-24 13:21:08 +0100390 if (uap->dmarx.chan)
391 dma_release_channel(uap->dmarx.chan);
Russell King68b65f72010-12-22 17:24:39 +0000392}
393
Russell King68b65f72010-12-22 17:24:39 +0000394/* Forward declare this for the refill routine */
395static int pl011_dma_tx_refill(struct uart_amba_port *uap);
396
397/*
398 * The current DMA TX buffer has been sent.
399 * Try to queue up another DMA buffer.
400 */
401static void pl011_dma_tx_callback(void *data)
402{
403 struct uart_amba_port *uap = data;
404 struct pl011_dmatx_data *dmatx = &uap->dmatx;
405 unsigned long flags;
406 u16 dmacr;
407
408 spin_lock_irqsave(&uap->port.lock, flags);
409 if (uap->dmatx.queued)
410 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
411 DMA_TO_DEVICE);
412
413 dmacr = uap->dmacr;
414 uap->dmacr = dmacr & ~UART011_TXDMAE;
415 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
416
417 /*
418 * If TX DMA was disabled, it means that we've stopped the DMA for
419 * some reason (eg, XOFF received, or we want to send an X-char.)
420 *
421 * Note: we need to be careful here of a potential race between DMA
422 * and the rest of the driver - if the driver disables TX DMA while
423 * a TX buffer completing, we must update the tx queued status to
424 * get further refills (hence we check dmacr).
425 */
426 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
427 uart_circ_empty(&uap->port.state->xmit)) {
428 uap->dmatx.queued = false;
429 spin_unlock_irqrestore(&uap->port.lock, flags);
430 return;
431 }
432
433 if (pl011_dma_tx_refill(uap) <= 0) {
434 /*
435 * We didn't queue a DMA buffer for some reason, but we
436 * have data pending to be sent. Re-enable the TX IRQ.
437 */
438 uap->im |= UART011_TXIM;
439 writew(uap->im, uap->port.membase + UART011_IMSC);
440 }
441 spin_unlock_irqrestore(&uap->port.lock, flags);
442}
443
444/*
445 * Try to refill the TX DMA buffer.
446 * Locking: called with port lock held and IRQs disabled.
447 * Returns:
448 * 1 if we queued up a TX DMA buffer.
449 * 0 if we didn't want to handle this by DMA
450 * <0 on error
451 */
452static int pl011_dma_tx_refill(struct uart_amba_port *uap)
453{
454 struct pl011_dmatx_data *dmatx = &uap->dmatx;
455 struct dma_chan *chan = dmatx->chan;
456 struct dma_device *dma_dev = chan->device;
457 struct dma_async_tx_descriptor *desc;
458 struct circ_buf *xmit = &uap->port.state->xmit;
459 unsigned int count;
460
461 /*
462 * Try to avoid the overhead involved in using DMA if the
463 * transaction fits in the first half of the FIFO, by using
464 * the standard interrupt handling. This ensures that we
465 * issue a uart_write_wakeup() at the appropriate time.
466 */
467 count = uart_circ_chars_pending(xmit);
468 if (count < (uap->fifosize >> 1)) {
469 uap->dmatx.queued = false;
470 return 0;
471 }
472
473 /*
474 * Bodge: don't send the last character by DMA, as this
475 * will prevent XON from notifying us to restart DMA.
476 */
477 count -= 1;
478
479 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
480 if (count > PL011_DMA_BUFFER_SIZE)
481 count = PL011_DMA_BUFFER_SIZE;
482
483 if (xmit->tail < xmit->head)
484 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
485 else {
486 size_t first = UART_XMIT_SIZE - xmit->tail;
487 size_t second = xmit->head;
488
489 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
490 if (second)
491 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
492 }
493
494 dmatx->sg.length = count;
495
496 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
497 uap->dmatx.queued = false;
498 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
499 return -EBUSY;
500 }
501
Alexandre Bounine16052822012-03-08 16:11:18 -0500502 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
Russell King68b65f72010-12-22 17:24:39 +0000503 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
504 if (!desc) {
505 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
506 uap->dmatx.queued = false;
507 /*
508 * If DMA cannot be used right now, we complete this
509 * transaction via IRQ and let the TTY layer retry.
510 */
511 dev_dbg(uap->port.dev, "TX DMA busy\n");
512 return -EBUSY;
513 }
514
515 /* Some data to go along to the callback */
516 desc->callback = pl011_dma_tx_callback;
517 desc->callback_param = uap;
518
519 /* All errors should happen at prepare time */
520 dmaengine_submit(desc);
521
522 /* Fire the DMA transaction */
523 dma_dev->device_issue_pending(chan);
524
525 uap->dmacr |= UART011_TXDMAE;
526 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
527 uap->dmatx.queued = true;
528
529 /*
530 * Now we know that DMA will fire, so advance the ring buffer
531 * with the stuff we just dispatched.
532 */
533 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
534 uap->port.icount.tx += count;
535
536 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
537 uart_write_wakeup(&uap->port);
538
539 return 1;
540}
541
542/*
543 * We received a transmit interrupt without a pending X-char but with
544 * pending characters.
545 * Locking: called with port lock held and IRQs disabled.
546 * Returns:
547 * false if we want to use PIO to transmit
548 * true if we queued a DMA buffer
549 */
550static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
551{
Linus Walleijead76f32011-02-24 13:21:08 +0100552 if (!uap->using_tx_dma)
Russell King68b65f72010-12-22 17:24:39 +0000553 return false;
554
555 /*
556 * If we already have a TX buffer queued, but received a
557 * TX interrupt, it will be because we've just sent an X-char.
558 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
559 */
560 if (uap->dmatx.queued) {
561 uap->dmacr |= UART011_TXDMAE;
562 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
563 uap->im &= ~UART011_TXIM;
564 writew(uap->im, uap->port.membase + UART011_IMSC);
565 return true;
566 }
567
568 /*
569 * We don't have a TX buffer queued, so try to queue one.
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300570 * If we successfully queued a buffer, mask the TX IRQ.
Russell King68b65f72010-12-22 17:24:39 +0000571 */
572 if (pl011_dma_tx_refill(uap) > 0) {
573 uap->im &= ~UART011_TXIM;
574 writew(uap->im, uap->port.membase + UART011_IMSC);
575 return true;
576 }
577 return false;
578}
579
580/*
581 * Stop the DMA transmit (eg, due to received XOFF).
582 * Locking: called with port lock held and IRQs disabled.
583 */
584static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
585{
586 if (uap->dmatx.queued) {
587 uap->dmacr &= ~UART011_TXDMAE;
588 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
589 }
590}
591
592/*
593 * Try to start a DMA transmit, or in the case of an XON/OFF
594 * character queued for send, try to get that character out ASAP.
595 * Locking: called with port lock held and IRQs disabled.
596 * Returns:
597 * false if we want the TX IRQ to be enabled
598 * true if we have a buffer queued
599 */
600static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
601{
602 u16 dmacr;
603
Linus Walleijead76f32011-02-24 13:21:08 +0100604 if (!uap->using_tx_dma)
Russell King68b65f72010-12-22 17:24:39 +0000605 return false;
606
607 if (!uap->port.x_char) {
608 /* no X-char, try to push chars out in DMA mode */
609 bool ret = true;
610
611 if (!uap->dmatx.queued) {
612 if (pl011_dma_tx_refill(uap) > 0) {
613 uap->im &= ~UART011_TXIM;
614 ret = true;
615 } else {
616 uap->im |= UART011_TXIM;
617 ret = false;
618 }
619 writew(uap->im, uap->port.membase + UART011_IMSC);
620 } else if (!(uap->dmacr & UART011_TXDMAE)) {
621 uap->dmacr |= UART011_TXDMAE;
622 writew(uap->dmacr,
623 uap->port.membase + UART011_DMACR);
624 }
625 return ret;
626 }
627
628 /*
629 * We have an X-char to send. Disable DMA to prevent it loading
630 * the TX fifo, and then see if we can stuff it into the FIFO.
631 */
632 dmacr = uap->dmacr;
633 uap->dmacr &= ~UART011_TXDMAE;
634 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
635
636 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
637 /*
638 * No space in the FIFO, so enable the transmit interrupt
639 * so we know when there is space. Note that once we've
640 * loaded the character, we should just re-enable DMA.
641 */
642 return false;
643 }
644
645 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
646 uap->port.icount.tx++;
647 uap->port.x_char = 0;
648
649 /* Success - restore the DMA state */
650 uap->dmacr = dmacr;
651 writew(dmacr, uap->port.membase + UART011_DMACR);
652
653 return true;
654}
655
656/*
657 * Flush the transmit buffer.
658 * Locking: called with port lock held and IRQs disabled.
659 */
660static void pl011_dma_flush_buffer(struct uart_port *port)
661{
662 struct uart_amba_port *uap = (struct uart_amba_port *)port;
663
Linus Walleijead76f32011-02-24 13:21:08 +0100664 if (!uap->using_tx_dma)
Russell King68b65f72010-12-22 17:24:39 +0000665 return;
666
667 /* Avoid deadlock with the DMA engine callback */
668 spin_unlock(&uap->port.lock);
669 dmaengine_terminate_all(uap->dmatx.chan);
670 spin_lock(&uap->port.lock);
671 if (uap->dmatx.queued) {
672 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
673 DMA_TO_DEVICE);
674 uap->dmatx.queued = false;
675 uap->dmacr &= ~UART011_TXDMAE;
676 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
677 }
678}
679
Linus Walleijead76f32011-02-24 13:21:08 +0100680static void pl011_dma_rx_callback(void *data);
681
682static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
683{
684 struct dma_chan *rxchan = uap->dmarx.chan;
Linus Walleijead76f32011-02-24 13:21:08 +0100685 struct pl011_dmarx_data *dmarx = &uap->dmarx;
686 struct dma_async_tx_descriptor *desc;
687 struct pl011_sgbuf *sgbuf;
688
689 if (!rxchan)
690 return -EIO;
691
692 /* Start the RX DMA job */
693 sgbuf = uap->dmarx.use_buf_b ?
694 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
Alexandre Bounine16052822012-03-08 16:11:18 -0500695 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
Vinod Koula485df42011-10-14 10:47:38 +0530696 DMA_DEV_TO_MEM,
Linus Walleijead76f32011-02-24 13:21:08 +0100697 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
698 /*
699 * If the DMA engine is busy and cannot prepare a
700 * channel, no big deal, the driver will fall back
701 * to interrupt mode as a result of this error code.
702 */
703 if (!desc) {
704 uap->dmarx.running = false;
705 dmaengine_terminate_all(rxchan);
706 return -EBUSY;
707 }
708
709 /* Some data to go along to the callback */
710 desc->callback = pl011_dma_rx_callback;
711 desc->callback_param = uap;
712 dmarx->cookie = dmaengine_submit(desc);
713 dma_async_issue_pending(rxchan);
714
715 uap->dmacr |= UART011_RXDMAE;
716 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
717 uap->dmarx.running = true;
718
719 uap->im &= ~UART011_RXIM;
720 writew(uap->im, uap->port.membase + UART011_IMSC);
721
722 return 0;
723}
724
725/*
726 * This is called when either the DMA job is complete, or
727 * the FIFO timeout interrupt occurred. This must be called
728 * with the port spinlock uap->port.lock held.
729 */
730static void pl011_dma_rx_chars(struct uart_amba_port *uap,
731 u32 pending, bool use_buf_b,
732 bool readfifo)
733{
Jiri Slaby05c7cd32013-01-03 15:53:04 +0100734 struct tty_port *port = &uap->port.state->port;
Linus Walleijead76f32011-02-24 13:21:08 +0100735 struct pl011_sgbuf *sgbuf = use_buf_b ?
736 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
Linus Walleijead76f32011-02-24 13:21:08 +0100737 int dma_count = 0;
738 u32 fifotaken = 0; /* only used for vdbg() */
739
Chanho Mincb06ff12013-03-27 18:38:11 +0900740 struct pl011_dmarx_data *dmarx = &uap->dmarx;
741 int dmataken = 0;
742
743 if (uap->dmarx.poll_rate) {
744 /* The data can be taken by polling */
745 dmataken = sgbuf->sg.length - dmarx->last_residue;
746 /* Recalculate the pending size */
747 if (pending >= dmataken)
748 pending -= dmataken;
749 }
750
751 /* Pick the remain data from the DMA */
Linus Walleijead76f32011-02-24 13:21:08 +0100752 if (pending) {
Linus Walleijead76f32011-02-24 13:21:08 +0100753
754 /*
755 * First take all chars in the DMA pipe, then look in the FIFO.
756 * Note that tty_insert_flip_buf() tries to take as many chars
757 * as it can.
758 */
Chanho Mincb06ff12013-03-27 18:38:11 +0900759 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
760 pending);
Linus Walleijead76f32011-02-24 13:21:08 +0100761
762 uap->port.icount.rx += dma_count;
763 if (dma_count < pending)
764 dev_warn(uap->port.dev,
765 "couldn't insert all characters (TTY is full?)\n");
766 }
767
Chanho Mincb06ff12013-03-27 18:38:11 +0900768 /* Reset the last_residue for Rx DMA poll */
769 if (uap->dmarx.poll_rate)
770 dmarx->last_residue = sgbuf->sg.length;
771
Linus Walleijead76f32011-02-24 13:21:08 +0100772 /*
773 * Only continue with trying to read the FIFO if all DMA chars have
774 * been taken first.
775 */
776 if (dma_count == pending && readfifo) {
777 /* Clear any error flags */
778 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
779 uap->port.membase + UART011_ICR);
780
781 /*
782 * If we read all the DMA'd characters, and we had an
Linus Walleij29772c42011-02-24 13:21:36 +0100783 * incomplete buffer, that could be due to an rx error, or
784 * maybe we just timed out. Read any pending chars and check
785 * the error status.
786 *
787 * Error conditions will only occur in the FIFO, these will
788 * trigger an immediate interrupt and stop the DMA job, so we
789 * will always find the error in the FIFO, never in the DMA
790 * buffer.
Linus Walleijead76f32011-02-24 13:21:08 +0100791 */
Linus Walleij29772c42011-02-24 13:21:36 +0100792 fifotaken = pl011_fifo_to_tty(uap);
Linus Walleijead76f32011-02-24 13:21:08 +0100793 }
794
795 spin_unlock(&uap->port.lock);
796 dev_vdbg(uap->port.dev,
797 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
798 dma_count, fifotaken);
Jiri Slaby2e124b42013-01-03 15:53:06 +0100799 tty_flip_buffer_push(port);
Linus Walleijead76f32011-02-24 13:21:08 +0100800 spin_lock(&uap->port.lock);
801}
802
803static void pl011_dma_rx_irq(struct uart_amba_port *uap)
804{
805 struct pl011_dmarx_data *dmarx = &uap->dmarx;
806 struct dma_chan *rxchan = dmarx->chan;
807 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
808 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
809 size_t pending;
810 struct dma_tx_state state;
811 enum dma_status dmastat;
812
813 /*
814 * Pause the transfer so we can trust the current counter,
815 * do this before we pause the PL011 block, else we may
816 * overflow the FIFO.
817 */
818 if (dmaengine_pause(rxchan))
819 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
820 dmastat = rxchan->device->device_tx_status(rxchan,
821 dmarx->cookie, &state);
822 if (dmastat != DMA_PAUSED)
823 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
824
825 /* Disable RX DMA - incoming data will wait in the FIFO */
826 uap->dmacr &= ~UART011_RXDMAE;
827 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
828 uap->dmarx.running = false;
829
830 pending = sgbuf->sg.length - state.residue;
831 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
832 /* Then we terminate the transfer - we now know our residue */
833 dmaengine_terminate_all(rxchan);
834
835 /*
836 * This will take the chars we have so far and insert
837 * into the framework.
838 */
839 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
840
841 /* Switch buffer & re-trigger DMA job */
842 dmarx->use_buf_b = !dmarx->use_buf_b;
843 if (pl011_dma_rx_trigger_dma(uap)) {
844 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
845 "fall back to interrupt mode\n");
846 uap->im |= UART011_RXIM;
847 writew(uap->im, uap->port.membase + UART011_IMSC);
848 }
849}
850
851static void pl011_dma_rx_callback(void *data)
852{
853 struct uart_amba_port *uap = data;
854 struct pl011_dmarx_data *dmarx = &uap->dmarx;
Chanho Min6dc01aa2012-02-20 10:24:40 +0900855 struct dma_chan *rxchan = dmarx->chan;
Linus Walleijead76f32011-02-24 13:21:08 +0100856 bool lastbuf = dmarx->use_buf_b;
Chanho Min6dc01aa2012-02-20 10:24:40 +0900857 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
858 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
859 size_t pending;
860 struct dma_tx_state state;
Linus Walleijead76f32011-02-24 13:21:08 +0100861 int ret;
862
863 /*
864 * This completion interrupt occurs typically when the
865 * RX buffer is totally stuffed but no timeout has yet
866 * occurred. When that happens, we just want the RX
867 * routine to flush out the secondary DMA buffer while
868 * we immediately trigger the next DMA job.
869 */
870 spin_lock_irq(&uap->port.lock);
Chanho Min6dc01aa2012-02-20 10:24:40 +0900871 /*
872 * Rx data can be taken by the UART interrupts during
873 * the DMA irq handler. So we check the residue here.
874 */
875 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
876 pending = sgbuf->sg.length - state.residue;
877 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
878 /* Then we terminate the transfer - we now know our residue */
879 dmaengine_terminate_all(rxchan);
880
Linus Walleijead76f32011-02-24 13:21:08 +0100881 uap->dmarx.running = false;
882 dmarx->use_buf_b = !lastbuf;
883 ret = pl011_dma_rx_trigger_dma(uap);
884
Chanho Min6dc01aa2012-02-20 10:24:40 +0900885 pl011_dma_rx_chars(uap, pending, lastbuf, false);
Linus Walleijead76f32011-02-24 13:21:08 +0100886 spin_unlock_irq(&uap->port.lock);
887 /*
888 * Do this check after we picked the DMA chars so we don't
889 * get some IRQ immediately from RX.
890 */
891 if (ret) {
892 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
893 "fall back to interrupt mode\n");
894 uap->im |= UART011_RXIM;
895 writew(uap->im, uap->port.membase + UART011_IMSC);
896 }
897}
898
899/*
900 * Stop accepting received characters, when we're shutting down or
901 * suspending this port.
902 * Locking: called with port lock held and IRQs disabled.
903 */
904static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
905{
906 /* FIXME. Just disable the DMA enable */
907 uap->dmacr &= ~UART011_RXDMAE;
908 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
909}
Russell King68b65f72010-12-22 17:24:39 +0000910
Chanho Mincb06ff12013-03-27 18:38:11 +0900911/*
912 * Timer handler for Rx DMA polling.
913 * Every polling, It checks the residue in the dma buffer and transfer
914 * data to the tty. Also, last_residue is updated for the next polling.
915 */
916static void pl011_dma_rx_poll(unsigned long args)
917{
918 struct uart_amba_port *uap = (struct uart_amba_port *)args;
919 struct tty_port *port = &uap->port.state->port;
920 struct pl011_dmarx_data *dmarx = &uap->dmarx;
921 struct dma_chan *rxchan = uap->dmarx.chan;
922 unsigned long flags = 0;
923 unsigned int dmataken = 0;
924 unsigned int size = 0;
925 struct pl011_sgbuf *sgbuf;
926 int dma_count;
927 struct dma_tx_state state;
928
929 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
930 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
931 if (likely(state.residue < dmarx->last_residue)) {
932 dmataken = sgbuf->sg.length - dmarx->last_residue;
933 size = dmarx->last_residue - state.residue;
934 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
935 size);
936 if (dma_count == size)
937 dmarx->last_residue = state.residue;
938 dmarx->last_jiffies = jiffies;
939 }
940 tty_flip_buffer_push(port);
941
942 /*
943 * If no data is received in poll_timeout, the driver will fall back
944 * to interrupt mode. We will retrigger DMA at the first interrupt.
945 */
946 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
947 > uap->dmarx.poll_timeout) {
948
949 spin_lock_irqsave(&uap->port.lock, flags);
950 pl011_dma_rx_stop(uap);
951 spin_unlock_irqrestore(&uap->port.lock, flags);
952
953 uap->dmarx.running = false;
954 dmaengine_terminate_all(rxchan);
955 del_timer(&uap->dmarx.timer);
956 } else {
957 mod_timer(&uap->dmarx.timer,
958 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
959 }
960}
961
Russell King68b65f72010-12-22 17:24:39 +0000962static void pl011_dma_startup(struct uart_amba_port *uap)
963{
Linus Walleijead76f32011-02-24 13:21:08 +0100964 int ret;
965
Russell King68b65f72010-12-22 17:24:39 +0000966 if (!uap->dmatx.chan)
967 return;
968
969 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
970 if (!uap->dmatx.buf) {
971 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
972 uap->port.fifosize = uap->fifosize;
973 return;
974 }
975
976 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
977
978 /* The DMA buffer is now the FIFO the TTY subsystem can use */
979 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
Linus Walleijead76f32011-02-24 13:21:08 +0100980 uap->using_tx_dma = true;
Russell King68b65f72010-12-22 17:24:39 +0000981
Linus Walleijead76f32011-02-24 13:21:08 +0100982 if (!uap->dmarx.chan)
983 goto skip_rx;
984
985 /* Allocate and map DMA RX buffers */
986 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
987 DMA_FROM_DEVICE);
988 if (ret) {
989 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
990 "RX buffer A", ret);
991 goto skip_rx;
992 }
993
994 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
995 DMA_FROM_DEVICE);
996 if (ret) {
997 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
998 "RX buffer B", ret);
999 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1000 DMA_FROM_DEVICE);
1001 goto skip_rx;
1002 }
1003
1004 uap->using_rx_dma = true;
1005
1006skip_rx:
Russell King68b65f72010-12-22 17:24:39 +00001007 /* Turn on DMA error (RX/TX will be enabled on demand) */
1008 uap->dmacr |= UART011_DMAONERR;
1009 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
Russell King38d62432010-12-22 17:59:16 +00001010
1011 /*
1012 * ST Micro variants has some specific dma burst threshold
1013 * compensation. Set this to 16 bytes, so burst will only
1014 * be issued above/below 16 bytes.
1015 */
1016 if (uap->vendor->dma_threshold)
1017 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1018 uap->port.membase + ST_UART011_DMAWM);
Linus Walleijead76f32011-02-24 13:21:08 +01001019
1020 if (uap->using_rx_dma) {
1021 if (pl011_dma_rx_trigger_dma(uap))
1022 dev_dbg(uap->port.dev, "could not trigger initial "
1023 "RX DMA job, fall back to interrupt mode\n");
Chanho Mincb06ff12013-03-27 18:38:11 +09001024 if (uap->dmarx.poll_rate) {
1025 init_timer(&(uap->dmarx.timer));
1026 uap->dmarx.timer.function = pl011_dma_rx_poll;
1027 uap->dmarx.timer.data = (unsigned long)uap;
1028 mod_timer(&uap->dmarx.timer,
1029 jiffies +
1030 msecs_to_jiffies(uap->dmarx.poll_rate));
1031 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1032 uap->dmarx.last_jiffies = jiffies;
1033 }
Linus Walleijead76f32011-02-24 13:21:08 +01001034 }
Russell King68b65f72010-12-22 17:24:39 +00001035}
1036
1037static void pl011_dma_shutdown(struct uart_amba_port *uap)
1038{
Linus Walleijead76f32011-02-24 13:21:08 +01001039 if (!(uap->using_tx_dma || uap->using_rx_dma))
Russell King68b65f72010-12-22 17:24:39 +00001040 return;
1041
1042 /* Disable RX and TX DMA */
1043 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1044 barrier();
1045
1046 spin_lock_irq(&uap->port.lock);
1047 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1048 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
1049 spin_unlock_irq(&uap->port.lock);
1050
Linus Walleijead76f32011-02-24 13:21:08 +01001051 if (uap->using_tx_dma) {
1052 /* In theory, this should already be done by pl011_dma_flush_buffer */
1053 dmaengine_terminate_all(uap->dmatx.chan);
1054 if (uap->dmatx.queued) {
1055 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1056 DMA_TO_DEVICE);
1057 uap->dmatx.queued = false;
1058 }
1059
1060 kfree(uap->dmatx.buf);
1061 uap->using_tx_dma = false;
Russell King68b65f72010-12-22 17:24:39 +00001062 }
1063
Linus Walleijead76f32011-02-24 13:21:08 +01001064 if (uap->using_rx_dma) {
1065 dmaengine_terminate_all(uap->dmarx.chan);
1066 /* Clean up the RX DMA */
1067 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1068 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
Chanho Mincb06ff12013-03-27 18:38:11 +09001069 if (uap->dmarx.poll_rate)
1070 del_timer_sync(&uap->dmarx.timer);
Linus Walleijead76f32011-02-24 13:21:08 +01001071 uap->using_rx_dma = false;
1072 }
Russell King68b65f72010-12-22 17:24:39 +00001073}
1074
Linus Walleijead76f32011-02-24 13:21:08 +01001075static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1076{
1077 return uap->using_rx_dma;
1078}
1079
1080static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1081{
1082 return uap->using_rx_dma && uap->dmarx.running;
1083}
1084
Russell King68b65f72010-12-22 17:24:39 +00001085#else
1086/* Blank functions if the DMA engine is not available */
1087static inline void pl011_dma_probe(struct uart_amba_port *uap)
1088{
1089}
1090
1091static inline void pl011_dma_remove(struct uart_amba_port *uap)
1092{
1093}
1094
1095static inline void pl011_dma_startup(struct uart_amba_port *uap)
1096{
1097}
1098
1099static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1100{
1101}
1102
1103static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1104{
1105 return false;
1106}
1107
1108static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1109{
1110}
1111
1112static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1113{
1114 return false;
1115}
1116
Linus Walleijead76f32011-02-24 13:21:08 +01001117static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1118{
1119}
1120
1121static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1122{
1123}
1124
1125static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1126{
1127 return -EIO;
1128}
1129
1130static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1131{
1132 return false;
1133}
1134
1135static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1136{
1137 return false;
1138}
1139
Russell King68b65f72010-12-22 17:24:39 +00001140#define pl011_dma_flush_buffer NULL
1141#endif
1142
Russell Kingb129a8c2005-08-31 10:12:14 +01001143static void pl011_stop_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001144{
1145 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1146
1147 uap->im &= ~UART011_TXIM;
1148 writew(uap->im, uap->port.membase + UART011_IMSC);
Russell King68b65f72010-12-22 17:24:39 +00001149 pl011_dma_tx_stop(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001150}
1151
Russell Kingb129a8c2005-08-31 10:12:14 +01001152static void pl011_start_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153{
1154 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1155
Russell King68b65f72010-12-22 17:24:39 +00001156 if (!pl011_dma_tx_start(uap)) {
1157 uap->im |= UART011_TXIM;
1158 writew(uap->im, uap->port.membase + UART011_IMSC);
1159 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001160}
1161
1162static void pl011_stop_rx(struct uart_port *port)
1163{
1164 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1165
1166 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1167 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1168 writew(uap->im, uap->port.membase + UART011_IMSC);
Linus Walleijead76f32011-02-24 13:21:08 +01001169
1170 pl011_dma_rx_stop(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171}
1172
1173static void pl011_enable_ms(struct uart_port *port)
1174{
1175 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1176
1177 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1178 writew(uap->im, uap->port.membase + UART011_IMSC);
1179}
1180
David Howells7d12e782006-10-05 14:55:46 +01001181static void pl011_rx_chars(struct uart_amba_port *uap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001182{
Linus Walleij29772c42011-02-24 13:21:36 +01001183 pl011_fifo_to_tty(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001184
Thomas Gleixner2389b272007-05-29 21:53:50 +01001185 spin_unlock(&uap->port.lock);
Jiri Slaby2e124b42013-01-03 15:53:06 +01001186 tty_flip_buffer_push(&uap->port.state->port);
Linus Walleijead76f32011-02-24 13:21:08 +01001187 /*
1188 * If we were temporarily out of DMA mode for a while,
1189 * attempt to switch back to DMA mode again.
1190 */
1191 if (pl011_dma_rx_available(uap)) {
1192 if (pl011_dma_rx_trigger_dma(uap)) {
1193 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1194 "fall back to interrupt mode again\n");
1195 uap->im |= UART011_RXIM;
Chanho Mincb06ff12013-03-27 18:38:11 +09001196 } else {
Linus Walleijead76f32011-02-24 13:21:08 +01001197 uap->im &= ~UART011_RXIM;
Chanho Min89fa28d2013-04-03 11:10:37 +09001198#ifdef CONFIG_DMA_ENGINE
Chanho Mincb06ff12013-03-27 18:38:11 +09001199 /* Start Rx DMA poll */
1200 if (uap->dmarx.poll_rate) {
1201 uap->dmarx.last_jiffies = jiffies;
1202 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1203 mod_timer(&uap->dmarx.timer,
1204 jiffies +
1205 msecs_to_jiffies(uap->dmarx.poll_rate));
1206 }
Chanho Min89fa28d2013-04-03 11:10:37 +09001207#endif
Chanho Mincb06ff12013-03-27 18:38:11 +09001208 }
1209
Linus Walleijead76f32011-02-24 13:21:08 +01001210 writew(uap->im, uap->port.membase + UART011_IMSC);
1211 }
Thomas Gleixner2389b272007-05-29 21:53:50 +01001212 spin_lock(&uap->port.lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213}
1214
1215static void pl011_tx_chars(struct uart_amba_port *uap)
1216{
Alan Coxebd2c8f2009-09-19 13:13:28 -07001217 struct circ_buf *xmit = &uap->port.state->xmit;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218 int count;
1219
1220 if (uap->port.x_char) {
1221 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1222 uap->port.icount.tx++;
1223 uap->port.x_char = 0;
1224 return;
1225 }
1226 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
Russell Kingb129a8c2005-08-31 10:12:14 +01001227 pl011_stop_tx(&uap->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228 return;
1229 }
1230
Russell King68b65f72010-12-22 17:24:39 +00001231 /* If we are using DMA mode, try to send some characters. */
1232 if (pl011_dma_tx_irq(uap))
1233 return;
1234
Russell Kingffca2b12010-12-22 17:13:05 +00001235 count = uap->fifosize >> 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001236 do {
1237 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1238 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1239 uap->port.icount.tx++;
1240 if (uart_circ_empty(xmit))
1241 break;
1242 } while (--count > 0);
1243
1244 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1245 uart_write_wakeup(&uap->port);
1246
1247 if (uart_circ_empty(xmit))
Russell Kingb129a8c2005-08-31 10:12:14 +01001248 pl011_stop_tx(&uap->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249}
1250
1251static void pl011_modem_status(struct uart_amba_port *uap)
1252{
1253 unsigned int status, delta;
1254
1255 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1256
1257 delta = status ^ uap->old_status;
1258 uap->old_status = status;
1259
1260 if (!delta)
1261 return;
1262
1263 if (delta & UART01x_FR_DCD)
1264 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1265
1266 if (delta & UART01x_FR_DSR)
1267 uap->port.icount.dsr++;
1268
1269 if (delta & UART01x_FR_CTS)
1270 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1271
Alan Coxbdc04e32009-09-19 13:13:31 -07001272 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001273}
1274
David Howells7d12e782006-10-05 14:55:46 +01001275static irqreturn_t pl011_int(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001276{
1277 struct uart_amba_port *uap = dev_id;
Russell King963cc982010-12-22 17:16:09 +00001278 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001279 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1280 int handled = 0;
Rajanikanth H.V4fd06902012-03-26 11:17:02 +02001281 unsigned int dummy_read;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001282
Russell King963cc982010-12-22 17:16:09 +00001283 spin_lock_irqsave(&uap->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001284 status = readw(uap->port.membase + UART011_MIS);
1285 if (status) {
1286 do {
Rajanikanth H.V4fd06902012-03-26 11:17:02 +02001287 if (uap->vendor->cts_event_workaround) {
1288 /* workaround to make sure that all bits are unlocked.. */
1289 writew(0x00, uap->port.membase + UART011_ICR);
1290
1291 /*
1292 * WA: introduce 26ns(1 uart clk) delay before W1C;
1293 * single apb access will incur 2 pclk(133.12Mhz) delay,
1294 * so add 2 dummy reads
1295 */
1296 dummy_read = readw(uap->port.membase + UART011_ICR);
1297 dummy_read = readw(uap->port.membase + UART011_ICR);
1298 }
1299
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300 writew(status & ~(UART011_TXIS|UART011_RTIS|
1301 UART011_RXIS),
1302 uap->port.membase + UART011_ICR);
1303
Linus Walleijead76f32011-02-24 13:21:08 +01001304 if (status & (UART011_RTIS|UART011_RXIS)) {
1305 if (pl011_dma_rx_running(uap))
1306 pl011_dma_rx_irq(uap);
1307 else
1308 pl011_rx_chars(uap);
1309 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001310 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1311 UART011_CTSMIS|UART011_RIMIS))
1312 pl011_modem_status(uap);
1313 if (status & UART011_TXIS)
1314 pl011_tx_chars(uap);
1315
Rajanikanth H.V4fd06902012-03-26 11:17:02 +02001316 if (pass_counter-- == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001317 break;
1318
1319 status = readw(uap->port.membase + UART011_MIS);
1320 } while (status != 0);
1321 handled = 1;
1322 }
1323
Russell King963cc982010-12-22 17:16:09 +00001324 spin_unlock_irqrestore(&uap->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001325
1326 return IRQ_RETVAL(handled);
1327}
1328
Linus Walleije643f872012-06-17 15:44:19 +02001329static unsigned int pl011_tx_empty(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330{
1331 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1332 unsigned int status = readw(uap->port.membase + UART01x_FR);
1333 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1334}
1335
Linus Walleije643f872012-06-17 15:44:19 +02001336static unsigned int pl011_get_mctrl(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337{
1338 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1339 unsigned int result = 0;
1340 unsigned int status = readw(uap->port.membase + UART01x_FR);
1341
Jiri Slaby5159f402007-10-18 23:40:31 -07001342#define TIOCMBIT(uartbit, tiocmbit) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001343 if (status & uartbit) \
1344 result |= tiocmbit
1345
Jiri Slaby5159f402007-10-18 23:40:31 -07001346 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1347 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1348 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1349 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1350#undef TIOCMBIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351 return result;
1352}
1353
1354static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1355{
1356 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1357 unsigned int cr;
1358
1359 cr = readw(uap->port.membase + UART011_CR);
1360
Jiri Slaby5159f402007-10-18 23:40:31 -07001361#define TIOCMBIT(tiocmbit, uartbit) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362 if (mctrl & tiocmbit) \
1363 cr |= uartbit; \
1364 else \
1365 cr &= ~uartbit
1366
Jiri Slaby5159f402007-10-18 23:40:31 -07001367 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1368 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1369 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1370 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1371 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
Rabin Vincent3b438162010-02-12 06:43:11 +01001372
1373 if (uap->autorts) {
1374 /* We need to disable auto-RTS if we want to turn RTS off */
1375 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1376 }
Jiri Slaby5159f402007-10-18 23:40:31 -07001377#undef TIOCMBIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001378
1379 writew(cr, uap->port.membase + UART011_CR);
1380}
1381
1382static void pl011_break_ctl(struct uart_port *port, int break_state)
1383{
1384 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1385 unsigned long flags;
1386 unsigned int lcr_h;
1387
1388 spin_lock_irqsave(&uap->port.lock, flags);
Linus Walleijec489aa2010-06-02 08:13:52 +01001389 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390 if (break_state == -1)
1391 lcr_h |= UART01x_LCRH_BRK;
1392 else
1393 lcr_h &= ~UART01x_LCRH_BRK;
Linus Walleijec489aa2010-06-02 08:13:52 +01001394 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001395 spin_unlock_irqrestore(&uap->port.lock, flags);
1396}
1397
Jason Wessel84b5ae12008-02-20 13:33:39 -06001398#ifdef CONFIG_CONSOLE_POLL
Anton Vorontsov5c8124a2012-09-24 14:27:55 -07001399
1400static void pl011_quiesce_irqs(struct uart_port *port)
1401{
1402 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1403 unsigned char __iomem *regs = uap->port.membase;
1404
1405 writew(readw(regs + UART011_MIS), regs + UART011_ICR);
1406 /*
1407 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1408 * we simply mask it. start_tx() will unmask it.
1409 *
1410 * Note we can race with start_tx(), and if the race happens, the
1411 * polling user might get another interrupt just after we clear it.
1412 * But it should be OK and can happen even w/o the race, e.g.
1413 * controller immediately got some new data and raised the IRQ.
1414 *
1415 * And whoever uses polling routines assumes that it manages the device
1416 * (including tx queue), so we're also fine with start_tx()'s caller
1417 * side.
1418 */
1419 writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);
1420}
1421
Linus Walleije643f872012-06-17 15:44:19 +02001422static int pl011_get_poll_char(struct uart_port *port)
Jason Wessel84b5ae12008-02-20 13:33:39 -06001423{
1424 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1425 unsigned int status;
1426
Anton Vorontsov5c8124a2012-09-24 14:27:55 -07001427 /*
1428 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1429 * debugger.
1430 */
1431 pl011_quiesce_irqs(port);
1432
Jason Wesself5316b42010-05-20 21:04:22 -05001433 status = readw(uap->port.membase + UART01x_FR);
1434 if (status & UART01x_FR_RXFE)
1435 return NO_POLL_CHAR;
Jason Wessel84b5ae12008-02-20 13:33:39 -06001436
1437 return readw(uap->port.membase + UART01x_DR);
1438}
1439
Linus Walleije643f872012-06-17 15:44:19 +02001440static void pl011_put_poll_char(struct uart_port *port,
Jason Wessel84b5ae12008-02-20 13:33:39 -06001441 unsigned char ch)
1442{
1443 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1444
1445 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1446 barrier();
1447
1448 writew(ch, uap->port.membase + UART01x_DR);
1449}
1450
1451#endif /* CONFIG_CONSOLE_POLL */
1452
Anton Vorontsovb3564c22012-09-24 14:27:54 -07001453static int pl011_hwinit(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454{
1455 struct uart_amba_port *uap = (struct uart_amba_port *)port;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001456 int retval;
1457
Linus Walleij78d80c52012-05-23 21:18:46 +02001458 /* Optionaly enable pins to be muxed in and configured */
1459 if (!IS_ERR(uap->pins_default)) {
1460 retval = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1461 if (retval)
1462 dev_err(port->dev,
1463 "could not set default pins\n");
1464 }
1465
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466 /*
1467 * Try to enable the clock producer.
1468 */
Julia Lawall1c4c4392012-08-26 18:01:01 +02001469 retval = clk_prepare_enable(uap->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001470 if (retval)
Julia Lawall1c4c4392012-08-26 18:01:01 +02001471 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001472
1473 uap->port.uartclk = clk_get_rate(uap->clk);
1474
Linus Walleij9b96fba2012-03-13 13:27:23 +01001475 /* Clear pending error and receive interrupts */
1476 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
1477 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
1478
Linus Torvalds1da177e2005-04-16 15:20:36 -07001479 /*
Anton Vorontsovb3564c22012-09-24 14:27:54 -07001480 * Save interrupts enable mask, and enable RX interrupts in case if
1481 * the interrupt is used for NMI entry.
1482 */
1483 uap->im = readw(uap->port.membase + UART011_IMSC);
1484 writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);
1485
1486 if (uap->port.dev->platform_data) {
1487 struct amba_pl011_data *plat;
1488
1489 plat = uap->port.dev->platform_data;
1490 if (plat->init)
1491 plat->init();
1492 }
1493 return 0;
1494 out:
1495 return retval;
1496}
1497
1498static int pl011_startup(struct uart_port *port)
1499{
1500 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1501 unsigned int cr;
1502 int retval;
1503
1504 retval = pl011_hwinit(port);
1505 if (retval)
1506 goto clk_dis;
1507
1508 writew(uap->im, uap->port.membase + UART011_IMSC);
1509
1510 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511 * Allocate the IRQ
1512 */
1513 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1514 if (retval)
1515 goto clk_dis;
1516
Russell Kingc19f12b2010-12-22 17:48:26 +00001517 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001518
1519 /*
1520 * Provoke TX FIFO interrupt into asserting.
1521 */
1522 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1523 writew(cr, uap->port.membase + UART011_CR);
1524 writew(0, uap->port.membase + UART011_FBRD);
1525 writew(1, uap->port.membase + UART011_IBRD);
Linus Walleijec489aa2010-06-02 08:13:52 +01001526 writew(0, uap->port.membase + uap->lcrh_rx);
1527 if (uap->lcrh_tx != uap->lcrh_rx) {
1528 int i;
1529 /*
1530 * Wait 10 PCLKs before writing LCRH_TX register,
1531 * to get this delay write read only register 10 times
1532 */
1533 for (i = 0; i < 10; ++i)
1534 writew(0xff, uap->port.membase + UART011_MIS);
1535 writew(0, uap->port.membase + uap->lcrh_tx);
1536 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001537 writew(0, uap->port.membase + UART01x_DR);
1538 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1539 barrier();
1540
Shreshtha Kumar Sahud8d8ffa2012-01-18 15:53:59 +05301541 /* restore RTS and DTR */
1542 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1543 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544 writew(cr, uap->port.membase + UART011_CR);
1545
1546 /*
1547 * initialise the old status of the modem signals
1548 */
1549 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1550
Russell King68b65f72010-12-22 17:24:39 +00001551 /* Startup DMA */
1552 pl011_dma_startup(uap);
1553
Linus Torvalds1da177e2005-04-16 15:20:36 -07001554 /*
Linus Walleijead76f32011-02-24 13:21:08 +01001555 * Finally, enable interrupts, only timeouts when using DMA
1556 * if initial RX DMA job failed, start in interrupt mode
1557 * as well.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001558 */
1559 spin_lock_irq(&uap->port.lock);
Linus Walleij9b96fba2012-03-13 13:27:23 +01001560 /* Clear out any spuriously appearing RX interrupts */
1561 writew(UART011_RTIS | UART011_RXIS,
1562 uap->port.membase + UART011_ICR);
Linus Walleijead76f32011-02-24 13:21:08 +01001563 uap->im = UART011_RTIM;
1564 if (!pl011_dma_rx_running(uap))
1565 uap->im |= UART011_RXIM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001566 writew(uap->im, uap->port.membase + UART011_IMSC);
1567 spin_unlock_irq(&uap->port.lock);
1568
1569 return 0;
1570
1571 clk_dis:
Julia Lawall1c4c4392012-08-26 18:01:01 +02001572 clk_disable_unprepare(uap->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001573 return retval;
1574}
1575
Linus Walleijec489aa2010-06-02 08:13:52 +01001576static void pl011_shutdown_channel(struct uart_amba_port *uap,
1577 unsigned int lcrh)
1578{
1579 unsigned long val;
1580
1581 val = readw(uap->port.membase + lcrh);
1582 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1583 writew(val, uap->port.membase + lcrh);
1584}
1585
Linus Torvalds1da177e2005-04-16 15:20:36 -07001586static void pl011_shutdown(struct uart_port *port)
1587{
1588 struct uart_amba_port *uap = (struct uart_amba_port *)port;
Shreshtha Kumar Sahud8d8ffa2012-01-18 15:53:59 +05301589 unsigned int cr;
Linus Walleij78d80c52012-05-23 21:18:46 +02001590 int retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001591
1592 /*
1593 * disable all interrupts
1594 */
1595 spin_lock_irq(&uap->port.lock);
1596 uap->im = 0;
1597 writew(uap->im, uap->port.membase + UART011_IMSC);
1598 writew(0xffff, uap->port.membase + UART011_ICR);
1599 spin_unlock_irq(&uap->port.lock);
1600
Russell King68b65f72010-12-22 17:24:39 +00001601 pl011_dma_shutdown(uap);
1602
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603 /*
1604 * Free the interrupt
1605 */
1606 free_irq(uap->port.irq, uap);
1607
1608 /*
1609 * disable the port
Shreshtha Kumar Sahud8d8ffa2012-01-18 15:53:59 +05301610 * disable the port. It should not disable RTS and DTR.
1611 * Also RTS and DTR state should be preserved to restore
1612 * it during startup().
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613 */
Rabin Vincent3b438162010-02-12 06:43:11 +01001614 uap->autorts = false;
Shreshtha Kumar Sahud8d8ffa2012-01-18 15:53:59 +05301615 cr = readw(uap->port.membase + UART011_CR);
1616 uap->old_cr = cr;
1617 cr &= UART011_CR_RTS | UART011_CR_DTR;
1618 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1619 writew(cr, uap->port.membase + UART011_CR);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001620
1621 /*
1622 * disable break condition and fifos
1623 */
Linus Walleijec489aa2010-06-02 08:13:52 +01001624 pl011_shutdown_channel(uap, uap->lcrh_rx);
1625 if (uap->lcrh_rx != uap->lcrh_tx)
1626 pl011_shutdown_channel(uap, uap->lcrh_tx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001627
1628 /*
1629 * Shut down the clock producer
1630 */
Julia Lawall1c4c4392012-08-26 18:01:01 +02001631 clk_disable_unprepare(uap->clk);
Linus Walleij78d80c52012-05-23 21:18:46 +02001632 /* Optionally let pins go into sleep states */
1633 if (!IS_ERR(uap->pins_sleep)) {
1634 retval = pinctrl_select_state(uap->pinctrl, uap->pins_sleep);
1635 if (retval)
1636 dev_err(port->dev,
1637 "could not set pins to sleep state\n");
1638 }
1639
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +02001640
1641 if (uap->port.dev->platform_data) {
1642 struct amba_pl011_data *plat;
1643
1644 plat = uap->port.dev->platform_data;
1645 if (plat->exit)
1646 plat->exit();
1647 }
1648
Linus Torvalds1da177e2005-04-16 15:20:36 -07001649}
1650
1651static void
Alan Cox606d0992006-12-08 02:38:45 -08001652pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1653 struct ktermios *old)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001654{
Rabin Vincent3b438162010-02-12 06:43:11 +01001655 struct uart_amba_port *uap = (struct uart_amba_port *)port;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001656 unsigned int lcr_h, old_cr;
1657 unsigned long flags;
Russell Kingc19f12b2010-12-22 17:48:26 +00001658 unsigned int baud, quot, clkdiv;
1659
1660 if (uap->vendor->oversampling)
1661 clkdiv = 8;
1662 else
1663 clkdiv = 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001664
1665 /*
1666 * Ask the core to calculate the divisor for us.
1667 */
Linus Walleijac3e3fb2010-06-02 20:40:22 +01001668 baud = uart_get_baud_rate(port, termios, old, 0,
Russell Kingc19f12b2010-12-22 17:48:26 +00001669 port->uartclk / clkdiv);
Chanho Min89fa28d2013-04-03 11:10:37 +09001670#ifdef CONFIG_DMA_ENGINE
Chanho Mincb06ff12013-03-27 18:38:11 +09001671 /*
1672 * Adjust RX DMA polling rate with baud rate if not specified.
1673 */
1674 if (uap->dmarx.auto_poll_rate)
1675 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
Chanho Min89fa28d2013-04-03 11:10:37 +09001676#endif
Linus Walleijac3e3fb2010-06-02 20:40:22 +01001677
1678 if (baud > port->uartclk/16)
1679 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1680 else
1681 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682
1683 switch (termios->c_cflag & CSIZE) {
1684 case CS5:
1685 lcr_h = UART01x_LCRH_WLEN_5;
1686 break;
1687 case CS6:
1688 lcr_h = UART01x_LCRH_WLEN_6;
1689 break;
1690 case CS7:
1691 lcr_h = UART01x_LCRH_WLEN_7;
1692 break;
1693 default: // CS8
1694 lcr_h = UART01x_LCRH_WLEN_8;
1695 break;
1696 }
1697 if (termios->c_cflag & CSTOPB)
1698 lcr_h |= UART01x_LCRH_STP2;
1699 if (termios->c_cflag & PARENB) {
1700 lcr_h |= UART01x_LCRH_PEN;
1701 if (!(termios->c_cflag & PARODD))
1702 lcr_h |= UART01x_LCRH_EPS;
1703 }
Russell Kingffca2b12010-12-22 17:13:05 +00001704 if (uap->fifosize > 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001705 lcr_h |= UART01x_LCRH_FEN;
1706
1707 spin_lock_irqsave(&port->lock, flags);
1708
1709 /*
1710 * Update the per-port timeout.
1711 */
1712 uart_update_timeout(port, termios->c_cflag, baud);
1713
Russell Kingb63d4f02005-11-19 11:10:35 +00001714 port->read_status_mask = UART011_DR_OE | 255;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001715 if (termios->c_iflag & INPCK)
Russell Kingb63d4f02005-11-19 11:10:35 +00001716 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001717 if (termios->c_iflag & (BRKINT | PARMRK))
Russell Kingb63d4f02005-11-19 11:10:35 +00001718 port->read_status_mask |= UART011_DR_BE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001719
1720 /*
1721 * Characters to ignore
1722 */
1723 port->ignore_status_mask = 0;
1724 if (termios->c_iflag & IGNPAR)
Russell Kingb63d4f02005-11-19 11:10:35 +00001725 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001726 if (termios->c_iflag & IGNBRK) {
Russell Kingb63d4f02005-11-19 11:10:35 +00001727 port->ignore_status_mask |= UART011_DR_BE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001728 /*
1729 * If we're ignoring parity and break indicators,
1730 * ignore overruns too (for real raw support).
1731 */
1732 if (termios->c_iflag & IGNPAR)
Russell Kingb63d4f02005-11-19 11:10:35 +00001733 port->ignore_status_mask |= UART011_DR_OE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001734 }
1735
1736 /*
1737 * Ignore all characters if CREAD is not set.
1738 */
1739 if ((termios->c_cflag & CREAD) == 0)
Russell Kingb63d4f02005-11-19 11:10:35 +00001740 port->ignore_status_mask |= UART_DUMMY_DR_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001741
1742 if (UART_ENABLE_MS(port, termios->c_cflag))
1743 pl011_enable_ms(port);
1744
1745 /* first, disable everything */
1746 old_cr = readw(port->membase + UART011_CR);
1747 writew(0, port->membase + UART011_CR);
1748
Rabin Vincent3b438162010-02-12 06:43:11 +01001749 if (termios->c_cflag & CRTSCTS) {
1750 if (old_cr & UART011_CR_RTS)
1751 old_cr |= UART011_CR_RTSEN;
1752
1753 old_cr |= UART011_CR_CTSEN;
1754 uap->autorts = true;
1755 } else {
1756 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1757 uap->autorts = false;
1758 }
1759
Russell Kingc19f12b2010-12-22 17:48:26 +00001760 if (uap->vendor->oversampling) {
1761 if (baud > port->uartclk / 16)
Linus Walleijac3e3fb2010-06-02 20:40:22 +01001762 old_cr |= ST_UART011_CR_OVSFACT;
1763 else
1764 old_cr &= ~ST_UART011_CR_OVSFACT;
1765 }
1766
Linus Walleijc5dd5532012-09-26 17:21:36 +02001767 /*
1768 * Workaround for the ST Micro oversampling variants to
1769 * increase the bitrate slightly, by lowering the divisor,
1770 * to avoid delayed sampling of start bit at high speeds,
1771 * else we see data corruption.
1772 */
1773 if (uap->vendor->oversampling) {
1774 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1775 quot -= 1;
1776 else if ((baud > 3250000) && (quot > 2))
1777 quot -= 2;
1778 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001779 /* Set baud rate */
1780 writew(quot & 0x3f, port->membase + UART011_FBRD);
1781 writew(quot >> 6, port->membase + UART011_IBRD);
1782
1783 /*
1784 * ----------v----------v----------v----------v-----
Linus Walleijc5dd5532012-09-26 17:21:36 +02001785 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
1786 * UART011_FBRD & UART011_IBRD.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001787 * ----------^----------^----------^----------^-----
1788 */
Linus Walleijec489aa2010-06-02 08:13:52 +01001789 writew(lcr_h, port->membase + uap->lcrh_rx);
1790 if (uap->lcrh_rx != uap->lcrh_tx) {
1791 int i;
1792 /*
1793 * Wait 10 PCLKs before writing LCRH_TX register,
1794 * to get this delay write read only register 10 times
1795 */
1796 for (i = 0; i < 10; ++i)
1797 writew(0xff, uap->port.membase + UART011_MIS);
1798 writew(lcr_h, port->membase + uap->lcrh_tx);
1799 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001800 writew(old_cr, port->membase + UART011_CR);
1801
1802 spin_unlock_irqrestore(&port->lock, flags);
1803}
1804
1805static const char *pl011_type(struct uart_port *port)
1806{
Russell Kinge8a7ba82010-12-28 09:16:54 +00001807 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1808 return uap->port.type == PORT_AMBA ? uap->type : NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001809}
1810
1811/*
1812 * Release the memory region(s) being used by 'port'
1813 */
Linus Walleije643f872012-06-17 15:44:19 +02001814static void pl011_release_port(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001815{
1816 release_mem_region(port->mapbase, SZ_4K);
1817}
1818
1819/*
1820 * Request the memory region(s) being used by 'port'
1821 */
Linus Walleije643f872012-06-17 15:44:19 +02001822static int pl011_request_port(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001823{
1824 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1825 != NULL ? 0 : -EBUSY;
1826}
1827
1828/*
1829 * Configure/autoconfigure the port.
1830 */
Linus Walleije643f872012-06-17 15:44:19 +02001831static void pl011_config_port(struct uart_port *port, int flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001832{
1833 if (flags & UART_CONFIG_TYPE) {
1834 port->type = PORT_AMBA;
Linus Walleije643f872012-06-17 15:44:19 +02001835 pl011_request_port(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001836 }
1837}
1838
1839/*
1840 * verify the new serial_struct (for TIOCSSERIAL).
1841 */
Linus Walleije643f872012-06-17 15:44:19 +02001842static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001843{
1844 int ret = 0;
1845 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1846 ret = -EINVAL;
Yinghai Lua62c4132008-08-19 20:49:55 -07001847 if (ser->irq < 0 || ser->irq >= nr_irqs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001848 ret = -EINVAL;
1849 if (ser->baud_base < 9600)
1850 ret = -EINVAL;
1851 return ret;
1852}
1853
1854static struct uart_ops amba_pl011_pops = {
Linus Walleije643f872012-06-17 15:44:19 +02001855 .tx_empty = pl011_tx_empty,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001856 .set_mctrl = pl011_set_mctrl,
Linus Walleije643f872012-06-17 15:44:19 +02001857 .get_mctrl = pl011_get_mctrl,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001858 .stop_tx = pl011_stop_tx,
1859 .start_tx = pl011_start_tx,
1860 .stop_rx = pl011_stop_rx,
1861 .enable_ms = pl011_enable_ms,
1862 .break_ctl = pl011_break_ctl,
1863 .startup = pl011_startup,
1864 .shutdown = pl011_shutdown,
Russell King68b65f72010-12-22 17:24:39 +00001865 .flush_buffer = pl011_dma_flush_buffer,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001866 .set_termios = pl011_set_termios,
1867 .type = pl011_type,
Linus Walleije643f872012-06-17 15:44:19 +02001868 .release_port = pl011_release_port,
1869 .request_port = pl011_request_port,
1870 .config_port = pl011_config_port,
1871 .verify_port = pl011_verify_port,
Jason Wessel84b5ae12008-02-20 13:33:39 -06001872#ifdef CONFIG_CONSOLE_POLL
Anton Vorontsovb3564c22012-09-24 14:27:54 -07001873 .poll_init = pl011_hwinit,
Linus Walleije643f872012-06-17 15:44:19 +02001874 .poll_get_char = pl011_get_poll_char,
1875 .poll_put_char = pl011_put_poll_char,
Jason Wessel84b5ae12008-02-20 13:33:39 -06001876#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001877};
1878
1879static struct uart_amba_port *amba_ports[UART_NR];
1880
1881#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1882
Russell Kingd3587882006-03-20 20:00:09 +00001883static void pl011_console_putchar(struct uart_port *port, int ch)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001884{
Russell Kingd3587882006-03-20 20:00:09 +00001885 struct uart_amba_port *uap = (struct uart_amba_port *)port;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886
Russell Kingd3587882006-03-20 20:00:09 +00001887 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1888 barrier();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001889 writew(ch, uap->port.membase + UART01x_DR);
1890}
1891
1892static void
1893pl011_console_write(struct console *co, const char *s, unsigned int count)
1894{
1895 struct uart_amba_port *uap = amba_ports[co->index];
1896 unsigned int status, old_cr, new_cr;
Rabin Vincentef605fd2012-01-17 11:52:28 +01001897 unsigned long flags;
1898 int locked = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001899
1900 clk_enable(uap->clk);
1901
Rabin Vincentef605fd2012-01-17 11:52:28 +01001902 local_irq_save(flags);
1903 if (uap->port.sysrq)
1904 locked = 0;
1905 else if (oops_in_progress)
1906 locked = spin_trylock(&uap->port.lock);
1907 else
1908 spin_lock(&uap->port.lock);
1909
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910 /*
1911 * First save the CR then disable the interrupts
1912 */
1913 old_cr = readw(uap->port.membase + UART011_CR);
1914 new_cr = old_cr & ~UART011_CR_CTSEN;
1915 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1916 writew(new_cr, uap->port.membase + UART011_CR);
1917
Russell Kingd3587882006-03-20 20:00:09 +00001918 uart_console_write(&uap->port, s, count, pl011_console_putchar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001919
1920 /*
1921 * Finally, wait for transmitter to become empty
1922 * and restore the TCR
1923 */
1924 do {
1925 status = readw(uap->port.membase + UART01x_FR);
1926 } while (status & UART01x_FR_BUSY);
1927 writew(old_cr, uap->port.membase + UART011_CR);
1928
Rabin Vincentef605fd2012-01-17 11:52:28 +01001929 if (locked)
1930 spin_unlock(&uap->port.lock);
1931 local_irq_restore(flags);
1932
Linus Torvalds1da177e2005-04-16 15:20:36 -07001933 clk_disable(uap->clk);
1934}
1935
1936static void __init
1937pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1938 int *parity, int *bits)
1939{
1940 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1941 unsigned int lcr_h, ibrd, fbrd;
1942
Linus Walleijec489aa2010-06-02 08:13:52 +01001943 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001944
1945 *parity = 'n';
1946 if (lcr_h & UART01x_LCRH_PEN) {
1947 if (lcr_h & UART01x_LCRH_EPS)
1948 *parity = 'e';
1949 else
1950 *parity = 'o';
1951 }
1952
1953 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1954 *bits = 7;
1955 else
1956 *bits = 8;
1957
1958 ibrd = readw(uap->port.membase + UART011_IBRD);
1959 fbrd = readw(uap->port.membase + UART011_FBRD);
1960
1961 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
Linus Walleijac3e3fb2010-06-02 20:40:22 +01001962
Russell Kingc19f12b2010-12-22 17:48:26 +00001963 if (uap->vendor->oversampling) {
Linus Walleijac3e3fb2010-06-02 20:40:22 +01001964 if (readw(uap->port.membase + UART011_CR)
1965 & ST_UART011_CR_OVSFACT)
1966 *baud *= 2;
1967 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001968 }
1969}
1970
1971static int __init pl011_console_setup(struct console *co, char *options)
1972{
1973 struct uart_amba_port *uap;
1974 int baud = 38400;
1975 int bits = 8;
1976 int parity = 'n';
1977 int flow = 'n';
Russell King4b4851c2011-09-22 11:35:30 +01001978 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001979
1980 /*
1981 * Check whether an invalid uart number has been specified, and
1982 * if so, search for the first available port that does have
1983 * console support.
1984 */
1985 if (co->index >= UART_NR)
1986 co->index = 0;
1987 uap = amba_ports[co->index];
Russell Kingd28122a2007-01-22 18:59:42 +00001988 if (!uap)
1989 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001990
Linus Walleij78d80c52012-05-23 21:18:46 +02001991 /* Allow pins to be muxed in and configured */
1992 if (!IS_ERR(uap->pins_default)) {
1993 ret = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1994 if (ret)
1995 dev_err(uap->port.dev,
1996 "could not set default pins\n");
1997 }
1998
Russell King4b4851c2011-09-22 11:35:30 +01001999 ret = clk_prepare(uap->clk);
2000 if (ret)
2001 return ret;
2002
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +02002003 if (uap->port.dev->platform_data) {
2004 struct amba_pl011_data *plat;
2005
2006 plat = uap->port.dev->platform_data;
2007 if (plat->init)
2008 plat->init();
2009 }
2010
Linus Torvalds1da177e2005-04-16 15:20:36 -07002011 uap->port.uartclk = clk_get_rate(uap->clk);
2012
2013 if (options)
2014 uart_parse_options(options, &baud, &parity, &bits, &flow);
2015 else
2016 pl011_console_get_options(uap, &baud, &parity, &bits);
2017
2018 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2019}
2020
Vincent Sanders2d934862005-09-14 22:36:03 +01002021static struct uart_driver amba_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002022static struct console amba_console = {
2023 .name = "ttyAMA",
2024 .write = pl011_console_write,
2025 .device = uart_console_device,
2026 .setup = pl011_console_setup,
2027 .flags = CON_PRINTBUFFER,
2028 .index = -1,
2029 .data = &amba_reg,
2030};
2031
2032#define AMBA_CONSOLE (&amba_console)
2033#else
2034#define AMBA_CONSOLE NULL
2035#endif
2036
2037static struct uart_driver amba_reg = {
2038 .owner = THIS_MODULE,
2039 .driver_name = "ttyAMA",
2040 .dev_name = "ttyAMA",
2041 .major = SERIAL_AMBA_MAJOR,
2042 .minor = SERIAL_AMBA_MINOR,
2043 .nr = UART_NR,
2044 .cons = AMBA_CONSOLE,
2045};
2046
Matthew Leach32614aa2012-08-28 16:41:28 +01002047static int pl011_probe_dt_alias(int index, struct device *dev)
2048{
2049 struct device_node *np;
2050 static bool seen_dev_with_alias = false;
2051 static bool seen_dev_without_alias = false;
2052 int ret = index;
2053
2054 if (!IS_ENABLED(CONFIG_OF))
2055 return ret;
2056
2057 np = dev->of_node;
2058 if (!np)
2059 return ret;
2060
2061 ret = of_alias_get_id(np, "serial");
2062 if (IS_ERR_VALUE(ret)) {
2063 seen_dev_without_alias = true;
2064 ret = index;
2065 } else {
2066 seen_dev_with_alias = true;
2067 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2068 dev_warn(dev, "requested serial port %d not available.\n", ret);
2069 ret = index;
2070 }
2071 }
2072
2073 if (seen_dev_with_alias && seen_dev_without_alias)
2074 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2075
2076 return ret;
2077}
2078
Russell Kingaa25afa2011-02-19 15:55:00 +00002079static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002080{
2081 struct uart_amba_port *uap;
Alessandro Rubini5926a292009-06-04 17:43:04 +01002082 struct vendor_data *vendor = id->data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002083 void __iomem *base;
2084 int i, ret;
2085
2086 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2087 if (amba_ports[i] == NULL)
2088 break;
2089
2090 if (i == ARRAY_SIZE(amba_ports)) {
2091 ret = -EBUSY;
2092 goto out;
2093 }
2094
Linus Walleijde609582012-10-15 13:36:01 +02002095 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2096 GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002097 if (uap == NULL) {
2098 ret = -ENOMEM;
2099 goto out;
2100 }
2101
Matthew Leach32614aa2012-08-28 16:41:28 +01002102 i = pl011_probe_dt_alias(i, &dev->dev);
2103
Linus Walleijde609582012-10-15 13:36:01 +02002104 base = devm_ioremap(&dev->dev, dev->res.start,
2105 resource_size(&dev->res));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002106 if (!base) {
2107 ret = -ENOMEM;
Linus Walleijde609582012-10-15 13:36:01 +02002108 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002109 }
2110
Linus Walleij78d80c52012-05-23 21:18:46 +02002111 uap->pinctrl = devm_pinctrl_get(&dev->dev);
2112 if (IS_ERR(uap->pinctrl)) {
2113 ret = PTR_ERR(uap->pinctrl);
Linus Walleijde609582012-10-15 13:36:01 +02002114 goto out;
Shawn Guo258e0552012-05-06 22:53:35 +08002115 }
Linus Walleij78d80c52012-05-23 21:18:46 +02002116 uap->pins_default = pinctrl_lookup_state(uap->pinctrl,
2117 PINCTRL_STATE_DEFAULT);
2118 if (IS_ERR(uap->pins_default))
2119 dev_err(&dev->dev, "could not get default pinstate\n");
2120
2121 uap->pins_sleep = pinctrl_lookup_state(uap->pinctrl,
2122 PINCTRL_STATE_SLEEP);
2123 if (IS_ERR(uap->pins_sleep))
2124 dev_dbg(&dev->dev, "could not get sleep pinstate\n");
Shawn Guo258e0552012-05-06 22:53:35 +08002125
Linus Walleijde609582012-10-15 13:36:01 +02002126 uap->clk = devm_clk_get(&dev->dev, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002127 if (IS_ERR(uap->clk)) {
2128 ret = PTR_ERR(uap->clk);
Linus Walleijde609582012-10-15 13:36:01 +02002129 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002130 }
2131
Russell Kingc19f12b2010-12-22 17:48:26 +00002132 uap->vendor = vendor;
Linus Walleijec489aa2010-06-02 08:13:52 +01002133 uap->lcrh_rx = vendor->lcrh_rx;
2134 uap->lcrh_tx = vendor->lcrh_tx;
Shreshtha Kumar Sahud8d8ffa2012-01-18 15:53:59 +05302135 uap->old_cr = 0;
Russell Kingffca2b12010-12-22 17:13:05 +00002136 uap->fifosize = vendor->fifosize;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002137 uap->port.dev = &dev->dev;
2138 uap->port.mapbase = dev->res.start;
2139 uap->port.membase = base;
2140 uap->port.iotype = UPIO_MEM;
2141 uap->port.irq = dev->irq[0];
Russell Kingffca2b12010-12-22 17:13:05 +00002142 uap->port.fifosize = uap->fifosize;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002143 uap->port.ops = &amba_pl011_pops;
2144 uap->port.flags = UPF_BOOT_AUTOCONF;
2145 uap->port.line = i;
Russell King68b65f72010-12-22 17:24:39 +00002146 pl011_dma_probe(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002147
Linus Walleijc3d8b762012-03-21 20:15:18 +01002148 /* Ensure interrupts from this UART are masked and cleared */
2149 writew(0, uap->port.membase + UART011_IMSC);
2150 writew(0xffff, uap->port.membase + UART011_ICR);
2151
Russell Kinge8a7ba82010-12-28 09:16:54 +00002152 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2153
Linus Torvalds1da177e2005-04-16 15:20:36 -07002154 amba_ports[i] = uap;
2155
2156 amba_set_drvdata(dev, uap);
2157 ret = uart_add_one_port(&amba_reg, &uap->port);
2158 if (ret) {
2159 amba_set_drvdata(dev, NULL);
2160 amba_ports[i] = NULL;
Russell King68b65f72010-12-22 17:24:39 +00002161 pl011_dma_remove(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002162 }
2163 out:
2164 return ret;
2165}
2166
2167static int pl011_remove(struct amba_device *dev)
2168{
2169 struct uart_amba_port *uap = amba_get_drvdata(dev);
2170 int i;
2171
2172 amba_set_drvdata(dev, NULL);
2173
2174 uart_remove_one_port(&amba_reg, &uap->port);
2175
2176 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2177 if (amba_ports[i] == uap)
2178 amba_ports[i] = NULL;
2179
Russell King68b65f72010-12-22 17:24:39 +00002180 pl011_dma_remove(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002181 return 0;
2182}
2183
Leo Chenb736b892009-07-28 23:43:33 +01002184#ifdef CONFIG_PM
2185static int pl011_suspend(struct amba_device *dev, pm_message_t state)
2186{
2187 struct uart_amba_port *uap = amba_get_drvdata(dev);
2188
2189 if (!uap)
2190 return -EINVAL;
2191
2192 return uart_suspend_port(&amba_reg, &uap->port);
2193}
2194
2195static int pl011_resume(struct amba_device *dev)
2196{
2197 struct uart_amba_port *uap = amba_get_drvdata(dev);
2198
2199 if (!uap)
2200 return -EINVAL;
2201
2202 return uart_resume_port(&amba_reg, &uap->port);
2203}
2204#endif
2205
Russell King2c39c9e2010-07-27 08:50:16 +01002206static struct amba_id pl011_ids[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002207 {
2208 .id = 0x00041011,
2209 .mask = 0x000fffff,
Alessandro Rubini5926a292009-06-04 17:43:04 +01002210 .data = &vendor_arm,
2211 },
2212 {
2213 .id = 0x00380802,
2214 .mask = 0x00ffffff,
2215 .data = &vendor_st,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002216 },
2217 { 0, 0 },
2218};
2219
Dave Martin60f7a332011-10-05 15:15:22 +01002220MODULE_DEVICE_TABLE(amba, pl011_ids);
2221
Linus Torvalds1da177e2005-04-16 15:20:36 -07002222static struct amba_driver pl011_driver = {
2223 .drv = {
2224 .name = "uart-pl011",
2225 },
2226 .id_table = pl011_ids,
2227 .probe = pl011_probe,
2228 .remove = pl011_remove,
Leo Chenb736b892009-07-28 23:43:33 +01002229#ifdef CONFIG_PM
2230 .suspend = pl011_suspend,
2231 .resume = pl011_resume,
2232#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002233};
2234
2235static int __init pl011_init(void)
2236{
2237 int ret;
2238 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2239
2240 ret = uart_register_driver(&amba_reg);
2241 if (ret == 0) {
2242 ret = amba_driver_register(&pl011_driver);
2243 if (ret)
2244 uart_unregister_driver(&amba_reg);
2245 }
2246 return ret;
2247}
2248
2249static void __exit pl011_exit(void)
2250{
2251 amba_driver_unregister(&pl011_driver);
2252 uart_unregister_driver(&amba_reg);
2253}
2254
Alessandro Rubini4dd9e742009-05-05 05:54:13 +01002255/*
2256 * While this can be a module, if builtin it's most likely the console
2257 * So let's leave module_exit but move module_init to an earlier place
2258 */
2259arch_initcall(pl011_init);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002260module_exit(pl011_exit);
2261
2262MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2263MODULE_DESCRIPTION("ARM AMBA serial port driver");
2264MODULE_LICENSE("GPL");