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Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001/* bnx2x.h: Broadcom Everest network driver.
2 *
Eilon Greensteind05c26c2009-01-17 23:26:13 -08003 * Copyright (c) 2007-2009 Broadcom Corporation
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
Eilon Greenstein24e3fce2008-06-12 14:30:28 -07009 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011 * Based on code from Michael Chan's bnx2 driver
12 */
13
14#ifndef BNX2X_H
15#define BNX2X_H
16
Eilon Greenstein34f80b02008-06-23 20:33:01 -070017/* compilation time flags */
18
19/* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21/* #define BNX2X_STOP_ON_ERROR */
22
Eilon Greenstein0c6671b2009-01-14 21:26:51 -080023#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24#define BCM_VLAN 1
25#endif
26
27
Eilon Greenstein555f6c72009-02-12 08:36:11 +000028#define BNX2X_MULTI_QUEUE
29
30#define BNX2X_NEW_NAPI
31
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020032/* error/debug prints */
33
Eilon Greenstein34f80b02008-06-23 20:33:01 -070034#define DRV_MODULE_NAME "bnx2x"
35#define PFX DRV_MODULE_NAME ": "
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020036
37/* for messages that are currently off */
Eilon Greenstein34f80b02008-06-23 20:33:01 -070038#define BNX2X_MSG_OFF 0
39#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
40#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
41#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
42#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
Eliezer Tamirf1410642008-02-28 11:51:50 -080043#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
44#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020045
Eilon Greenstein34f80b02008-06-23 20:33:01 -070046#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020047
48/* regular debug print */
49#define DP(__mask, __fmt, __args...) do { \
50 if (bp->msglevel & (__mask)) \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070051 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
Eilon Greenstein6378c022008-08-13 15:59:25 -070052 bp->dev ? (bp->dev->name) : "?", ##__args); \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070053 } while (0)
54
55/* errors debug print */
56#define BNX2X_DBG_ERR(__fmt, __args...) do { \
57 if (bp->msglevel & NETIF_MSG_PROBE) \
58 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
Eilon Greenstein6378c022008-08-13 15:59:25 -070059 bp->dev ? (bp->dev->name) : "?", ##__args); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020060 } while (0)
61
62/* for errors (never masked) */
63#define BNX2X_ERR(__fmt, __args...) do { \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070064 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
Eilon Greenstein6378c022008-08-13 15:59:25 -070065 bp->dev ? (bp->dev->name) : "?", ##__args); \
Eliezer Tamirf1410642008-02-28 11:51:50 -080066 } while (0)
67
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020068/* before we have a dev->name use dev_info() */
69#define BNX2X_DEV_INFO(__fmt, __args...) do { \
70 if (bp->msglevel & NETIF_MSG_PROBE) \
71 dev_info(&bp->pdev->dev, __fmt, ##__args); \
72 } while (0)
73
74
75#ifdef BNX2X_STOP_ON_ERROR
76#define bnx2x_panic() do { \
77 bp->panic = 1; \
78 BNX2X_ERR("driver assert\n"); \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070079 bnx2x_int_disable(bp); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020080 bnx2x_panic_dump(bp); \
81 } while (0)
82#else
83#define bnx2x_panic() do { \
84 BNX2X_ERR("driver assert\n"); \
85 bnx2x_panic_dump(bp); \
86 } while (0)
87#endif
88
89
Eilon Greenstein34f80b02008-06-23 20:33:01 -070090#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
91#define U64_HI(x) (u32)(((u64)(x)) >> 32)
92#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020093
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020094
Eilon Greenstein34f80b02008-06-23 20:33:01 -070095#define REG_ADDR(bp, offset) (bp->regview + offset)
96
97#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
98#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
99#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
100
101#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200102#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700103#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
104#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200105
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700106#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
107#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200108
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700109#define REG_RD_DMAE(bp, offset, valp, len32) \
110 do { \
111 bnx2x_read_dmae(bp, offset, len32);\
112 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
113 } while (0)
114
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700115#define REG_WR_DMAE(bp, offset, valp, len32) \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200116 do { \
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700117 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200118 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
119 offset, len32); \
120 } while (0)
121
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700122#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
123 offsetof(struct shmem_region, field))
124#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
125#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200126
Eilon Greenstein345b5d52008-08-13 15:58:12 -0700127#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
Eilon Greenstein3196a882008-08-13 15:58:49 -0700128#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200129
130
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700131/* fast path */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200132
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200133struct sw_rx_bd {
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700134 struct sk_buff *skb;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200135 DECLARE_PCI_UNMAP_ADDR(mapping)
136};
137
138struct sw_tx_bd {
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700139 struct sk_buff *skb;
140 u16 first_bd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200141};
142
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700143struct sw_rx_page {
144 struct page *page;
145 DECLARE_PCI_UNMAP_ADDR(mapping)
146};
147
148
149/* MC hsi */
150#define BCM_PAGE_SHIFT 12
151#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
152#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
153#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
154
155#define PAGES_PER_SGE_SHIFT 0
156#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
Eilon Greenstein4f40f2c2009-01-14 21:24:17 -0800157#define SGE_PAGE_SIZE PAGE_SIZE
158#define SGE_PAGE_SHIFT PAGE_SHIFT
159#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN(addr)
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700160
161/* SGE ring related macros */
162#define NUM_RX_SGE_PAGES 2
163#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
164#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
Eilon Greenstein33471622008-08-13 15:59:08 -0700165/* RX_SGE_CNT is promised to be a power of 2 */
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700166#define RX_SGE_MASK (RX_SGE_CNT - 1)
167#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
168#define MAX_RX_SGE (NUM_RX_SGE - 1)
169#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
170 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
171#define RX_SGE(x) ((x) & MAX_RX_SGE)
172
173/* SGE producer mask related macros */
174/* Number of bits in one sge_mask array element */
175#define RX_SGE_MASK_ELEM_SZ 64
176#define RX_SGE_MASK_ELEM_SHIFT 6
177#define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
178
179/* Creates a bitmask of all ones in less significant bits.
180 idx - index of the most significant bit in the created mask */
181#define RX_SGE_ONES_MASK(idx) \
182 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
183#define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
184
185/* Number of u64 elements in SGE mask array */
186#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
187 RX_SGE_MASK_ELEM_SZ)
188#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
189#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
190
191
Eilon Greensteinde832a52009-02-12 08:36:33 +0000192struct bnx2x_eth_q_stats {
193 u32 total_bytes_received_hi;
194 u32 total_bytes_received_lo;
195 u32 total_bytes_transmitted_hi;
196 u32 total_bytes_transmitted_lo;
197 u32 total_unicast_packets_received_hi;
198 u32 total_unicast_packets_received_lo;
199 u32 total_multicast_packets_received_hi;
200 u32 total_multicast_packets_received_lo;
201 u32 total_broadcast_packets_received_hi;
202 u32 total_broadcast_packets_received_lo;
203 u32 total_unicast_packets_transmitted_hi;
204 u32 total_unicast_packets_transmitted_lo;
205 u32 total_multicast_packets_transmitted_hi;
206 u32 total_multicast_packets_transmitted_lo;
207 u32 total_broadcast_packets_transmitted_hi;
208 u32 total_broadcast_packets_transmitted_lo;
209 u32 valid_bytes_received_hi;
210 u32 valid_bytes_received_lo;
211
212 u32 error_bytes_received_hi;
213 u32 error_bytes_received_lo;
214 u32 etherstatsoverrsizepkts_hi;
215 u32 etherstatsoverrsizepkts_lo;
216 u32 no_buff_discard_hi;
217 u32 no_buff_discard_lo;
218
219 u32 driver_xoff;
220 u32 rx_err_discard_pkt;
221 u32 rx_skb_alloc_failed;
222 u32 hw_csum_err;
223};
224
225#define BNX2X_NUM_Q_STATS 11
226#define Q_STATS_OFFSET32(stat_name) \
227 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
228
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200229struct bnx2x_fastpath {
230
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700231 struct napi_struct napi;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200232
233 struct host_status_block *status_blk;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700234 dma_addr_t status_blk_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200235
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700236 struct eth_tx_db_data *hw_tx_prods;
237 dma_addr_t tx_prods_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200238
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700239 struct sw_tx_bd *tx_buf_ring;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200240
241 struct eth_tx_bd *tx_desc_ring;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700242 dma_addr_t tx_desc_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200243
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700244 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
245 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200246
247 struct eth_rx_bd *rx_desc_ring;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700248 dma_addr_t rx_desc_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200249
250 union eth_rx_cqe *rx_comp_ring;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700251 dma_addr_t rx_comp_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200252
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700253 /* SGE ring */
254 struct eth_rx_sge *rx_sge_ring;
255 dma_addr_t rx_sge_mapping;
256
257 u64 sge_mask[RX_SGE_MASK_LEN];
258
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700259 int state;
260#define BNX2X_FP_STATE_CLOSED 0
261#define BNX2X_FP_STATE_IRQ 0x80000
262#define BNX2X_FP_STATE_OPENING 0x90000
263#define BNX2X_FP_STATE_OPEN 0xa0000
264#define BNX2X_FP_STATE_HALTING 0xb0000
265#define BNX2X_FP_STATE_HALTED 0xc0000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200266
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700267 u8 index; /* number in fp array */
268 u8 cl_id; /* eth client id */
269 u8 sb_id; /* status block number in HW */
270#define FP_IDX(fp) (fp->index)
271#define FP_CL_ID(fp) (fp->cl_id)
272#define BP_CL_ID(bp) (bp->fp[0].cl_id)
273#define FP_SB_ID(fp) (fp->sb_id)
274#define CNIC_SB_ID 0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200275
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700276 u16 tx_pkt_prod;
277 u16 tx_pkt_cons;
278 u16 tx_bd_prod;
279 u16 tx_bd_cons;
280 u16 *tx_cons_sb;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200281
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700282 u16 fp_c_idx;
283 u16 fp_u_idx;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200284
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700285 u16 rx_bd_prod;
286 u16 rx_bd_cons;
287 u16 rx_comp_prod;
288 u16 rx_comp_cons;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700289 u16 rx_sge_prod;
290 /* The last maximal completed SGE */
291 u16 last_max_sge;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700292 u16 *rx_cons_sb;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700293 u16 *rx_bd_cons_sb;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200294
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700295 unsigned long tx_pkt,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200296 rx_pkt,
Yitchak Gertner66e855f2008-08-13 15:49:05 -0700297 rx_calls;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700298 /* TPA related */
299 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
300 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
301#define BNX2X_TPA_START 1
302#define BNX2X_TPA_STOP 2
303 u8 disable_tpa;
304#ifdef BNX2X_STOP_ON_ERROR
305 u64 tpa_queue_used;
306#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200307
Eilon Greensteinde832a52009-02-12 08:36:33 +0000308 struct tstorm_per_client_stats old_tclient;
309 struct ustorm_per_client_stats old_uclient;
310 struct xstorm_per_client_stats old_xclient;
311 struct bnx2x_eth_q_stats eth_q_stats;
312
Eilon Greenstein555f6c72009-02-12 08:36:11 +0000313 char name[IFNAMSIZ];
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700314 struct bnx2x *bp; /* parent */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200315};
316
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700317#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700318
Eilon Greenstein237907c2009-01-14 06:42:44 +0000319#define BNX2X_HAS_WORK(fp) (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -0700320
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700321
322/* MC hsi */
323#define MAX_FETCH_BD 13 /* HW max BDs per packet */
324#define RX_COPY_THRESH 92
325
326#define NUM_TX_RINGS 16
327#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
328#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
329#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
330#define MAX_TX_BD (NUM_TX_BD - 1)
331#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
332#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
333 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
334#define TX_BD(x) ((x) & MAX_TX_BD)
335#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
336
337/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
338#define NUM_RX_RINGS 8
339#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
340#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
341#define RX_DESC_MASK (RX_DESC_CNT - 1)
342#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
343#define MAX_RX_BD (NUM_RX_BD - 1)
344#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
345#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
346 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
347#define RX_BD(x) ((x) & MAX_RX_BD)
348
349/* As long as CQE is 4 times bigger than BD entry we have to allocate
350 4 times more pages for CQ ring in order to keep it balanced with
351 BD ring */
352#define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
353#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
354#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
355#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
356#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
357#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
358#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
359 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
360#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
361
362
Eilon Greenstein33471622008-08-13 15:59:08 -0700363/* This is needed for determining of last_max */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700364#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
365
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700366#define __SGE_MASK_SET_BIT(el, bit) \
367 do { \
368 el = ((el) | ((u64)0x1 << (bit))); \
369 } while (0)
370
371#define __SGE_MASK_CLEAR_BIT(el, bit) \
372 do { \
373 el = ((el) & (~((u64)0x1 << (bit)))); \
374 } while (0)
375
376#define SGE_MASK_SET_BIT(fp, idx) \
377 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
378 ((idx) & RX_SGE_MASK_ELEM_MASK))
379
380#define SGE_MASK_CLEAR_BIT(fp, idx) \
381 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
382 ((idx) & RX_SGE_MASK_ELEM_MASK))
383
384
385/* used on a CID received from the HW */
386#define SW_CID(x) (le32_to_cpu(x) & \
387 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
388#define CQE_CMD(x) (le32_to_cpu(x) >> \
389 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
390
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700391#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
392 le32_to_cpu((bd)->addr_lo))
393#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
394
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700395
396#define DPM_TRIGER_TYPE 0x40
397#define DOORBELL(bp, cid, val) \
398 do { \
399 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
400 DPM_TRIGER_TYPE); \
401 } while (0)
402
403
404/* TX CSUM helpers */
405#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
406 skb->csum_offset)
407#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
408 skb->csum_offset))
409
410#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
411
412#define XMIT_PLAIN 0
413#define XMIT_CSUM_V4 0x1
414#define XMIT_CSUM_V6 0x2
415#define XMIT_CSUM_TCP 0x4
416#define XMIT_GSO_V4 0x8
417#define XMIT_GSO_V6 0x10
418
419#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
420#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
421
422
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700423/* stuff added to make the code fit 80Col */
424
425#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
426
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700427#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
428#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
429#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
430 (TPA_TYPE_START | TPA_TYPE_END))
431
Eilon Greenstein1adcd8b2008-08-13 15:48:29 -0700432#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
433
434#define BNX2X_IP_CSUM_ERR(cqe) \
435 (!((cqe)->fast_path_cqe.status_flags & \
436 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
437 ((cqe)->fast_path_cqe.type_error_flags & \
438 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
439
440#define BNX2X_L4_CSUM_ERR(cqe) \
441 (!((cqe)->fast_path_cqe.status_flags & \
442 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
443 ((cqe)->fast_path_cqe.type_error_flags & \
444 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
445
446#define BNX2X_RX_CSUM_OK(cqe) \
447 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700448
449#define BNX2X_RX_SUM_FIX(cqe) \
450 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
451 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
452 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
453
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200454
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700455#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
456#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
457
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700458#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
459#define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
460#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200461
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700462#define BNX2X_RX_SB_INDEX \
463 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200464
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700465#define BNX2X_RX_SB_BD_INDEX \
466 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200467
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700468#define BNX2X_RX_SB_INDEX_NUM \
469 (((U_SB_ETH_RX_CQ_INDEX << \
470 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
471 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
472 ((U_SB_ETH_RX_BD_INDEX << \
473 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
474 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200475
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700476#define BNX2X_TX_SB_INDEX \
477 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200478
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700479
480/* end of fast path */
481
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700482/* common */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200483
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700484struct bnx2x_common {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200485
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700486 u32 chip_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200487/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700488#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200489
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700490#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700491#define CHIP_NUM_57710 0x164e
492#define CHIP_NUM_57711 0x164f
493#define CHIP_NUM_57711E 0x1650
494#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
495#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
496#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
497#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
498 CHIP_IS_57711E(bp))
499#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200500
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700501#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700502#define CHIP_REV_Ax 0x00000000
503/* assume maximum 5 revisions */
504#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
505/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
506#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
507 !(CHIP_REV(bp) & 0x00001000))
508/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
509#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
510 (CHIP_REV(bp) & 0x00001000))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200511
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700512#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
513 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
514
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700515#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
516#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200517
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700518 int flash_size;
519#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
520#define NVRAM_TIMEOUT_COUNT 30000
521#define NVRAM_PAGE_SIZE 256
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200522
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700523 u32 shmem_base;
524
525 u32 hw_config;
Eliezer Tamirf1410642008-02-28 11:51:50 -0800526 u32 board;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200527
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700528 u32 bc_ver;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200529
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700530 char *name;
531};
532
533
534/* end of common */
535
536/* port */
537
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700538struct nig_stats {
539 u32 brb_discard;
540 u32 brb_packet;
541 u32 brb_truncate;
542 u32 flow_ctrl_discard;
543 u32 flow_ctrl_octets;
544 u32 flow_ctrl_packet;
545 u32 mng_discard;
546 u32 mng_octet_inp;
547 u32 mng_octet_out;
548 u32 mng_packet_inp;
549 u32 mng_packet_out;
550 u32 pbf_octets;
551 u32 pbf_packet;
552 u32 safc_inp;
553 u32 egress_mac_pkt0_lo;
554 u32 egress_mac_pkt0_hi;
555 u32 egress_mac_pkt1_lo;
556 u32 egress_mac_pkt1_hi;
557};
558
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700559struct bnx2x_port {
560 u32 pmf;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200561
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700562 u32 link_config;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200563
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700564 u32 supported;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200565/* link settings - missing defines */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700566#define SUPPORTED_2500baseX_Full (1 << 15)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200567
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700568 u32 advertising;
569/* link settings - missing defines */
570#define ADVERTISED_2500baseX_Full (1 << 15)
571
572 u32 phy_addr;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700573
574 /* used to synchronize phy accesses */
575 struct mutex phy_mutex;
576
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700577 u32 port_stx;
578
579 struct nig_stats old_nig_stats;
580};
581
582/* end of port */
583
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700584
585enum bnx2x_stats_event {
586 STATS_EVENT_PMF = 0,
587 STATS_EVENT_LINK_UP,
588 STATS_EVENT_UPDATE,
589 STATS_EVENT_STOP,
590 STATS_EVENT_MAX
591};
592
593enum bnx2x_stats_state {
594 STATS_STATE_DISABLED = 0,
595 STATS_STATE_ENABLED,
596 STATS_STATE_MAX
597};
598
599struct bnx2x_eth_stats {
600 u32 total_bytes_received_hi;
601 u32 total_bytes_received_lo;
602 u32 total_bytes_transmitted_hi;
603 u32 total_bytes_transmitted_lo;
604 u32 total_unicast_packets_received_hi;
605 u32 total_unicast_packets_received_lo;
606 u32 total_multicast_packets_received_hi;
607 u32 total_multicast_packets_received_lo;
608 u32 total_broadcast_packets_received_hi;
609 u32 total_broadcast_packets_received_lo;
610 u32 total_unicast_packets_transmitted_hi;
611 u32 total_unicast_packets_transmitted_lo;
612 u32 total_multicast_packets_transmitted_hi;
613 u32 total_multicast_packets_transmitted_lo;
614 u32 total_broadcast_packets_transmitted_hi;
615 u32 total_broadcast_packets_transmitted_lo;
616 u32 valid_bytes_received_hi;
617 u32 valid_bytes_received_lo;
618
619 u32 error_bytes_received_hi;
620 u32 error_bytes_received_lo;
Eilon Greensteinde832a52009-02-12 08:36:33 +0000621 u32 etherstatsoverrsizepkts_hi;
622 u32 etherstatsoverrsizepkts_lo;
623 u32 no_buff_discard_hi;
624 u32 no_buff_discard_lo;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700625
626 u32 rx_stat_ifhcinbadoctets_hi;
627 u32 rx_stat_ifhcinbadoctets_lo;
628 u32 tx_stat_ifhcoutbadoctets_hi;
629 u32 tx_stat_ifhcoutbadoctets_lo;
630 u32 rx_stat_dot3statsfcserrors_hi;
631 u32 rx_stat_dot3statsfcserrors_lo;
632 u32 rx_stat_dot3statsalignmenterrors_hi;
633 u32 rx_stat_dot3statsalignmenterrors_lo;
634 u32 rx_stat_dot3statscarriersenseerrors_hi;
635 u32 rx_stat_dot3statscarriersenseerrors_lo;
636 u32 rx_stat_falsecarriererrors_hi;
637 u32 rx_stat_falsecarriererrors_lo;
638 u32 rx_stat_etherstatsundersizepkts_hi;
639 u32 rx_stat_etherstatsundersizepkts_lo;
640 u32 rx_stat_dot3statsframestoolong_hi;
641 u32 rx_stat_dot3statsframestoolong_lo;
642 u32 rx_stat_etherstatsfragments_hi;
643 u32 rx_stat_etherstatsfragments_lo;
644 u32 rx_stat_etherstatsjabbers_hi;
645 u32 rx_stat_etherstatsjabbers_lo;
646 u32 rx_stat_maccontrolframesreceived_hi;
647 u32 rx_stat_maccontrolframesreceived_lo;
648 u32 rx_stat_bmac_xpf_hi;
649 u32 rx_stat_bmac_xpf_lo;
650 u32 rx_stat_bmac_xcf_hi;
651 u32 rx_stat_bmac_xcf_lo;
652 u32 rx_stat_xoffstateentered_hi;
653 u32 rx_stat_xoffstateentered_lo;
654 u32 rx_stat_xonpauseframesreceived_hi;
655 u32 rx_stat_xonpauseframesreceived_lo;
656 u32 rx_stat_xoffpauseframesreceived_hi;
657 u32 rx_stat_xoffpauseframesreceived_lo;
658 u32 tx_stat_outxonsent_hi;
659 u32 tx_stat_outxonsent_lo;
660 u32 tx_stat_outxoffsent_hi;
661 u32 tx_stat_outxoffsent_lo;
662 u32 tx_stat_flowcontroldone_hi;
663 u32 tx_stat_flowcontroldone_lo;
664 u32 tx_stat_etherstatscollisions_hi;
665 u32 tx_stat_etherstatscollisions_lo;
666 u32 tx_stat_dot3statssinglecollisionframes_hi;
667 u32 tx_stat_dot3statssinglecollisionframes_lo;
668 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
669 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
670 u32 tx_stat_dot3statsdeferredtransmissions_hi;
671 u32 tx_stat_dot3statsdeferredtransmissions_lo;
672 u32 tx_stat_dot3statsexcessivecollisions_hi;
673 u32 tx_stat_dot3statsexcessivecollisions_lo;
674 u32 tx_stat_dot3statslatecollisions_hi;
675 u32 tx_stat_dot3statslatecollisions_lo;
676 u32 tx_stat_etherstatspkts64octets_hi;
677 u32 tx_stat_etherstatspkts64octets_lo;
678 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
679 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
680 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
681 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
682 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
683 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
684 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
685 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
686 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
687 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
688 u32 tx_stat_etherstatspktsover1522octets_hi;
689 u32 tx_stat_etherstatspktsover1522octets_lo;
690 u32 tx_stat_bmac_2047_hi;
691 u32 tx_stat_bmac_2047_lo;
692 u32 tx_stat_bmac_4095_hi;
693 u32 tx_stat_bmac_4095_lo;
694 u32 tx_stat_bmac_9216_hi;
695 u32 tx_stat_bmac_9216_lo;
696 u32 tx_stat_bmac_16383_hi;
697 u32 tx_stat_bmac_16383_lo;
698 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
699 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
700 u32 tx_stat_bmac_ufl_hi;
701 u32 tx_stat_bmac_ufl_lo;
702
Eilon Greensteinde832a52009-02-12 08:36:33 +0000703 u32 pause_frames_received_hi;
704 u32 pause_frames_received_lo;
705 u32 pause_frames_sent_hi;
706 u32 pause_frames_sent_lo;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700707
708 u32 etherstatspkts1024octetsto1522octets_hi;
709 u32 etherstatspkts1024octetsto1522octets_lo;
710 u32 etherstatspktsover1522octets_hi;
711 u32 etherstatspktsover1522octets_lo;
712
Eilon Greensteinde832a52009-02-12 08:36:33 +0000713 u32 brb_drop_hi;
714 u32 brb_drop_lo;
715 u32 brb_truncate_hi;
716 u32 brb_truncate_lo;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700717
718 u32 mac_filter_discard;
719 u32 xxoverflow_discard;
720 u32 brb_truncate_discard;
721 u32 mac_discard;
722
723 u32 driver_xoff;
Yitchak Gertner66e855f2008-08-13 15:49:05 -0700724 u32 rx_err_discard_pkt;
725 u32 rx_skb_alloc_failed;
726 u32 hw_csum_err;
Eilon Greensteinde832a52009-02-12 08:36:33 +0000727
728 u32 nig_timer_max;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700729};
730
Eilon Greensteinde832a52009-02-12 08:36:33 +0000731#define BNX2X_NUM_STATS 41
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700732#define STATS_OFFSET32(stat_name) \
733 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
734
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700735
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700736#define MAX_CONTEXT 16
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700737
738union cdu_context {
739 struct eth_context eth;
740 char pad[1024];
741};
742
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700743#define MAX_DMAE_C 8
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700744
745/* DMA memory not used in fastpath */
746struct bnx2x_slowpath {
747 union cdu_context context[MAX_CONTEXT];
748 struct eth_stats_query fw_stats;
749 struct mac_configuration_cmd mac_config;
750 struct mac_configuration_cmd mcast_config;
751
752 /* used by dmae command executer */
753 struct dmae_command dmae[MAX_DMAE_C];
754
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700755 u32 stats_comp;
756 union mac_stats mac_stats;
757 struct nig_stats nig_stats;
758 struct host_port_stats port_stats;
759 struct host_func_stats func_stats;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700760
761 u32 wb_comp;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700762 u32 wb_data[4];
763};
764
765#define bnx2x_sp(bp, var) (&bp->slowpath->var)
766#define bnx2x_sp_mapping(bp, var) \
767 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200768
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200769
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700770/* attn group wiring */
771#define MAX_DYNAMIC_ATTN_GRPS 8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200772
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700773struct attn_route {
774 u32 sig[4];
775};
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200776
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700777struct bnx2x {
778 /* Fields used in the tx and intr/napi performance paths
779 * are grouped together in the beginning of the structure
780 */
781 struct bnx2x_fastpath fp[MAX_CONTEXT];
782 void __iomem *regview;
783 void __iomem *doorbells;
Eilon Greensteina5f67a042009-01-14 21:28:13 -0800784#define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200785
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700786 struct net_device *dev;
787 struct pci_dev *pdev;
788
789 atomic_t intr_sem;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700790 struct msix_entry msix_table[MAX_CONTEXT+1];
Eilon Greenstein8badd272009-02-12 08:36:15 +0000791#define INT_MODE_INTx 1
792#define INT_MODE_MSI 2
793#define INT_MODE_MSIX 3
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700794
795 int tx_ring_size;
796
797#ifdef BCM_VLAN
798 struct vlan_group *vlgrp;
799#endif
800
801 u32 rx_csum;
802 u32 rx_offset;
Eilon Greenstein437cf2f2008-09-03 14:38:00 -0700803 u32 rx_buf_size;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700804#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
805#define ETH_MIN_PACKET_SIZE 60
806#define ETH_MAX_PACKET_SIZE 1500
807#define ETH_MAX_JUMBO_PACKET_SIZE 9600
808
Eilon Greenstein0f008462009-02-12 08:36:18 +0000809 /* Max supported alignment is 256 (8 shift) */
810#define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
811 L1_CACHE_SHIFT : 8)
812#define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
813
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700814 struct host_def_status_block *def_status_blk;
815#define DEF_SB_ID 16
816 u16 def_c_idx;
817 u16 def_u_idx;
818 u16 def_x_idx;
819 u16 def_t_idx;
820 u16 def_att_idx;
821 u32 attn_state;
822 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700823 u32 nig_mask;
824
825 /* slow path ring */
826 struct eth_spe *spq;
827 dma_addr_t spq_mapping;
828 u16 spq_prod_idx;
829 struct eth_spe *spq_prod_bd;
830 struct eth_spe *spq_last_bd;
831 u16 *dsb_sp_prod;
832 u16 spq_left; /* serialize spq */
833 /* used to synchronize spq accesses */
834 spinlock_t spq_lock;
835
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700836 /* Flags for marking that there is a STAT_QUERY or
837 SET_MAC ramrod pending */
838 u8 stats_pending;
839 u8 set_mac_pending;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700840
Eilon Greenstein33471622008-08-13 15:59:08 -0700841 /* End of fields used in the performance code paths */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700842
843 int panic;
844 int msglevel;
845
846 u32 flags;
847#define PCIX_FLAG 1
848#define PCI_32BIT_FLAG 2
849#define ONE_TDMA_FLAG 4 /* no longer used */
850#define NO_WOL_FLAG 8
851#define USING_DAC_FLAG 0x10
852#define USING_MSIX_FLAG 0x20
Eilon Greenstein8badd272009-02-12 08:36:15 +0000853#define USING_MSI_FLAG 0x40
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700854#define TPA_ENABLE_FLAG 0x80
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700855#define NO_MCP_FLAG 0x100
856#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
Eilon Greenstein0c6671b2009-01-14 21:26:51 -0800857#define HW_VLAN_TX_FLAG 0x400
858#define HW_VLAN_RX_FLAG 0x800
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700859
860 int func;
861#define BP_PORT(bp) (bp->func % PORT_MAX)
862#define BP_FUNC(bp) (bp->func)
863#define BP_E1HVN(bp) (bp->func >> 1)
864#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700865
866 int pm_cap;
867 int pcie_cap;
868
Eilon Greenstein1cf167f2009-01-14 21:22:18 -0800869 struct delayed_work sp_task;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700870 struct work_struct reset_task;
871
872 struct timer_list timer;
873 int timer_interval;
874 int current_interval;
875
876 u16 fw_seq;
877 u16 fw_drv_pulse_wr_seq;
878 u32 func_stx;
879
880 struct link_params link_params;
881 struct link_vars link_vars;
882
883 struct bnx2x_common common;
884 struct bnx2x_port port;
885
886 u32 mf_config;
887 u16 e1hov;
888 u8 e1hmf;
Eilon Greenstein3196a882008-08-13 15:58:49 -0700889#define IS_E1HMF(bp) (bp->e1hmf != 0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200890
Eliezer Tamirf1410642008-02-28 11:51:50 -0800891 u8 wol;
892
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700893 int rx_ring_size;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200894
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700895 u16 tx_quick_cons_trip_int;
896 u16 tx_quick_cons_trip;
897 u16 tx_ticks_int;
898 u16 tx_ticks;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200899
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700900 u16 rx_quick_cons_trip_int;
901 u16 rx_quick_cons_trip;
902 u16 rx_ticks_int;
903 u16 rx_ticks;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200904
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700905 u32 lin_cnt;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200906
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700907 int state;
908#define BNX2X_STATE_CLOSED 0x0
909#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
910#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200911#define BNX2X_STATE_OPEN 0x3000
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700912#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200913#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
914#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700915#define BNX2X_STATE_DISABLED 0xd000
916#define BNX2X_STATE_DIAG 0xe000
917#define BNX2X_STATE_ERROR 0xf000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200918
Eilon Greenstein555f6c72009-02-12 08:36:11 +0000919 int multi_mode;
920 int num_rx_queues;
921 int num_tx_queues;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200922
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700923 u32 rx_mode;
924#define BNX2X_RX_MODE_NONE 0
925#define BNX2X_RX_MODE_NORMAL 1
926#define BNX2X_RX_MODE_ALLMULTI 2
927#define BNX2X_RX_MODE_PROMISC 3
928#define BNX2X_MAX_MULTICAST 64
929#define BNX2X_MAX_EMUL_MULTI 16
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200930
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700931 dma_addr_t def_status_blk_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200932
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700933 struct bnx2x_slowpath *slowpath;
934 dma_addr_t slowpath_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200935
936#ifdef BCM_ISCSI
937 void *t1;
938 dma_addr_t t1_mapping;
939 void *t2;
940 dma_addr_t t2_mapping;
941 void *timers;
942 dma_addr_t timers_mapping;
943 void *qm;
944 dma_addr_t qm_mapping;
945#endif
946
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700947 int dmae_ready;
948 /* used to synchronize dmae accesses */
949 struct mutex dmae_mutex;
950 struct dmae_command init_dmae;
951
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700952 /* used to synchronize stats collecting */
953 int stats_state;
954 /* used by dmae command loader */
955 struct dmae_command stats_dmae;
956 int executer_idx;
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700957
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700958 u16 stats_counter;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700959 struct bnx2x_eth_stats eth_stats;
960
961 struct z_stream_s *strm;
962 void *gunzip_buf;
963 dma_addr_t gunzip_mapping;
964 int gunzip_outlen;
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700965#define FW_BUF_SIZE 0x8000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200966
967};
968
969
Eilon Greenstein555f6c72009-02-12 08:36:11 +0000970#define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT / E1HVN_MAX) : \
971 MAX_CONTEXT)
972#define BNX2X_NUM_QUEUES(bp) max(bp->num_rx_queues, bp->num_tx_queues)
973#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
Eilon Greenstein3196a882008-08-13 15:58:49 -0700974
Eilon Greenstein555f6c72009-02-12 08:36:11 +0000975#define for_each_rx_queue(bp, var) \
976 for (var = 0; var < bp->num_rx_queues; var++)
977#define for_each_tx_queue(bp, var) \
978 for (var = 0; var < bp->num_tx_queues; var++)
979#define for_each_queue(bp, var) \
980 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
Eilon Greenstein3196a882008-08-13 15:58:49 -0700981#define for_each_nondefault_queue(bp, var) \
Eilon Greenstein555f6c72009-02-12 08:36:11 +0000982 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
Eilon Greenstein3196a882008-08-13 15:58:49 -0700983
984
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700985void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
986void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
987 u32 len32);
Eilon Greenstein17de50b2008-08-13 15:56:59 -0700988int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700989
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700990static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
991 int wait)
992{
993 u32 val;
994
995 do {
996 val = REG_RD(bp, reg);
997 if (val == expected)
998 break;
999 ms -= wait;
1000 msleep(wait);
1001
1002 } while (ms > 0);
1003
1004 return val;
1005}
1006
1007
1008/* load/unload mode */
1009#define LOAD_NORMAL 0
1010#define LOAD_OPEN 1
1011#define LOAD_DIAG 2
1012#define UNLOAD_NORMAL 0
1013#define UNLOAD_CLOSE 1
1014
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001015
Eilon Greensteinad8d3942008-06-23 20:29:02 -07001016/* DMAE command defines */
1017#define DMAE_CMD_SRC_PCI 0
1018#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1019
1020#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1021#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1022
1023#define DMAE_CMD_C_DST_PCI 0
1024#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1025
1026#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1027
1028#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1029#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1030#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1031#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1032
1033#define DMAE_CMD_PORT_0 0
1034#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1035
1036#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1037#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1038#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1039
1040#define DMAE_LEN32_RD_MAX 0x80
1041#define DMAE_LEN32_WR_MAX 0x400
1042
1043#define DMAE_COMP_VAL 0xe0d0d0ae
1044
1045#define MAX_DMAE_C_PER_PORT 8
1046#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1047 BP_E1HVN(bp))
1048#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1049 E1HVN_MAX)
1050
1051
Eliezer Tamir25047952008-02-28 11:50:16 -08001052/* PCIE link and speed */
1053#define PCICFG_LINK_WIDTH 0x1f00000
1054#define PCICFG_LINK_WIDTH_SHIFT 20
1055#define PCICFG_LINK_SPEED 0xf0000
1056#define PCICFG_LINK_SPEED_SHIFT 16
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001057
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001058
Eilon Greensteind3d4f492009-02-12 08:36:27 +00001059#define BNX2X_NUM_TESTS 7
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001060
1061#define BNX2X_MAC_LOOPBACK 0
1062#define BNX2X_PHY_LOOPBACK 1
1063#define BNX2X_MAC_LOOPBACK_FAILED 1
1064#define BNX2X_PHY_LOOPBACK_FAILED 2
1065#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1066 BNX2X_PHY_LOOPBACK_FAILED)
Eliezer Tamir96fc1782008-02-28 11:57:55 -08001067
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001068
1069#define STROM_ASSERT_ARRAY_SIZE 50
1070
Eliezer Tamir96fc1782008-02-28 11:57:55 -08001071
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001072/* must be used on a CID before placing it on a HW ring */
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001073#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001074
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001075#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1076#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1077
1078
1079#define BNX2X_BTR 3
1080#define MAX_SPQ_PENDING 8
1081
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001082
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001083/* CMNG constants
1084 derived from lab experiments, and not from system spec calculations !!! */
1085#define DEF_MIN_RATE 100
1086/* resolution of the rate shaping timer - 100 usec */
1087#define RS_PERIODIC_TIMEOUT_USEC 100
1088/* resolution of fairness algorithm in usecs -
Eilon Greenstein33471622008-08-13 15:59:08 -07001089 coefficient for calculating the actual t fair */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001090#define T_FAIR_COEF 10000000
1091/* number of bytes in single QM arbitration cycle -
Eilon Greenstein33471622008-08-13 15:59:08 -07001092 coefficient for calculating the fairness timer */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001093#define QM_ARB_BYTES 40000
1094#define FAIR_MEM 2
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001095
1096
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001097#define ATTN_NIG_FOR_FUNC (1L << 8)
1098#define ATTN_SW_TIMER_4_FUNC (1L << 9)
1099#define GPIO_2_FUNC (1L << 10)
1100#define GPIO_3_FUNC (1L << 11)
1101#define GPIO_4_FUNC (1L << 12)
1102#define ATTN_GENERAL_ATTN_1 (1L << 13)
1103#define ATTN_GENERAL_ATTN_2 (1L << 14)
1104#define ATTN_GENERAL_ATTN_3 (1L << 15)
1105#define ATTN_GENERAL_ATTN_4 (1L << 13)
1106#define ATTN_GENERAL_ATTN_5 (1L << 14)
1107#define ATTN_GENERAL_ATTN_6 (1L << 15)
1108
1109#define ATTN_HARD_WIRED_MASK 0xff00
1110#define ATTENTION_ID 4
1111
1112
1113/* stuff added to make the code fit 80Col */
1114
1115#define BNX2X_PMF_LINK_ASSERT \
1116 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1117
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001118#define BNX2X_MC_ASSERT_BITS \
1119 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1120 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1121 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1122 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1123
1124#define BNX2X_MCP_ASSERT \
1125 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1126
1127#define BNX2X_DOORQ_ASSERT \
1128 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
1129
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001130#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1131#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1132 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1133 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1134 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1135 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1136 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1137
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001138#define HW_INTERRUT_ASSERT_SET_0 \
1139 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1140 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1141 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1142 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001143#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001144 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1145 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1146 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1147 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1148#define HW_INTERRUT_ASSERT_SET_1 \
1149 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1150 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1151 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1152 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1153 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1154 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1155 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1156 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1157 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1158 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1159 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001160#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001161 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1162 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1163 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1164 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1165 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1166 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1167 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1168 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1169 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1170 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1171#define HW_INTERRUT_ASSERT_SET_2 \
1172 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1173 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1174 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1175 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1176 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001177#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001178 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1179 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1180 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1181 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1182 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1183 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1184
1185
Eilon Greenstein555f6c72009-02-12 08:36:11 +00001186#define MULTI_FLAGS(bp) \
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001187 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1188 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1189 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1190 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
Eilon Greenstein555f6c72009-02-12 08:36:11 +00001191 (bp->multi_mode << \
1192 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001193
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001194#define MULTI_MASK 0x7f
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001195
1196
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001197#define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1198#define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1199#define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1200#define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001201
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001202#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001203
1204#define BNX2X_SP_DSB_INDEX \
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001205(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001206
1207
1208#define CAM_IS_INVALID(x) \
1209(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1210
1211#define CAM_INVALIDATE(x) \
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001212 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001213
1214
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001215/* Number of u32 elements in MC hash array */
1216#define MC_HASH_SIZE 8
1217#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1218 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1219
1220
1221#ifndef PXP2_REG_PXP2_INT_STS
1222#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1223#endif
1224
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001225/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1226
1227#endif /* bnx2x.h */