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Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +01001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * @file op_model_ppro.h
Andi Kleenb9917022008-08-18 14:50:31 +02003 * Family 6 perfmon and architectural perfmon MSR operations
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 *
5 * @remark Copyright 2002 OProfile authors
Andi Kleenb9917022008-08-18 14:50:31 +02006 * @remark Copyright 2008 Intel Corporation
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * @remark Read the file COPYING
8 *
9 * @author John Levon
10 * @author Philippe Elie
11 * @author Graydon Hoare
Andi Kleenb9917022008-08-18 14:50:31 +020012 * @author Andi Kleen
Robert Richter3370d352009-05-25 15:10:32 +020013 * @author Robert Richter <robert.richter@amd.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014 */
15
16#include <linux/oprofile.h>
Andi Kleenb9917022008-08-18 14:50:31 +020017#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <asm/ptrace.h>
19#include <asm/msr.h>
20#include <asm/apic.h>
Don Zickus3e4ff112006-06-26 13:57:01 +020021#include <asm/nmi.h>
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010022
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include "op_x86_model.h"
24#include "op_counter.h"
25
Andi Kleenb9917022008-08-18 14:50:31 +020026static int num_counters = 2;
27static int counter_width = 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Robert Richter3370d352009-05-25 15:10:32 +020029#define MSR_PPRO_EVENTSEL_RESERVED ((0xFFFFFFFFULL<<32)|(1ULL<<21))
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Andi Kleenb9917022008-08-18 14:50:31 +020031static u64 *reset_value;
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010032
Robert Richter83300ce2010-03-23 20:01:54 +010033static void ppro_shutdown(struct op_msrs const * const msrs)
34{
35 int i;
36
37 for (i = 0; i < num_counters; ++i) {
38 if (!msrs->counters[i].addr)
39 continue;
40 release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
41 release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
42 }
43 if (reset_value) {
44 kfree(reset_value);
45 reset_value = NULL;
46 }
47}
48
Robert Richter8617f982010-02-26 17:20:55 +010049static int ppro_fill_in_addresses(struct op_msrs * const msrs)
Linus Torvalds1da177e2005-04-16 15:20:36 -070050{
Don Zickuscb9c4482006-09-26 10:52:26 +020051 int i;
52
Andi Kleenb9917022008-08-18 14:50:31 +020053 for (i = 0; i < num_counters; i++) {
Robert Richterd0e41202010-03-23 19:33:21 +010054 if (!reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
Robert Richter8617f982010-02-26 17:20:55 +010055 goto fail;
Robert Richterd0e41202010-03-23 19:33:21 +010056 if (!reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) {
57 release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
Robert Richter8617f982010-02-26 17:20:55 +010058 goto fail;
Robert Richterd0e41202010-03-23 19:33:21 +010059 }
60 /* both registers must be reserved */
61 msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
62 msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
Robert Richter8617f982010-02-26 17:20:55 +010063 continue;
64 fail:
65 if (!counter_config[i].enabled)
66 continue;
67 op_x86_warn_reserved(i);
68 ppro_shutdown(msrs);
69 return -EBUSY;
Don Zickuscb9c4482006-09-26 10:52:26 +020070 }
Robert Richter8617f982010-02-26 17:20:55 +010071
72 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070073}
74
75
Robert Richteref8828d2009-05-25 19:31:44 +020076static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
77 struct op_msrs const * const msrs)
Linus Torvalds1da177e2005-04-16 15:20:36 -070078{
Robert Richter3370d352009-05-25 15:10:32 +020079 u64 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -070080 int i;
81
Andi Kleenb9917022008-08-18 14:50:31 +020082 if (!reset_value) {
Robert Richterc17c8fb2010-02-25 20:20:25 +010083 reset_value = kzalloc(sizeof(reset_value[0]) * num_counters,
Andi Kleenb9917022008-08-18 14:50:31 +020084 GFP_ATOMIC);
85 if (!reset_value)
86 return;
87 }
88
89 if (cpu_has_arch_perfmon) {
90 union cpuid10_eax eax;
91 eax.full = cpuid_eax(0xa);
Tim Blechmann780eef92009-02-19 17:34:03 +010092
93 /*
94 * For Core2 (family 6, model 15), don't reset the
95 * counter width:
96 */
97 if (!(eax.split.version_id == 0 &&
98 current_cpu_data.x86 == 6 &&
99 current_cpu_data.x86_model == 15)) {
100
101 if (counter_width < eax.split.bit_width)
102 counter_width = eax.split.bit_width;
103 }
Andi Kleenb9917022008-08-18 14:50:31 +0200104 }
105
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106 /* clear all counters */
Robert Richter6e63ea42009-07-07 19:25:39 +0200107 for (i = 0; i < num_counters; ++i) {
Robert Richter8617f982010-02-26 17:20:55 +0100108 if (!msrs->controls[i].addr)
Don Zickuscb9c4482006-09-26 10:52:26 +0200109 continue;
Robert Richter3370d352009-05-25 15:10:32 +0200110 rdmsrl(msrs->controls[i].addr, val);
Robert Richterbb1165d2010-03-01 14:21:23 +0100111 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
Robert Richter98a2e732010-02-23 18:14:58 +0100112 op_x86_warn_in_use(i);
Robert Richter3370d352009-05-25 15:10:32 +0200113 val &= model->reserved;
114 wrmsrl(msrs->controls[i].addr, val);
Robert Richterd0e41202010-03-23 19:33:21 +0100115 /*
116 * avoid a false detection of ctr overflows in NMI *
117 * handler
118 */
Andi Kleenb9917022008-08-18 14:50:31 +0200119 wrmsrl(msrs->counters[i].addr, -1LL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 }
121
122 /* enable active counters */
Andi Kleenb9917022008-08-18 14:50:31 +0200123 for (i = 0; i < num_counters; ++i) {
Robert Richter217d3cf2009-06-04 02:36:44 +0200124 if (counter_config[i].enabled && msrs->counters[i].addr) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 reset_value[i] = counter_config[i].count;
Andi Kleenb9917022008-08-18 14:50:31 +0200126 wrmsrl(msrs->counters[i].addr, -reset_value[i]);
Robert Richter3370d352009-05-25 15:10:32 +0200127 rdmsrl(msrs->controls[i].addr, val);
128 val &= model->reserved;
129 val |= op_x86_get_ctrl(model, &counter_config[i]);
130 wrmsrl(msrs->controls[i].addr, val);
Don Zickuscb9c4482006-09-26 10:52:26 +0200131 } else {
132 reset_value[i] = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133 }
134 }
135}
136
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100137
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138static int ppro_check_ctrs(struct pt_regs * const regs,
139 struct op_msrs const * const msrs)
140{
Andi Kleen7c64ade2008-11-07 14:02:49 +0100141 u64 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142 int i;
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100143
Ingo Molnar82aa9a12009-02-05 15:23:08 +0100144 /*
145 * This can happen if perf counters are in use when
146 * we steal the die notifier NMI.
147 */
148 if (unlikely(!reset_value))
149 goto out;
150
Robert Richter6e63ea42009-07-07 19:25:39 +0200151 for (i = 0; i < num_counters; ++i) {
Don Zickuscb9c4482006-09-26 10:52:26 +0200152 if (!reset_value[i])
153 continue;
Andi Kleen7c64ade2008-11-07 14:02:49 +0100154 rdmsrl(msrs->counters[i].addr, val);
Robert Richter42399ad2009-05-25 17:59:06 +0200155 if (val & (1ULL << (counter_width - 1)))
156 continue;
157 oprofile_add_sample(regs, i);
158 wrmsrl(msrs->counters[i].addr, -reset_value[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159 }
160
Ingo Molnar82aa9a12009-02-05 15:23:08 +0100161out:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162 /* Only P6 based Pentium M need to re-unmask the apic vector but it
163 * doesn't hurt other P6 variant */
164 apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
165
166 /* We can't work out if we really handled an interrupt. We
167 * might have caught a *second* counter just after overflowing
168 * the interrupt for this counter then arrives
169 * and we don't find a counter that's overflowed, so we
170 * would return 0 and get dazed + confused. Instead we always
171 * assume we found an overflow. This sucks.
172 */
173 return 1;
174}
175
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100176
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177static void ppro_start(struct op_msrs const * const msrs)
178{
Robert Richterdea37662009-05-25 18:11:52 +0200179 u64 val;
Arun Sharma6b77df02006-09-29 02:00:01 -0700180 int i;
Don Zickuscb9c4482006-09-26 10:52:26 +0200181
Eric Dumazet9ea84ad2008-12-02 07:21:21 +0100182 if (!reset_value)
183 return;
Andi Kleenb9917022008-08-18 14:50:31 +0200184 for (i = 0; i < num_counters; ++i) {
Arun Sharma6b77df02006-09-29 02:00:01 -0700185 if (reset_value[i]) {
Robert Richterdea37662009-05-25 18:11:52 +0200186 rdmsrl(msrs->controls[i].addr, val);
Robert Richterbb1165d2010-03-01 14:21:23 +0100187 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
Robert Richterdea37662009-05-25 18:11:52 +0200188 wrmsrl(msrs->controls[i].addr, val);
Arun Sharma6b77df02006-09-29 02:00:01 -0700189 }
Don Zickuscb9c4482006-09-26 10:52:26 +0200190 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191}
192
193
194static void ppro_stop(struct op_msrs const * const msrs)
195{
Robert Richterdea37662009-05-25 18:11:52 +0200196 u64 val;
Arun Sharma6b77df02006-09-29 02:00:01 -0700197 int i;
Don Zickuscb9c4482006-09-26 10:52:26 +0200198
Eric Dumazet9ea84ad2008-12-02 07:21:21 +0100199 if (!reset_value)
200 return;
Andi Kleenb9917022008-08-18 14:50:31 +0200201 for (i = 0; i < num_counters; ++i) {
Arun Sharma6b77df02006-09-29 02:00:01 -0700202 if (!reset_value[i])
203 continue;
Robert Richterdea37662009-05-25 18:11:52 +0200204 rdmsrl(msrs->controls[i].addr, val);
Robert Richterbb1165d2010-03-01 14:21:23 +0100205 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
Robert Richterdea37662009-05-25 18:11:52 +0200206 wrmsrl(msrs->controls[i].addr, val);
Don Zickuscb9c4482006-09-26 10:52:26 +0200207 }
208}
209
Robert Richter259a83a2009-07-09 15:12:35 +0200210struct op_x86_model_spec op_ppro_spec = {
Robert Richter849620f2009-05-14 17:10:52 +0200211 .num_counters = 2,
212 .num_controls = 2,
Robert Richter3370d352009-05-25 15:10:32 +0200213 .reserved = MSR_PPRO_EVENTSEL_RESERVED,
Robert Richterc92960f2008-09-05 17:12:36 +0200214 .fill_in_addresses = &ppro_fill_in_addresses,
215 .setup_ctrs = &ppro_setup_ctrs,
216 .check_ctrs = &ppro_check_ctrs,
217 .start = &ppro_start,
218 .stop = &ppro_stop,
219 .shutdown = &ppro_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220};
Andi Kleenb9917022008-08-18 14:50:31 +0200221
222/*
223 * Architectural performance monitoring.
224 *
225 * Newer Intel CPUs (Core1+) have support for architectural
226 * events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details.
227 * The advantage of this is that it can be done without knowing about
228 * the specific CPU.
229 */
230
Robert Richtere4192942008-10-12 15:12:34 -0400231static void arch_perfmon_setup_counters(void)
Andi Kleenb9917022008-08-18 14:50:31 +0200232{
233 union cpuid10_eax eax;
234
235 eax.full = cpuid_eax(0xa);
236
237 /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */
238 if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 &&
239 current_cpu_data.x86_model == 15) {
240 eax.split.version_id = 2;
Robert Richter948b1bb2010-03-29 18:36:50 +0200241 eax.split.num_counters = 2;
Andi Kleenb9917022008-08-18 14:50:31 +0200242 eax.split.bit_width = 40;
243 }
244
Robert Richter948b1bb2010-03-29 18:36:50 +0200245 num_counters = eax.split.num_counters;
Andi Kleenb9917022008-08-18 14:50:31 +0200246
247 op_arch_perfmon_spec.num_counters = num_counters;
248 op_arch_perfmon_spec.num_controls = num_counters;
249}
250
Robert Richtere4192942008-10-12 15:12:34 -0400251static int arch_perfmon_init(struct oprofile_operations *ignore)
252{
253 arch_perfmon_setup_counters();
254 return 0;
255}
256
Andi Kleenb9917022008-08-18 14:50:31 +0200257struct op_x86_model_spec op_arch_perfmon_spec = {
Robert Richter3370d352009-05-25 15:10:32 +0200258 .reserved = MSR_PPRO_EVENTSEL_RESERVED,
Robert Richtere4192942008-10-12 15:12:34 -0400259 .init = &arch_perfmon_init,
Andi Kleenb9917022008-08-18 14:50:31 +0200260 /* num_counters/num_controls filled in at runtime */
Robert Richter5a289392008-10-15 22:19:41 +0200261 .fill_in_addresses = &ppro_fill_in_addresses,
Andi Kleenb9917022008-08-18 14:50:31 +0200262 /* user space does the cpuid check for available events */
Robert Richter5a289392008-10-15 22:19:41 +0200263 .setup_ctrs = &ppro_setup_ctrs,
264 .check_ctrs = &ppro_check_ctrs,
265 .start = &ppro_start,
266 .stop = &ppro_stop,
267 .shutdown = &ppro_shutdown
Andi Kleenb9917022008-08-18 14:50:31 +0200268};