Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #include <asm/dma-iommu.h> |
| 16 | #include <linux/clk.h> |
| 17 | #include <linux/dma-mapping.h> |
| 18 | #include <linux/ipc_logging.h> |
| 19 | #include <linux/io.h> |
| 20 | #include <linux/list.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/msm-bus.h> |
| 23 | #include <linux/msm-bus-board.h> |
| 24 | #include <linux/of.h> |
| 25 | #include <linux/of_platform.h> |
| 26 | #include <linux/pm_runtime.h> |
| 27 | #include <linux/qcom-geni-se.h> |
| 28 | #include <linux/spinlock.h> |
| 29 | |
| 30 | #define GENI_SE_IOMMU_VA_START (0x40000000) |
| 31 | #define GENI_SE_IOMMU_VA_SIZE (0xC0000000) |
| 32 | |
| 33 | #define NUM_LOG_PAGES 2 |
Karthikeyan Ramasubramanian | 8bef5ea | 2017-05-11 17:02:46 -0600 | [diff] [blame^] | 34 | #define MAX_CLK_PERF_LEVEL 32 |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 35 | static unsigned long default_bus_bw_set[] = {0, 19200000, 50000000, 100000000}; |
| 36 | |
| 37 | /** |
| 38 | * @struct geni_se_device - Data structure to represent the QUPv3 Core |
| 39 | * @dev: Device pointer of the QUPv3 core. |
| 40 | * @cb_dev: Device pointer of the context bank in the IOMMU. |
| 41 | * @iommu_lock: Lock to protect IOMMU Mapping & attachment. |
| 42 | * @iommu_map: IOMMU map of the memory space supported by this core. |
| 43 | * @iommu_s1_bypass: Bypass IOMMU stage 1 translation. |
| 44 | * @base: Base address of this instance of QUPv3 core. |
| 45 | * @bus_bw: Client handle to the bus bandwidth request. |
| 46 | * @bus_mas_id: Master Endpoint ID for bus BW request. |
| 47 | * @bus_slv_id: Slave Endpoint ID for bus BW request. |
| 48 | * @ab_ib_lock: Lock to protect the bus ab & ib values, list. |
| 49 | * @ab_list_head: Sorted resource list based on average bus BW. |
| 50 | * @ib_list_head: Sorted resource list based on instantaneous bus BW. |
| 51 | * @cur_ab: Current Bus Average BW request value. |
| 52 | * @cur_ib: Current Bus Instantaneous BW request value. |
| 53 | * @bus_bw_set: Clock plan for the bus driver. |
| 54 | * @cur_bus_bw_idx: Current index within the bus clock plan. |
Karthikeyan Ramasubramanian | 8bef5ea | 2017-05-11 17:02:46 -0600 | [diff] [blame^] | 55 | * @num_clk_levels: Number of valid clock levels in clk_perf_tbl. |
| 56 | * @clk_perf_tbl: Table of clock frequency input to Serial Engine clock. |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 57 | * @log_ctx: Logging context to hold the debug information |
| 58 | */ |
| 59 | struct geni_se_device { |
| 60 | struct device *dev; |
| 61 | struct device *cb_dev; |
| 62 | struct mutex iommu_lock; |
| 63 | struct dma_iommu_mapping *iommu_map; |
| 64 | bool iommu_s1_bypass; |
| 65 | void __iomem *base; |
| 66 | struct msm_bus_client_handle *bus_bw; |
| 67 | u32 bus_mas_id; |
| 68 | u32 bus_slv_id; |
| 69 | spinlock_t ab_ib_lock; |
| 70 | struct list_head ab_list_head; |
| 71 | struct list_head ib_list_head; |
| 72 | unsigned long cur_ab; |
| 73 | unsigned long cur_ib; |
| 74 | int bus_bw_set_size; |
| 75 | unsigned long *bus_bw_set; |
| 76 | int cur_bus_bw_idx; |
Karthikeyan Ramasubramanian | 8bef5ea | 2017-05-11 17:02:46 -0600 | [diff] [blame^] | 77 | unsigned int num_clk_levels; |
| 78 | unsigned long *clk_perf_tbl; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 79 | void *log_ctx; |
| 80 | }; |
| 81 | |
| 82 | /* Offset of QUPV3 Hardware Version Register */ |
| 83 | #define QUPV3_HW_VER (0x4) |
| 84 | |
| 85 | #define HW_VER_MAJOR_MASK GENMASK(31, 28) |
| 86 | #define HW_VER_MAJOR_SHFT 28 |
| 87 | #define HW_VER_MINOR_MASK GENMASK(27, 16) |
| 88 | #define HW_VER_MINOR_SHFT 16 |
| 89 | #define HW_VER_STEP_MASK GENMASK(15, 0) |
| 90 | |
| 91 | static int geni_se_iommu_map_and_attach(struct geni_se_device *geni_se_dev); |
| 92 | |
| 93 | /** |
| 94 | * geni_read_reg_nolog() - Helper function to read from a GENI register |
| 95 | * @base: Base address of the serial engine's register block. |
| 96 | * @offset: Offset within the serial engine's register block. |
| 97 | * |
| 98 | * Return: Return the contents of the register. |
| 99 | */ |
| 100 | unsigned int geni_read_reg_nolog(void __iomem *base, int offset) |
| 101 | { |
| 102 | return readl_relaxed_no_log(base + offset); |
| 103 | } |
| 104 | EXPORT_SYMBOL(geni_read_reg_nolog); |
| 105 | |
| 106 | /** |
| 107 | * geni_write_reg_nolog() - Helper function to write into a GENI register |
| 108 | * @value: Value to be written into the register. |
| 109 | * @base: Base address of the serial engine's register block. |
| 110 | * @offset: Offset within the serial engine's register block. |
| 111 | */ |
| 112 | void geni_write_reg_nolog(unsigned int value, void __iomem *base, int offset) |
| 113 | { |
| 114 | return writel_relaxed_no_log(value, (base + offset)); |
| 115 | } |
| 116 | EXPORT_SYMBOL(geni_write_reg_nolog); |
| 117 | |
| 118 | /** |
| 119 | * geni_read_reg() - Helper function to read from a GENI register |
| 120 | * @base: Base address of the serial engine's register block. |
| 121 | * @offset: Offset within the serial engine's register block. |
| 122 | * |
| 123 | * Return: Return the contents of the register. |
| 124 | */ |
| 125 | unsigned int geni_read_reg(void __iomem *base, int offset) |
| 126 | { |
| 127 | return readl_relaxed(base + offset); |
| 128 | } |
| 129 | EXPORT_SYMBOL(geni_read_reg); |
| 130 | |
| 131 | /** |
| 132 | * geni_write_reg() - Helper function to write into a GENI register |
| 133 | * @value: Value to be written into the register. |
| 134 | * @base: Base address of the serial engine's register block. |
| 135 | * @offset: Offset within the serial engine's register block. |
| 136 | */ |
| 137 | void geni_write_reg(unsigned int value, void __iomem *base, int offset) |
| 138 | { |
| 139 | return writel_relaxed(value, (base + offset)); |
| 140 | } |
| 141 | EXPORT_SYMBOL(geni_write_reg); |
| 142 | |
| 143 | /** |
| 144 | * get_se_proto() - Read the protocol configured for a serial engine |
| 145 | * @base: Base address of the serial engine's register block. |
| 146 | * |
| 147 | * Return: Protocol value as configured in the serial engine. |
| 148 | */ |
| 149 | int get_se_proto(void __iomem *base) |
| 150 | { |
| 151 | int proto; |
| 152 | |
| 153 | proto = ((geni_read_reg(base, GENI_FW_REVISION_RO) |
| 154 | & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT); |
| 155 | return proto; |
| 156 | } |
| 157 | EXPORT_SYMBOL(get_se_proto); |
| 158 | |
| 159 | static int se_geni_irq_en(void __iomem *base) |
| 160 | { |
| 161 | unsigned int common_geni_m_irq_en; |
| 162 | unsigned int common_geni_s_irq_en; |
| 163 | |
| 164 | common_geni_m_irq_en = geni_read_reg(base, SE_GENI_M_IRQ_EN); |
| 165 | common_geni_s_irq_en = geni_read_reg(base, SE_GENI_S_IRQ_EN); |
| 166 | /* Common to all modes */ |
| 167 | common_geni_m_irq_en |= M_COMMON_GENI_M_IRQ_EN; |
| 168 | common_geni_s_irq_en |= S_COMMON_GENI_S_IRQ_EN; |
| 169 | |
| 170 | geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN); |
| 171 | geni_write_reg(common_geni_s_irq_en, base, SE_GENI_S_IRQ_EN); |
| 172 | return 0; |
| 173 | } |
| 174 | |
| 175 | |
| 176 | static void se_set_rx_rfr_wm(void __iomem *base, unsigned int rx_wm, |
| 177 | unsigned int rx_rfr) |
| 178 | { |
| 179 | geni_write_reg(rx_wm, base, SE_GENI_RX_WATERMARK_REG); |
| 180 | geni_write_reg(rx_rfr, base, SE_GENI_RX_RFR_WATERMARK_REG); |
| 181 | } |
| 182 | |
| 183 | static int se_io_set_mode(void __iomem *base) |
| 184 | { |
| 185 | unsigned int io_mode; |
| 186 | unsigned int geni_dma_mode; |
| 187 | |
| 188 | io_mode = geni_read_reg(base, SE_IRQ_EN); |
| 189 | geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN); |
| 190 | |
| 191 | io_mode |= (GENI_M_IRQ_EN | GENI_S_IRQ_EN); |
| 192 | io_mode |= (DMA_TX_IRQ_EN | DMA_RX_IRQ_EN); |
| 193 | geni_dma_mode &= ~GENI_DMA_MODE_EN; |
| 194 | |
| 195 | geni_write_reg(io_mode, base, SE_IRQ_EN); |
| 196 | geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN); |
| 197 | geni_write_reg(0, base, SE_GSI_EVENT_EN); |
| 198 | return 0; |
| 199 | } |
| 200 | |
| 201 | static void se_io_init(void __iomem *base) |
| 202 | { |
| 203 | unsigned int io_op_ctrl; |
| 204 | unsigned int geni_cgc_ctrl; |
| 205 | unsigned int dma_general_cfg; |
| 206 | |
| 207 | geni_cgc_ctrl = geni_read_reg(base, GENI_CGC_CTRL); |
| 208 | dma_general_cfg = geni_read_reg(base, SE_DMA_GENERAL_CFG); |
| 209 | geni_cgc_ctrl |= DEFAULT_CGC_EN; |
| 210 | dma_general_cfg |= (AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON | |
| 211 | DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON); |
| 212 | io_op_ctrl = DEFAULT_IO_OUTPUT_CTRL_MSK; |
| 213 | geni_write_reg(geni_cgc_ctrl, base, GENI_CGC_CTRL); |
| 214 | geni_write_reg(dma_general_cfg, base, SE_DMA_GENERAL_CFG); |
| 215 | |
| 216 | geni_write_reg(io_op_ctrl, base, GENI_OUTPUT_CTRL); |
| 217 | geni_write_reg(FORCE_DEFAULT, base, GENI_FORCE_DEFAULT_REG); |
| 218 | } |
| 219 | |
| 220 | /** |
| 221 | * geni_se_init() - Initialize the GENI Serial Engine |
| 222 | * @base: Base address of the serial engine's register block. |
| 223 | * @rx_wm: Receive watermark to be configured. |
| 224 | * @rx_rfr_wm: Ready-for-receive watermark to be configured. |
| 225 | * |
| 226 | * This function is used to initialize the GENI serial engine, configure |
| 227 | * receive watermark and ready-for-receive watermarks. |
| 228 | * |
| 229 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 230 | */ |
| 231 | int geni_se_init(void __iomem *base, unsigned int rx_wm, unsigned int rx_rfr) |
| 232 | { |
| 233 | int ret; |
| 234 | |
| 235 | se_io_init(base); |
| 236 | ret = se_io_set_mode(base); |
| 237 | if (ret) |
| 238 | return ret; |
| 239 | |
| 240 | se_set_rx_rfr_wm(base, rx_wm, rx_rfr); |
| 241 | ret = se_geni_irq_en(base); |
| 242 | return ret; |
| 243 | } |
| 244 | EXPORT_SYMBOL(geni_se_init); |
| 245 | |
| 246 | static int geni_se_select_fifo_mode(void __iomem *base) |
| 247 | { |
| 248 | int proto = get_se_proto(base); |
| 249 | unsigned int common_geni_m_irq_en; |
| 250 | unsigned int common_geni_s_irq_en; |
| 251 | unsigned int geni_dma_mode; |
| 252 | |
| 253 | geni_write_reg(0, base, SE_GSI_EVENT_EN); |
| 254 | geni_write_reg(0xFFFFFFFF, base, SE_GENI_M_IRQ_CLEAR); |
| 255 | geni_write_reg(0xFFFFFFFF, base, SE_GENI_S_IRQ_CLEAR); |
| 256 | geni_write_reg(0xFFFFFFFF, base, SE_DMA_TX_IRQ_CLR); |
| 257 | geni_write_reg(0xFFFFFFFF, base, SE_DMA_RX_IRQ_CLR); |
| 258 | geni_write_reg(0xFFFFFFFF, base, SE_IRQ_EN); |
| 259 | |
| 260 | common_geni_m_irq_en = geni_read_reg(base, SE_GENI_M_IRQ_EN); |
| 261 | common_geni_s_irq_en = geni_read_reg(base, SE_GENI_S_IRQ_EN); |
| 262 | geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN); |
| 263 | if (proto != UART) { |
| 264 | common_geni_m_irq_en |= |
| 265 | (M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | |
| 266 | M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); |
| 267 | common_geni_s_irq_en |= S_CMD_DONE_EN; |
| 268 | } |
| 269 | geni_dma_mode &= ~GENI_DMA_MODE_EN; |
| 270 | |
| 271 | geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN); |
| 272 | geni_write_reg(common_geni_s_irq_en, base, SE_GENI_S_IRQ_EN); |
| 273 | geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN); |
| 274 | return 0; |
| 275 | } |
| 276 | |
| 277 | static int geni_se_select_dma_mode(void __iomem *base) |
| 278 | { |
| 279 | unsigned int geni_dma_mode = 0; |
| 280 | |
| 281 | geni_write_reg(0, base, SE_GSI_EVENT_EN); |
| 282 | geni_write_reg(0xFFFFFFFF, base, SE_GENI_M_IRQ_CLEAR); |
| 283 | geni_write_reg(0xFFFFFFFF, base, SE_GENI_S_IRQ_CLEAR); |
| 284 | geni_write_reg(0xFFFFFFFF, base, SE_DMA_TX_IRQ_CLR); |
| 285 | geni_write_reg(0xFFFFFFFF, base, SE_DMA_RX_IRQ_CLR); |
| 286 | geni_write_reg(0xFFFFFFFF, base, SE_IRQ_EN); |
| 287 | |
| 288 | geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN); |
| 289 | geni_dma_mode |= GENI_DMA_MODE_EN; |
| 290 | geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN); |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | static int geni_se_select_gsi_mode(void __iomem *base) |
| 295 | { |
| 296 | unsigned int io_mode = 0; |
| 297 | unsigned int geni_dma_mode = 0; |
| 298 | unsigned int gsi_event_en = 0; |
| 299 | |
| 300 | geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN); |
| 301 | gsi_event_en = geni_read_reg(base, SE_GSI_EVENT_EN); |
| 302 | io_mode = geni_read_reg(base, SE_IRQ_EN); |
| 303 | |
| 304 | geni_dma_mode |= GENI_DMA_MODE_EN; |
| 305 | io_mode &= ~(DMA_TX_IRQ_EN | DMA_RX_IRQ_EN); |
| 306 | gsi_event_en |= (DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | |
| 307 | GENI_M_EVENT_EN | GENI_S_EVENT_EN); |
| 308 | |
| 309 | geni_write_reg(io_mode, base, SE_IRQ_EN); |
| 310 | geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN); |
| 311 | geni_write_reg(gsi_event_en, base, SE_GSI_EVENT_EN); |
| 312 | return 0; |
| 313 | |
| 314 | } |
| 315 | |
| 316 | /** |
| 317 | * geni_se_select_mode() - Select the serial engine transfer mode |
| 318 | * @base: Base address of the serial engine's register block. |
| 319 | * @mode: Transfer mode to be selected. |
| 320 | * |
| 321 | * Return: 0 on success, standard Linux error codes on failure. |
| 322 | */ |
| 323 | int geni_se_select_mode(void __iomem *base, int mode) |
| 324 | { |
| 325 | int ret = 0; |
| 326 | |
| 327 | switch (mode) { |
| 328 | case FIFO_MODE: |
| 329 | geni_se_select_fifo_mode(base); |
| 330 | break; |
| 331 | case SE_DMA: |
| 332 | geni_se_select_dma_mode(base); |
| 333 | break; |
| 334 | case GSI_DMA: |
| 335 | geni_se_select_gsi_mode(base); |
| 336 | break; |
| 337 | default: |
| 338 | ret = -EINVAL; |
| 339 | break; |
| 340 | } |
| 341 | |
| 342 | return ret; |
| 343 | } |
| 344 | EXPORT_SYMBOL(geni_se_select_mode); |
| 345 | |
| 346 | /** |
| 347 | * geni_setup_m_cmd() - Setup the primary sequencer |
| 348 | * @base: Base address of the serial engine's register block. |
| 349 | * @cmd: Command/Operation to setup in the primary sequencer. |
| 350 | * @params: Parameter for the sequencer command. |
| 351 | * |
| 352 | * This function is used to configure the primary sequencer with the |
| 353 | * command and its assoicated parameters. |
| 354 | */ |
| 355 | void geni_setup_m_cmd(void __iomem *base, u32 cmd, u32 params) |
| 356 | { |
| 357 | u32 m_cmd = (cmd << M_OPCODE_SHFT); |
| 358 | |
| 359 | m_cmd |= (params & M_PARAMS_MSK); |
| 360 | geni_write_reg(m_cmd, base, SE_GENI_M_CMD0); |
| 361 | } |
| 362 | EXPORT_SYMBOL(geni_setup_m_cmd); |
| 363 | |
| 364 | /** |
| 365 | * geni_setup_s_cmd() - Setup the secondary sequencer |
| 366 | * @base: Base address of the serial engine's register block. |
| 367 | * @cmd: Command/Operation to setup in the secondary sequencer. |
| 368 | * @params: Parameter for the sequencer command. |
| 369 | * |
| 370 | * This function is used to configure the secondary sequencer with the |
| 371 | * command and its assoicated parameters. |
| 372 | */ |
| 373 | void geni_setup_s_cmd(void __iomem *base, u32 cmd, u32 params) |
| 374 | { |
| 375 | u32 s_cmd = geni_read_reg(base, SE_GENI_S_CMD0); |
| 376 | |
| 377 | s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK); |
| 378 | s_cmd |= (cmd << S_OPCODE_SHFT); |
| 379 | s_cmd |= (params & S_PARAMS_MSK); |
| 380 | geni_write_reg(s_cmd, base, SE_GENI_S_CMD0); |
| 381 | } |
| 382 | EXPORT_SYMBOL(geni_setup_s_cmd); |
| 383 | |
| 384 | /** |
| 385 | * geni_cancel_m_cmd() - Cancel the command configured in the primary sequencer |
| 386 | * @base: Base address of the serial engine's register block. |
| 387 | * |
| 388 | * This function is used to cancel the currently configured command in the |
| 389 | * primary sequencer. |
| 390 | */ |
| 391 | void geni_cancel_m_cmd(void __iomem *base) |
| 392 | { |
| 393 | geni_write_reg(M_GENI_CMD_CANCEL, base, SE_GENI_S_CMD_CTRL_REG); |
| 394 | } |
| 395 | EXPORT_SYMBOL(geni_cancel_m_cmd); |
| 396 | |
| 397 | /** |
| 398 | * geni_cancel_s_cmd() - Cancel the command configured in the secondary |
| 399 | * sequencer |
| 400 | * @base: Base address of the serial engine's register block. |
| 401 | * |
| 402 | * This function is used to cancel the currently configured command in the |
| 403 | * secondary sequencer. |
| 404 | */ |
| 405 | void geni_cancel_s_cmd(void __iomem *base) |
| 406 | { |
| 407 | geni_write_reg(S_GENI_CMD_CANCEL, base, SE_GENI_S_CMD_CTRL_REG); |
| 408 | } |
| 409 | EXPORT_SYMBOL(geni_cancel_s_cmd); |
| 410 | |
| 411 | /** |
| 412 | * geni_abort_m_cmd() - Abort the command configured in the primary sequencer |
| 413 | * @base: Base address of the serial engine's register block. |
| 414 | * |
| 415 | * This function is used to force abort the currently configured command in the |
| 416 | * primary sequencer. |
| 417 | */ |
| 418 | void geni_abort_m_cmd(void __iomem *base) |
| 419 | { |
| 420 | geni_write_reg(M_GENI_CMD_ABORT, base, SE_GENI_M_CMD_CTRL_REG); |
| 421 | } |
| 422 | EXPORT_SYMBOL(geni_abort_m_cmd); |
| 423 | |
| 424 | /** |
| 425 | * geni_abort_s_cmd() - Abort the command configured in the secondary |
| 426 | * sequencer |
| 427 | * @base: Base address of the serial engine's register block. |
| 428 | * |
| 429 | * This function is used to force abort the currently configured command in the |
| 430 | * secondary sequencer. |
| 431 | */ |
| 432 | void geni_abort_s_cmd(void __iomem *base) |
| 433 | { |
| 434 | geni_write_reg(S_GENI_CMD_ABORT, base, SE_GENI_S_CMD_CTRL_REG); |
| 435 | } |
| 436 | EXPORT_SYMBOL(geni_abort_s_cmd); |
| 437 | |
| 438 | /** |
| 439 | * get_tx_fifo_depth() - Get the TX fifo depth of the serial engine |
| 440 | * @base: Base address of the serial engine's register block. |
| 441 | * |
| 442 | * This function is used to get the depth i.e. number of elements in the |
| 443 | * TX fifo of the serial engine. |
| 444 | * |
| 445 | * Return: TX fifo depth in units of FIFO words. |
| 446 | */ |
| 447 | int get_tx_fifo_depth(void __iomem *base) |
| 448 | { |
| 449 | int tx_fifo_depth; |
| 450 | |
| 451 | tx_fifo_depth = ((geni_read_reg(base, SE_HW_PARAM_0) |
| 452 | & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT); |
| 453 | return tx_fifo_depth; |
| 454 | } |
| 455 | EXPORT_SYMBOL(get_tx_fifo_depth); |
| 456 | |
| 457 | /** |
| 458 | * get_tx_fifo_width() - Get the TX fifo width of the serial engine |
| 459 | * @base: Base address of the serial engine's register block. |
| 460 | * |
| 461 | * This function is used to get the width i.e. word size per element in the |
| 462 | * TX fifo of the serial engine. |
| 463 | * |
| 464 | * Return: TX fifo width in bits |
| 465 | */ |
| 466 | int get_tx_fifo_width(void __iomem *base) |
| 467 | { |
| 468 | int tx_fifo_width; |
| 469 | |
| 470 | tx_fifo_width = ((geni_read_reg(base, SE_HW_PARAM_0) |
| 471 | & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT); |
| 472 | return tx_fifo_width; |
| 473 | } |
| 474 | EXPORT_SYMBOL(get_tx_fifo_width); |
| 475 | |
| 476 | /** |
| 477 | * get_rx_fifo_depth() - Get the RX fifo depth of the serial engine |
| 478 | * @base: Base address of the serial engine's register block. |
| 479 | * |
| 480 | * This function is used to get the depth i.e. number of elements in the |
| 481 | * RX fifo of the serial engine. |
| 482 | * |
| 483 | * Return: RX fifo depth in units of FIFO words |
| 484 | */ |
| 485 | int get_rx_fifo_depth(void __iomem *base) |
| 486 | { |
| 487 | int rx_fifo_depth; |
| 488 | |
| 489 | rx_fifo_depth = ((geni_read_reg(base, SE_HW_PARAM_1) |
| 490 | & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT); |
| 491 | return rx_fifo_depth; |
| 492 | } |
| 493 | EXPORT_SYMBOL(get_rx_fifo_depth); |
| 494 | |
| 495 | /** |
| 496 | * se_get_packing_config() - Get the packing configuration based on input |
| 497 | * @bpw: Bits of data per transfer word. |
| 498 | * @pack_words: Number of words per fifo element. |
| 499 | * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. |
| 500 | * @cfg0: Output buffer to hold the first half of configuration. |
| 501 | * @cfg1: Output buffer to hold the second half of configuration. |
| 502 | * |
| 503 | * This function is used to calculate the packing configuration based on |
| 504 | * the input packing requirement and the configuration logic. |
| 505 | */ |
| 506 | void se_get_packing_config(int bpw, int pack_words, bool msb_to_lsb, |
| 507 | unsigned long *cfg0, unsigned long *cfg1) |
| 508 | { |
| 509 | u32 cfg[4] = {0}; |
| 510 | int len; |
| 511 | int temp_bpw = bpw; |
| 512 | int idx_start = (msb_to_lsb ? (bpw - 1) : 0); |
| 513 | int idx = idx_start; |
| 514 | int idx_delta = (msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE); |
| 515 | int ceil_bpw = ((bpw & (BITS_PER_BYTE - 1)) ? |
| 516 | ((bpw & ~(BITS_PER_BYTE - 1)) + BITS_PER_BYTE) : bpw); |
| 517 | int iter = (ceil_bpw * pack_words) >> 3; |
| 518 | int i; |
| 519 | |
| 520 | if (unlikely(iter <= 0 || iter > 4)) { |
| 521 | *cfg0 = 0; |
| 522 | *cfg1 = 0; |
| 523 | return; |
| 524 | } |
| 525 | |
| 526 | for (i = 0; i < iter; i++) { |
| 527 | len = (temp_bpw < BITS_PER_BYTE) ? |
| 528 | (temp_bpw - 1) : BITS_PER_BYTE - 1; |
| 529 | cfg[i] = ((idx << 5) | (msb_to_lsb << 4) | (len << 1)); |
| 530 | idx = ((temp_bpw - BITS_PER_BYTE) <= 0) ? |
| 531 | ((i + 1) * BITS_PER_BYTE) + idx_start : |
| 532 | idx + idx_delta; |
| 533 | temp_bpw = ((temp_bpw - BITS_PER_BYTE) <= 0) ? |
| 534 | bpw : (temp_bpw - BITS_PER_BYTE); |
| 535 | } |
| 536 | cfg[iter - 1] |= 1; |
| 537 | *cfg0 = cfg[0] | (cfg[1] << 10); |
| 538 | *cfg1 = cfg[2] | (cfg[3] << 10); |
| 539 | } |
| 540 | EXPORT_SYMBOL(se_get_packing_config); |
| 541 | |
| 542 | /** |
| 543 | * se_config_packing() - Packing configuration of the serial engine |
| 544 | * @base: Base address of the serial engine's register block. |
| 545 | * @bpw: Bits of data per transfer word. |
| 546 | * @pack_words: Number of words per fifo element. |
| 547 | * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. |
| 548 | * |
| 549 | * This function is used to configure the packing rules for the current |
| 550 | * transfer. |
| 551 | */ |
| 552 | void se_config_packing(void __iomem *base, int bpw, |
| 553 | int pack_words, bool msb_to_lsb) |
| 554 | { |
| 555 | unsigned long cfg0, cfg1; |
| 556 | |
| 557 | se_get_packing_config(bpw, pack_words, msb_to_lsb, &cfg0, &cfg1); |
| 558 | geni_write_reg(cfg0, base, SE_GENI_TX_PACKING_CFG0); |
| 559 | geni_write_reg(cfg1, base, SE_GENI_TX_PACKING_CFG1); |
| 560 | geni_write_reg(cfg0, base, SE_GENI_RX_PACKING_CFG0); |
| 561 | geni_write_reg(cfg1, base, SE_GENI_RX_PACKING_CFG1); |
| 562 | if (pack_words || bpw == 32) |
| 563 | geni_write_reg((bpw >> 4), base, SE_GENI_BYTE_GRAN); |
| 564 | } |
| 565 | EXPORT_SYMBOL(se_config_packing); |
| 566 | |
| 567 | static void se_geni_clks_off(struct se_geni_rsc *rsc) |
| 568 | { |
| 569 | clk_disable_unprepare(rsc->se_clk); |
| 570 | clk_disable_unprepare(rsc->s_ahb_clk); |
| 571 | clk_disable_unprepare(rsc->m_ahb_clk); |
| 572 | } |
| 573 | |
| 574 | static bool geni_se_check_bus_bw(struct geni_se_device *geni_se_dev) |
| 575 | { |
| 576 | int i; |
| 577 | int new_bus_bw_idx = geni_se_dev->bus_bw_set_size - 1; |
| 578 | unsigned long new_bus_bw; |
| 579 | bool bus_bw_update = false; |
| 580 | |
| 581 | new_bus_bw = max(geni_se_dev->cur_ib, geni_se_dev->cur_ab) / |
| 582 | DEFAULT_BUS_WIDTH; |
| 583 | for (i = 0; i < geni_se_dev->bus_bw_set_size; i++) { |
| 584 | if (geni_se_dev->bus_bw_set[i] >= new_bus_bw) { |
| 585 | new_bus_bw_idx = i; |
| 586 | break; |
| 587 | } |
| 588 | } |
| 589 | |
| 590 | if (geni_se_dev->cur_bus_bw_idx != new_bus_bw_idx) { |
| 591 | geni_se_dev->cur_bus_bw_idx = new_bus_bw_idx; |
| 592 | bus_bw_update = true; |
| 593 | } |
| 594 | return bus_bw_update; |
| 595 | } |
| 596 | |
| 597 | static int geni_se_rmv_ab_ib(struct geni_se_device *geni_se_dev, |
| 598 | struct se_geni_rsc *rsc) |
| 599 | { |
| 600 | unsigned long flags; |
| 601 | struct se_geni_rsc *tmp; |
| 602 | bool bus_bw_update = false; |
| 603 | int ret = 0; |
| 604 | |
| 605 | if (unlikely(list_empty(&rsc->ab_list) || list_empty(&rsc->ib_list))) |
| 606 | return -EINVAL; |
| 607 | |
| 608 | spin_lock_irqsave(&geni_se_dev->ab_ib_lock, flags); |
| 609 | list_del_init(&rsc->ab_list); |
| 610 | geni_se_dev->cur_ab -= rsc->ab; |
| 611 | |
| 612 | list_del_init(&rsc->ib_list); |
| 613 | tmp = list_first_entry_or_null(&geni_se_dev->ib_list_head, |
| 614 | struct se_geni_rsc, ib_list); |
| 615 | if (tmp && tmp->ib != geni_se_dev->cur_ib) |
| 616 | geni_se_dev->cur_ib = tmp->ib; |
| 617 | else if (!tmp && geni_se_dev->cur_ib) |
| 618 | geni_se_dev->cur_ib = 0; |
| 619 | |
| 620 | bus_bw_update = geni_se_check_bus_bw(geni_se_dev); |
| 621 | spin_unlock_irqrestore(&geni_se_dev->ab_ib_lock, flags); |
| 622 | |
| 623 | if (bus_bw_update) |
| 624 | ret = msm_bus_scale_update_bw(geni_se_dev->bus_bw, |
| 625 | geni_se_dev->cur_ab, |
| 626 | geni_se_dev->cur_ib); |
| 627 | GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, |
| 628 | "%s: %lu:%lu (%lu:%lu) %d\n", __func__, |
| 629 | geni_se_dev->cur_ab, geni_se_dev->cur_ib, |
| 630 | rsc->ab, rsc->ib, bus_bw_update); |
| 631 | return ret; |
| 632 | } |
| 633 | |
| 634 | /** |
| 635 | * se_geni_resources_off() - Turn off resources associated with the serial |
| 636 | * engine |
| 637 | * @rsc: Handle to resources associated with the serial engine. |
| 638 | * |
| 639 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 640 | */ |
| 641 | int se_geni_resources_off(struct se_geni_rsc *rsc) |
| 642 | { |
| 643 | int ret = 0; |
| 644 | struct geni_se_device *geni_se_dev; |
| 645 | |
| 646 | if (unlikely(!rsc || !rsc->wrapper_dev)) |
| 647 | return -EINVAL; |
| 648 | |
| 649 | geni_se_dev = dev_get_drvdata(rsc->wrapper_dev); |
| 650 | if (unlikely(!geni_se_dev || !geni_se_dev->bus_bw)) |
| 651 | return -ENODEV; |
| 652 | |
| 653 | ret = pinctrl_select_state(rsc->geni_pinctrl, rsc->geni_gpio_sleep); |
| 654 | if (ret) { |
| 655 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 656 | "%s: Error %d pinctrl_select_state\n", __func__, ret); |
| 657 | return ret; |
| 658 | } |
| 659 | se_geni_clks_off(rsc); |
| 660 | ret = geni_se_rmv_ab_ib(geni_se_dev, rsc); |
| 661 | if (ret) |
| 662 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 663 | "%s: Error %d during bus_bw_update\n", __func__, ret); |
| 664 | return ret; |
| 665 | } |
| 666 | EXPORT_SYMBOL(se_geni_resources_off); |
| 667 | |
| 668 | static int se_geni_clks_on(struct se_geni_rsc *rsc) |
| 669 | { |
| 670 | int ret; |
| 671 | |
| 672 | ret = clk_prepare_enable(rsc->m_ahb_clk); |
| 673 | if (ret) |
| 674 | return ret; |
| 675 | |
| 676 | ret = clk_prepare_enable(rsc->s_ahb_clk); |
| 677 | if (ret) { |
| 678 | clk_disable_unprepare(rsc->m_ahb_clk); |
| 679 | return ret; |
| 680 | } |
| 681 | |
| 682 | ret = clk_prepare_enable(rsc->se_clk); |
| 683 | if (ret) { |
| 684 | clk_disable_unprepare(rsc->s_ahb_clk); |
| 685 | clk_disable_unprepare(rsc->m_ahb_clk); |
| 686 | } |
| 687 | return ret; |
| 688 | } |
| 689 | |
| 690 | static int geni_se_add_ab_ib(struct geni_se_device *geni_se_dev, |
| 691 | struct se_geni_rsc *rsc) |
| 692 | { |
| 693 | unsigned long flags; |
| 694 | struct se_geni_rsc *tmp; |
| 695 | struct list_head *ins_list_head; |
| 696 | bool bus_bw_update = false; |
| 697 | int ret = 0; |
| 698 | |
| 699 | spin_lock_irqsave(&geni_se_dev->ab_ib_lock, flags); |
| 700 | list_add(&rsc->ab_list, &geni_se_dev->ab_list_head); |
| 701 | geni_se_dev->cur_ab += rsc->ab; |
| 702 | |
| 703 | ins_list_head = &geni_se_dev->ib_list_head; |
| 704 | list_for_each_entry(tmp, &geni_se_dev->ib_list_head, ib_list) { |
| 705 | if (tmp->ib < rsc->ib) |
| 706 | break; |
| 707 | ins_list_head = &tmp->ib_list; |
| 708 | } |
| 709 | list_add(&rsc->ib_list, ins_list_head); |
| 710 | /* Currently inserted node has greater average BW value */ |
| 711 | if (ins_list_head == &geni_se_dev->ib_list_head) |
| 712 | geni_se_dev->cur_ib = tmp->ib; |
| 713 | |
| 714 | bus_bw_update = geni_se_check_bus_bw(geni_se_dev); |
| 715 | spin_unlock_irqrestore(&geni_se_dev->ab_ib_lock, flags); |
| 716 | |
| 717 | if (bus_bw_update) |
| 718 | ret = msm_bus_scale_update_bw(geni_se_dev->bus_bw, |
| 719 | geni_se_dev->cur_ab, |
| 720 | geni_se_dev->cur_ib); |
| 721 | GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, |
| 722 | "%s: %lu:%lu (%lu:%lu) %d\n", __func__, |
| 723 | geni_se_dev->cur_ab, geni_se_dev->cur_ib, |
| 724 | rsc->ab, rsc->ib, bus_bw_update); |
| 725 | return ret; |
| 726 | } |
| 727 | |
| 728 | /** |
| 729 | * se_geni_resources_on() - Turn on resources associated with the serial |
| 730 | * engine |
| 731 | * @rsc: Handle to resources associated with the serial engine. |
| 732 | * |
| 733 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 734 | */ |
| 735 | int se_geni_resources_on(struct se_geni_rsc *rsc) |
| 736 | { |
| 737 | int ret = 0; |
| 738 | struct geni_se_device *geni_se_dev; |
| 739 | |
| 740 | if (unlikely(!rsc || !rsc->wrapper_dev)) |
| 741 | return -EINVAL; |
| 742 | |
| 743 | geni_se_dev = dev_get_drvdata(rsc->wrapper_dev); |
| 744 | if (unlikely(!geni_se_dev)) |
| 745 | return -EPROBE_DEFER; |
| 746 | |
| 747 | ret = geni_se_add_ab_ib(geni_se_dev, rsc); |
| 748 | if (ret) { |
| 749 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 750 | "%s: Error %d during bus_bw_update\n", __func__, ret); |
| 751 | return ret; |
| 752 | } |
| 753 | |
| 754 | ret = se_geni_clks_on(rsc); |
| 755 | if (ret) { |
| 756 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 757 | "%s: Error %d during clks_on\n", __func__, ret); |
| 758 | geni_se_rmv_ab_ib(geni_se_dev, rsc); |
| 759 | return ret; |
| 760 | } |
| 761 | |
| 762 | ret = pinctrl_select_state(rsc->geni_pinctrl, rsc->geni_gpio_active); |
| 763 | if (ret) { |
| 764 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 765 | "%s: Error %d pinctrl_select_state\n", __func__, ret); |
| 766 | se_geni_clks_off(rsc); |
| 767 | geni_se_rmv_ab_ib(geni_se_dev, rsc); |
| 768 | } |
| 769 | return ret; |
| 770 | } |
| 771 | EXPORT_SYMBOL(se_geni_resources_on); |
| 772 | |
| 773 | /** |
| 774 | * geni_se_resources_init() - Init the SE resource structure |
| 775 | * @rsc: SE resource structure to be initialized. |
| 776 | * @ab: Initial Average bus bandwidth request value. |
| 777 | * @ib: Initial Instantaneous bus bandwidth request value. |
| 778 | * |
| 779 | * Return: 0 on success, standard Linux error codes on failure. |
| 780 | */ |
| 781 | int geni_se_resources_init(struct se_geni_rsc *rsc, |
| 782 | unsigned long ab, unsigned long ib) |
| 783 | { |
| 784 | struct geni_se_device *geni_se_dev; |
| 785 | |
| 786 | if (unlikely(!rsc || !rsc->wrapper_dev)) |
| 787 | return -EINVAL; |
| 788 | |
| 789 | geni_se_dev = dev_get_drvdata(rsc->wrapper_dev); |
| 790 | if (unlikely(!geni_se_dev)) |
| 791 | return -EPROBE_DEFER; |
| 792 | |
| 793 | if (unlikely(IS_ERR_OR_NULL(geni_se_dev->bus_bw))) { |
| 794 | geni_se_dev->bus_bw = msm_bus_scale_register( |
| 795 | geni_se_dev->bus_mas_id, |
| 796 | geni_se_dev->bus_slv_id, |
| 797 | (char *)dev_name(geni_se_dev->dev), |
| 798 | false); |
| 799 | if (IS_ERR_OR_NULL(geni_se_dev->bus_bw)) { |
| 800 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 801 | "%s: Error creating bus client\n", __func__); |
| 802 | return (int)PTR_ERR(geni_se_dev->bus_bw); |
| 803 | } |
| 804 | } |
| 805 | |
| 806 | rsc->ab = ab; |
| 807 | rsc->ib = ib; |
| 808 | INIT_LIST_HEAD(&rsc->ab_list); |
| 809 | INIT_LIST_HEAD(&rsc->ib_list); |
| 810 | geni_se_iommu_map_and_attach(geni_se_dev); |
| 811 | return 0; |
| 812 | } |
| 813 | EXPORT_SYMBOL(geni_se_resources_init); |
| 814 | |
| 815 | /** |
Karthikeyan Ramasubramanian | 8bef5ea | 2017-05-11 17:02:46 -0600 | [diff] [blame^] | 816 | * geni_se_clk_tbl_get() - Get the clock table to program DFS |
| 817 | * @rsc: Resource for which the clock table is requested. |
| 818 | * @tbl: Table in which the output is returned. |
| 819 | * |
| 820 | * This function is called by the protocol drivers to determine the different |
| 821 | * clock frequencies supported by Serail Engine Core Clock. The protocol |
| 822 | * drivers use the output to determine the clock frequency index to be |
| 823 | * programmed into DFS. |
| 824 | * |
| 825 | * Return: number of valid performance levels in the table on success, |
| 826 | * standard Linux error codes on failure. |
| 827 | */ |
| 828 | int geni_se_clk_tbl_get(struct se_geni_rsc *rsc, unsigned long **tbl) |
| 829 | { |
| 830 | struct geni_se_device *geni_se_dev; |
| 831 | int i; |
| 832 | unsigned long prev_freq = 0; |
| 833 | |
| 834 | if (unlikely(!rsc || !rsc->wrapper_dev || !rsc->se_clk || !tbl)) |
| 835 | return -EINVAL; |
| 836 | |
| 837 | *tbl = NULL; |
| 838 | geni_se_dev = dev_get_drvdata(rsc->wrapper_dev); |
| 839 | if (unlikely(!geni_se_dev)) |
| 840 | return -EPROBE_DEFER; |
| 841 | |
| 842 | if (geni_se_dev->clk_perf_tbl) { |
| 843 | *tbl = geni_se_dev->clk_perf_tbl; |
| 844 | return geni_se_dev->num_clk_levels; |
| 845 | } |
| 846 | |
| 847 | geni_se_dev->clk_perf_tbl = kzalloc(sizeof(*geni_se_dev->clk_perf_tbl) * |
| 848 | MAX_CLK_PERF_LEVEL, GFP_KERNEL); |
| 849 | if (!geni_se_dev->clk_perf_tbl) |
| 850 | return -ENOMEM; |
| 851 | |
| 852 | for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) { |
| 853 | geni_se_dev->clk_perf_tbl[i] = clk_round_rate(rsc->se_clk, |
| 854 | prev_freq + 1); |
| 855 | if (geni_se_dev->clk_perf_tbl[i] == prev_freq) { |
| 856 | geni_se_dev->clk_perf_tbl[i] = 0; |
| 857 | break; |
| 858 | } |
| 859 | prev_freq = geni_se_dev->clk_perf_tbl[i]; |
| 860 | } |
| 861 | geni_se_dev->num_clk_levels = i; |
| 862 | *tbl = geni_se_dev->clk_perf_tbl; |
| 863 | return geni_se_dev->num_clk_levels; |
| 864 | } |
| 865 | EXPORT_SYMBOL(geni_se_clk_tbl_get); |
| 866 | |
| 867 | /** |
| 868 | * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency |
| 869 | * @rsc: Resource for which the clock frequency is requested. |
| 870 | * @req_freq: Requested clock frequency. |
| 871 | * @index: Index of the resultant frequency in the table. |
| 872 | * @res_freq: Resultant frequency which matches or is closer to the |
| 873 | * requested frequency. |
| 874 | * @exact: Flag to indicate exact multiple requirement of the requested |
| 875 | * frequency . |
| 876 | * |
| 877 | * This function is called by the protocol drivers to determine the matching |
| 878 | * or closest frequency of the Serial Engine clock to be selected in order |
| 879 | * to meet the performance requirements. |
| 880 | * |
| 881 | * Return: 0 on success, standard Linux error codes on failure. |
| 882 | */ |
| 883 | int geni_se_clk_freq_match(struct se_geni_rsc *rsc, unsigned long req_freq, |
| 884 | unsigned int *index, unsigned long *res_freq, |
| 885 | bool exact) |
| 886 | { |
| 887 | unsigned long *tbl; |
| 888 | int num_clk_levels; |
| 889 | int i; |
| 890 | |
| 891 | num_clk_levels = geni_se_clk_tbl_get(rsc, &tbl); |
| 892 | if (num_clk_levels < 0) |
| 893 | return num_clk_levels; |
| 894 | |
| 895 | if (num_clk_levels == 0) |
| 896 | return -EFAULT; |
| 897 | |
| 898 | *res_freq = 0; |
| 899 | for (i = 0; i < num_clk_levels; i++) { |
| 900 | if (!(tbl[i] % req_freq)) { |
| 901 | *index = i; |
| 902 | *res_freq = tbl[i]; |
| 903 | return 0; |
| 904 | } |
| 905 | |
| 906 | if (!(*res_freq) || ((tbl[i] > *res_freq) && |
| 907 | (tbl[i] < req_freq))) { |
| 908 | *index = i; |
| 909 | *res_freq = tbl[i]; |
| 910 | } |
| 911 | } |
| 912 | |
| 913 | if (exact || !(*res_freq)) |
| 914 | return -ENOKEY; |
| 915 | |
| 916 | return 0; |
| 917 | } |
| 918 | EXPORT_SYMBOL(geni_se_clk_freq_match); |
| 919 | |
| 920 | /** |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 921 | * geni_se_tx_dma_prep() - Prepare the Serial Engine for TX DMA transfer |
| 922 | * @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped. |
| 923 | * @base: Base address of the SE register block. |
| 924 | * @tx_buf: Pointer to the TX buffer. |
| 925 | * @tx_len: Length of the TX buffer. |
| 926 | * @tx_dma: Pointer to store the mapped DMA address. |
| 927 | * |
| 928 | * This function is used to prepare the buffers for DMA TX. |
| 929 | * |
| 930 | * Return: 0 on success, standard Linux error codes on error/failure. |
| 931 | */ |
| 932 | int geni_se_tx_dma_prep(struct device *wrapper_dev, void __iomem *base, |
| 933 | void *tx_buf, int tx_len, dma_addr_t *tx_dma) |
| 934 | { |
| 935 | int ret; |
| 936 | |
| 937 | if (unlikely(!wrapper_dev || !base || !tx_buf || !tx_len || !tx_dma)) |
| 938 | return -EINVAL; |
| 939 | |
| 940 | ret = geni_se_iommu_map_buf(wrapper_dev, tx_dma, tx_buf, tx_len, |
| 941 | DMA_TO_DEVICE); |
| 942 | if (ret) |
| 943 | return ret; |
| 944 | |
| 945 | geni_write_reg(7, base, SE_DMA_TX_IRQ_EN_SET); |
| 946 | geni_write_reg((u32)(*tx_dma), base, SE_DMA_TX_PTR_L); |
| 947 | geni_write_reg((u32)((*tx_dma) >> 32), base, SE_DMA_TX_PTR_H); |
| 948 | geni_write_reg(1, base, SE_DMA_TX_ATTR); |
| 949 | geni_write_reg(tx_len, base, SE_DMA_TX_LEN); |
| 950 | return 0; |
| 951 | } |
| 952 | EXPORT_SYMBOL(geni_se_tx_dma_prep); |
| 953 | |
| 954 | /** |
| 955 | * geni_se_rx_dma_prep() - Prepare the Serial Engine for RX DMA transfer |
| 956 | * @wrapper_dev: QUPv3 Wrapper Device to which the RX buffer is mapped. |
| 957 | * @base: Base address of the SE register block. |
| 958 | * @rx_buf: Pointer to the RX buffer. |
| 959 | * @rx_len: Length of the RX buffer. |
| 960 | * @rx_dma: Pointer to store the mapped DMA address. |
| 961 | * |
| 962 | * This function is used to prepare the buffers for DMA RX. |
| 963 | * |
| 964 | * Return: 0 on success, standard Linux error codes on error/failure. |
| 965 | */ |
| 966 | int geni_se_rx_dma_prep(struct device *wrapper_dev, void __iomem *base, |
| 967 | void *rx_buf, int rx_len, dma_addr_t *rx_dma) |
| 968 | { |
| 969 | int ret; |
| 970 | |
| 971 | if (unlikely(!wrapper_dev || !base || !rx_buf || !rx_len || !rx_dma)) |
| 972 | return -EINVAL; |
| 973 | |
| 974 | ret = geni_se_iommu_map_buf(wrapper_dev, rx_dma, rx_buf, rx_len, |
| 975 | DMA_FROM_DEVICE); |
| 976 | if (ret) |
| 977 | return ret; |
| 978 | |
| 979 | geni_write_reg(7, base, SE_DMA_RX_IRQ_EN_SET); |
| 980 | geni_write_reg((u32)(*rx_dma), base, SE_DMA_RX_PTR_L); |
| 981 | geni_write_reg((u32)((*rx_dma) >> 32), base, SE_DMA_RX_PTR_H); |
| 982 | /* RX does not have EOT bit */ |
| 983 | geni_write_reg(0, base, SE_DMA_RX_ATTR); |
| 984 | geni_write_reg(rx_len, base, SE_DMA_RX_LEN); |
| 985 | return 0; |
| 986 | } |
| 987 | EXPORT_SYMBOL(geni_se_rx_dma_prep); |
| 988 | |
| 989 | /** |
| 990 | * geni_se_tx_dma_unprep() - Unprepare the Serial Engine after TX DMA transfer |
| 991 | * @wrapper_dev: QUPv3 Wrapper Device to which the RX buffer is mapped. |
| 992 | * @tx_dma: DMA address of the TX buffer. |
| 993 | * @tx_len: Length of the TX buffer. |
| 994 | * |
| 995 | * This function is used to unprepare the DMA buffers after DMA TX. |
| 996 | */ |
| 997 | void geni_se_tx_dma_unprep(struct device *wrapper_dev, |
| 998 | dma_addr_t tx_dma, int tx_len) |
| 999 | { |
| 1000 | if (tx_dma) |
| 1001 | geni_se_iommu_unmap_buf(wrapper_dev, &tx_dma, tx_len, |
| 1002 | DMA_TO_DEVICE); |
| 1003 | } |
| 1004 | EXPORT_SYMBOL(geni_se_tx_dma_unprep); |
| 1005 | |
| 1006 | /** |
| 1007 | * geni_se_rx_dma_unprep() - Unprepare the Serial Engine after RX DMA transfer |
| 1008 | * @wrapper_dev: QUPv3 Wrapper Device to which the RX buffer is mapped. |
| 1009 | * @rx_dma: DMA address of the RX buffer. |
| 1010 | * @rx_len: Length of the RX buffer. |
| 1011 | * |
| 1012 | * This function is used to unprepare the DMA buffers after DMA RX. |
| 1013 | */ |
| 1014 | void geni_se_rx_dma_unprep(struct device *wrapper_dev, |
| 1015 | dma_addr_t rx_dma, int rx_len) |
| 1016 | { |
| 1017 | if (rx_dma) |
| 1018 | geni_se_iommu_unmap_buf(wrapper_dev, &rx_dma, rx_len, |
| 1019 | DMA_FROM_DEVICE); |
| 1020 | } |
| 1021 | EXPORT_SYMBOL(geni_se_rx_dma_unprep); |
| 1022 | |
| 1023 | /** |
| 1024 | * geni_se_qupv3_hw_version() - Read the QUPv3 Hardware version |
| 1025 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 1026 | * @major: Buffer for Major Version field. |
| 1027 | * @minor: Buffer for Minor Version field. |
| 1028 | * @step: Buffer for Step Version field. |
| 1029 | * |
| 1030 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 1031 | */ |
| 1032 | int geni_se_qupv3_hw_version(struct device *wrapper_dev, unsigned int *major, |
| 1033 | unsigned int *minor, unsigned int *step) |
| 1034 | { |
| 1035 | unsigned int version; |
| 1036 | struct geni_se_device *geni_se_dev; |
| 1037 | |
| 1038 | if (!wrapper_dev || !major || !minor || !step) |
| 1039 | return -EINVAL; |
| 1040 | |
| 1041 | geni_se_dev = dev_get_drvdata(wrapper_dev); |
| 1042 | if (unlikely(!geni_se_dev)) |
| 1043 | return -ENODEV; |
| 1044 | |
| 1045 | version = geni_read_reg(geni_se_dev->base, QUPV3_HW_VER); |
| 1046 | *major = (version & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT; |
| 1047 | *minor = (version & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT; |
| 1048 | *step = version & HW_VER_STEP_MASK; |
| 1049 | return 0; |
| 1050 | } |
| 1051 | EXPORT_SYMBOL(geni_se_qupv3_hw_version); |
| 1052 | |
| 1053 | static int geni_se_iommu_map_and_attach(struct geni_se_device *geni_se_dev) |
| 1054 | { |
| 1055 | dma_addr_t va_start = GENI_SE_IOMMU_VA_START; |
| 1056 | size_t va_size = GENI_SE_IOMMU_VA_SIZE; |
| 1057 | int bypass = 1; |
| 1058 | struct device *cb_dev = geni_se_dev->cb_dev; |
| 1059 | |
| 1060 | mutex_lock(&geni_se_dev->iommu_lock); |
| 1061 | if (likely(geni_se_dev->iommu_map)) { |
| 1062 | mutex_unlock(&geni_se_dev->iommu_lock); |
| 1063 | return 0; |
| 1064 | } |
| 1065 | |
| 1066 | geni_se_dev->iommu_map = arm_iommu_create_mapping(&platform_bus_type, |
| 1067 | va_start, va_size); |
| 1068 | if (IS_ERR(geni_se_dev->iommu_map)) { |
| 1069 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 1070 | "%s:%s iommu_create_mapping failure\n", |
| 1071 | __func__, dev_name(cb_dev)); |
| 1072 | mutex_unlock(&geni_se_dev->iommu_lock); |
| 1073 | return PTR_ERR(geni_se_dev->iommu_map); |
| 1074 | } |
| 1075 | |
| 1076 | if (geni_se_dev->iommu_s1_bypass) { |
| 1077 | if (iommu_domain_set_attr(geni_se_dev->iommu_map->domain, |
| 1078 | DOMAIN_ATTR_S1_BYPASS, &bypass)) { |
| 1079 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 1080 | "%s:%s Couldn't bypass s1 translation\n", |
| 1081 | __func__, dev_name(cb_dev)); |
| 1082 | arm_iommu_release_mapping(geni_se_dev->iommu_map); |
| 1083 | geni_se_dev->iommu_map = NULL; |
| 1084 | mutex_unlock(&geni_se_dev->iommu_lock); |
| 1085 | return -EIO; |
| 1086 | } |
| 1087 | } |
| 1088 | |
| 1089 | if (arm_iommu_attach_device(cb_dev, geni_se_dev->iommu_map)) { |
| 1090 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 1091 | "%s:%s couldn't arm_iommu_attach_device\n", |
| 1092 | __func__, dev_name(cb_dev)); |
| 1093 | arm_iommu_release_mapping(geni_se_dev->iommu_map); |
| 1094 | geni_se_dev->iommu_map = NULL; |
| 1095 | mutex_unlock(&geni_se_dev->iommu_lock); |
| 1096 | return -EIO; |
| 1097 | } |
| 1098 | mutex_unlock(&geni_se_dev->iommu_lock); |
| 1099 | GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, "%s:%s successful\n", |
| 1100 | __func__, dev_name(cb_dev)); |
| 1101 | return 0; |
| 1102 | } |
| 1103 | |
| 1104 | /** |
| 1105 | * geni_se_iommu_map_buf() - Map a single buffer into QUPv3 context bank |
| 1106 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 1107 | * @iova: Pointer in which the mapped virtual address is stored. |
| 1108 | * @buf: Address of the buffer that needs to be mapped. |
| 1109 | * @size: Size of the buffer. |
| 1110 | * @dir: Direction of the DMA transfer. |
| 1111 | * |
| 1112 | * This function is used to map an already allocated buffer into the |
| 1113 | * QUPv3 context bank device space. |
| 1114 | * |
| 1115 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 1116 | */ |
| 1117 | int geni_se_iommu_map_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 1118 | void *buf, size_t size, enum dma_data_direction dir) |
| 1119 | { |
| 1120 | struct device *cb_dev; |
| 1121 | struct geni_se_device *geni_se_dev; |
| 1122 | |
| 1123 | if (!wrapper_dev || !iova || !buf || !size) |
| 1124 | return -EINVAL; |
| 1125 | |
| 1126 | *iova = DMA_ERROR_CODE; |
| 1127 | geni_se_dev = dev_get_drvdata(wrapper_dev); |
| 1128 | if (!geni_se_dev || !geni_se_dev->cb_dev) |
| 1129 | return -ENODEV; |
| 1130 | |
| 1131 | cb_dev = geni_se_dev->cb_dev; |
| 1132 | |
| 1133 | *iova = dma_map_single(cb_dev, buf, size, dir); |
| 1134 | if (dma_mapping_error(cb_dev, *iova)) |
| 1135 | return -EIO; |
| 1136 | return 0; |
| 1137 | } |
| 1138 | EXPORT_SYMBOL(geni_se_iommu_map_buf); |
| 1139 | |
| 1140 | /** |
| 1141 | * geni_se_iommu_alloc_buf() - Allocate & map a single buffer into QUPv3 |
| 1142 | * context bank |
| 1143 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 1144 | * @iova: Pointer in which the mapped virtual address is stored. |
| 1145 | * @size: Size of the buffer. |
| 1146 | * |
| 1147 | * This function is used to allocate a buffer and map it into the |
| 1148 | * QUPv3 context bank device space. |
| 1149 | * |
| 1150 | * Return: address of the buffer on success, NULL or ERR_PTR on |
| 1151 | * failure/error. |
| 1152 | */ |
| 1153 | void *geni_se_iommu_alloc_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 1154 | size_t size) |
| 1155 | { |
| 1156 | struct device *cb_dev; |
| 1157 | struct geni_se_device *geni_se_dev; |
| 1158 | void *buf = NULL; |
| 1159 | |
| 1160 | if (!wrapper_dev || !iova || !size) |
| 1161 | return ERR_PTR(-EINVAL); |
| 1162 | |
| 1163 | *iova = DMA_ERROR_CODE; |
| 1164 | geni_se_dev = dev_get_drvdata(wrapper_dev); |
| 1165 | if (!geni_se_dev || !geni_se_dev->cb_dev) |
| 1166 | return ERR_PTR(-ENODEV); |
| 1167 | |
| 1168 | cb_dev = geni_se_dev->cb_dev; |
| 1169 | |
| 1170 | buf = dma_alloc_coherent(cb_dev, size, iova, GFP_KERNEL); |
| 1171 | if (!buf) |
| 1172 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 1173 | "%s: Failed dma_alloc_coherent\n", __func__); |
| 1174 | return buf; |
| 1175 | } |
| 1176 | EXPORT_SYMBOL(geni_se_iommu_alloc_buf); |
| 1177 | |
| 1178 | /** |
| 1179 | * geni_se_iommu_unmap_buf() - Unmap a single buffer from QUPv3 context bank |
| 1180 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 1181 | * @iova: Pointer in which the mapped virtual address is stored. |
| 1182 | * @size: Size of the buffer. |
| 1183 | * @dir: Direction of the DMA transfer. |
| 1184 | * |
| 1185 | * This function is used to unmap an already mapped buffer from the |
| 1186 | * QUPv3 context bank device space. |
| 1187 | * |
| 1188 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 1189 | */ |
| 1190 | int geni_se_iommu_unmap_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 1191 | size_t size, enum dma_data_direction dir) |
| 1192 | { |
| 1193 | struct device *cb_dev; |
| 1194 | struct geni_se_device *geni_se_dev; |
| 1195 | |
| 1196 | if (!wrapper_dev || !iova || !size) |
| 1197 | return -EINVAL; |
| 1198 | |
| 1199 | geni_se_dev = dev_get_drvdata(wrapper_dev); |
| 1200 | if (!geni_se_dev || !geni_se_dev->cb_dev) |
| 1201 | return -ENODEV; |
| 1202 | |
| 1203 | cb_dev = geni_se_dev->cb_dev; |
| 1204 | |
| 1205 | dma_unmap_single(cb_dev, *iova, size, dir); |
| 1206 | return 0; |
| 1207 | } |
| 1208 | EXPORT_SYMBOL(geni_se_iommu_unmap_buf); |
| 1209 | |
| 1210 | /** |
| 1211 | * geni_se_iommu_free_buf() - Unmap & free a single buffer from QUPv3 |
| 1212 | * context bank |
| 1213 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 1214 | * @iova: Pointer in which the mapped virtual address is stored. |
| 1215 | * @buf: Address of the buffer. |
| 1216 | * @size: Size of the buffer. |
| 1217 | * |
| 1218 | * This function is used to unmap and free a buffer from the |
| 1219 | * QUPv3 context bank device space. |
| 1220 | * |
| 1221 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 1222 | */ |
| 1223 | int geni_se_iommu_free_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 1224 | void *buf, size_t size) |
| 1225 | { |
| 1226 | struct device *cb_dev; |
| 1227 | struct geni_se_device *geni_se_dev; |
| 1228 | |
| 1229 | if (!wrapper_dev || !iova || !buf || !size) |
| 1230 | return -EINVAL; |
| 1231 | |
| 1232 | geni_se_dev = dev_get_drvdata(wrapper_dev); |
| 1233 | if (!geni_se_dev || !geni_se_dev->cb_dev) |
| 1234 | return -ENODEV; |
| 1235 | |
| 1236 | cb_dev = geni_se_dev->cb_dev; |
| 1237 | |
| 1238 | dma_free_coherent(cb_dev, size, buf, *iova); |
| 1239 | return 0; |
| 1240 | } |
| 1241 | EXPORT_SYMBOL(geni_se_iommu_free_buf); |
| 1242 | |
| 1243 | static const struct of_device_id geni_se_dt_match[] = { |
| 1244 | { .compatible = "qcom,qupv3-geni-se", }, |
| 1245 | { .compatible = "qcom,qupv3-geni-se-cb", }, |
| 1246 | {} |
| 1247 | }; |
| 1248 | |
| 1249 | static int geni_se_iommu_probe(struct device *dev) |
| 1250 | { |
| 1251 | struct geni_se_device *geni_se_dev; |
| 1252 | |
| 1253 | if (unlikely(!dev->parent)) { |
| 1254 | dev_err(dev, "%s no parent for this device\n", __func__); |
| 1255 | return -EINVAL; |
| 1256 | } |
| 1257 | |
| 1258 | geni_se_dev = dev_get_drvdata(dev->parent); |
| 1259 | if (unlikely(!geni_se_dev)) { |
| 1260 | dev_err(dev, "%s geni_se_dev not found\n", __func__); |
| 1261 | return -EINVAL; |
| 1262 | } |
| 1263 | geni_se_dev->cb_dev = dev; |
| 1264 | |
| 1265 | GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, |
| 1266 | "%s: Probe successful\n", __func__); |
| 1267 | return 0; |
| 1268 | } |
| 1269 | |
| 1270 | static int geni_se_probe(struct platform_device *pdev) |
| 1271 | { |
| 1272 | int ret; |
| 1273 | struct device *dev = &pdev->dev; |
| 1274 | struct resource *res; |
| 1275 | struct geni_se_device *geni_se_dev; |
| 1276 | |
| 1277 | if (of_device_is_compatible(dev->of_node, "qcom,qupv3-geni-se-cb")) |
| 1278 | return geni_se_iommu_probe(dev); |
| 1279 | |
| 1280 | geni_se_dev = devm_kzalloc(dev, sizeof(*geni_se_dev), GFP_KERNEL); |
| 1281 | if (!geni_se_dev) |
| 1282 | return -ENOMEM; |
| 1283 | |
| 1284 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1285 | if (!res) { |
| 1286 | dev_err(dev, "%s: Mandatory resource info not found\n", |
| 1287 | __func__); |
| 1288 | devm_kfree(dev, geni_se_dev); |
| 1289 | return -EINVAL; |
| 1290 | } |
| 1291 | |
| 1292 | geni_se_dev->base = devm_ioremap_resource(dev, res); |
| 1293 | if (IS_ERR_OR_NULL(geni_se_dev->base)) { |
| 1294 | dev_err(dev, "%s: Error mapping the resource\n", __func__); |
| 1295 | devm_kfree(dev, geni_se_dev); |
| 1296 | return -EFAULT; |
| 1297 | } |
| 1298 | |
| 1299 | geni_se_dev->dev = dev; |
| 1300 | ret = of_property_read_u32(dev->of_node, "qcom,bus-mas-id", |
| 1301 | &geni_se_dev->bus_mas_id); |
| 1302 | if (ret) { |
| 1303 | dev_err(dev, "%s: Error missing bus master id\n", __func__); |
| 1304 | devm_iounmap(dev, geni_se_dev->base); |
| 1305 | devm_kfree(dev, geni_se_dev); |
| 1306 | } |
| 1307 | ret = of_property_read_u32(dev->of_node, "qcom,bus-slv-id", |
| 1308 | &geni_se_dev->bus_slv_id); |
| 1309 | if (ret) { |
| 1310 | dev_err(dev, "%s: Error missing bus slave id\n", __func__); |
| 1311 | devm_iounmap(dev, geni_se_dev->base); |
| 1312 | devm_kfree(dev, geni_se_dev); |
| 1313 | } |
| 1314 | |
| 1315 | geni_se_dev->iommu_s1_bypass = of_property_read_bool(dev->of_node, |
| 1316 | "qcom,iommu-s1-bypass"); |
| 1317 | geni_se_dev->bus_bw_set = default_bus_bw_set; |
| 1318 | geni_se_dev->bus_bw_set_size = ARRAY_SIZE(default_bus_bw_set); |
| 1319 | mutex_init(&geni_se_dev->iommu_lock); |
| 1320 | INIT_LIST_HEAD(&geni_se_dev->ab_list_head); |
| 1321 | INIT_LIST_HEAD(&geni_se_dev->ib_list_head); |
| 1322 | spin_lock_init(&geni_se_dev->ab_ib_lock); |
| 1323 | geni_se_dev->log_ctx = ipc_log_context_create(NUM_LOG_PAGES, |
| 1324 | dev_name(geni_se_dev->dev), 0); |
| 1325 | if (!geni_se_dev->log_ctx) |
| 1326 | dev_err(dev, "%s Failed to allocate log context\n", __func__); |
| 1327 | dev_set_drvdata(dev, geni_se_dev); |
| 1328 | |
| 1329 | ret = of_platform_populate(dev->of_node, geni_se_dt_match, NULL, dev); |
| 1330 | if (ret) { |
| 1331 | dev_err(dev, "%s: Error populating children\n", __func__); |
| 1332 | devm_iounmap(dev, geni_se_dev->base); |
| 1333 | devm_kfree(dev, geni_se_dev); |
| 1334 | } |
| 1335 | |
| 1336 | GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, |
| 1337 | "%s: Probe successful\n", __func__); |
| 1338 | return ret; |
| 1339 | } |
| 1340 | |
| 1341 | static int geni_se_remove(struct platform_device *pdev) |
| 1342 | { |
| 1343 | struct device *dev = &pdev->dev; |
| 1344 | struct geni_se_device *geni_se_dev = dev_get_drvdata(dev); |
| 1345 | |
| 1346 | if (likely(!IS_ERR_OR_NULL(geni_se_dev->iommu_map))) { |
| 1347 | arm_iommu_detach_device(geni_se_dev->cb_dev); |
| 1348 | arm_iommu_release_mapping(geni_se_dev->iommu_map); |
| 1349 | } |
| 1350 | ipc_log_context_destroy(geni_se_dev->log_ctx); |
| 1351 | devm_iounmap(dev, geni_se_dev->base); |
| 1352 | devm_kfree(dev, geni_se_dev); |
| 1353 | return 0; |
| 1354 | } |
| 1355 | |
| 1356 | static struct platform_driver geni_se_driver = { |
| 1357 | .driver = { |
| 1358 | .name = "qupv3_geni_se", |
| 1359 | .of_match_table = geni_se_dt_match, |
| 1360 | }, |
| 1361 | .probe = geni_se_probe, |
| 1362 | .remove = geni_se_remove, |
| 1363 | }; |
| 1364 | |
| 1365 | static int __init geni_se_driver_init(void) |
| 1366 | { |
| 1367 | return platform_driver_register(&geni_se_driver); |
| 1368 | } |
| 1369 | arch_initcall(geni_se_driver_init); |
| 1370 | |
| 1371 | static void __exit geni_se_driver_exit(void) |
| 1372 | { |
| 1373 | platform_driver_unregister(&geni_se_driver); |
| 1374 | } |
| 1375 | module_exit(geni_se_driver_exit); |
| 1376 | |
| 1377 | MODULE_DESCRIPTION("GENI Serial Engine Driver"); |
| 1378 | MODULE_LICENSE("GPL v2"); |