Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This software is licensed under the terms of the GNU General Public |
| 5 | * License version 2, as published by the Free Software Foundation, and |
| 6 | * may be copied, distributed, and modified under those terms. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/bitops.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/of.h> |
| 21 | #include <linux/of_device.h> |
| 22 | #include <linux/clk-provider.h> |
| 23 | #include <linux/regmap.h> |
| 24 | #include <linux/reset-controller.h> |
| 25 | |
| 26 | #include <dt-bindings/clock/qcom,mmcc-msm8960.h> |
| 27 | #include <dt-bindings/reset/qcom,mmcc-msm8960.h> |
| 28 | |
Stephen Boyd | 49fc825 | 2014-03-21 17:59:37 -0700 | [diff] [blame] | 29 | #include "common.h" |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 30 | #include "clk-regmap.h" |
| 31 | #include "clk-pll.h" |
| 32 | #include "clk-rcg.h" |
| 33 | #include "clk-branch.h" |
| 34 | #include "reset.h" |
| 35 | |
| 36 | #define P_PXO 0 |
| 37 | #define P_PLL8 1 |
| 38 | #define P_PLL2 2 |
| 39 | #define P_PLL3 3 |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 40 | #define P_PLL15 3 |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 41 | |
Stephen Boyd | ff20783 | 2014-07-08 18:36:06 -0700 | [diff] [blame] | 42 | #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 43 | |
| 44 | static u8 mmcc_pxo_pll8_pll2_map[] = { |
| 45 | [P_PXO] = 0, |
| 46 | [P_PLL8] = 2, |
| 47 | [P_PLL2] = 1, |
| 48 | }; |
| 49 | |
| 50 | static const char *mmcc_pxo_pll8_pll2[] = { |
| 51 | "pxo", |
| 52 | "pll8_vote", |
| 53 | "pll2", |
| 54 | }; |
| 55 | |
| 56 | static u8 mmcc_pxo_pll8_pll2_pll3_map[] = { |
| 57 | [P_PXO] = 0, |
| 58 | [P_PLL8] = 2, |
| 59 | [P_PLL2] = 1, |
| 60 | [P_PLL3] = 3, |
| 61 | }; |
| 62 | |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 63 | static const char *mmcc_pxo_pll8_pll2_pll15[] = { |
| 64 | "pxo", |
| 65 | "pll8_vote", |
| 66 | "pll2", |
| 67 | "pll15", |
| 68 | }; |
| 69 | |
| 70 | static u8 mmcc_pxo_pll8_pll2_pll15_map[] = { |
| 71 | [P_PXO] = 0, |
| 72 | [P_PLL8] = 2, |
| 73 | [P_PLL2] = 1, |
| 74 | [P_PLL15] = 3, |
| 75 | }; |
| 76 | |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 77 | static const char *mmcc_pxo_pll8_pll2_pll3[] = { |
| 78 | "pxo", |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 79 | "pll8_vote", |
Stephen Boyd | ff20783 | 2014-07-08 18:36:06 -0700 | [diff] [blame] | 80 | "pll2", |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 81 | "pll3", |
| 82 | }; |
| 83 | |
| 84 | static struct clk_pll pll2 = { |
| 85 | .l_reg = 0x320, |
| 86 | .m_reg = 0x324, |
| 87 | .n_reg = 0x328, |
| 88 | .config_reg = 0x32c, |
| 89 | .mode_reg = 0x31c, |
| 90 | .status_reg = 0x334, |
| 91 | .status_bit = 16, |
| 92 | .clkr.hw.init = &(struct clk_init_data){ |
| 93 | .name = "pll2", |
| 94 | .parent_names = (const char *[]){ "pxo" }, |
| 95 | .num_parents = 1, |
| 96 | .ops = &clk_pll_ops, |
| 97 | }, |
| 98 | }; |
| 99 | |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 100 | static struct clk_pll pll15 = { |
| 101 | .l_reg = 0x33c, |
| 102 | .m_reg = 0x340, |
| 103 | .n_reg = 0x344, |
| 104 | .config_reg = 0x348, |
| 105 | .mode_reg = 0x338, |
| 106 | .status_reg = 0x350, |
| 107 | .status_bit = 16, |
| 108 | .clkr.hw.init = &(struct clk_init_data){ |
| 109 | .name = "pll15", |
| 110 | .parent_names = (const char *[]){ "pxo" }, |
| 111 | .num_parents = 1, |
| 112 | .ops = &clk_pll_ops, |
| 113 | }, |
| 114 | }; |
| 115 | |
| 116 | static const struct pll_config pll15_config = { |
| 117 | .l = 33, |
| 118 | .m = 1, |
| 119 | .n = 3, |
| 120 | .vco_val = 0x2 << 16, |
| 121 | .vco_mask = 0x3 << 16, |
| 122 | .pre_div_val = 0x0, |
| 123 | .pre_div_mask = BIT(19), |
| 124 | .post_div_val = 0x0, |
| 125 | .post_div_mask = 0x3 << 20, |
| 126 | .mn_ena_mask = BIT(22), |
| 127 | .main_output_mask = BIT(23), |
| 128 | }; |
| 129 | |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 130 | static struct freq_tbl clk_tbl_cam[] = { |
| 131 | { 6000000, P_PLL8, 4, 1, 16 }, |
| 132 | { 8000000, P_PLL8, 4, 1, 12 }, |
| 133 | { 12000000, P_PLL8, 4, 1, 8 }, |
| 134 | { 16000000, P_PLL8, 4, 1, 6 }, |
| 135 | { 19200000, P_PLL8, 4, 1, 5 }, |
| 136 | { 24000000, P_PLL8, 4, 1, 4 }, |
| 137 | { 32000000, P_PLL8, 4, 1, 3 }, |
| 138 | { 48000000, P_PLL8, 4, 1, 2 }, |
| 139 | { 64000000, P_PLL8, 3, 1, 2 }, |
| 140 | { 96000000, P_PLL8, 4, 0, 0 }, |
| 141 | { 128000000, P_PLL8, 3, 0, 0 }, |
| 142 | { } |
| 143 | }; |
| 144 | |
| 145 | static struct clk_rcg camclk0_src = { |
| 146 | .ns_reg = 0x0148, |
| 147 | .md_reg = 0x0144, |
| 148 | .mn = { |
| 149 | .mnctr_en_bit = 5, |
| 150 | .mnctr_reset_bit = 8, |
| 151 | .reset_in_cc = true, |
| 152 | .mnctr_mode_shift = 6, |
| 153 | .n_val_shift = 24, |
| 154 | .m_val_shift = 8, |
| 155 | .width = 8, |
| 156 | }, |
| 157 | .p = { |
| 158 | .pre_div_shift = 14, |
| 159 | .pre_div_width = 2, |
| 160 | }, |
| 161 | .s = { |
| 162 | .src_sel_shift = 0, |
| 163 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 164 | }, |
| 165 | .freq_tbl = clk_tbl_cam, |
| 166 | .clkr = { |
| 167 | .enable_reg = 0x0140, |
| 168 | .enable_mask = BIT(2), |
| 169 | .hw.init = &(struct clk_init_data){ |
| 170 | .name = "camclk0_src", |
| 171 | .parent_names = mmcc_pxo_pll8_pll2, |
| 172 | .num_parents = 3, |
| 173 | .ops = &clk_rcg_ops, |
| 174 | }, |
| 175 | }, |
| 176 | }; |
| 177 | |
| 178 | static struct clk_branch camclk0_clk = { |
| 179 | .halt_reg = 0x01e8, |
| 180 | .halt_bit = 15, |
| 181 | .clkr = { |
| 182 | .enable_reg = 0x0140, |
| 183 | .enable_mask = BIT(0), |
| 184 | .hw.init = &(struct clk_init_data){ |
| 185 | .name = "camclk0_clk", |
| 186 | .parent_names = (const char *[]){ "camclk0_src" }, |
| 187 | .num_parents = 1, |
| 188 | .ops = &clk_branch_ops, |
| 189 | }, |
| 190 | }, |
| 191 | |
| 192 | }; |
| 193 | |
| 194 | static struct clk_rcg camclk1_src = { |
| 195 | .ns_reg = 0x015c, |
| 196 | .md_reg = 0x0158, |
| 197 | .mn = { |
| 198 | .mnctr_en_bit = 5, |
| 199 | .mnctr_reset_bit = 8, |
| 200 | .reset_in_cc = true, |
| 201 | .mnctr_mode_shift = 6, |
| 202 | .n_val_shift = 24, |
| 203 | .m_val_shift = 8, |
| 204 | .width = 8, |
| 205 | }, |
| 206 | .p = { |
| 207 | .pre_div_shift = 14, |
| 208 | .pre_div_width = 2, |
| 209 | }, |
| 210 | .s = { |
| 211 | .src_sel_shift = 0, |
| 212 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 213 | }, |
| 214 | .freq_tbl = clk_tbl_cam, |
| 215 | .clkr = { |
| 216 | .enable_reg = 0x0154, |
| 217 | .enable_mask = BIT(2), |
| 218 | .hw.init = &(struct clk_init_data){ |
| 219 | .name = "camclk1_src", |
| 220 | .parent_names = mmcc_pxo_pll8_pll2, |
| 221 | .num_parents = 3, |
| 222 | .ops = &clk_rcg_ops, |
| 223 | }, |
| 224 | }, |
| 225 | }; |
| 226 | |
| 227 | static struct clk_branch camclk1_clk = { |
| 228 | .halt_reg = 0x01e8, |
| 229 | .halt_bit = 16, |
| 230 | .clkr = { |
| 231 | .enable_reg = 0x0154, |
| 232 | .enable_mask = BIT(0), |
| 233 | .hw.init = &(struct clk_init_data){ |
| 234 | .name = "camclk1_clk", |
| 235 | .parent_names = (const char *[]){ "camclk1_src" }, |
| 236 | .num_parents = 1, |
| 237 | .ops = &clk_branch_ops, |
| 238 | }, |
| 239 | }, |
| 240 | |
| 241 | }; |
| 242 | |
| 243 | static struct clk_rcg camclk2_src = { |
| 244 | .ns_reg = 0x0228, |
| 245 | .md_reg = 0x0224, |
| 246 | .mn = { |
| 247 | .mnctr_en_bit = 5, |
| 248 | .mnctr_reset_bit = 8, |
| 249 | .reset_in_cc = true, |
| 250 | .mnctr_mode_shift = 6, |
| 251 | .n_val_shift = 24, |
| 252 | .m_val_shift = 8, |
| 253 | .width = 8, |
| 254 | }, |
| 255 | .p = { |
| 256 | .pre_div_shift = 14, |
| 257 | .pre_div_width = 2, |
| 258 | }, |
| 259 | .s = { |
| 260 | .src_sel_shift = 0, |
| 261 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 262 | }, |
| 263 | .freq_tbl = clk_tbl_cam, |
| 264 | .clkr = { |
| 265 | .enable_reg = 0x0220, |
| 266 | .enable_mask = BIT(2), |
| 267 | .hw.init = &(struct clk_init_data){ |
| 268 | .name = "camclk2_src", |
| 269 | .parent_names = mmcc_pxo_pll8_pll2, |
| 270 | .num_parents = 3, |
| 271 | .ops = &clk_rcg_ops, |
| 272 | }, |
| 273 | }, |
| 274 | }; |
| 275 | |
| 276 | static struct clk_branch camclk2_clk = { |
| 277 | .halt_reg = 0x01e8, |
| 278 | .halt_bit = 16, |
| 279 | .clkr = { |
| 280 | .enable_reg = 0x0220, |
| 281 | .enable_mask = BIT(0), |
| 282 | .hw.init = &(struct clk_init_data){ |
| 283 | .name = "camclk2_clk", |
| 284 | .parent_names = (const char *[]){ "camclk2_src" }, |
| 285 | .num_parents = 1, |
| 286 | .ops = &clk_branch_ops, |
| 287 | }, |
| 288 | }, |
| 289 | |
| 290 | }; |
| 291 | |
| 292 | static struct freq_tbl clk_tbl_csi[] = { |
| 293 | { 27000000, P_PXO, 1, 0, 0 }, |
| 294 | { 85330000, P_PLL8, 1, 2, 9 }, |
| 295 | { 177780000, P_PLL2, 1, 2, 9 }, |
| 296 | { } |
| 297 | }; |
| 298 | |
| 299 | static struct clk_rcg csi0_src = { |
| 300 | .ns_reg = 0x0048, |
| 301 | .md_reg = 0x0044, |
| 302 | .mn = { |
| 303 | .mnctr_en_bit = 5, |
| 304 | .mnctr_reset_bit = 7, |
| 305 | .mnctr_mode_shift = 6, |
| 306 | .n_val_shift = 24, |
| 307 | .m_val_shift = 8, |
| 308 | .width = 8, |
| 309 | }, |
| 310 | .p = { |
| 311 | .pre_div_shift = 14, |
| 312 | .pre_div_width = 2, |
| 313 | }, |
| 314 | .s = { |
| 315 | .src_sel_shift = 0, |
| 316 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 317 | }, |
| 318 | .freq_tbl = clk_tbl_csi, |
| 319 | .clkr = { |
| 320 | .enable_reg = 0x0040, |
| 321 | .enable_mask = BIT(2), |
| 322 | .hw.init = &(struct clk_init_data){ |
| 323 | .name = "csi0_src", |
| 324 | .parent_names = mmcc_pxo_pll8_pll2, |
| 325 | .num_parents = 3, |
| 326 | .ops = &clk_rcg_ops, |
| 327 | }, |
| 328 | }, |
| 329 | }; |
| 330 | |
| 331 | static struct clk_branch csi0_clk = { |
| 332 | .halt_reg = 0x01cc, |
| 333 | .halt_bit = 13, |
| 334 | .clkr = { |
| 335 | .enable_reg = 0x0040, |
| 336 | .enable_mask = BIT(0), |
| 337 | .hw.init = &(struct clk_init_data){ |
| 338 | .parent_names = (const char *[]){ "csi0_src" }, |
| 339 | .num_parents = 1, |
| 340 | .name = "csi0_clk", |
| 341 | .ops = &clk_branch_ops, |
| 342 | .flags = CLK_SET_RATE_PARENT, |
| 343 | }, |
| 344 | }, |
| 345 | }; |
| 346 | |
| 347 | static struct clk_branch csi0_phy_clk = { |
| 348 | .halt_reg = 0x01e8, |
| 349 | .halt_bit = 9, |
| 350 | .clkr = { |
| 351 | .enable_reg = 0x0040, |
| 352 | .enable_mask = BIT(8), |
| 353 | .hw.init = &(struct clk_init_data){ |
| 354 | .parent_names = (const char *[]){ "csi0_src" }, |
| 355 | .num_parents = 1, |
| 356 | .name = "csi0_phy_clk", |
| 357 | .ops = &clk_branch_ops, |
| 358 | .flags = CLK_SET_RATE_PARENT, |
| 359 | }, |
| 360 | }, |
| 361 | }; |
| 362 | |
| 363 | static struct clk_rcg csi1_src = { |
| 364 | .ns_reg = 0x0010, |
| 365 | .md_reg = 0x0028, |
| 366 | .mn = { |
| 367 | .mnctr_en_bit = 5, |
| 368 | .mnctr_reset_bit = 7, |
| 369 | .mnctr_mode_shift = 6, |
| 370 | .n_val_shift = 24, |
| 371 | .m_val_shift = 8, |
| 372 | .width = 8, |
| 373 | }, |
| 374 | .p = { |
| 375 | .pre_div_shift = 14, |
| 376 | .pre_div_width = 2, |
| 377 | }, |
| 378 | .s = { |
| 379 | .src_sel_shift = 0, |
| 380 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 381 | }, |
| 382 | .freq_tbl = clk_tbl_csi, |
| 383 | .clkr = { |
| 384 | .enable_reg = 0x0024, |
| 385 | .enable_mask = BIT(2), |
| 386 | .hw.init = &(struct clk_init_data){ |
| 387 | .name = "csi1_src", |
| 388 | .parent_names = mmcc_pxo_pll8_pll2, |
| 389 | .num_parents = 3, |
| 390 | .ops = &clk_rcg_ops, |
| 391 | }, |
| 392 | }, |
| 393 | }; |
| 394 | |
| 395 | static struct clk_branch csi1_clk = { |
| 396 | .halt_reg = 0x01cc, |
| 397 | .halt_bit = 14, |
| 398 | .clkr = { |
| 399 | .enable_reg = 0x0024, |
| 400 | .enable_mask = BIT(0), |
| 401 | .hw.init = &(struct clk_init_data){ |
| 402 | .parent_names = (const char *[]){ "csi1_src" }, |
| 403 | .num_parents = 1, |
| 404 | .name = "csi1_clk", |
| 405 | .ops = &clk_branch_ops, |
| 406 | .flags = CLK_SET_RATE_PARENT, |
| 407 | }, |
| 408 | }, |
| 409 | }; |
| 410 | |
| 411 | static struct clk_branch csi1_phy_clk = { |
| 412 | .halt_reg = 0x01e8, |
| 413 | .halt_bit = 10, |
| 414 | .clkr = { |
| 415 | .enable_reg = 0x0024, |
| 416 | .enable_mask = BIT(8), |
| 417 | .hw.init = &(struct clk_init_data){ |
| 418 | .parent_names = (const char *[]){ "csi1_src" }, |
| 419 | .num_parents = 1, |
| 420 | .name = "csi1_phy_clk", |
| 421 | .ops = &clk_branch_ops, |
| 422 | .flags = CLK_SET_RATE_PARENT, |
| 423 | }, |
| 424 | }, |
| 425 | }; |
| 426 | |
| 427 | static struct clk_rcg csi2_src = { |
| 428 | .ns_reg = 0x0234, |
| 429 | .md_reg = 0x022c, |
| 430 | .mn = { |
| 431 | .mnctr_en_bit = 5, |
| 432 | .mnctr_reset_bit = 7, |
| 433 | .mnctr_mode_shift = 6, |
| 434 | .n_val_shift = 24, |
| 435 | .m_val_shift = 8, |
| 436 | .width = 8, |
| 437 | }, |
| 438 | .p = { |
| 439 | .pre_div_shift = 14, |
| 440 | .pre_div_width = 2, |
| 441 | }, |
| 442 | .s = { |
| 443 | .src_sel_shift = 0, |
| 444 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 445 | }, |
| 446 | .freq_tbl = clk_tbl_csi, |
| 447 | .clkr = { |
| 448 | .enable_reg = 0x022c, |
| 449 | .enable_mask = BIT(2), |
| 450 | .hw.init = &(struct clk_init_data){ |
| 451 | .name = "csi2_src", |
| 452 | .parent_names = mmcc_pxo_pll8_pll2, |
| 453 | .num_parents = 3, |
| 454 | .ops = &clk_rcg_ops, |
| 455 | }, |
| 456 | }, |
| 457 | }; |
| 458 | |
| 459 | static struct clk_branch csi2_clk = { |
| 460 | .halt_reg = 0x01cc, |
| 461 | .halt_bit = 29, |
| 462 | .clkr = { |
| 463 | .enable_reg = 0x022c, |
| 464 | .enable_mask = BIT(0), |
| 465 | .hw.init = &(struct clk_init_data){ |
| 466 | .parent_names = (const char *[]){ "csi2_src" }, |
| 467 | .num_parents = 1, |
| 468 | .name = "csi2_clk", |
| 469 | .ops = &clk_branch_ops, |
| 470 | .flags = CLK_SET_RATE_PARENT, |
| 471 | }, |
| 472 | }, |
| 473 | }; |
| 474 | |
| 475 | static struct clk_branch csi2_phy_clk = { |
| 476 | .halt_reg = 0x01e8, |
| 477 | .halt_bit = 29, |
| 478 | .clkr = { |
| 479 | .enable_reg = 0x022c, |
| 480 | .enable_mask = BIT(8), |
| 481 | .hw.init = &(struct clk_init_data){ |
| 482 | .parent_names = (const char *[]){ "csi2_src" }, |
| 483 | .num_parents = 1, |
| 484 | .name = "csi2_phy_clk", |
| 485 | .ops = &clk_branch_ops, |
| 486 | .flags = CLK_SET_RATE_PARENT, |
| 487 | }, |
| 488 | }, |
| 489 | }; |
| 490 | |
| 491 | struct clk_pix_rdi { |
| 492 | u32 s_reg; |
| 493 | u32 s_mask; |
| 494 | u32 s2_reg; |
| 495 | u32 s2_mask; |
| 496 | struct clk_regmap clkr; |
| 497 | }; |
| 498 | |
| 499 | #define to_clk_pix_rdi(_hw) \ |
| 500 | container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr) |
| 501 | |
| 502 | static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) |
| 503 | { |
| 504 | int i; |
| 505 | int ret = 0; |
| 506 | u32 val; |
| 507 | struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); |
| 508 | struct clk *clk = hw->clk; |
| 509 | int num_parents = __clk_get_num_parents(hw->clk); |
| 510 | |
| 511 | /* |
| 512 | * These clocks select three inputs via two muxes. One mux selects |
| 513 | * between csi0 and csi1 and the second mux selects between that mux's |
| 514 | * output and csi2. The source and destination selections for each |
| 515 | * mux must be clocking for the switch to succeed so just turn on |
| 516 | * all three sources because it's easier than figuring out what source |
| 517 | * needs to be on at what time. |
| 518 | */ |
| 519 | for (i = 0; i < num_parents; i++) { |
| 520 | ret = clk_prepare_enable(clk_get_parent_by_index(clk, i)); |
| 521 | if (ret) |
| 522 | goto err; |
| 523 | } |
| 524 | |
| 525 | if (index == 2) |
| 526 | val = rdi->s2_mask; |
| 527 | else |
| 528 | val = 0; |
| 529 | regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val); |
| 530 | /* |
| 531 | * Wait at least 6 cycles of slowest clock |
| 532 | * for the glitch-free MUX to fully switch sources. |
| 533 | */ |
| 534 | udelay(1); |
| 535 | |
| 536 | if (index == 1) |
| 537 | val = rdi->s_mask; |
| 538 | else |
| 539 | val = 0; |
| 540 | regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val); |
| 541 | /* |
| 542 | * Wait at least 6 cycles of slowest clock |
| 543 | * for the glitch-free MUX to fully switch sources. |
| 544 | */ |
| 545 | udelay(1); |
| 546 | |
| 547 | err: |
| 548 | for (i--; i >= 0; i--) |
| 549 | clk_disable_unprepare(clk_get_parent_by_index(clk, i)); |
| 550 | |
| 551 | return ret; |
| 552 | } |
| 553 | |
| 554 | static u8 pix_rdi_get_parent(struct clk_hw *hw) |
| 555 | { |
| 556 | u32 val; |
| 557 | struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); |
| 558 | |
| 559 | |
| 560 | regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val); |
| 561 | if (val & rdi->s2_mask) |
| 562 | return 2; |
| 563 | |
| 564 | regmap_read(rdi->clkr.regmap, rdi->s_reg, &val); |
| 565 | if (val & rdi->s_mask) |
| 566 | return 1; |
| 567 | |
| 568 | return 0; |
| 569 | } |
| 570 | |
| 571 | static const struct clk_ops clk_ops_pix_rdi = { |
| 572 | .enable = clk_enable_regmap, |
| 573 | .disable = clk_disable_regmap, |
| 574 | .set_parent = pix_rdi_set_parent, |
| 575 | .get_parent = pix_rdi_get_parent, |
| 576 | .determine_rate = __clk_mux_determine_rate, |
| 577 | }; |
| 578 | |
| 579 | static const char *pix_rdi_parents[] = { |
| 580 | "csi0_clk", |
| 581 | "csi1_clk", |
| 582 | "csi2_clk", |
| 583 | }; |
| 584 | |
| 585 | static struct clk_pix_rdi csi_pix_clk = { |
| 586 | .s_reg = 0x0058, |
| 587 | .s_mask = BIT(25), |
| 588 | .s2_reg = 0x0238, |
| 589 | .s2_mask = BIT(13), |
| 590 | .clkr = { |
| 591 | .enable_reg = 0x0058, |
| 592 | .enable_mask = BIT(26), |
| 593 | .hw.init = &(struct clk_init_data){ |
| 594 | .name = "csi_pix_clk", |
| 595 | .parent_names = pix_rdi_parents, |
| 596 | .num_parents = 3, |
| 597 | .ops = &clk_ops_pix_rdi, |
| 598 | }, |
| 599 | }, |
| 600 | }; |
| 601 | |
| 602 | static struct clk_pix_rdi csi_pix1_clk = { |
| 603 | .s_reg = 0x0238, |
| 604 | .s_mask = BIT(8), |
| 605 | .s2_reg = 0x0238, |
| 606 | .s2_mask = BIT(9), |
| 607 | .clkr = { |
| 608 | .enable_reg = 0x0238, |
| 609 | .enable_mask = BIT(10), |
| 610 | .hw.init = &(struct clk_init_data){ |
| 611 | .name = "csi_pix1_clk", |
| 612 | .parent_names = pix_rdi_parents, |
| 613 | .num_parents = 3, |
| 614 | .ops = &clk_ops_pix_rdi, |
| 615 | }, |
| 616 | }, |
| 617 | }; |
| 618 | |
| 619 | static struct clk_pix_rdi csi_rdi_clk = { |
| 620 | .s_reg = 0x0058, |
| 621 | .s_mask = BIT(12), |
| 622 | .s2_reg = 0x0238, |
| 623 | .s2_mask = BIT(12), |
| 624 | .clkr = { |
| 625 | .enable_reg = 0x0058, |
| 626 | .enable_mask = BIT(13), |
| 627 | .hw.init = &(struct clk_init_data){ |
| 628 | .name = "csi_rdi_clk", |
| 629 | .parent_names = pix_rdi_parents, |
| 630 | .num_parents = 3, |
| 631 | .ops = &clk_ops_pix_rdi, |
| 632 | }, |
| 633 | }, |
| 634 | }; |
| 635 | |
| 636 | static struct clk_pix_rdi csi_rdi1_clk = { |
| 637 | .s_reg = 0x0238, |
| 638 | .s_mask = BIT(0), |
| 639 | .s2_reg = 0x0238, |
| 640 | .s2_mask = BIT(1), |
| 641 | .clkr = { |
| 642 | .enable_reg = 0x0238, |
| 643 | .enable_mask = BIT(2), |
| 644 | .hw.init = &(struct clk_init_data){ |
| 645 | .name = "csi_rdi1_clk", |
| 646 | .parent_names = pix_rdi_parents, |
| 647 | .num_parents = 3, |
| 648 | .ops = &clk_ops_pix_rdi, |
| 649 | }, |
| 650 | }, |
| 651 | }; |
| 652 | |
| 653 | static struct clk_pix_rdi csi_rdi2_clk = { |
| 654 | .s_reg = 0x0238, |
| 655 | .s_mask = BIT(4), |
| 656 | .s2_reg = 0x0238, |
| 657 | .s2_mask = BIT(5), |
| 658 | .clkr = { |
| 659 | .enable_reg = 0x0238, |
| 660 | .enable_mask = BIT(6), |
| 661 | .hw.init = &(struct clk_init_data){ |
| 662 | .name = "csi_rdi2_clk", |
| 663 | .parent_names = pix_rdi_parents, |
| 664 | .num_parents = 3, |
| 665 | .ops = &clk_ops_pix_rdi, |
| 666 | }, |
| 667 | }, |
| 668 | }; |
| 669 | |
| 670 | static struct freq_tbl clk_tbl_csiphytimer[] = { |
| 671 | { 85330000, P_PLL8, 1, 2, 9 }, |
| 672 | { 177780000, P_PLL2, 1, 2, 9 }, |
| 673 | { } |
| 674 | }; |
| 675 | |
| 676 | static struct clk_rcg csiphytimer_src = { |
| 677 | .ns_reg = 0x0168, |
| 678 | .md_reg = 0x0164, |
| 679 | .mn = { |
| 680 | .mnctr_en_bit = 5, |
| 681 | .mnctr_reset_bit = 8, |
| 682 | .reset_in_cc = true, |
| 683 | .mnctr_mode_shift = 6, |
| 684 | .n_val_shift = 24, |
| 685 | .m_val_shift = 8, |
| 686 | .width = 8, |
| 687 | }, |
| 688 | .p = { |
| 689 | .pre_div_shift = 14, |
| 690 | .pre_div_width = 2, |
| 691 | }, |
| 692 | .s = { |
| 693 | .src_sel_shift = 0, |
| 694 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 695 | }, |
| 696 | .freq_tbl = clk_tbl_csiphytimer, |
| 697 | .clkr = { |
| 698 | .enable_reg = 0x0160, |
| 699 | .enable_mask = BIT(2), |
| 700 | .hw.init = &(struct clk_init_data){ |
| 701 | .name = "csiphytimer_src", |
| 702 | .parent_names = mmcc_pxo_pll8_pll2, |
| 703 | .num_parents = 3, |
| 704 | .ops = &clk_rcg_ops, |
| 705 | }, |
| 706 | }, |
| 707 | }; |
| 708 | |
| 709 | static const char *csixphy_timer_src[] = { "csiphytimer_src" }; |
| 710 | |
| 711 | static struct clk_branch csiphy0_timer_clk = { |
| 712 | .halt_reg = 0x01e8, |
| 713 | .halt_bit = 17, |
| 714 | .clkr = { |
| 715 | .enable_reg = 0x0160, |
| 716 | .enable_mask = BIT(0), |
| 717 | .hw.init = &(struct clk_init_data){ |
| 718 | .parent_names = csixphy_timer_src, |
| 719 | .num_parents = 1, |
| 720 | .name = "csiphy0_timer_clk", |
| 721 | .ops = &clk_branch_ops, |
| 722 | .flags = CLK_SET_RATE_PARENT, |
| 723 | }, |
| 724 | }, |
| 725 | }; |
| 726 | |
| 727 | static struct clk_branch csiphy1_timer_clk = { |
| 728 | .halt_reg = 0x01e8, |
| 729 | .halt_bit = 18, |
| 730 | .clkr = { |
| 731 | .enable_reg = 0x0160, |
| 732 | .enable_mask = BIT(9), |
| 733 | .hw.init = &(struct clk_init_data){ |
| 734 | .parent_names = csixphy_timer_src, |
| 735 | .num_parents = 1, |
| 736 | .name = "csiphy1_timer_clk", |
| 737 | .ops = &clk_branch_ops, |
| 738 | .flags = CLK_SET_RATE_PARENT, |
| 739 | }, |
| 740 | }, |
| 741 | }; |
| 742 | |
| 743 | static struct clk_branch csiphy2_timer_clk = { |
| 744 | .halt_reg = 0x01e8, |
| 745 | .halt_bit = 30, |
| 746 | .clkr = { |
| 747 | .enable_reg = 0x0160, |
| 748 | .enable_mask = BIT(11), |
| 749 | .hw.init = &(struct clk_init_data){ |
| 750 | .parent_names = csixphy_timer_src, |
| 751 | .num_parents = 1, |
| 752 | .name = "csiphy2_timer_clk", |
| 753 | .ops = &clk_branch_ops, |
| 754 | .flags = CLK_SET_RATE_PARENT, |
| 755 | }, |
| 756 | }, |
| 757 | }; |
| 758 | |
| 759 | static struct freq_tbl clk_tbl_gfx2d[] = { |
Stephen Boyd | ff20783 | 2014-07-08 18:36:06 -0700 | [diff] [blame] | 760 | F_MN( 27000000, P_PXO, 1, 0), |
| 761 | F_MN( 48000000, P_PLL8, 1, 8), |
| 762 | F_MN( 54857000, P_PLL8, 1, 7), |
| 763 | F_MN( 64000000, P_PLL8, 1, 6), |
| 764 | F_MN( 76800000, P_PLL8, 1, 5), |
| 765 | F_MN( 96000000, P_PLL8, 1, 4), |
| 766 | F_MN(128000000, P_PLL8, 1, 3), |
| 767 | F_MN(145455000, P_PLL2, 2, 11), |
| 768 | F_MN(160000000, P_PLL2, 1, 5), |
| 769 | F_MN(177778000, P_PLL2, 2, 9), |
| 770 | F_MN(200000000, P_PLL2, 1, 4), |
| 771 | F_MN(228571000, P_PLL2, 2, 7), |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 772 | { } |
| 773 | }; |
| 774 | |
| 775 | static struct clk_dyn_rcg gfx2d0_src = { |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 776 | .ns_reg[0] = 0x0070, |
| 777 | .ns_reg[1] = 0x0070, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 778 | .md_reg[0] = 0x0064, |
| 779 | .md_reg[1] = 0x0068, |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 780 | .bank_reg = 0x0060, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 781 | .mn[0] = { |
| 782 | .mnctr_en_bit = 8, |
| 783 | .mnctr_reset_bit = 25, |
| 784 | .mnctr_mode_shift = 9, |
| 785 | .n_val_shift = 20, |
| 786 | .m_val_shift = 4, |
| 787 | .width = 4, |
| 788 | }, |
| 789 | .mn[1] = { |
| 790 | .mnctr_en_bit = 5, |
| 791 | .mnctr_reset_bit = 24, |
| 792 | .mnctr_mode_shift = 6, |
| 793 | .n_val_shift = 16, |
| 794 | .m_val_shift = 4, |
| 795 | .width = 4, |
| 796 | }, |
| 797 | .s[0] = { |
| 798 | .src_sel_shift = 3, |
| 799 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 800 | }, |
| 801 | .s[1] = { |
| 802 | .src_sel_shift = 0, |
| 803 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 804 | }, |
| 805 | .mux_sel_bit = 11, |
| 806 | .freq_tbl = clk_tbl_gfx2d, |
| 807 | .clkr = { |
| 808 | .enable_reg = 0x0060, |
| 809 | .enable_mask = BIT(2), |
| 810 | .hw.init = &(struct clk_init_data){ |
| 811 | .name = "gfx2d0_src", |
| 812 | .parent_names = mmcc_pxo_pll8_pll2, |
| 813 | .num_parents = 3, |
| 814 | .ops = &clk_dyn_rcg_ops, |
| 815 | }, |
| 816 | }, |
| 817 | }; |
| 818 | |
| 819 | static struct clk_branch gfx2d0_clk = { |
| 820 | .halt_reg = 0x01c8, |
| 821 | .halt_bit = 9, |
| 822 | .clkr = { |
| 823 | .enable_reg = 0x0060, |
| 824 | .enable_mask = BIT(0), |
| 825 | .hw.init = &(struct clk_init_data){ |
| 826 | .name = "gfx2d0_clk", |
| 827 | .parent_names = (const char *[]){ "gfx2d0_src" }, |
| 828 | .num_parents = 1, |
| 829 | .ops = &clk_branch_ops, |
| 830 | .flags = CLK_SET_RATE_PARENT, |
| 831 | }, |
| 832 | }, |
| 833 | }; |
| 834 | |
| 835 | static struct clk_dyn_rcg gfx2d1_src = { |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 836 | .ns_reg[0] = 0x007c, |
| 837 | .ns_reg[1] = 0x007c, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 838 | .md_reg[0] = 0x0078, |
| 839 | .md_reg[1] = 0x006c, |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 840 | .bank_reg = 0x0074, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 841 | .mn[0] = { |
| 842 | .mnctr_en_bit = 8, |
| 843 | .mnctr_reset_bit = 25, |
| 844 | .mnctr_mode_shift = 9, |
| 845 | .n_val_shift = 20, |
| 846 | .m_val_shift = 4, |
| 847 | .width = 4, |
| 848 | }, |
| 849 | .mn[1] = { |
| 850 | .mnctr_en_bit = 5, |
| 851 | .mnctr_reset_bit = 24, |
| 852 | .mnctr_mode_shift = 6, |
| 853 | .n_val_shift = 16, |
| 854 | .m_val_shift = 4, |
| 855 | .width = 4, |
| 856 | }, |
| 857 | .s[0] = { |
| 858 | .src_sel_shift = 3, |
| 859 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 860 | }, |
| 861 | .s[1] = { |
| 862 | .src_sel_shift = 0, |
| 863 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 864 | }, |
| 865 | .mux_sel_bit = 11, |
| 866 | .freq_tbl = clk_tbl_gfx2d, |
| 867 | .clkr = { |
| 868 | .enable_reg = 0x0074, |
| 869 | .enable_mask = BIT(2), |
| 870 | .hw.init = &(struct clk_init_data){ |
| 871 | .name = "gfx2d1_src", |
| 872 | .parent_names = mmcc_pxo_pll8_pll2, |
| 873 | .num_parents = 3, |
| 874 | .ops = &clk_dyn_rcg_ops, |
| 875 | }, |
| 876 | }, |
| 877 | }; |
| 878 | |
| 879 | static struct clk_branch gfx2d1_clk = { |
| 880 | .halt_reg = 0x01c8, |
| 881 | .halt_bit = 14, |
| 882 | .clkr = { |
| 883 | .enable_reg = 0x0074, |
| 884 | .enable_mask = BIT(0), |
| 885 | .hw.init = &(struct clk_init_data){ |
| 886 | .name = "gfx2d1_clk", |
| 887 | .parent_names = (const char *[]){ "gfx2d1_src" }, |
| 888 | .num_parents = 1, |
| 889 | .ops = &clk_branch_ops, |
| 890 | .flags = CLK_SET_RATE_PARENT, |
| 891 | }, |
| 892 | }, |
| 893 | }; |
| 894 | |
| 895 | static struct freq_tbl clk_tbl_gfx3d[] = { |
Stephen Boyd | ff20783 | 2014-07-08 18:36:06 -0700 | [diff] [blame] | 896 | F_MN( 27000000, P_PXO, 1, 0), |
| 897 | F_MN( 48000000, P_PLL8, 1, 8), |
| 898 | F_MN( 54857000, P_PLL8, 1, 7), |
| 899 | F_MN( 64000000, P_PLL8, 1, 6), |
| 900 | F_MN( 76800000, P_PLL8, 1, 5), |
| 901 | F_MN( 96000000, P_PLL8, 1, 4), |
| 902 | F_MN(128000000, P_PLL8, 1, 3), |
| 903 | F_MN(145455000, P_PLL2, 2, 11), |
| 904 | F_MN(160000000, P_PLL2, 1, 5), |
| 905 | F_MN(177778000, P_PLL2, 2, 9), |
| 906 | F_MN(200000000, P_PLL2, 1, 4), |
| 907 | F_MN(228571000, P_PLL2, 2, 7), |
| 908 | F_MN(266667000, P_PLL2, 1, 3), |
| 909 | F_MN(300000000, P_PLL3, 1, 4), |
| 910 | F_MN(320000000, P_PLL2, 2, 5), |
| 911 | F_MN(400000000, P_PLL2, 1, 2), |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 912 | { } |
| 913 | }; |
| 914 | |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 915 | static struct freq_tbl clk_tbl_gfx3d_8064[] = { |
| 916 | F_MN( 27000000, P_PXO, 0, 0), |
| 917 | F_MN( 48000000, P_PLL8, 1, 8), |
| 918 | F_MN( 54857000, P_PLL8, 1, 7), |
| 919 | F_MN( 64000000, P_PLL8, 1, 6), |
| 920 | F_MN( 76800000, P_PLL8, 1, 5), |
| 921 | F_MN( 96000000, P_PLL8, 1, 4), |
| 922 | F_MN(128000000, P_PLL8, 1, 3), |
| 923 | F_MN(145455000, P_PLL2, 2, 11), |
| 924 | F_MN(160000000, P_PLL2, 1, 5), |
| 925 | F_MN(177778000, P_PLL2, 2, 9), |
| 926 | F_MN(192000000, P_PLL8, 1, 2), |
| 927 | F_MN(200000000, P_PLL2, 1, 4), |
| 928 | F_MN(228571000, P_PLL2, 2, 7), |
| 929 | F_MN(266667000, P_PLL2, 1, 3), |
| 930 | F_MN(320000000, P_PLL2, 2, 5), |
| 931 | F_MN(400000000, P_PLL2, 1, 2), |
| 932 | F_MN(450000000, P_PLL15, 1, 2), |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 933 | { } |
| 934 | }; |
| 935 | |
| 936 | static struct clk_dyn_rcg gfx3d_src = { |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 937 | .ns_reg[0] = 0x008c, |
| 938 | .ns_reg[1] = 0x008c, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 939 | .md_reg[0] = 0x0084, |
| 940 | .md_reg[1] = 0x0088, |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 941 | .bank_reg = 0x0080, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 942 | .mn[0] = { |
| 943 | .mnctr_en_bit = 8, |
| 944 | .mnctr_reset_bit = 25, |
| 945 | .mnctr_mode_shift = 9, |
| 946 | .n_val_shift = 18, |
| 947 | .m_val_shift = 4, |
| 948 | .width = 4, |
| 949 | }, |
| 950 | .mn[1] = { |
| 951 | .mnctr_en_bit = 5, |
| 952 | .mnctr_reset_bit = 24, |
| 953 | .mnctr_mode_shift = 6, |
| 954 | .n_val_shift = 14, |
| 955 | .m_val_shift = 4, |
| 956 | .width = 4, |
| 957 | }, |
| 958 | .s[0] = { |
| 959 | .src_sel_shift = 3, |
| 960 | .parent_map = mmcc_pxo_pll8_pll2_pll3_map, |
| 961 | }, |
| 962 | .s[1] = { |
| 963 | .src_sel_shift = 0, |
| 964 | .parent_map = mmcc_pxo_pll8_pll2_pll3_map, |
| 965 | }, |
| 966 | .mux_sel_bit = 11, |
| 967 | .freq_tbl = clk_tbl_gfx3d, |
| 968 | .clkr = { |
| 969 | .enable_reg = 0x0080, |
| 970 | .enable_mask = BIT(2), |
| 971 | .hw.init = &(struct clk_init_data){ |
| 972 | .name = "gfx3d_src", |
| 973 | .parent_names = mmcc_pxo_pll8_pll2_pll3, |
Stephen Boyd | ff20783 | 2014-07-08 18:36:06 -0700 | [diff] [blame] | 974 | .num_parents = 4, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 975 | .ops = &clk_dyn_rcg_ops, |
| 976 | }, |
| 977 | }, |
| 978 | }; |
| 979 | |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 980 | static const struct clk_init_data gfx3d_8064_init = { |
| 981 | .name = "gfx3d_src", |
| 982 | .parent_names = mmcc_pxo_pll8_pll2_pll15, |
| 983 | .num_parents = 4, |
| 984 | .ops = &clk_dyn_rcg_ops, |
| 985 | }; |
| 986 | |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 987 | static struct clk_branch gfx3d_clk = { |
| 988 | .halt_reg = 0x01c8, |
| 989 | .halt_bit = 4, |
| 990 | .clkr = { |
| 991 | .enable_reg = 0x0080, |
| 992 | .enable_mask = BIT(0), |
| 993 | .hw.init = &(struct clk_init_data){ |
| 994 | .name = "gfx3d_clk", |
| 995 | .parent_names = (const char *[]){ "gfx3d_src" }, |
| 996 | .num_parents = 1, |
| 997 | .ops = &clk_branch_ops, |
| 998 | .flags = CLK_SET_RATE_PARENT, |
| 999 | }, |
| 1000 | }, |
| 1001 | }; |
| 1002 | |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 1003 | static struct freq_tbl clk_tbl_vcap[] = { |
| 1004 | F_MN( 27000000, P_PXO, 0, 0), |
| 1005 | F_MN( 54860000, P_PLL8, 1, 7), |
| 1006 | F_MN( 64000000, P_PLL8, 1, 6), |
| 1007 | F_MN( 76800000, P_PLL8, 1, 5), |
| 1008 | F_MN(128000000, P_PLL8, 1, 3), |
| 1009 | F_MN(160000000, P_PLL2, 1, 5), |
| 1010 | F_MN(200000000, P_PLL2, 1, 4), |
| 1011 | { } |
| 1012 | }; |
| 1013 | |
| 1014 | static struct clk_dyn_rcg vcap_src = { |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 1015 | .ns_reg[0] = 0x021c, |
| 1016 | .ns_reg[1] = 0x021c, |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 1017 | .md_reg[0] = 0x01ec, |
| 1018 | .md_reg[1] = 0x0218, |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 1019 | .bank_reg = 0x0178, |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 1020 | .mn[0] = { |
| 1021 | .mnctr_en_bit = 8, |
| 1022 | .mnctr_reset_bit = 23, |
| 1023 | .mnctr_mode_shift = 9, |
| 1024 | .n_val_shift = 18, |
| 1025 | .m_val_shift = 4, |
| 1026 | .width = 4, |
| 1027 | }, |
| 1028 | .mn[1] = { |
| 1029 | .mnctr_en_bit = 5, |
| 1030 | .mnctr_reset_bit = 22, |
| 1031 | .mnctr_mode_shift = 6, |
| 1032 | .n_val_shift = 14, |
| 1033 | .m_val_shift = 4, |
| 1034 | .width = 4, |
| 1035 | }, |
| 1036 | .s[0] = { |
| 1037 | .src_sel_shift = 3, |
| 1038 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1039 | }, |
| 1040 | .s[1] = { |
| 1041 | .src_sel_shift = 0, |
| 1042 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1043 | }, |
| 1044 | .mux_sel_bit = 11, |
| 1045 | .freq_tbl = clk_tbl_vcap, |
| 1046 | .clkr = { |
| 1047 | .enable_reg = 0x0178, |
| 1048 | .enable_mask = BIT(2), |
| 1049 | .hw.init = &(struct clk_init_data){ |
| 1050 | .name = "vcap_src", |
| 1051 | .parent_names = mmcc_pxo_pll8_pll2, |
| 1052 | .num_parents = 3, |
| 1053 | .ops = &clk_dyn_rcg_ops, |
| 1054 | }, |
| 1055 | }, |
| 1056 | }; |
| 1057 | |
| 1058 | static struct clk_branch vcap_clk = { |
| 1059 | .halt_reg = 0x0240, |
| 1060 | .halt_bit = 15, |
| 1061 | .clkr = { |
| 1062 | .enable_reg = 0x0178, |
| 1063 | .enable_mask = BIT(0), |
| 1064 | .hw.init = &(struct clk_init_data){ |
| 1065 | .name = "vcap_clk", |
| 1066 | .parent_names = (const char *[]){ "vcap_src" }, |
| 1067 | .num_parents = 1, |
| 1068 | .ops = &clk_branch_ops, |
| 1069 | .flags = CLK_SET_RATE_PARENT, |
| 1070 | }, |
| 1071 | }, |
| 1072 | }; |
| 1073 | |
| 1074 | static struct clk_branch vcap_npl_clk = { |
| 1075 | .halt_reg = 0x0240, |
| 1076 | .halt_bit = 25, |
| 1077 | .clkr = { |
| 1078 | .enable_reg = 0x0178, |
| 1079 | .enable_mask = BIT(13), |
| 1080 | .hw.init = &(struct clk_init_data){ |
| 1081 | .name = "vcap_npl_clk", |
| 1082 | .parent_names = (const char *[]){ "vcap_src" }, |
| 1083 | .num_parents = 1, |
| 1084 | .ops = &clk_branch_ops, |
| 1085 | .flags = CLK_SET_RATE_PARENT, |
| 1086 | }, |
| 1087 | }, |
| 1088 | }; |
| 1089 | |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1090 | static struct freq_tbl clk_tbl_ijpeg[] = { |
| 1091 | { 27000000, P_PXO, 1, 0, 0 }, |
| 1092 | { 36570000, P_PLL8, 1, 2, 21 }, |
| 1093 | { 54860000, P_PLL8, 7, 0, 0 }, |
| 1094 | { 96000000, P_PLL8, 4, 0, 0 }, |
| 1095 | { 109710000, P_PLL8, 1, 2, 7 }, |
| 1096 | { 128000000, P_PLL8, 3, 0, 0 }, |
| 1097 | { 153600000, P_PLL8, 1, 2, 5 }, |
| 1098 | { 200000000, P_PLL2, 4, 0, 0 }, |
| 1099 | { 228571000, P_PLL2, 1, 2, 7 }, |
| 1100 | { 266667000, P_PLL2, 1, 1, 3 }, |
| 1101 | { 320000000, P_PLL2, 1, 2, 5 }, |
| 1102 | { } |
| 1103 | }; |
| 1104 | |
| 1105 | static struct clk_rcg ijpeg_src = { |
| 1106 | .ns_reg = 0x00a0, |
| 1107 | .md_reg = 0x009c, |
| 1108 | .mn = { |
| 1109 | .mnctr_en_bit = 5, |
| 1110 | .mnctr_reset_bit = 7, |
| 1111 | .mnctr_mode_shift = 6, |
| 1112 | .n_val_shift = 16, |
| 1113 | .m_val_shift = 8, |
| 1114 | .width = 8, |
| 1115 | }, |
| 1116 | .p = { |
| 1117 | .pre_div_shift = 12, |
| 1118 | .pre_div_width = 2, |
| 1119 | }, |
| 1120 | .s = { |
| 1121 | .src_sel_shift = 0, |
| 1122 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1123 | }, |
| 1124 | .freq_tbl = clk_tbl_ijpeg, |
| 1125 | .clkr = { |
| 1126 | .enable_reg = 0x0098, |
| 1127 | .enable_mask = BIT(2), |
| 1128 | .hw.init = &(struct clk_init_data){ |
| 1129 | .name = "ijpeg_src", |
| 1130 | .parent_names = mmcc_pxo_pll8_pll2, |
| 1131 | .num_parents = 3, |
| 1132 | .ops = &clk_rcg_ops, |
| 1133 | }, |
| 1134 | }, |
| 1135 | }; |
| 1136 | |
| 1137 | static struct clk_branch ijpeg_clk = { |
| 1138 | .halt_reg = 0x01c8, |
| 1139 | .halt_bit = 24, |
| 1140 | .clkr = { |
| 1141 | .enable_reg = 0x0098, |
| 1142 | .enable_mask = BIT(0), |
| 1143 | .hw.init = &(struct clk_init_data){ |
| 1144 | .name = "ijpeg_clk", |
| 1145 | .parent_names = (const char *[]){ "ijpeg_src" }, |
| 1146 | .num_parents = 1, |
| 1147 | .ops = &clk_branch_ops, |
| 1148 | .flags = CLK_SET_RATE_PARENT, |
| 1149 | }, |
| 1150 | }, |
| 1151 | }; |
| 1152 | |
| 1153 | static struct freq_tbl clk_tbl_jpegd[] = { |
| 1154 | { 64000000, P_PLL8, 6 }, |
| 1155 | { 76800000, P_PLL8, 5 }, |
| 1156 | { 96000000, P_PLL8, 4 }, |
| 1157 | { 160000000, P_PLL2, 5 }, |
| 1158 | { 200000000, P_PLL2, 4 }, |
| 1159 | { } |
| 1160 | }; |
| 1161 | |
| 1162 | static struct clk_rcg jpegd_src = { |
| 1163 | .ns_reg = 0x00ac, |
| 1164 | .p = { |
| 1165 | .pre_div_shift = 12, |
Stephen Boyd | ff20783 | 2014-07-08 18:36:06 -0700 | [diff] [blame] | 1166 | .pre_div_width = 4, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1167 | }, |
| 1168 | .s = { |
| 1169 | .src_sel_shift = 0, |
| 1170 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1171 | }, |
| 1172 | .freq_tbl = clk_tbl_jpegd, |
| 1173 | .clkr = { |
| 1174 | .enable_reg = 0x00a4, |
| 1175 | .enable_mask = BIT(2), |
| 1176 | .hw.init = &(struct clk_init_data){ |
| 1177 | .name = "jpegd_src", |
| 1178 | .parent_names = mmcc_pxo_pll8_pll2, |
| 1179 | .num_parents = 3, |
| 1180 | .ops = &clk_rcg_ops, |
| 1181 | }, |
| 1182 | }, |
| 1183 | }; |
| 1184 | |
| 1185 | static struct clk_branch jpegd_clk = { |
| 1186 | .halt_reg = 0x01c8, |
| 1187 | .halt_bit = 19, |
| 1188 | .clkr = { |
| 1189 | .enable_reg = 0x00a4, |
| 1190 | .enable_mask = BIT(0), |
| 1191 | .hw.init = &(struct clk_init_data){ |
| 1192 | .name = "jpegd_clk", |
| 1193 | .parent_names = (const char *[]){ "jpegd_src" }, |
| 1194 | .num_parents = 1, |
| 1195 | .ops = &clk_branch_ops, |
| 1196 | .flags = CLK_SET_RATE_PARENT, |
| 1197 | }, |
| 1198 | }, |
| 1199 | }; |
| 1200 | |
| 1201 | static struct freq_tbl clk_tbl_mdp[] = { |
| 1202 | { 9600000, P_PLL8, 1, 1, 40 }, |
| 1203 | { 13710000, P_PLL8, 1, 1, 28 }, |
| 1204 | { 27000000, P_PXO, 1, 0, 0 }, |
| 1205 | { 29540000, P_PLL8, 1, 1, 13 }, |
| 1206 | { 34910000, P_PLL8, 1, 1, 11 }, |
| 1207 | { 38400000, P_PLL8, 1, 1, 10 }, |
| 1208 | { 59080000, P_PLL8, 1, 2, 13 }, |
| 1209 | { 76800000, P_PLL8, 1, 1, 5 }, |
| 1210 | { 85330000, P_PLL8, 1, 2, 9 }, |
| 1211 | { 96000000, P_PLL8, 1, 1, 4 }, |
| 1212 | { 128000000, P_PLL8, 1, 1, 3 }, |
| 1213 | { 160000000, P_PLL2, 1, 1, 5 }, |
| 1214 | { 177780000, P_PLL2, 1, 2, 9 }, |
| 1215 | { 200000000, P_PLL2, 1, 1, 4 }, |
| 1216 | { 228571000, P_PLL2, 1, 2, 7 }, |
| 1217 | { 266667000, P_PLL2, 1, 1, 3 }, |
| 1218 | { } |
| 1219 | }; |
| 1220 | |
| 1221 | static struct clk_dyn_rcg mdp_src = { |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 1222 | .ns_reg[0] = 0x00d0, |
| 1223 | .ns_reg[1] = 0x00d0, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1224 | .md_reg[0] = 0x00c4, |
| 1225 | .md_reg[1] = 0x00c8, |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 1226 | .bank_reg = 0x00c0, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1227 | .mn[0] = { |
| 1228 | .mnctr_en_bit = 8, |
| 1229 | .mnctr_reset_bit = 31, |
| 1230 | .mnctr_mode_shift = 9, |
| 1231 | .n_val_shift = 22, |
| 1232 | .m_val_shift = 8, |
| 1233 | .width = 8, |
| 1234 | }, |
| 1235 | .mn[1] = { |
| 1236 | .mnctr_en_bit = 5, |
| 1237 | .mnctr_reset_bit = 30, |
| 1238 | .mnctr_mode_shift = 6, |
| 1239 | .n_val_shift = 14, |
| 1240 | .m_val_shift = 8, |
| 1241 | .width = 8, |
| 1242 | }, |
| 1243 | .s[0] = { |
| 1244 | .src_sel_shift = 3, |
| 1245 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1246 | }, |
| 1247 | .s[1] = { |
| 1248 | .src_sel_shift = 0, |
| 1249 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1250 | }, |
| 1251 | .mux_sel_bit = 11, |
| 1252 | .freq_tbl = clk_tbl_mdp, |
| 1253 | .clkr = { |
| 1254 | .enable_reg = 0x00c0, |
| 1255 | .enable_mask = BIT(2), |
| 1256 | .hw.init = &(struct clk_init_data){ |
| 1257 | .name = "mdp_src", |
| 1258 | .parent_names = mmcc_pxo_pll8_pll2, |
| 1259 | .num_parents = 3, |
| 1260 | .ops = &clk_dyn_rcg_ops, |
| 1261 | }, |
| 1262 | }, |
| 1263 | }; |
| 1264 | |
| 1265 | static struct clk_branch mdp_clk = { |
| 1266 | .halt_reg = 0x01d0, |
| 1267 | .halt_bit = 10, |
| 1268 | .clkr = { |
| 1269 | .enable_reg = 0x00c0, |
| 1270 | .enable_mask = BIT(0), |
| 1271 | .hw.init = &(struct clk_init_data){ |
| 1272 | .name = "mdp_clk", |
| 1273 | .parent_names = (const char *[]){ "mdp_src" }, |
| 1274 | .num_parents = 1, |
| 1275 | .ops = &clk_branch_ops, |
| 1276 | .flags = CLK_SET_RATE_PARENT, |
| 1277 | }, |
| 1278 | }, |
| 1279 | }; |
| 1280 | |
| 1281 | static struct clk_branch mdp_lut_clk = { |
| 1282 | .halt_reg = 0x01e8, |
| 1283 | .halt_bit = 13, |
| 1284 | .clkr = { |
| 1285 | .enable_reg = 0x016c, |
| 1286 | .enable_mask = BIT(0), |
| 1287 | .hw.init = &(struct clk_init_data){ |
Stephen Boyd | f87dfca | 2014-07-08 18:36:06 -0700 | [diff] [blame] | 1288 | .parent_names = (const char *[]){ "mdp_src" }, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1289 | .num_parents = 1, |
| 1290 | .name = "mdp_lut_clk", |
| 1291 | .ops = &clk_branch_ops, |
| 1292 | .flags = CLK_SET_RATE_PARENT, |
| 1293 | }, |
| 1294 | }, |
| 1295 | }; |
| 1296 | |
| 1297 | static struct clk_branch mdp_vsync_clk = { |
| 1298 | .halt_reg = 0x01cc, |
| 1299 | .halt_bit = 22, |
| 1300 | .clkr = { |
| 1301 | .enable_reg = 0x0058, |
| 1302 | .enable_mask = BIT(6), |
| 1303 | .hw.init = &(struct clk_init_data){ |
| 1304 | .name = "mdp_vsync_clk", |
| 1305 | .parent_names = (const char *[]){ "pxo" }, |
| 1306 | .num_parents = 1, |
| 1307 | .ops = &clk_branch_ops |
| 1308 | }, |
| 1309 | }, |
| 1310 | }; |
| 1311 | |
| 1312 | static struct freq_tbl clk_tbl_rot[] = { |
| 1313 | { 27000000, P_PXO, 1 }, |
| 1314 | { 29540000, P_PLL8, 13 }, |
| 1315 | { 32000000, P_PLL8, 12 }, |
| 1316 | { 38400000, P_PLL8, 10 }, |
| 1317 | { 48000000, P_PLL8, 8 }, |
| 1318 | { 54860000, P_PLL8, 7 }, |
| 1319 | { 64000000, P_PLL8, 6 }, |
| 1320 | { 76800000, P_PLL8, 5 }, |
| 1321 | { 96000000, P_PLL8, 4 }, |
| 1322 | { 100000000, P_PLL2, 8 }, |
| 1323 | { 114290000, P_PLL2, 7 }, |
| 1324 | { 133330000, P_PLL2, 6 }, |
| 1325 | { 160000000, P_PLL2, 5 }, |
| 1326 | { 200000000, P_PLL2, 4 }, |
| 1327 | { } |
| 1328 | }; |
| 1329 | |
| 1330 | static struct clk_dyn_rcg rot_src = { |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 1331 | .ns_reg[0] = 0x00e8, |
| 1332 | .ns_reg[1] = 0x00e8, |
| 1333 | .bank_reg = 0x00e8, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1334 | .p[0] = { |
| 1335 | .pre_div_shift = 22, |
| 1336 | .pre_div_width = 4, |
| 1337 | }, |
| 1338 | .p[1] = { |
| 1339 | .pre_div_shift = 26, |
| 1340 | .pre_div_width = 4, |
| 1341 | }, |
| 1342 | .s[0] = { |
| 1343 | .src_sel_shift = 16, |
| 1344 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1345 | }, |
| 1346 | .s[1] = { |
| 1347 | .src_sel_shift = 19, |
| 1348 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1349 | }, |
| 1350 | .mux_sel_bit = 30, |
| 1351 | .freq_tbl = clk_tbl_rot, |
| 1352 | .clkr = { |
| 1353 | .enable_reg = 0x00e0, |
| 1354 | .enable_mask = BIT(2), |
| 1355 | .hw.init = &(struct clk_init_data){ |
| 1356 | .name = "rot_src", |
| 1357 | .parent_names = mmcc_pxo_pll8_pll2, |
| 1358 | .num_parents = 3, |
| 1359 | .ops = &clk_dyn_rcg_ops, |
| 1360 | }, |
| 1361 | }, |
| 1362 | }; |
| 1363 | |
| 1364 | static struct clk_branch rot_clk = { |
| 1365 | .halt_reg = 0x01d0, |
| 1366 | .halt_bit = 15, |
| 1367 | .clkr = { |
| 1368 | .enable_reg = 0x00e0, |
| 1369 | .enable_mask = BIT(0), |
| 1370 | .hw.init = &(struct clk_init_data){ |
| 1371 | .name = "rot_clk", |
| 1372 | .parent_names = (const char *[]){ "rot_src" }, |
| 1373 | .num_parents = 1, |
| 1374 | .ops = &clk_branch_ops, |
| 1375 | .flags = CLK_SET_RATE_PARENT, |
| 1376 | }, |
| 1377 | }, |
| 1378 | }; |
| 1379 | |
| 1380 | #define P_HDMI_PLL 1 |
| 1381 | |
| 1382 | static u8 mmcc_pxo_hdmi_map[] = { |
| 1383 | [P_PXO] = 0, |
Stephen Boyd | c556bcd | 2014-06-25 14:44:19 -0700 | [diff] [blame] | 1384 | [P_HDMI_PLL] = 3, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1385 | }; |
| 1386 | |
| 1387 | static const char *mmcc_pxo_hdmi[] = { |
| 1388 | "pxo", |
| 1389 | "hdmi_pll", |
| 1390 | }; |
| 1391 | |
| 1392 | static struct freq_tbl clk_tbl_tv[] = { |
Stephen Boyd | 404c1ff | 2014-07-11 12:55:27 -0700 | [diff] [blame] | 1393 | { .src = P_HDMI_PLL, .pre_div = 1 }, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1394 | { } |
| 1395 | }; |
| 1396 | |
| 1397 | static struct clk_rcg tv_src = { |
| 1398 | .ns_reg = 0x00f4, |
| 1399 | .md_reg = 0x00f0, |
| 1400 | .mn = { |
| 1401 | .mnctr_en_bit = 5, |
| 1402 | .mnctr_reset_bit = 7, |
| 1403 | .mnctr_mode_shift = 6, |
| 1404 | .n_val_shift = 16, |
| 1405 | .m_val_shift = 8, |
| 1406 | .width = 8, |
| 1407 | }, |
| 1408 | .p = { |
| 1409 | .pre_div_shift = 14, |
| 1410 | .pre_div_width = 2, |
| 1411 | }, |
| 1412 | .s = { |
| 1413 | .src_sel_shift = 0, |
| 1414 | .parent_map = mmcc_pxo_hdmi_map, |
| 1415 | }, |
| 1416 | .freq_tbl = clk_tbl_tv, |
| 1417 | .clkr = { |
| 1418 | .enable_reg = 0x00ec, |
| 1419 | .enable_mask = BIT(2), |
| 1420 | .hw.init = &(struct clk_init_data){ |
| 1421 | .name = "tv_src", |
| 1422 | .parent_names = mmcc_pxo_hdmi, |
| 1423 | .num_parents = 2, |
Stephen Boyd | 404c1ff | 2014-07-11 12:55:27 -0700 | [diff] [blame] | 1424 | .ops = &clk_rcg_bypass_ops, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1425 | .flags = CLK_SET_RATE_PARENT, |
| 1426 | }, |
| 1427 | }, |
| 1428 | }; |
| 1429 | |
| 1430 | static const char *tv_src_name[] = { "tv_src" }; |
| 1431 | |
| 1432 | static struct clk_branch tv_enc_clk = { |
| 1433 | .halt_reg = 0x01d4, |
| 1434 | .halt_bit = 9, |
| 1435 | .clkr = { |
| 1436 | .enable_reg = 0x00ec, |
| 1437 | .enable_mask = BIT(8), |
| 1438 | .hw.init = &(struct clk_init_data){ |
| 1439 | .parent_names = tv_src_name, |
| 1440 | .num_parents = 1, |
| 1441 | .name = "tv_enc_clk", |
| 1442 | .ops = &clk_branch_ops, |
| 1443 | .flags = CLK_SET_RATE_PARENT, |
| 1444 | }, |
| 1445 | }, |
| 1446 | }; |
| 1447 | |
| 1448 | static struct clk_branch tv_dac_clk = { |
| 1449 | .halt_reg = 0x01d4, |
| 1450 | .halt_bit = 10, |
| 1451 | .clkr = { |
| 1452 | .enable_reg = 0x00ec, |
| 1453 | .enable_mask = BIT(10), |
| 1454 | .hw.init = &(struct clk_init_data){ |
| 1455 | .parent_names = tv_src_name, |
| 1456 | .num_parents = 1, |
| 1457 | .name = "tv_dac_clk", |
| 1458 | .ops = &clk_branch_ops, |
| 1459 | .flags = CLK_SET_RATE_PARENT, |
| 1460 | }, |
| 1461 | }, |
| 1462 | }; |
| 1463 | |
| 1464 | static struct clk_branch mdp_tv_clk = { |
| 1465 | .halt_reg = 0x01d4, |
| 1466 | .halt_bit = 12, |
| 1467 | .clkr = { |
| 1468 | .enable_reg = 0x00ec, |
| 1469 | .enable_mask = BIT(0), |
| 1470 | .hw.init = &(struct clk_init_data){ |
| 1471 | .parent_names = tv_src_name, |
| 1472 | .num_parents = 1, |
| 1473 | .name = "mdp_tv_clk", |
| 1474 | .ops = &clk_branch_ops, |
| 1475 | .flags = CLK_SET_RATE_PARENT, |
| 1476 | }, |
| 1477 | }, |
| 1478 | }; |
| 1479 | |
| 1480 | static struct clk_branch hdmi_tv_clk = { |
| 1481 | .halt_reg = 0x01d4, |
| 1482 | .halt_bit = 11, |
| 1483 | .clkr = { |
| 1484 | .enable_reg = 0x00ec, |
| 1485 | .enable_mask = BIT(12), |
| 1486 | .hw.init = &(struct clk_init_data){ |
| 1487 | .parent_names = tv_src_name, |
| 1488 | .num_parents = 1, |
| 1489 | .name = "hdmi_tv_clk", |
| 1490 | .ops = &clk_branch_ops, |
| 1491 | .flags = CLK_SET_RATE_PARENT, |
| 1492 | }, |
| 1493 | }, |
| 1494 | }; |
| 1495 | |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 1496 | static struct clk_branch rgb_tv_clk = { |
| 1497 | .halt_reg = 0x0240, |
| 1498 | .halt_bit = 27, |
| 1499 | .clkr = { |
| 1500 | .enable_reg = 0x0124, |
| 1501 | .enable_mask = BIT(14), |
| 1502 | .hw.init = &(struct clk_init_data){ |
| 1503 | .parent_names = tv_src_name, |
| 1504 | .num_parents = 1, |
| 1505 | .name = "rgb_tv_clk", |
| 1506 | .ops = &clk_branch_ops, |
| 1507 | .flags = CLK_SET_RATE_PARENT, |
| 1508 | }, |
| 1509 | }, |
| 1510 | }; |
| 1511 | |
| 1512 | static struct clk_branch npl_tv_clk = { |
| 1513 | .halt_reg = 0x0240, |
| 1514 | .halt_bit = 26, |
| 1515 | .clkr = { |
| 1516 | .enable_reg = 0x0124, |
| 1517 | .enable_mask = BIT(16), |
| 1518 | .hw.init = &(struct clk_init_data){ |
| 1519 | .parent_names = tv_src_name, |
| 1520 | .num_parents = 1, |
| 1521 | .name = "npl_tv_clk", |
| 1522 | .ops = &clk_branch_ops, |
| 1523 | .flags = CLK_SET_RATE_PARENT, |
| 1524 | }, |
| 1525 | }, |
| 1526 | }; |
| 1527 | |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1528 | static struct clk_branch hdmi_app_clk = { |
| 1529 | .halt_reg = 0x01cc, |
| 1530 | .halt_bit = 25, |
| 1531 | .clkr = { |
| 1532 | .enable_reg = 0x005c, |
| 1533 | .enable_mask = BIT(11), |
| 1534 | .hw.init = &(struct clk_init_data){ |
| 1535 | .parent_names = (const char *[]){ "pxo" }, |
| 1536 | .num_parents = 1, |
| 1537 | .name = "hdmi_app_clk", |
| 1538 | .ops = &clk_branch_ops, |
| 1539 | }, |
| 1540 | }, |
| 1541 | }; |
| 1542 | |
| 1543 | static struct freq_tbl clk_tbl_vcodec[] = { |
Stephen Boyd | ff20783 | 2014-07-08 18:36:06 -0700 | [diff] [blame] | 1544 | F_MN( 27000000, P_PXO, 1, 0), |
| 1545 | F_MN( 32000000, P_PLL8, 1, 12), |
| 1546 | F_MN( 48000000, P_PLL8, 1, 8), |
| 1547 | F_MN( 54860000, P_PLL8, 1, 7), |
| 1548 | F_MN( 96000000, P_PLL8, 1, 4), |
| 1549 | F_MN(133330000, P_PLL2, 1, 6), |
| 1550 | F_MN(200000000, P_PLL2, 1, 4), |
| 1551 | F_MN(228570000, P_PLL2, 2, 7), |
| 1552 | F_MN(266670000, P_PLL2, 1, 3), |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1553 | { } |
| 1554 | }; |
| 1555 | |
| 1556 | static struct clk_dyn_rcg vcodec_src = { |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 1557 | .ns_reg[0] = 0x0100, |
| 1558 | .ns_reg[1] = 0x0100, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1559 | .md_reg[0] = 0x00fc, |
| 1560 | .md_reg[1] = 0x0128, |
Stephen Boyd | 229fd4a | 2014-04-28 15:59:16 -0700 | [diff] [blame] | 1561 | .bank_reg = 0x00f8, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1562 | .mn[0] = { |
| 1563 | .mnctr_en_bit = 5, |
| 1564 | .mnctr_reset_bit = 31, |
| 1565 | .mnctr_mode_shift = 6, |
| 1566 | .n_val_shift = 11, |
| 1567 | .m_val_shift = 8, |
| 1568 | .width = 8, |
| 1569 | }, |
| 1570 | .mn[1] = { |
| 1571 | .mnctr_en_bit = 10, |
| 1572 | .mnctr_reset_bit = 30, |
| 1573 | .mnctr_mode_shift = 11, |
| 1574 | .n_val_shift = 19, |
| 1575 | .m_val_shift = 8, |
| 1576 | .width = 8, |
| 1577 | }, |
| 1578 | .s[0] = { |
| 1579 | .src_sel_shift = 27, |
| 1580 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1581 | }, |
| 1582 | .s[1] = { |
| 1583 | .src_sel_shift = 0, |
| 1584 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1585 | }, |
| 1586 | .mux_sel_bit = 13, |
| 1587 | .freq_tbl = clk_tbl_vcodec, |
| 1588 | .clkr = { |
| 1589 | .enable_reg = 0x00f8, |
| 1590 | .enable_mask = BIT(2), |
| 1591 | .hw.init = &(struct clk_init_data){ |
| 1592 | .name = "vcodec_src", |
| 1593 | .parent_names = mmcc_pxo_pll8_pll2, |
| 1594 | .num_parents = 3, |
| 1595 | .ops = &clk_dyn_rcg_ops, |
| 1596 | }, |
| 1597 | }, |
| 1598 | }; |
| 1599 | |
| 1600 | static struct clk_branch vcodec_clk = { |
| 1601 | .halt_reg = 0x01d0, |
| 1602 | .halt_bit = 29, |
| 1603 | .clkr = { |
| 1604 | .enable_reg = 0x00f8, |
| 1605 | .enable_mask = BIT(0), |
| 1606 | .hw.init = &(struct clk_init_data){ |
| 1607 | .name = "vcodec_clk", |
| 1608 | .parent_names = (const char *[]){ "vcodec_src" }, |
| 1609 | .num_parents = 1, |
| 1610 | .ops = &clk_branch_ops, |
| 1611 | .flags = CLK_SET_RATE_PARENT, |
| 1612 | }, |
| 1613 | }, |
| 1614 | }; |
| 1615 | |
| 1616 | static struct freq_tbl clk_tbl_vpe[] = { |
| 1617 | { 27000000, P_PXO, 1 }, |
| 1618 | { 34909000, P_PLL8, 11 }, |
| 1619 | { 38400000, P_PLL8, 10 }, |
| 1620 | { 64000000, P_PLL8, 6 }, |
| 1621 | { 76800000, P_PLL8, 5 }, |
| 1622 | { 96000000, P_PLL8, 4 }, |
| 1623 | { 100000000, P_PLL2, 8 }, |
| 1624 | { 160000000, P_PLL2, 5 }, |
| 1625 | { } |
| 1626 | }; |
| 1627 | |
| 1628 | static struct clk_rcg vpe_src = { |
| 1629 | .ns_reg = 0x0118, |
| 1630 | .p = { |
| 1631 | .pre_div_shift = 12, |
| 1632 | .pre_div_width = 4, |
| 1633 | }, |
| 1634 | .s = { |
| 1635 | .src_sel_shift = 0, |
| 1636 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1637 | }, |
| 1638 | .freq_tbl = clk_tbl_vpe, |
| 1639 | .clkr = { |
| 1640 | .enable_reg = 0x0110, |
| 1641 | .enable_mask = BIT(2), |
| 1642 | .hw.init = &(struct clk_init_data){ |
| 1643 | .name = "vpe_src", |
| 1644 | .parent_names = mmcc_pxo_pll8_pll2, |
| 1645 | .num_parents = 3, |
| 1646 | .ops = &clk_rcg_ops, |
| 1647 | }, |
| 1648 | }, |
| 1649 | }; |
| 1650 | |
| 1651 | static struct clk_branch vpe_clk = { |
| 1652 | .halt_reg = 0x01c8, |
| 1653 | .halt_bit = 28, |
| 1654 | .clkr = { |
| 1655 | .enable_reg = 0x0110, |
| 1656 | .enable_mask = BIT(0), |
| 1657 | .hw.init = &(struct clk_init_data){ |
| 1658 | .name = "vpe_clk", |
| 1659 | .parent_names = (const char *[]){ "vpe_src" }, |
| 1660 | .num_parents = 1, |
| 1661 | .ops = &clk_branch_ops, |
| 1662 | .flags = CLK_SET_RATE_PARENT, |
| 1663 | }, |
| 1664 | }, |
| 1665 | }; |
| 1666 | |
| 1667 | static struct freq_tbl clk_tbl_vfe[] = { |
| 1668 | { 13960000, P_PLL8, 1, 2, 55 }, |
| 1669 | { 27000000, P_PXO, 1, 0, 0 }, |
| 1670 | { 36570000, P_PLL8, 1, 2, 21 }, |
| 1671 | { 38400000, P_PLL8, 2, 1, 5 }, |
| 1672 | { 45180000, P_PLL8, 1, 2, 17 }, |
| 1673 | { 48000000, P_PLL8, 2, 1, 4 }, |
| 1674 | { 54860000, P_PLL8, 1, 1, 7 }, |
| 1675 | { 64000000, P_PLL8, 2, 1, 3 }, |
| 1676 | { 76800000, P_PLL8, 1, 1, 5 }, |
| 1677 | { 96000000, P_PLL8, 2, 1, 2 }, |
| 1678 | { 109710000, P_PLL8, 1, 2, 7 }, |
| 1679 | { 128000000, P_PLL8, 1, 1, 3 }, |
| 1680 | { 153600000, P_PLL8, 1, 2, 5 }, |
| 1681 | { 200000000, P_PLL2, 2, 1, 2 }, |
| 1682 | { 228570000, P_PLL2, 1, 2, 7 }, |
| 1683 | { 266667000, P_PLL2, 1, 1, 3 }, |
| 1684 | { 320000000, P_PLL2, 1, 2, 5 }, |
| 1685 | { } |
| 1686 | }; |
| 1687 | |
| 1688 | static struct clk_rcg vfe_src = { |
| 1689 | .ns_reg = 0x0108, |
| 1690 | .mn = { |
| 1691 | .mnctr_en_bit = 5, |
| 1692 | .mnctr_reset_bit = 7, |
| 1693 | .mnctr_mode_shift = 6, |
| 1694 | .n_val_shift = 16, |
| 1695 | .m_val_shift = 8, |
| 1696 | .width = 8, |
| 1697 | }, |
| 1698 | .p = { |
| 1699 | .pre_div_shift = 10, |
| 1700 | .pre_div_width = 1, |
| 1701 | }, |
| 1702 | .s = { |
| 1703 | .src_sel_shift = 0, |
| 1704 | .parent_map = mmcc_pxo_pll8_pll2_map, |
| 1705 | }, |
| 1706 | .freq_tbl = clk_tbl_vfe, |
| 1707 | .clkr = { |
| 1708 | .enable_reg = 0x0104, |
| 1709 | .enable_mask = BIT(2), |
| 1710 | .hw.init = &(struct clk_init_data){ |
| 1711 | .name = "vfe_src", |
| 1712 | .parent_names = mmcc_pxo_pll8_pll2, |
| 1713 | .num_parents = 3, |
| 1714 | .ops = &clk_rcg_ops, |
| 1715 | }, |
| 1716 | }, |
| 1717 | }; |
| 1718 | |
| 1719 | static struct clk_branch vfe_clk = { |
| 1720 | .halt_reg = 0x01cc, |
| 1721 | .halt_bit = 6, |
| 1722 | .clkr = { |
| 1723 | .enable_reg = 0x0104, |
| 1724 | .enable_mask = BIT(0), |
| 1725 | .hw.init = &(struct clk_init_data){ |
| 1726 | .name = "vfe_clk", |
| 1727 | .parent_names = (const char *[]){ "vfe_src" }, |
| 1728 | .num_parents = 1, |
| 1729 | .ops = &clk_branch_ops, |
| 1730 | .flags = CLK_SET_RATE_PARENT, |
| 1731 | }, |
| 1732 | }, |
| 1733 | }; |
| 1734 | |
| 1735 | static struct clk_branch vfe_csi_clk = { |
| 1736 | .halt_reg = 0x01cc, |
| 1737 | .halt_bit = 8, |
| 1738 | .clkr = { |
| 1739 | .enable_reg = 0x0104, |
| 1740 | .enable_mask = BIT(12), |
| 1741 | .hw.init = &(struct clk_init_data){ |
| 1742 | .parent_names = (const char *[]){ "vfe_src" }, |
| 1743 | .num_parents = 1, |
| 1744 | .name = "vfe_csi_clk", |
| 1745 | .ops = &clk_branch_ops, |
| 1746 | .flags = CLK_SET_RATE_PARENT, |
| 1747 | }, |
| 1748 | }, |
| 1749 | }; |
| 1750 | |
| 1751 | static struct clk_branch gmem_axi_clk = { |
| 1752 | .halt_reg = 0x01d8, |
| 1753 | .halt_bit = 6, |
| 1754 | .clkr = { |
| 1755 | .enable_reg = 0x0018, |
| 1756 | .enable_mask = BIT(24), |
| 1757 | .hw.init = &(struct clk_init_data){ |
| 1758 | .name = "gmem_axi_clk", |
| 1759 | .ops = &clk_branch_ops, |
| 1760 | .flags = CLK_IS_ROOT, |
| 1761 | }, |
| 1762 | }, |
| 1763 | }; |
| 1764 | |
| 1765 | static struct clk_branch ijpeg_axi_clk = { |
| 1766 | .hwcg_reg = 0x0018, |
| 1767 | .hwcg_bit = 11, |
| 1768 | .halt_reg = 0x01d8, |
| 1769 | .halt_bit = 4, |
| 1770 | .clkr = { |
| 1771 | .enable_reg = 0x0018, |
| 1772 | .enable_mask = BIT(21), |
| 1773 | .hw.init = &(struct clk_init_data){ |
| 1774 | .name = "ijpeg_axi_clk", |
| 1775 | .ops = &clk_branch_ops, |
| 1776 | .flags = CLK_IS_ROOT, |
| 1777 | }, |
| 1778 | }, |
| 1779 | }; |
| 1780 | |
| 1781 | static struct clk_branch mmss_imem_axi_clk = { |
| 1782 | .hwcg_reg = 0x0018, |
| 1783 | .hwcg_bit = 15, |
| 1784 | .halt_reg = 0x01d8, |
| 1785 | .halt_bit = 7, |
| 1786 | .clkr = { |
| 1787 | .enable_reg = 0x0018, |
| 1788 | .enable_mask = BIT(22), |
| 1789 | .hw.init = &(struct clk_init_data){ |
| 1790 | .name = "mmss_imem_axi_clk", |
| 1791 | .ops = &clk_branch_ops, |
| 1792 | .flags = CLK_IS_ROOT, |
| 1793 | }, |
| 1794 | }, |
| 1795 | }; |
| 1796 | |
| 1797 | static struct clk_branch jpegd_axi_clk = { |
| 1798 | .halt_reg = 0x01d8, |
| 1799 | .halt_bit = 5, |
| 1800 | .clkr = { |
| 1801 | .enable_reg = 0x0018, |
| 1802 | .enable_mask = BIT(25), |
| 1803 | .hw.init = &(struct clk_init_data){ |
| 1804 | .name = "jpegd_axi_clk", |
| 1805 | .ops = &clk_branch_ops, |
| 1806 | .flags = CLK_IS_ROOT, |
| 1807 | }, |
| 1808 | }, |
| 1809 | }; |
| 1810 | |
| 1811 | static struct clk_branch vcodec_axi_b_clk = { |
| 1812 | .hwcg_reg = 0x0114, |
| 1813 | .hwcg_bit = 22, |
| 1814 | .halt_reg = 0x01e8, |
| 1815 | .halt_bit = 25, |
| 1816 | .clkr = { |
| 1817 | .enable_reg = 0x0114, |
| 1818 | .enable_mask = BIT(23), |
| 1819 | .hw.init = &(struct clk_init_data){ |
| 1820 | .name = "vcodec_axi_b_clk", |
| 1821 | .ops = &clk_branch_ops, |
| 1822 | .flags = CLK_IS_ROOT, |
| 1823 | }, |
| 1824 | }, |
| 1825 | }; |
| 1826 | |
| 1827 | static struct clk_branch vcodec_axi_a_clk = { |
| 1828 | .hwcg_reg = 0x0114, |
| 1829 | .hwcg_bit = 24, |
| 1830 | .halt_reg = 0x01e8, |
| 1831 | .halt_bit = 26, |
| 1832 | .clkr = { |
| 1833 | .enable_reg = 0x0114, |
| 1834 | .enable_mask = BIT(25), |
| 1835 | .hw.init = &(struct clk_init_data){ |
| 1836 | .name = "vcodec_axi_a_clk", |
| 1837 | .ops = &clk_branch_ops, |
| 1838 | .flags = CLK_IS_ROOT, |
| 1839 | }, |
| 1840 | }, |
| 1841 | }; |
| 1842 | |
| 1843 | static struct clk_branch vcodec_axi_clk = { |
| 1844 | .hwcg_reg = 0x0018, |
| 1845 | .hwcg_bit = 13, |
| 1846 | .halt_reg = 0x01d8, |
| 1847 | .halt_bit = 3, |
| 1848 | .clkr = { |
| 1849 | .enable_reg = 0x0018, |
| 1850 | .enable_mask = BIT(19), |
| 1851 | .hw.init = &(struct clk_init_data){ |
| 1852 | .name = "vcodec_axi_clk", |
| 1853 | .ops = &clk_branch_ops, |
| 1854 | .flags = CLK_IS_ROOT, |
| 1855 | }, |
| 1856 | }, |
| 1857 | }; |
| 1858 | |
| 1859 | static struct clk_branch vfe_axi_clk = { |
| 1860 | .halt_reg = 0x01d8, |
| 1861 | .halt_bit = 0, |
| 1862 | .clkr = { |
| 1863 | .enable_reg = 0x0018, |
| 1864 | .enable_mask = BIT(18), |
| 1865 | .hw.init = &(struct clk_init_data){ |
| 1866 | .name = "vfe_axi_clk", |
| 1867 | .ops = &clk_branch_ops, |
| 1868 | .flags = CLK_IS_ROOT, |
| 1869 | }, |
| 1870 | }, |
| 1871 | }; |
| 1872 | |
| 1873 | static struct clk_branch mdp_axi_clk = { |
| 1874 | .hwcg_reg = 0x0018, |
| 1875 | .hwcg_bit = 16, |
| 1876 | .halt_reg = 0x01d8, |
| 1877 | .halt_bit = 8, |
| 1878 | .clkr = { |
| 1879 | .enable_reg = 0x0018, |
| 1880 | .enable_mask = BIT(23), |
| 1881 | .hw.init = &(struct clk_init_data){ |
| 1882 | .name = "mdp_axi_clk", |
| 1883 | .ops = &clk_branch_ops, |
| 1884 | .flags = CLK_IS_ROOT, |
| 1885 | }, |
| 1886 | }, |
| 1887 | }; |
| 1888 | |
| 1889 | static struct clk_branch rot_axi_clk = { |
| 1890 | .hwcg_reg = 0x0020, |
| 1891 | .hwcg_bit = 25, |
| 1892 | .halt_reg = 0x01d8, |
| 1893 | .halt_bit = 2, |
| 1894 | .clkr = { |
| 1895 | .enable_reg = 0x0020, |
| 1896 | .enable_mask = BIT(24), |
| 1897 | .hw.init = &(struct clk_init_data){ |
| 1898 | .name = "rot_axi_clk", |
| 1899 | .ops = &clk_branch_ops, |
| 1900 | .flags = CLK_IS_ROOT, |
| 1901 | }, |
| 1902 | }, |
| 1903 | }; |
| 1904 | |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 1905 | static struct clk_branch vcap_axi_clk = { |
| 1906 | .halt_reg = 0x0240, |
| 1907 | .halt_bit = 20, |
| 1908 | .hwcg_reg = 0x0244, |
| 1909 | .hwcg_bit = 11, |
| 1910 | .clkr = { |
| 1911 | .enable_reg = 0x0244, |
| 1912 | .enable_mask = BIT(12), |
| 1913 | .hw.init = &(struct clk_init_data){ |
| 1914 | .name = "vcap_axi_clk", |
| 1915 | .ops = &clk_branch_ops, |
| 1916 | .flags = CLK_IS_ROOT, |
| 1917 | }, |
| 1918 | }, |
| 1919 | }; |
| 1920 | |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 1921 | static struct clk_branch vpe_axi_clk = { |
| 1922 | .hwcg_reg = 0x0020, |
| 1923 | .hwcg_bit = 27, |
| 1924 | .halt_reg = 0x01d8, |
| 1925 | .halt_bit = 1, |
| 1926 | .clkr = { |
| 1927 | .enable_reg = 0x0020, |
| 1928 | .enable_mask = BIT(26), |
| 1929 | .hw.init = &(struct clk_init_data){ |
| 1930 | .name = "vpe_axi_clk", |
| 1931 | .ops = &clk_branch_ops, |
| 1932 | .flags = CLK_IS_ROOT, |
| 1933 | }, |
| 1934 | }, |
| 1935 | }; |
| 1936 | |
| 1937 | static struct clk_branch gfx3d_axi_clk = { |
| 1938 | .hwcg_reg = 0x0244, |
| 1939 | .hwcg_bit = 24, |
| 1940 | .halt_reg = 0x0240, |
| 1941 | .halt_bit = 30, |
| 1942 | .clkr = { |
| 1943 | .enable_reg = 0x0244, |
| 1944 | .enable_mask = BIT(25), |
| 1945 | .hw.init = &(struct clk_init_data){ |
| 1946 | .name = "gfx3d_axi_clk", |
| 1947 | .ops = &clk_branch_ops, |
| 1948 | .flags = CLK_IS_ROOT, |
| 1949 | }, |
| 1950 | }, |
| 1951 | }; |
| 1952 | |
| 1953 | static struct clk_branch amp_ahb_clk = { |
| 1954 | .halt_reg = 0x01dc, |
| 1955 | .halt_bit = 18, |
| 1956 | .clkr = { |
| 1957 | .enable_reg = 0x0008, |
| 1958 | .enable_mask = BIT(24), |
| 1959 | .hw.init = &(struct clk_init_data){ |
| 1960 | .name = "amp_ahb_clk", |
| 1961 | .ops = &clk_branch_ops, |
| 1962 | .flags = CLK_IS_ROOT, |
| 1963 | }, |
| 1964 | }, |
| 1965 | }; |
| 1966 | |
| 1967 | static struct clk_branch csi_ahb_clk = { |
| 1968 | .halt_reg = 0x01dc, |
| 1969 | .halt_bit = 16, |
| 1970 | .clkr = { |
| 1971 | .enable_reg = 0x0008, |
| 1972 | .enable_mask = BIT(7), |
| 1973 | .hw.init = &(struct clk_init_data){ |
| 1974 | .name = "csi_ahb_clk", |
| 1975 | .ops = &clk_branch_ops, |
| 1976 | .flags = CLK_IS_ROOT |
| 1977 | }, |
| 1978 | }, |
| 1979 | }; |
| 1980 | |
| 1981 | static struct clk_branch dsi_m_ahb_clk = { |
| 1982 | .halt_reg = 0x01dc, |
| 1983 | .halt_bit = 19, |
| 1984 | .clkr = { |
| 1985 | .enable_reg = 0x0008, |
| 1986 | .enable_mask = BIT(9), |
| 1987 | .hw.init = &(struct clk_init_data){ |
| 1988 | .name = "dsi_m_ahb_clk", |
| 1989 | .ops = &clk_branch_ops, |
| 1990 | .flags = CLK_IS_ROOT, |
| 1991 | }, |
| 1992 | }, |
| 1993 | }; |
| 1994 | |
| 1995 | static struct clk_branch dsi_s_ahb_clk = { |
| 1996 | .hwcg_reg = 0x0038, |
| 1997 | .hwcg_bit = 20, |
| 1998 | .halt_reg = 0x01dc, |
| 1999 | .halt_bit = 21, |
| 2000 | .clkr = { |
| 2001 | .enable_reg = 0x0008, |
| 2002 | .enable_mask = BIT(18), |
| 2003 | .hw.init = &(struct clk_init_data){ |
| 2004 | .name = "dsi_s_ahb_clk", |
| 2005 | .ops = &clk_branch_ops, |
| 2006 | .flags = CLK_IS_ROOT, |
| 2007 | }, |
| 2008 | }, |
| 2009 | }; |
| 2010 | |
| 2011 | static struct clk_branch dsi2_m_ahb_clk = { |
| 2012 | .halt_reg = 0x01d8, |
| 2013 | .halt_bit = 18, |
| 2014 | .clkr = { |
| 2015 | .enable_reg = 0x0008, |
| 2016 | .enable_mask = BIT(17), |
| 2017 | .hw.init = &(struct clk_init_data){ |
| 2018 | .name = "dsi2_m_ahb_clk", |
| 2019 | .ops = &clk_branch_ops, |
| 2020 | .flags = CLK_IS_ROOT |
| 2021 | }, |
| 2022 | }, |
| 2023 | }; |
| 2024 | |
| 2025 | static struct clk_branch dsi2_s_ahb_clk = { |
| 2026 | .hwcg_reg = 0x0038, |
| 2027 | .hwcg_bit = 15, |
| 2028 | .halt_reg = 0x01dc, |
| 2029 | .halt_bit = 20, |
| 2030 | .clkr = { |
| 2031 | .enable_reg = 0x0008, |
| 2032 | .enable_mask = BIT(22), |
| 2033 | .hw.init = &(struct clk_init_data){ |
| 2034 | .name = "dsi2_s_ahb_clk", |
| 2035 | .ops = &clk_branch_ops, |
| 2036 | .flags = CLK_IS_ROOT, |
| 2037 | }, |
| 2038 | }, |
| 2039 | }; |
| 2040 | |
| 2041 | static struct clk_branch gfx2d0_ahb_clk = { |
| 2042 | .hwcg_reg = 0x0038, |
| 2043 | .hwcg_bit = 28, |
| 2044 | .halt_reg = 0x01dc, |
| 2045 | .halt_bit = 2, |
| 2046 | .clkr = { |
| 2047 | .enable_reg = 0x0008, |
| 2048 | .enable_mask = BIT(19), |
| 2049 | .hw.init = &(struct clk_init_data){ |
| 2050 | .name = "gfx2d0_ahb_clk", |
| 2051 | .ops = &clk_branch_ops, |
| 2052 | .flags = CLK_IS_ROOT, |
| 2053 | }, |
| 2054 | }, |
| 2055 | }; |
| 2056 | |
| 2057 | static struct clk_branch gfx2d1_ahb_clk = { |
| 2058 | .hwcg_reg = 0x0038, |
| 2059 | .hwcg_bit = 29, |
| 2060 | .halt_reg = 0x01dc, |
| 2061 | .halt_bit = 3, |
| 2062 | .clkr = { |
| 2063 | .enable_reg = 0x0008, |
| 2064 | .enable_mask = BIT(2), |
| 2065 | .hw.init = &(struct clk_init_data){ |
| 2066 | .name = "gfx2d1_ahb_clk", |
| 2067 | .ops = &clk_branch_ops, |
| 2068 | .flags = CLK_IS_ROOT, |
| 2069 | }, |
| 2070 | }, |
| 2071 | }; |
| 2072 | |
| 2073 | static struct clk_branch gfx3d_ahb_clk = { |
| 2074 | .hwcg_reg = 0x0038, |
| 2075 | .hwcg_bit = 27, |
| 2076 | .halt_reg = 0x01dc, |
| 2077 | .halt_bit = 4, |
| 2078 | .clkr = { |
| 2079 | .enable_reg = 0x0008, |
| 2080 | .enable_mask = BIT(3), |
| 2081 | .hw.init = &(struct clk_init_data){ |
| 2082 | .name = "gfx3d_ahb_clk", |
| 2083 | .ops = &clk_branch_ops, |
| 2084 | .flags = CLK_IS_ROOT, |
| 2085 | }, |
| 2086 | }, |
| 2087 | }; |
| 2088 | |
| 2089 | static struct clk_branch hdmi_m_ahb_clk = { |
| 2090 | .hwcg_reg = 0x0038, |
| 2091 | .hwcg_bit = 21, |
| 2092 | .halt_reg = 0x01dc, |
| 2093 | .halt_bit = 5, |
| 2094 | .clkr = { |
| 2095 | .enable_reg = 0x0008, |
| 2096 | .enable_mask = BIT(14), |
| 2097 | .hw.init = &(struct clk_init_data){ |
| 2098 | .name = "hdmi_m_ahb_clk", |
| 2099 | .ops = &clk_branch_ops, |
| 2100 | .flags = CLK_IS_ROOT, |
| 2101 | }, |
| 2102 | }, |
| 2103 | }; |
| 2104 | |
| 2105 | static struct clk_branch hdmi_s_ahb_clk = { |
| 2106 | .hwcg_reg = 0x0038, |
| 2107 | .hwcg_bit = 22, |
| 2108 | .halt_reg = 0x01dc, |
| 2109 | .halt_bit = 6, |
| 2110 | .clkr = { |
| 2111 | .enable_reg = 0x0008, |
| 2112 | .enable_mask = BIT(4), |
| 2113 | .hw.init = &(struct clk_init_data){ |
| 2114 | .name = "hdmi_s_ahb_clk", |
| 2115 | .ops = &clk_branch_ops, |
| 2116 | .flags = CLK_IS_ROOT, |
| 2117 | }, |
| 2118 | }, |
| 2119 | }; |
| 2120 | |
| 2121 | static struct clk_branch ijpeg_ahb_clk = { |
| 2122 | .halt_reg = 0x01dc, |
| 2123 | .halt_bit = 9, |
| 2124 | .clkr = { |
| 2125 | .enable_reg = 0x0008, |
| 2126 | .enable_mask = BIT(5), |
| 2127 | .hw.init = &(struct clk_init_data){ |
| 2128 | .name = "ijpeg_ahb_clk", |
| 2129 | .ops = &clk_branch_ops, |
| 2130 | .flags = CLK_IS_ROOT |
| 2131 | }, |
| 2132 | }, |
| 2133 | }; |
| 2134 | |
| 2135 | static struct clk_branch mmss_imem_ahb_clk = { |
| 2136 | .hwcg_reg = 0x0038, |
| 2137 | .hwcg_bit = 12, |
| 2138 | .halt_reg = 0x01dc, |
| 2139 | .halt_bit = 10, |
| 2140 | .clkr = { |
| 2141 | .enable_reg = 0x0008, |
| 2142 | .enable_mask = BIT(6), |
| 2143 | .hw.init = &(struct clk_init_data){ |
| 2144 | .name = "mmss_imem_ahb_clk", |
| 2145 | .ops = &clk_branch_ops, |
| 2146 | .flags = CLK_IS_ROOT |
| 2147 | }, |
| 2148 | }, |
| 2149 | }; |
| 2150 | |
| 2151 | static struct clk_branch jpegd_ahb_clk = { |
| 2152 | .halt_reg = 0x01dc, |
| 2153 | .halt_bit = 7, |
| 2154 | .clkr = { |
| 2155 | .enable_reg = 0x0008, |
| 2156 | .enable_mask = BIT(21), |
| 2157 | .hw.init = &(struct clk_init_data){ |
| 2158 | .name = "jpegd_ahb_clk", |
| 2159 | .ops = &clk_branch_ops, |
| 2160 | .flags = CLK_IS_ROOT, |
| 2161 | }, |
| 2162 | }, |
| 2163 | }; |
| 2164 | |
| 2165 | static struct clk_branch mdp_ahb_clk = { |
| 2166 | .halt_reg = 0x01dc, |
| 2167 | .halt_bit = 11, |
| 2168 | .clkr = { |
| 2169 | .enable_reg = 0x0008, |
| 2170 | .enable_mask = BIT(10), |
| 2171 | .hw.init = &(struct clk_init_data){ |
| 2172 | .name = "mdp_ahb_clk", |
| 2173 | .ops = &clk_branch_ops, |
| 2174 | .flags = CLK_IS_ROOT, |
| 2175 | }, |
| 2176 | }, |
| 2177 | }; |
| 2178 | |
| 2179 | static struct clk_branch rot_ahb_clk = { |
| 2180 | .halt_reg = 0x01dc, |
| 2181 | .halt_bit = 13, |
| 2182 | .clkr = { |
| 2183 | .enable_reg = 0x0008, |
| 2184 | .enable_mask = BIT(12), |
| 2185 | .hw.init = &(struct clk_init_data){ |
| 2186 | .name = "rot_ahb_clk", |
| 2187 | .ops = &clk_branch_ops, |
| 2188 | .flags = CLK_IS_ROOT |
| 2189 | }, |
| 2190 | }, |
| 2191 | }; |
| 2192 | |
| 2193 | static struct clk_branch smmu_ahb_clk = { |
| 2194 | .hwcg_reg = 0x0008, |
| 2195 | .hwcg_bit = 26, |
| 2196 | .halt_reg = 0x01dc, |
| 2197 | .halt_bit = 22, |
| 2198 | .clkr = { |
| 2199 | .enable_reg = 0x0008, |
| 2200 | .enable_mask = BIT(15), |
| 2201 | .hw.init = &(struct clk_init_data){ |
| 2202 | .name = "smmu_ahb_clk", |
| 2203 | .ops = &clk_branch_ops, |
| 2204 | .flags = CLK_IS_ROOT, |
| 2205 | }, |
| 2206 | }, |
| 2207 | }; |
| 2208 | |
| 2209 | static struct clk_branch tv_enc_ahb_clk = { |
| 2210 | .halt_reg = 0x01dc, |
| 2211 | .halt_bit = 23, |
| 2212 | .clkr = { |
| 2213 | .enable_reg = 0x0008, |
| 2214 | .enable_mask = BIT(25), |
| 2215 | .hw.init = &(struct clk_init_data){ |
| 2216 | .name = "tv_enc_ahb_clk", |
| 2217 | .ops = &clk_branch_ops, |
| 2218 | .flags = CLK_IS_ROOT, |
| 2219 | }, |
| 2220 | }, |
| 2221 | }; |
| 2222 | |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 2223 | static struct clk_branch vcap_ahb_clk = { |
| 2224 | .halt_reg = 0x0240, |
| 2225 | .halt_bit = 23, |
| 2226 | .clkr = { |
| 2227 | .enable_reg = 0x0248, |
| 2228 | .enable_mask = BIT(1), |
| 2229 | .hw.init = &(struct clk_init_data){ |
| 2230 | .name = "vcap_ahb_clk", |
| 2231 | .ops = &clk_branch_ops, |
| 2232 | .flags = CLK_IS_ROOT, |
| 2233 | }, |
| 2234 | }, |
| 2235 | }; |
| 2236 | |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 2237 | static struct clk_branch vcodec_ahb_clk = { |
| 2238 | .hwcg_reg = 0x0038, |
| 2239 | .hwcg_bit = 26, |
| 2240 | .halt_reg = 0x01dc, |
| 2241 | .halt_bit = 12, |
| 2242 | .clkr = { |
| 2243 | .enable_reg = 0x0008, |
| 2244 | .enable_mask = BIT(11), |
| 2245 | .hw.init = &(struct clk_init_data){ |
| 2246 | .name = "vcodec_ahb_clk", |
| 2247 | .ops = &clk_branch_ops, |
| 2248 | .flags = CLK_IS_ROOT, |
| 2249 | }, |
| 2250 | }, |
| 2251 | }; |
| 2252 | |
| 2253 | static struct clk_branch vfe_ahb_clk = { |
| 2254 | .halt_reg = 0x01dc, |
| 2255 | .halt_bit = 14, |
| 2256 | .clkr = { |
| 2257 | .enable_reg = 0x0008, |
| 2258 | .enable_mask = BIT(13), |
| 2259 | .hw.init = &(struct clk_init_data){ |
| 2260 | .name = "vfe_ahb_clk", |
| 2261 | .ops = &clk_branch_ops, |
| 2262 | .flags = CLK_IS_ROOT, |
| 2263 | }, |
| 2264 | }, |
| 2265 | }; |
| 2266 | |
| 2267 | static struct clk_branch vpe_ahb_clk = { |
| 2268 | .halt_reg = 0x01dc, |
| 2269 | .halt_bit = 15, |
| 2270 | .clkr = { |
| 2271 | .enable_reg = 0x0008, |
| 2272 | .enable_mask = BIT(16), |
| 2273 | .hw.init = &(struct clk_init_data){ |
| 2274 | .name = "vpe_ahb_clk", |
| 2275 | .ops = &clk_branch_ops, |
| 2276 | .flags = CLK_IS_ROOT, |
| 2277 | }, |
| 2278 | }, |
| 2279 | }; |
| 2280 | |
| 2281 | static struct clk_regmap *mmcc_msm8960_clks[] = { |
| 2282 | [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr, |
| 2283 | [AMP_AHB_CLK] = &_ahb_clk.clkr, |
| 2284 | [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr, |
| 2285 | [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr, |
| 2286 | [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr, |
| 2287 | [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr, |
| 2288 | [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr, |
| 2289 | [VPE_AHB_CLK] = &vpe_ahb_clk.clkr, |
| 2290 | [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr, |
| 2291 | [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr, |
| 2292 | [VFE_AHB_CLK] = &vfe_ahb_clk.clkr, |
| 2293 | [ROT_AHB_CLK] = &rot_ahb_clk.clkr, |
| 2294 | [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr, |
| 2295 | [MDP_AHB_CLK] = &mdp_ahb_clk.clkr, |
| 2296 | [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr, |
| 2297 | [CSI_AHB_CLK] = &csi_ahb_clk.clkr, |
| 2298 | [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr, |
| 2299 | [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr, |
| 2300 | [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr, |
| 2301 | [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr, |
| 2302 | [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr, |
| 2303 | [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr, |
| 2304 | [GMEM_AXI_CLK] = &gmem_axi_clk.clkr, |
| 2305 | [MDP_AXI_CLK] = &mdp_axi_clk.clkr, |
| 2306 | [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr, |
| 2307 | [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr, |
| 2308 | [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr, |
| 2309 | [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr, |
| 2310 | [VFE_AXI_CLK] = &vfe_axi_clk.clkr, |
| 2311 | [VPE_AXI_CLK] = &vpe_axi_clk.clkr, |
| 2312 | [ROT_AXI_CLK] = &rot_axi_clk.clkr, |
| 2313 | [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr, |
| 2314 | [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr, |
| 2315 | [CSI0_SRC] = &csi0_src.clkr, |
| 2316 | [CSI0_CLK] = &csi0_clk.clkr, |
| 2317 | [CSI0_PHY_CLK] = &csi0_phy_clk.clkr, |
| 2318 | [CSI1_SRC] = &csi1_src.clkr, |
| 2319 | [CSI1_CLK] = &csi1_clk.clkr, |
| 2320 | [CSI1_PHY_CLK] = &csi1_phy_clk.clkr, |
| 2321 | [CSI2_SRC] = &csi2_src.clkr, |
| 2322 | [CSI2_CLK] = &csi2_clk.clkr, |
| 2323 | [CSI2_PHY_CLK] = &csi2_phy_clk.clkr, |
| 2324 | [CSI_PIX_CLK] = &csi_pix_clk.clkr, |
| 2325 | [CSI_RDI_CLK] = &csi_rdi_clk.clkr, |
| 2326 | [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr, |
| 2327 | [HDMI_APP_CLK] = &hdmi_app_clk.clkr, |
| 2328 | [CSI_PIX1_CLK] = &csi_pix1_clk.clkr, |
| 2329 | [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr, |
| 2330 | [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr, |
| 2331 | [GFX2D0_SRC] = &gfx2d0_src.clkr, |
| 2332 | [GFX2D0_CLK] = &gfx2d0_clk.clkr, |
| 2333 | [GFX2D1_SRC] = &gfx2d1_src.clkr, |
| 2334 | [GFX2D1_CLK] = &gfx2d1_clk.clkr, |
| 2335 | [GFX3D_SRC] = &gfx3d_src.clkr, |
| 2336 | [GFX3D_CLK] = &gfx3d_clk.clkr, |
| 2337 | [IJPEG_SRC] = &ijpeg_src.clkr, |
| 2338 | [IJPEG_CLK] = &ijpeg_clk.clkr, |
| 2339 | [JPEGD_SRC] = &jpegd_src.clkr, |
| 2340 | [JPEGD_CLK] = &jpegd_clk.clkr, |
| 2341 | [MDP_SRC] = &mdp_src.clkr, |
| 2342 | [MDP_CLK] = &mdp_clk.clkr, |
| 2343 | [MDP_LUT_CLK] = &mdp_lut_clk.clkr, |
| 2344 | [ROT_SRC] = &rot_src.clkr, |
| 2345 | [ROT_CLK] = &rot_clk.clkr, |
| 2346 | [TV_ENC_CLK] = &tv_enc_clk.clkr, |
| 2347 | [TV_DAC_CLK] = &tv_dac_clk.clkr, |
| 2348 | [HDMI_TV_CLK] = &hdmi_tv_clk.clkr, |
| 2349 | [MDP_TV_CLK] = &mdp_tv_clk.clkr, |
| 2350 | [TV_SRC] = &tv_src.clkr, |
| 2351 | [VCODEC_SRC] = &vcodec_src.clkr, |
| 2352 | [VCODEC_CLK] = &vcodec_clk.clkr, |
| 2353 | [VFE_SRC] = &vfe_src.clkr, |
| 2354 | [VFE_CLK] = &vfe_clk.clkr, |
| 2355 | [VFE_CSI_CLK] = &vfe_csi_clk.clkr, |
| 2356 | [VPE_SRC] = &vpe_src.clkr, |
| 2357 | [VPE_CLK] = &vpe_clk.clkr, |
| 2358 | [CAMCLK0_SRC] = &camclk0_src.clkr, |
| 2359 | [CAMCLK0_CLK] = &camclk0_clk.clkr, |
| 2360 | [CAMCLK1_SRC] = &camclk1_src.clkr, |
| 2361 | [CAMCLK1_CLK] = &camclk1_clk.clkr, |
| 2362 | [CAMCLK2_SRC] = &camclk2_src.clkr, |
| 2363 | [CAMCLK2_CLK] = &camclk2_clk.clkr, |
| 2364 | [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr, |
| 2365 | [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr, |
| 2366 | [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr, |
| 2367 | [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr, |
| 2368 | [PLL2] = &pll2.clkr, |
| 2369 | }; |
| 2370 | |
| 2371 | static const struct qcom_reset_map mmcc_msm8960_resets[] = { |
| 2372 | [VPE_AXI_RESET] = { 0x0208, 15 }, |
| 2373 | [IJPEG_AXI_RESET] = { 0x0208, 14 }, |
| 2374 | [MPD_AXI_RESET] = { 0x0208, 13 }, |
| 2375 | [VFE_AXI_RESET] = { 0x0208, 9 }, |
| 2376 | [SP_AXI_RESET] = { 0x0208, 8 }, |
| 2377 | [VCODEC_AXI_RESET] = { 0x0208, 7 }, |
| 2378 | [ROT_AXI_RESET] = { 0x0208, 6 }, |
| 2379 | [VCODEC_AXI_A_RESET] = { 0x0208, 5 }, |
| 2380 | [VCODEC_AXI_B_RESET] = { 0x0208, 4 }, |
| 2381 | [FAB_S3_AXI_RESET] = { 0x0208, 3 }, |
| 2382 | [FAB_S2_AXI_RESET] = { 0x0208, 2 }, |
| 2383 | [FAB_S1_AXI_RESET] = { 0x0208, 1 }, |
| 2384 | [FAB_S0_AXI_RESET] = { 0x0208 }, |
| 2385 | [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 }, |
| 2386 | [SMMU_VPE_AHB_RESET] = { 0x020c, 30 }, |
| 2387 | [SMMU_VFE_AHB_RESET] = { 0x020c, 29 }, |
| 2388 | [SMMU_ROT_AHB_RESET] = { 0x020c, 28 }, |
| 2389 | [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 }, |
| 2390 | [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 }, |
| 2391 | [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 }, |
| 2392 | [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 }, |
| 2393 | [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 }, |
| 2394 | [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 }, |
| 2395 | [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 }, |
| 2396 | [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 }, |
| 2397 | [APU_AHB_RESET] = { 0x020c, 18 }, |
| 2398 | [CSI_AHB_RESET] = { 0x020c, 17 }, |
| 2399 | [TV_ENC_AHB_RESET] = { 0x020c, 15 }, |
| 2400 | [VPE_AHB_RESET] = { 0x020c, 14 }, |
| 2401 | [FABRIC_AHB_RESET] = { 0x020c, 13 }, |
| 2402 | [GFX2D0_AHB_RESET] = { 0x020c, 12 }, |
| 2403 | [GFX2D1_AHB_RESET] = { 0x020c, 11 }, |
| 2404 | [GFX3D_AHB_RESET] = { 0x020c, 10 }, |
| 2405 | [HDMI_AHB_RESET] = { 0x020c, 9 }, |
| 2406 | [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 }, |
| 2407 | [IJPEG_AHB_RESET] = { 0x020c, 7 }, |
| 2408 | [DSI_M_AHB_RESET] = { 0x020c, 6 }, |
| 2409 | [DSI_S_AHB_RESET] = { 0x020c, 5 }, |
| 2410 | [JPEGD_AHB_RESET] = { 0x020c, 4 }, |
| 2411 | [MDP_AHB_RESET] = { 0x020c, 3 }, |
| 2412 | [ROT_AHB_RESET] = { 0x020c, 2 }, |
| 2413 | [VCODEC_AHB_RESET] = { 0x020c, 1 }, |
| 2414 | [VFE_AHB_RESET] = { 0x020c, 0 }, |
| 2415 | [DSI2_M_AHB_RESET] = { 0x0210, 31 }, |
| 2416 | [DSI2_S_AHB_RESET] = { 0x0210, 30 }, |
| 2417 | [CSIPHY2_RESET] = { 0x0210, 29 }, |
| 2418 | [CSI_PIX1_RESET] = { 0x0210, 28 }, |
| 2419 | [CSIPHY0_RESET] = { 0x0210, 27 }, |
| 2420 | [CSIPHY1_RESET] = { 0x0210, 26 }, |
| 2421 | [DSI2_RESET] = { 0x0210, 25 }, |
| 2422 | [VFE_CSI_RESET] = { 0x0210, 24 }, |
| 2423 | [MDP_RESET] = { 0x0210, 21 }, |
| 2424 | [AMP_RESET] = { 0x0210, 20 }, |
| 2425 | [JPEGD_RESET] = { 0x0210, 19 }, |
| 2426 | [CSI1_RESET] = { 0x0210, 18 }, |
| 2427 | [VPE_RESET] = { 0x0210, 17 }, |
| 2428 | [MMSS_FABRIC_RESET] = { 0x0210, 16 }, |
| 2429 | [VFE_RESET] = { 0x0210, 15 }, |
| 2430 | [GFX2D0_RESET] = { 0x0210, 14 }, |
| 2431 | [GFX2D1_RESET] = { 0x0210, 13 }, |
| 2432 | [GFX3D_RESET] = { 0x0210, 12 }, |
| 2433 | [HDMI_RESET] = { 0x0210, 11 }, |
| 2434 | [MMSS_IMEM_RESET] = { 0x0210, 10 }, |
| 2435 | [IJPEG_RESET] = { 0x0210, 9 }, |
| 2436 | [CSI0_RESET] = { 0x0210, 8 }, |
| 2437 | [DSI_RESET] = { 0x0210, 7 }, |
| 2438 | [VCODEC_RESET] = { 0x0210, 6 }, |
| 2439 | [MDP_TV_RESET] = { 0x0210, 4 }, |
| 2440 | [MDP_VSYNC_RESET] = { 0x0210, 3 }, |
| 2441 | [ROT_RESET] = { 0x0210, 2 }, |
| 2442 | [TV_HDMI_RESET] = { 0x0210, 1 }, |
| 2443 | [TV_ENC_RESET] = { 0x0210 }, |
| 2444 | [CSI2_RESET] = { 0x0214, 2 }, |
| 2445 | [CSI_RDI1_RESET] = { 0x0214, 1 }, |
| 2446 | [CSI_RDI2_RESET] = { 0x0214 }, |
| 2447 | }; |
| 2448 | |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 2449 | static struct clk_regmap *mmcc_apq8064_clks[] = { |
| 2450 | [AMP_AHB_CLK] = &_ahb_clk.clkr, |
| 2451 | [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr, |
| 2452 | [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr, |
| 2453 | [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr, |
| 2454 | [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr, |
| 2455 | [VPE_AHB_CLK] = &vpe_ahb_clk.clkr, |
| 2456 | [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr, |
| 2457 | [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr, |
| 2458 | [VFE_AHB_CLK] = &vfe_ahb_clk.clkr, |
| 2459 | [ROT_AHB_CLK] = &rot_ahb_clk.clkr, |
| 2460 | [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr, |
| 2461 | [MDP_AHB_CLK] = &mdp_ahb_clk.clkr, |
| 2462 | [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr, |
| 2463 | [CSI_AHB_CLK] = &csi_ahb_clk.clkr, |
| 2464 | [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr, |
| 2465 | [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr, |
| 2466 | [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr, |
| 2467 | [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr, |
| 2468 | [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr, |
| 2469 | [GMEM_AXI_CLK] = &gmem_axi_clk.clkr, |
| 2470 | [MDP_AXI_CLK] = &mdp_axi_clk.clkr, |
| 2471 | [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr, |
| 2472 | [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr, |
| 2473 | [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr, |
| 2474 | [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr, |
| 2475 | [VFE_AXI_CLK] = &vfe_axi_clk.clkr, |
| 2476 | [VPE_AXI_CLK] = &vpe_axi_clk.clkr, |
| 2477 | [ROT_AXI_CLK] = &rot_axi_clk.clkr, |
| 2478 | [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr, |
| 2479 | [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr, |
| 2480 | [CSI0_SRC] = &csi0_src.clkr, |
| 2481 | [CSI0_CLK] = &csi0_clk.clkr, |
| 2482 | [CSI0_PHY_CLK] = &csi0_phy_clk.clkr, |
| 2483 | [CSI1_SRC] = &csi1_src.clkr, |
| 2484 | [CSI1_CLK] = &csi1_clk.clkr, |
| 2485 | [CSI1_PHY_CLK] = &csi1_phy_clk.clkr, |
| 2486 | [CSI2_SRC] = &csi2_src.clkr, |
| 2487 | [CSI2_CLK] = &csi2_clk.clkr, |
| 2488 | [CSI2_PHY_CLK] = &csi2_phy_clk.clkr, |
| 2489 | [CSI_PIX_CLK] = &csi_pix_clk.clkr, |
| 2490 | [CSI_RDI_CLK] = &csi_rdi_clk.clkr, |
| 2491 | [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr, |
| 2492 | [HDMI_APP_CLK] = &hdmi_app_clk.clkr, |
| 2493 | [CSI_PIX1_CLK] = &csi_pix1_clk.clkr, |
| 2494 | [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr, |
| 2495 | [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr, |
| 2496 | [GFX3D_SRC] = &gfx3d_src.clkr, |
| 2497 | [GFX3D_CLK] = &gfx3d_clk.clkr, |
| 2498 | [IJPEG_SRC] = &ijpeg_src.clkr, |
| 2499 | [IJPEG_CLK] = &ijpeg_clk.clkr, |
| 2500 | [JPEGD_SRC] = &jpegd_src.clkr, |
| 2501 | [JPEGD_CLK] = &jpegd_clk.clkr, |
| 2502 | [MDP_SRC] = &mdp_src.clkr, |
| 2503 | [MDP_CLK] = &mdp_clk.clkr, |
| 2504 | [MDP_LUT_CLK] = &mdp_lut_clk.clkr, |
| 2505 | [ROT_SRC] = &rot_src.clkr, |
| 2506 | [ROT_CLK] = &rot_clk.clkr, |
| 2507 | [TV_DAC_CLK] = &tv_dac_clk.clkr, |
| 2508 | [HDMI_TV_CLK] = &hdmi_tv_clk.clkr, |
| 2509 | [MDP_TV_CLK] = &mdp_tv_clk.clkr, |
| 2510 | [TV_SRC] = &tv_src.clkr, |
| 2511 | [VCODEC_SRC] = &vcodec_src.clkr, |
| 2512 | [VCODEC_CLK] = &vcodec_clk.clkr, |
| 2513 | [VFE_SRC] = &vfe_src.clkr, |
| 2514 | [VFE_CLK] = &vfe_clk.clkr, |
| 2515 | [VFE_CSI_CLK] = &vfe_csi_clk.clkr, |
| 2516 | [VPE_SRC] = &vpe_src.clkr, |
| 2517 | [VPE_CLK] = &vpe_clk.clkr, |
| 2518 | [CAMCLK0_SRC] = &camclk0_src.clkr, |
| 2519 | [CAMCLK0_CLK] = &camclk0_clk.clkr, |
| 2520 | [CAMCLK1_SRC] = &camclk1_src.clkr, |
| 2521 | [CAMCLK1_CLK] = &camclk1_clk.clkr, |
| 2522 | [CAMCLK2_SRC] = &camclk2_src.clkr, |
| 2523 | [CAMCLK2_CLK] = &camclk2_clk.clkr, |
| 2524 | [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr, |
| 2525 | [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr, |
| 2526 | [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr, |
| 2527 | [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr, |
| 2528 | [PLL2] = &pll2.clkr, |
| 2529 | [RGB_TV_CLK] = &rgb_tv_clk.clkr, |
| 2530 | [NPL_TV_CLK] = &npl_tv_clk.clkr, |
| 2531 | [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr, |
| 2532 | [VCAP_AXI_CLK] = &vcap_axi_clk.clkr, |
| 2533 | [VCAP_SRC] = &vcap_src.clkr, |
| 2534 | [VCAP_CLK] = &vcap_clk.clkr, |
| 2535 | [VCAP_NPL_CLK] = &vcap_npl_clk.clkr, |
| 2536 | [PLL15] = &pll15.clkr, |
| 2537 | }; |
| 2538 | |
| 2539 | static const struct qcom_reset_map mmcc_apq8064_resets[] = { |
| 2540 | [GFX3D_AXI_RESET] = { 0x0208, 17 }, |
| 2541 | [VCAP_AXI_RESET] = { 0x0208, 16 }, |
| 2542 | [VPE_AXI_RESET] = { 0x0208, 15 }, |
| 2543 | [IJPEG_AXI_RESET] = { 0x0208, 14 }, |
| 2544 | [MPD_AXI_RESET] = { 0x0208, 13 }, |
| 2545 | [VFE_AXI_RESET] = { 0x0208, 9 }, |
| 2546 | [SP_AXI_RESET] = { 0x0208, 8 }, |
| 2547 | [VCODEC_AXI_RESET] = { 0x0208, 7 }, |
| 2548 | [ROT_AXI_RESET] = { 0x0208, 6 }, |
| 2549 | [VCODEC_AXI_A_RESET] = { 0x0208, 5 }, |
| 2550 | [VCODEC_AXI_B_RESET] = { 0x0208, 4 }, |
| 2551 | [FAB_S3_AXI_RESET] = { 0x0208, 3 }, |
| 2552 | [FAB_S2_AXI_RESET] = { 0x0208, 2 }, |
| 2553 | [FAB_S1_AXI_RESET] = { 0x0208, 1 }, |
| 2554 | [FAB_S0_AXI_RESET] = { 0x0208 }, |
| 2555 | [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 }, |
| 2556 | [SMMU_VPE_AHB_RESET] = { 0x020c, 30 }, |
| 2557 | [SMMU_VFE_AHB_RESET] = { 0x020c, 29 }, |
| 2558 | [SMMU_ROT_AHB_RESET] = { 0x020c, 28 }, |
| 2559 | [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 }, |
| 2560 | [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 }, |
| 2561 | [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 }, |
| 2562 | [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 }, |
| 2563 | [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 }, |
| 2564 | [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 }, |
| 2565 | [APU_AHB_RESET] = { 0x020c, 18 }, |
| 2566 | [CSI_AHB_RESET] = { 0x020c, 17 }, |
| 2567 | [TV_ENC_AHB_RESET] = { 0x020c, 15 }, |
| 2568 | [VPE_AHB_RESET] = { 0x020c, 14 }, |
| 2569 | [FABRIC_AHB_RESET] = { 0x020c, 13 }, |
| 2570 | [GFX3D_AHB_RESET] = { 0x020c, 10 }, |
| 2571 | [HDMI_AHB_RESET] = { 0x020c, 9 }, |
| 2572 | [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 }, |
| 2573 | [IJPEG_AHB_RESET] = { 0x020c, 7 }, |
| 2574 | [DSI_M_AHB_RESET] = { 0x020c, 6 }, |
| 2575 | [DSI_S_AHB_RESET] = { 0x020c, 5 }, |
| 2576 | [JPEGD_AHB_RESET] = { 0x020c, 4 }, |
| 2577 | [MDP_AHB_RESET] = { 0x020c, 3 }, |
| 2578 | [ROT_AHB_RESET] = { 0x020c, 2 }, |
| 2579 | [VCODEC_AHB_RESET] = { 0x020c, 1 }, |
| 2580 | [VFE_AHB_RESET] = { 0x020c, 0 }, |
| 2581 | [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 }, |
| 2582 | [VCAP_AHB_RESET] = { 0x0200, 2 }, |
| 2583 | [DSI2_M_AHB_RESET] = { 0x0200, 1 }, |
| 2584 | [DSI2_S_AHB_RESET] = { 0x0200, 0 }, |
| 2585 | [CSIPHY2_RESET] = { 0x0210, 31 }, |
| 2586 | [CSI_PIX1_RESET] = { 0x0210, 30 }, |
| 2587 | [CSIPHY0_RESET] = { 0x0210, 29 }, |
| 2588 | [CSIPHY1_RESET] = { 0x0210, 28 }, |
| 2589 | [CSI_RDI_RESET] = { 0x0210, 27 }, |
| 2590 | [CSI_PIX_RESET] = { 0x0210, 26 }, |
| 2591 | [DSI2_RESET] = { 0x0210, 25 }, |
| 2592 | [VFE_CSI_RESET] = { 0x0210, 24 }, |
| 2593 | [MDP_RESET] = { 0x0210, 21 }, |
| 2594 | [AMP_RESET] = { 0x0210, 20 }, |
| 2595 | [JPEGD_RESET] = { 0x0210, 19 }, |
| 2596 | [CSI1_RESET] = { 0x0210, 18 }, |
| 2597 | [VPE_RESET] = { 0x0210, 17 }, |
| 2598 | [MMSS_FABRIC_RESET] = { 0x0210, 16 }, |
| 2599 | [VFE_RESET] = { 0x0210, 15 }, |
| 2600 | [GFX3D_RESET] = { 0x0210, 12 }, |
| 2601 | [HDMI_RESET] = { 0x0210, 11 }, |
| 2602 | [MMSS_IMEM_RESET] = { 0x0210, 10 }, |
| 2603 | [IJPEG_RESET] = { 0x0210, 9 }, |
| 2604 | [CSI0_RESET] = { 0x0210, 8 }, |
| 2605 | [DSI_RESET] = { 0x0210, 7 }, |
| 2606 | [VCODEC_RESET] = { 0x0210, 6 }, |
| 2607 | [MDP_TV_RESET] = { 0x0210, 4 }, |
| 2608 | [MDP_VSYNC_RESET] = { 0x0210, 3 }, |
| 2609 | [ROT_RESET] = { 0x0210, 2 }, |
| 2610 | [TV_HDMI_RESET] = { 0x0210, 1 }, |
| 2611 | [VCAP_NPL_RESET] = { 0x0214, 4 }, |
| 2612 | [VCAP_RESET] = { 0x0214, 3 }, |
| 2613 | [CSI2_RESET] = { 0x0214, 2 }, |
| 2614 | [CSI_RDI1_RESET] = { 0x0214, 1 }, |
| 2615 | [CSI_RDI2_RESET] = { 0x0214 }, |
| 2616 | }; |
| 2617 | |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 2618 | static const struct regmap_config mmcc_msm8960_regmap_config = { |
| 2619 | .reg_bits = 32, |
| 2620 | .reg_stride = 4, |
| 2621 | .val_bits = 32, |
| 2622 | .max_register = 0x334, |
| 2623 | .fast_io = true, |
| 2624 | }; |
| 2625 | |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 2626 | static const struct regmap_config mmcc_apq8064_regmap_config = { |
| 2627 | .reg_bits = 32, |
| 2628 | .reg_stride = 4, |
| 2629 | .val_bits = 32, |
| 2630 | .max_register = 0x350, |
| 2631 | .fast_io = true, |
| 2632 | }; |
| 2633 | |
Stephen Boyd | 49fc825 | 2014-03-21 17:59:37 -0700 | [diff] [blame] | 2634 | static const struct qcom_cc_desc mmcc_msm8960_desc = { |
| 2635 | .config = &mmcc_msm8960_regmap_config, |
| 2636 | .clks = mmcc_msm8960_clks, |
| 2637 | .num_clks = ARRAY_SIZE(mmcc_msm8960_clks), |
| 2638 | .resets = mmcc_msm8960_resets, |
| 2639 | .num_resets = ARRAY_SIZE(mmcc_msm8960_resets), |
| 2640 | }; |
| 2641 | |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 2642 | static const struct qcom_cc_desc mmcc_apq8064_desc = { |
| 2643 | .config = &mmcc_apq8064_regmap_config, |
| 2644 | .clks = mmcc_apq8064_clks, |
| 2645 | .num_clks = ARRAY_SIZE(mmcc_apq8064_clks), |
| 2646 | .resets = mmcc_apq8064_resets, |
| 2647 | .num_resets = ARRAY_SIZE(mmcc_apq8064_resets), |
| 2648 | }; |
| 2649 | |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 2650 | static const struct of_device_id mmcc_msm8960_match_table[] = { |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 2651 | { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc }, |
| 2652 | { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc }, |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 2653 | { } |
| 2654 | }; |
| 2655 | MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table); |
| 2656 | |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 2657 | static int mmcc_msm8960_probe(struct platform_device *pdev) |
| 2658 | { |
Stephen Boyd | e216ce6 | 2014-07-15 14:52:22 -0700 | [diff] [blame] | 2659 | const struct of_device_id *match; |
| 2660 | struct regmap *regmap; |
| 2661 | bool is_8064; |
| 2662 | struct device *dev = &pdev->dev; |
| 2663 | |
| 2664 | match = of_match_device(mmcc_msm8960_match_table, dev); |
| 2665 | if (!match) |
| 2666 | return -EINVAL; |
| 2667 | |
| 2668 | is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064"); |
| 2669 | if (is_8064) { |
| 2670 | gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064; |
| 2671 | gfx3d_src.clkr.hw.init = &gfx3d_8064_init; |
| 2672 | gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map; |
| 2673 | gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map; |
| 2674 | } |
| 2675 | |
| 2676 | regmap = qcom_cc_map(pdev, match->data); |
| 2677 | if (IS_ERR(regmap)) |
| 2678 | return PTR_ERR(regmap); |
| 2679 | |
| 2680 | clk_pll_configure_sr(&pll15, regmap, &pll15_config, false); |
| 2681 | |
| 2682 | return qcom_cc_really_probe(pdev, match->data, regmap); |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 2683 | } |
| 2684 | |
| 2685 | static int mmcc_msm8960_remove(struct platform_device *pdev) |
| 2686 | { |
Stephen Boyd | 49fc825 | 2014-03-21 17:59:37 -0700 | [diff] [blame] | 2687 | qcom_cc_remove(pdev); |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 2688 | return 0; |
| 2689 | } |
| 2690 | |
| 2691 | static struct platform_driver mmcc_msm8960_driver = { |
| 2692 | .probe = mmcc_msm8960_probe, |
| 2693 | .remove = mmcc_msm8960_remove, |
| 2694 | .driver = { |
| 2695 | .name = "mmcc-msm8960", |
Stephen Boyd | 6d00b56 | 2014-01-15 10:47:29 -0800 | [diff] [blame] | 2696 | .of_match_table = mmcc_msm8960_match_table, |
| 2697 | }, |
| 2698 | }; |
| 2699 | |
| 2700 | module_platform_driver(mmcc_msm8960_driver); |
| 2701 | |
| 2702 | MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver"); |
| 2703 | MODULE_LICENSE("GPL v2"); |
| 2704 | MODULE_ALIAS("platform:mmcc-msm8960"); |