blob: b3bcf72dc65623f412c3902a425ffdcd98b9b563 [file] [log] [blame]
Dave Airlie0d6aa602006-01-02 20:14:23 +11001/*
Dave Airliebc54fd12005-06-23 22:46:46 +10002 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110025 */
Dave Airliebc54fd12005-06-23 22:46:46 +100026
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#ifndef _I915_DRM_H_
28#define _I915_DRM_H_
29
30/* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints.
32 */
33
34#include "drm.h"
35
36/* Each region is a minimum of 16k, and there are at most 255 of them.
37 */
38#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40#define I915_LOG_MIN_TEX_REGION_SIZE 14
41
42typedef struct _drm_i915_init {
43 enum {
44 I915_INIT_DMA = 0x01,
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03
47 } func;
48 unsigned int mmio_offset;
49 int sarea_priv_offset;
50 unsigned int ring_start;
51 unsigned int ring_end;
52 unsigned int ring_size;
53 unsigned int front_offset;
54 unsigned int back_offset;
55 unsigned int depth_offset;
56 unsigned int w;
57 unsigned int h;
58 unsigned int pitch;
59 unsigned int pitch_bits;
60 unsigned int back_pitch;
61 unsigned int depth_pitch;
62 unsigned int cpp;
63 unsigned int chipset;
64} drm_i915_init_t;
65
66typedef struct _drm_i915_sarea {
Dave Airliec60ce622007-07-11 15:27:12 +100067 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 int last_upload; /* last time texture was uploaded */
69 int last_enqueue; /* last time a buffer was enqueued */
70 int last_dispatch; /* age of the most recently dispatched buffer */
71 int ctxOwner; /* last context to upload state */
72 int texAge;
73 int pf_enabled; /* is pageflipping allowed? */
74 int pf_active;
75 int pf_current_page; /* which buffer is being displayed? */
76 int perf_boxes; /* performance boxes to be displayed */
Dave Airliede227f52006-01-25 15:31:43 +110077 int width, height; /* screen size in pixels */
78
79 drm_handle_t front_handle;
80 int front_offset;
81 int front_size;
82
83 drm_handle_t back_handle;
84 int back_offset;
85 int back_size;
86
87 drm_handle_t depth_handle;
88 int depth_offset;
89 int depth_size;
90
91 drm_handle_t tex_handle;
92 int tex_offset;
93 int tex_size;
94 int log_tex_granularity;
95 int pitch;
96 int rotation; /* 0, 90, 180 or 270 */
97 int rotated_offset;
98 int rotated_size;
99 int rotated_pitch;
100 int virtualX, virtualY;
Alan Hourihanec29b6692006-08-12 16:29:24 +1000101
102 unsigned int front_tiled;
103 unsigned int back_tiled;
104 unsigned int depth_tiled;
105 unsigned int rotated_tiled;
106 unsigned int rotated2_tiled;
=?utf-8?q?Michel_D=C3=A4nzer?=376642c2006-10-25 00:09:35 +1000107
Dave Airlieaf6061a2008-05-07 12:15:39 +1000108 int pipeA_x;
109 int pipeA_y;
110 int pipeA_w;
111 int pipeA_h;
112 int pipeB_x;
113 int pipeB_y;
114 int pipeB_w;
115 int pipeB_h;
Dave Airliedfef2452008-12-19 15:07:46 +1000116
117 /* fill out some space for old userspace triple buffer */
118 drm_handle_t unused_handle;
119 uint32_t unused1, unused2, unused3;
120
121 /* buffer object handles for static buffers. May change
122 * over the lifetime of the client.
123 */
124 uint32_t front_bo_handle;
125 uint32_t back_bo_handle;
126 uint32_t unused_bo_handle;
127 uint32_t depth_bo_handle;
128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129} drm_i915_sarea_t;
130
Dave Airliedfef2452008-12-19 15:07:46 +1000131/* due to userspace building against these headers we need some compat here */
132#define planeA_x pipeA_x
133#define planeA_y pipeA_y
134#define planeA_w pipeA_w
135#define planeA_h pipeA_h
136#define planeB_x pipeB_x
137#define planeB_y pipeB_y
138#define planeB_w pipeB_w
139#define planeB_h pipeB_h
140
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141/* Flags for perf_boxes
142 */
143#define I915_BOX_RING_EMPTY 0x1
144#define I915_BOX_FLIP 0x2
145#define I915_BOX_WAIT 0x4
146#define I915_BOX_TEXTURE_LOAD 0x8
147#define I915_BOX_LOST_CONTEXT 0x10
148
149/* I915 specific ioctls
150 * The device specific ioctl range is 0x40 to 0x79.
151 */
152#define DRM_I915_INIT 0x00
153#define DRM_I915_FLUSH 0x01
154#define DRM_I915_FLIP 0x02
155#define DRM_I915_BATCHBUFFER 0x03
156#define DRM_I915_IRQ_EMIT 0x04
157#define DRM_I915_IRQ_WAIT 0x05
158#define DRM_I915_GETPARAM 0x06
159#define DRM_I915_SETPARAM 0x07
160#define DRM_I915_ALLOC 0x08
161#define DRM_I915_FREE 0x09
162#define DRM_I915_INIT_HEAP 0x0a
163#define DRM_I915_CMDBUFFER 0x0b
Dave Airliede227f52006-01-25 15:31:43 +1100164#define DRM_I915_DESTROY_HEAP 0x0c
Dave Airlie702880f2006-06-24 17:07:34 +1000165#define DRM_I915_SET_VBLANK_PIPE 0x0d
166#define DRM_I915_GET_VBLANK_PIPE 0x0e
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000167#define DRM_I915_VBLANK_SWAP 0x0f
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000168#define DRM_I915_HWS_ADDR 0x11
Eric Anholt673a3942008-07-30 12:06:12 -0700169#define DRM_I915_GEM_INIT 0x13
170#define DRM_I915_GEM_EXECBUFFER 0x14
171#define DRM_I915_GEM_PIN 0x15
172#define DRM_I915_GEM_UNPIN 0x16
173#define DRM_I915_GEM_BUSY 0x17
174#define DRM_I915_GEM_THROTTLE 0x18
175#define DRM_I915_GEM_ENTERVT 0x19
176#define DRM_I915_GEM_LEAVEVT 0x1a
177#define DRM_I915_GEM_CREATE 0x1b
178#define DRM_I915_GEM_PREAD 0x1c
179#define DRM_I915_GEM_PWRITE 0x1d
180#define DRM_I915_GEM_MMAP 0x1e
181#define DRM_I915_GEM_SET_DOMAIN 0x1f
182#define DRM_I915_GEM_SW_FINISH 0x20
183#define DRM_I915_GEM_SET_TILING 0x21
184#define DRM_I915_GEM_GET_TILING 0x22
Eric Anholt5a125c32008-10-22 21:40:13 -0700185#define DRM_I915_GEM_GET_APERTURE 0x23
Jesse Barnesde151cf2008-11-12 10:03:55 -0800186#define DRM_I915_GEM_MMAP_GTT 0x24
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187
188#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
189#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
Dave Airlieaf6061a2008-05-07 12:15:39 +1000190#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
192#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
193#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
194#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
195#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
196#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
197#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
198#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
199#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
Dave Airliede227f52006-01-25 15:31:43 +1100200#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
Dave Airlie702880f2006-06-24 17:07:34 +1000201#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
202#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
=?utf-8?q?Michel_D=C3=A4nzer?=541f29a2006-10-24 23:38:54 +1000203#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
Eric Anholt8d391aa2008-12-17 22:32:14 -0800204#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
205#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
Eric Anholt673a3942008-07-30 12:06:12 -0700206#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
207#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
208#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
209#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
210#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
211#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
212#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
213#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
214#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
215#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
Jesse Barnesde151cf2008-11-12 10:03:55 -0800216#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
Eric Anholt673a3942008-07-30 12:06:12 -0700217#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
218#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
219#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
220#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
Eric Anholt5a125c32008-10-22 21:40:13 -0700221#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222
223/* Allow drivers to submit batchbuffers directly to hardware, relying
224 * on the security mechanisms provided by hardware.
225 */
Jesse Barnes79e53942008-11-07 14:24:08 -0800226typedef struct drm_i915_batchbuffer {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227 int start; /* agp offset */
228 int used; /* nr bytes in use */
229 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
230 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
231 int num_cliprects; /* mulitpass with multiple cliprects? */
Dave Airliec60ce622007-07-11 15:27:12 +1000232 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233} drm_i915_batchbuffer_t;
234
235/* As above, but pass a pointer to userspace buffer which can be
236 * validated by the kernel prior to sending to hardware.
237 */
238typedef struct _drm_i915_cmdbuffer {
239 char __user *buf; /* pointer to userspace command buffer */
240 int sz; /* nr bytes in buf */
241 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
242 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
243 int num_cliprects; /* mulitpass with multiple cliprects? */
Dave Airliec60ce622007-07-11 15:27:12 +1000244 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245} drm_i915_cmdbuffer_t;
246
247/* Userspace can request & wait on irq's:
248 */
249typedef struct drm_i915_irq_emit {
250 int __user *irq_seq;
251} drm_i915_irq_emit_t;
252
253typedef struct drm_i915_irq_wait {
254 int irq_seq;
255} drm_i915_irq_wait_t;
256
257/* Ioctl to query kernel params:
258 */
259#define I915_PARAM_IRQ_ACTIVE 1
260#define I915_PARAM_ALLOW_BATCHBUFFER 2
Dave Airlie0d6aa602006-01-02 20:14:23 +1100261#define I915_PARAM_LAST_DISPATCH 3
Kristian Høgsberged4c9c42008-08-20 11:08:52 -0400262#define I915_PARAM_CHIPSET_ID 4
Eric Anholt673a3942008-07-30 12:06:12 -0700263#define I915_PARAM_HAS_GEM 5
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264
265typedef struct drm_i915_getparam {
266 int param;
267 int __user *value;
268} drm_i915_getparam_t;
269
270/* Ioctl to set kernel params:
271 */
272#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
273#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
274#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
275
276typedef struct drm_i915_setparam {
277 int param;
278 int value;
279} drm_i915_setparam_t;
280
281/* A memory manager for regions of shared memory:
282 */
283#define I915_MEM_REGION_AGP 1
284
285typedef struct drm_i915_mem_alloc {
286 int region;
287 int alignment;
288 int size;
289 int __user *region_offset; /* offset from start of fb or agp */
290} drm_i915_mem_alloc_t;
291
292typedef struct drm_i915_mem_free {
293 int region;
294 int region_offset;
295} drm_i915_mem_free_t;
296
297typedef struct drm_i915_mem_init_heap {
298 int region;
299 int size;
300 int start;
301} drm_i915_mem_init_heap_t;
302
Dave Airliede227f52006-01-25 15:31:43 +1100303/* Allow memory manager to be torn down and re-initialized (eg on
304 * rotate):
305 */
306typedef struct drm_i915_mem_destroy_heap {
307 int region;
308} drm_i915_mem_destroy_heap_t;
309
Dave Airlie702880f2006-06-24 17:07:34 +1000310/* Allow X server to configure which pipes to monitor for vblank signals
311 */
312#define DRM_I915_VBLANK_PIPE_A 1
313#define DRM_I915_VBLANK_PIPE_B 2
314
315typedef struct drm_i915_vblank_pipe {
316 int pipe;
317} drm_i915_vblank_pipe_t;
318
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000319/* Schedule buffer swap at given vertical blank:
320 */
321typedef struct drm_i915_vblank_swap {
322 drm_drawable_t drawable;
Dave Airliec60ce622007-07-11 15:27:12 +1000323 enum drm_vblank_seq_type seqtype;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000324 unsigned int sequence;
325} drm_i915_vblank_swap_t;
326
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000327typedef struct drm_i915_hws_addr {
328 uint64_t addr;
329} drm_i915_hws_addr_t;
330
Eric Anholt673a3942008-07-30 12:06:12 -0700331struct drm_i915_gem_init {
332 /**
333 * Beginning offset in the GTT to be managed by the DRM memory
334 * manager.
335 */
336 uint64_t gtt_start;
337 /**
338 * Ending offset in the GTT to be managed by the DRM memory
339 * manager.
340 */
341 uint64_t gtt_end;
342};
343
344struct drm_i915_gem_create {
345 /**
346 * Requested size for the object.
347 *
348 * The (page-aligned) allocated size for the object will be returned.
349 */
350 uint64_t size;
351 /**
352 * Returned handle for the object.
353 *
354 * Object handles are nonzero.
355 */
356 uint32_t handle;
357 uint32_t pad;
358};
359
360struct drm_i915_gem_pread {
361 /** Handle for the object being read. */
362 uint32_t handle;
363 uint32_t pad;
364 /** Offset into the object to read from */
365 uint64_t offset;
366 /** Length of data to read */
367 uint64_t size;
368 /**
369 * Pointer to write the data into.
370 *
371 * This is a fixed-size type for 32/64 compatibility.
372 */
373 uint64_t data_ptr;
374};
375
376struct drm_i915_gem_pwrite {
377 /** Handle for the object being written to. */
378 uint32_t handle;
379 uint32_t pad;
380 /** Offset into the object to write to */
381 uint64_t offset;
382 /** Length of data to write */
383 uint64_t size;
384 /**
385 * Pointer to read the data from.
386 *
387 * This is a fixed-size type for 32/64 compatibility.
388 */
389 uint64_t data_ptr;
390};
391
392struct drm_i915_gem_mmap {
393 /** Handle for the object being mapped. */
394 uint32_t handle;
395 uint32_t pad;
396 /** Offset in the object to map. */
397 uint64_t offset;
398 /**
399 * Length of data to map.
400 *
401 * The value will be page-aligned.
402 */
403 uint64_t size;
404 /**
405 * Returned pointer the data was mapped at.
406 *
407 * This is a fixed-size type for 32/64 compatibility.
408 */
409 uint64_t addr_ptr;
410};
411
Jesse Barnesde151cf2008-11-12 10:03:55 -0800412struct drm_i915_gem_mmap_gtt {
413 /** Handle for the object being mapped. */
414 uint32_t handle;
415 uint32_t pad;
416 /**
417 * Fake offset to use for subsequent mmap call
418 *
419 * This is a fixed-size type for 32/64 compatibility.
420 */
421 uint64_t offset;
422};
423
Eric Anholt673a3942008-07-30 12:06:12 -0700424struct drm_i915_gem_set_domain {
425 /** Handle for the object */
426 uint32_t handle;
427
428 /** New read domains */
429 uint32_t read_domains;
430
431 /** New write domain */
432 uint32_t write_domain;
433};
434
435struct drm_i915_gem_sw_finish {
436 /** Handle for the object */
437 uint32_t handle;
438};
439
440struct drm_i915_gem_relocation_entry {
441 /**
442 * Handle of the buffer being pointed to by this relocation entry.
443 *
444 * It's appealing to make this be an index into the mm_validate_entry
445 * list to refer to the buffer, but this allows the driver to create
446 * a relocation list for state buffers and not re-write it per
447 * exec using the buffer.
448 */
449 uint32_t target_handle;
450
451 /**
452 * Value to be added to the offset of the target buffer to make up
453 * the relocation entry.
454 */
455 uint32_t delta;
456
457 /** Offset in the buffer the relocation entry will be written into */
458 uint64_t offset;
459
460 /**
461 * Offset value of the target buffer that the relocation entry was last
462 * written as.
463 *
464 * If the buffer has the same offset as last time, we can skip syncing
465 * and writing the relocation. This value is written back out by
466 * the execbuffer ioctl when the relocation is written.
467 */
468 uint64_t presumed_offset;
469
470 /**
471 * Target memory domains read by this operation.
472 */
473 uint32_t read_domains;
474
475 /**
476 * Target memory domains written by this operation.
477 *
478 * Note that only one domain may be written by the whole
479 * execbuffer operation, so that where there are conflicts,
480 * the application will get -EINVAL back.
481 */
482 uint32_t write_domain;
483};
484
485/** @{
486 * Intel memory domains
487 *
488 * Most of these just align with the various caches in
489 * the system and are used to flush and invalidate as
490 * objects end up cached in different domains.
491 */
492/** CPU cache */
493#define I915_GEM_DOMAIN_CPU 0x00000001
494/** Render cache, used by 2D and 3D drawing */
495#define I915_GEM_DOMAIN_RENDER 0x00000002
496/** Sampler cache, used by texture engine */
497#define I915_GEM_DOMAIN_SAMPLER 0x00000004
498/** Command queue, used to load batch buffers */
499#define I915_GEM_DOMAIN_COMMAND 0x00000008
500/** Instruction cache, used by shader programs */
501#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
502/** Vertex address cache */
503#define I915_GEM_DOMAIN_VERTEX 0x00000020
504/** GTT domain - aperture and scanout */
505#define I915_GEM_DOMAIN_GTT 0x00000040
506/** @} */
507
508struct drm_i915_gem_exec_object {
509 /**
510 * User's handle for a buffer to be bound into the GTT for this
511 * operation.
512 */
513 uint32_t handle;
514
515 /** Number of relocations to be performed on this buffer */
516 uint32_t relocation_count;
517 /**
518 * Pointer to array of struct drm_i915_gem_relocation_entry containing
519 * the relocations to be performed in this buffer.
520 */
521 uint64_t relocs_ptr;
522
523 /** Required alignment in graphics aperture */
524 uint64_t alignment;
525
526 /**
527 * Returned value of the updated offset of the object, for future
528 * presumed_offset writes.
529 */
530 uint64_t offset;
531};
532
533struct drm_i915_gem_execbuffer {
534 /**
535 * List of buffers to be validated with their relocations to be
536 * performend on them.
537 *
538 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
539 *
540 * These buffers must be listed in an order such that all relocations
541 * a buffer is performing refer to buffers that have already appeared
542 * in the validate list.
543 */
544 uint64_t buffers_ptr;
545 uint32_t buffer_count;
546
547 /** Offset in the batchbuffer to start execution from. */
548 uint32_t batch_start_offset;
549 /** Bytes used in batchbuffer from batch_start_offset */
550 uint32_t batch_len;
551 uint32_t DR1;
552 uint32_t DR4;
553 uint32_t num_cliprects;
554 /** This is a struct drm_clip_rect *cliprects */
555 uint64_t cliprects_ptr;
556};
557
558struct drm_i915_gem_pin {
559 /** Handle of the buffer to be pinned. */
560 uint32_t handle;
561 uint32_t pad;
562
563 /** alignment required within the aperture */
564 uint64_t alignment;
565
566 /** Returned GTT offset of the buffer. */
567 uint64_t offset;
568};
569
570struct drm_i915_gem_unpin {
571 /** Handle of the buffer to be unpinned. */
572 uint32_t handle;
573 uint32_t pad;
574};
575
576struct drm_i915_gem_busy {
577 /** Handle of the buffer to check for busy */
578 uint32_t handle;
579
580 /** Return busy status (1 if busy, 0 if idle) */
581 uint32_t busy;
582};
583
584#define I915_TILING_NONE 0
585#define I915_TILING_X 1
586#define I915_TILING_Y 2
587
588#define I915_BIT_6_SWIZZLE_NONE 0
589#define I915_BIT_6_SWIZZLE_9 1
590#define I915_BIT_6_SWIZZLE_9_10 2
591#define I915_BIT_6_SWIZZLE_9_11 3
592#define I915_BIT_6_SWIZZLE_9_10_11 4
593/* Not seen by userland */
594#define I915_BIT_6_SWIZZLE_UNKNOWN 5
595
596struct drm_i915_gem_set_tiling {
597 /** Handle of the buffer to have its tiling state updated */
598 uint32_t handle;
599
600 /**
601 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
602 * I915_TILING_Y).
603 *
604 * This value is to be set on request, and will be updated by the
605 * kernel on successful return with the actual chosen tiling layout.
606 *
607 * The tiling mode may be demoted to I915_TILING_NONE when the system
608 * has bit 6 swizzling that can't be managed correctly by GEM.
609 *
610 * Buffer contents become undefined when changing tiling_mode.
611 */
612 uint32_t tiling_mode;
613
614 /**
615 * Stride in bytes for the object when in I915_TILING_X or
616 * I915_TILING_Y.
617 */
618 uint32_t stride;
619
620 /**
621 * Returned address bit 6 swizzling required for CPU access through
622 * mmap mapping.
623 */
624 uint32_t swizzle_mode;
625};
626
627struct drm_i915_gem_get_tiling {
628 /** Handle of the buffer to get tiling state for. */
629 uint32_t handle;
630
631 /**
632 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
633 * I915_TILING_Y).
634 */
635 uint32_t tiling_mode;
636
637 /**
638 * Returned address bit 6 swizzling required for CPU access through
639 * mmap mapping.
640 */
641 uint32_t swizzle_mode;
642};
643
Eric Anholt5a125c32008-10-22 21:40:13 -0700644struct drm_i915_gem_get_aperture {
645 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
646 uint64_t aper_size;
647
648 /**
649 * Available space in the aperture used by i915_gem_execbuffer, in
650 * bytes
651 */
652 uint64_t aper_available_size;
653};
654
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655#endif /* _I915_DRM_H_ */